• HCD-V5500 is the deck, CD section
in MHC-V5500/V7700AV.
Manufactured under license from Dolby Laboratories
Licensing Corporation.
“DOLBY” and the doub le-D symbol a are trademarks
of Dolby Laboratories Licensing Corporation.
CDCD Mechanism TypeCDM38-5BD21
SectionBase Unit NameBU-5BD21
Tape deckModel Name Using Similar MechanismHCD-V8800
SectionT ape Transport Mechanism T ypeTCM-220WR2E
E Model
Chinese Model
Model Name Using Similar MechanismHCD-V8800
Optical Pick-up TypeKSS-213B/S-N
VIDEO CD/CD player section
SystemCompact disc and digital
audio system
LaserSemiconductor laser
(λ=780nm)
Emission duration:
continuous
Laser outputMax.44.6 µW*
*This output is the value
measured at a distance of
200 mm from the
objective lens surface on
the Optical Pick-up Block
with 7 mm aperture.
Audio
Frequency response 2 Hz - 20 kHz(±0.5 dB)
Wavelength780 - 790 nm
Signal-to-noise ratio More than 90 dB
Dynamic rangeMore than 90 dB
Video
Color system format NTSC, PAL
SPECIFICATIONS
CD OPTICAL DIGITAL OUT
(Square optical connector jack, rear panel)
Wavelength600 nm
Output Level–18 dBm
3-1. Back Panel, CD Block Removal········································· 5
3-2. Cassette Lid (A)/(B) Assy, Mechanism Deck Removal ···· 5
3-3. Main Board, Resistor Board, Video Board,
Video In Board, Front Panel Assy Removal ······················· 6
8.ELECTRICAL PARTS LIST ··································· 76
— 2 —
Page 3
SECTION 1
H
VIDEO board
TP709 (LED)
Oscilloscope
+
_
SERVICING NOTE
SELF-DIAGNOSIS
This model has the self-diagnosis function for the VIDEO and
AUDIO decoder sections.
Immediately after the power on, the self-diagnosis function searches
each operation of IC’s around the mechanism control microcomputer
(IC701).
The results can be checked by connecting an oscilloscope to TP709
(LED) of the VIDEO board.
Oscilloscope (Waveform)Symptom
H
No error
L
Light
Note: The LED for check (D701) is mounted to some sets
(FORMER TYPE). In this case, confirm the lighting
condition of LED.
#º OPTICAL DIGITAL OUT
#¡ SYSTEM CONTROL CONNECTOR
#™ SYSTEM SELECT SWITCH
#™#£
#¢#∞
#£ VIDEO IN JACK
#¢ MONITOR OUT JACK
#∞ S VIDEO JACK
— 4 —
Page 5
SECTION 3
0
DISASSEMBLY
Note :Follow the disassembly procedure in the numerical order given.
3-1.BACK PANEL, CD BLOCK REMOVAL
9
CD block
8
Screw
+BVTP 3
×
10
CASE
Unscrew the fi ve case attachment in the screws (case)
(M3 × 8) × 4, (+BV 3 × 8) × 1 and remove the case.
3
Back panel
1
Screw
+BVTP 3
2
Screw
+BVTP 3
×
1
×
8
7
Screw
+BVTP 3
3-2.CASSETTE LID (A)/(B) ASSY, MECHANISM DECK REMOVAL
1
Press the EJECT button and open the cassette lid.
Mechanism Deck (TCM-220WR2E)
7
+BVTP 2.6
6
Screw
4
5
CN112 (9 pin)
CN111 (8 pin)
×
10
×
8
1
Screw
+BVTP 3
Flat wire (19 core)
2
×
10
1
3
1
8
6
Screw
+BVTT 3
— 5 —
4
Flat wire (11 core)
5
Flat wire (21 core)
×
8
Page 6
3-3.MAIN BOARD, RESISTOR BOARD, VIDEO BOARD, VIDEO IN BOARD ,
d
FRONT PANEL ASSY REMOVAL
6
3
Screw
+BVTP 3
7
Bracket V (T)
9
VIDEO board
7
Bracket V (B)
×
10
Screw
+BVTP 3
×
10
8
Screw
+BVTP 3
5
!£
+BVTP 3
×
8
!º
Screw
+BVTP 3
Screw
4
×
8
×
8
!¡
VIDEO IN board
!™
Bracket (BP)
!¢
Bracket (H/S)
!∞
Resistor board
1
2
Front panel assy
Screw
+BVTP 3
×
8
• Tray (Slide) getting out procedure on the power supply is OFF
Rotate the BU CAM assembly in the direction of the arrow and pull out the slide.
!§
Screw
+BVTP 3
!¶
Main boar
×
8
Tray (Slide)
1
BU CAM assy
— 6 —
Page 7
SECTION 4
TEST MODE
VIDEO CD COLOR-BARS MODE
On this mode, the data of the color-bars signal as a picture signal
and the 1kHz sine wave signal as a sound signal are output by the
mechanism control microcomputer (IC701) for video CD signal
check. When measurement of the voltage and waveform on the
VIDEO board, perform it in this mode.
For reference, the color-bars signal can be observed at J9001
(VIDEO OUT) and the sound signal can be observed at J101
(VIDEO (AUDIO) OUT) using an oscilloscope.
1.Connect the lead wire to both ends of the land of SL701 (CAL
BAR) of the VIDEO board.
2.Turn the power on. Press FUNCTION button to select CD.
3.After 2 or 3 seconds later, connect the lead wire.
4.After measuring, remove the lead wire connected.
Note : The 1kHz sine wave is not outputted when the CD is played
once, but it is not error.
[VIDEO BARD ] (SIDE B)
SL703 (AFADJ)
SL702 (ADJ)
IC751
IC251
SL701 (CAL BAR)
— 7 —
Page 8
SECTION 5
ADJUSTMENTS
5-1.MECHANICAL ADJUSTMENT
PRECAUTION
1.Clean the following parts with a denatured-alcohol-moistened
swab:
2. Demagnetize the record/playback head with a head
demagnetizer.
3.Do not use a magnetized screwdriver for the adjustments.
4.After the adjustments, apply suitable locking compound to the
parts adjusted.
5.The adjustments should be performed with the rated power
supply voltage unless otherwise noted.
• T orque Measurement
ModeTorque MeterMeter Reading
ForwardCQ-102C
Forward
Back Tension(0.028 – 0.083 oz•inch)
ReverseCQ-102RC
Reverse
Back Tension(0.028 – 0.083 oz•inch)
FF, REWCQ-201B
CQ-102C
CQ-102RC
36 to 61g•cm
(0.50 – 0.84 oz•inch)
2 to 6g•cm
36 to 61g•cm
(0.50 – 0.84 oz•inch)
2 to 6g•cm
61 to 143g•cm
(0.85 – 1.99 oz•inch)
5-2.ELECTRICAL ADJUSTMENT
DECK SECTION
1.The adjustment should be performed in the publication.
(Be sure to make playback adjustment at first.)
2.The adjustment and measurement should be performed for both
L-CH and R-CH.
• Switch position
DOLBY NR switch : OFF
FUNCTION button : OFF
EFFECT switch: OFF
DBFB switch: OFF
3.Deck section electrical adjustments are made in test mode by
press key switch same time CD STOP DECK A ST OP and
DECK B STOP button.
4.Input point and output level measurement point.
• T ape Tension Measurement
ModeTension MeterMeter Reading
ForwardCQ-403A
ReverseCQ-403R
more than 100 g (3.53 oz)
more than 100 g (3.53 oz)
•Test Tape
TapeSignalUsed for
P-4-A10010 kHz, –10 dB
P-4-L300315 Hz, 0dBLevel Adjustment
WS-48B3 kHz, 0dBTape Speed Adjustment
0 dB=0.775V
Record/Playback Head Azimuth Adjustment
DECK ADECK B
Procedure:
1.Forward Playback mode
Reverse Playback mode
Head Azimuth Adjustment
— 8 —
Page 9
2.Turn the adjustment screw for the maximum output levels. If
t
these levels do not match, turn the adjustment screw until both
of output levels match together within 1 dB.
3.Playback Mode
Tape Speed AdjustmentDECK ADECK B
Note: Start the T ape Speed adjustment as belo w after setting to the
test mode.
Set to test mode. (Press key switch same time CD STOP
DECK A STOP and DECK B STOP button.)
Test mode off. (Power off.)
Procedure:
• Perform high speed adjustment before normal speed adjustment.
Mode: Playback
4.Change the playback mode and repeat the steps 1 to 3.
5.After the adjustment, lock the adjustment screw with suitable
locking compound.
Adjustment Location:
— Record/playback head (Deck A and B) —
Speed
*High
Normal
Deck
A
B
A
B
Adjustment
RV652
RV652
RV651
RV651
Frequency counter
5,910 to 6,090 Hz
2,910 to 3,090 Hz
* Continue to press HIGH SPEED DUBBING switch (S259) in
playback mode : High speed playback.
Frequency difference between the beginning and the end of the
tape should be within ± 3%.
Frequency difference between deck A and deck B the beginning
of the tape should be within 1.5 %.
Adjustment Location: AUDIO board (See page 10)
Sample Value of Wow and flutter
W.RMS (JIS) within 0.3%
(test tape: WS-48B)
Playback level Adjustment DECK ADECK B
Procedure:
— FWD playback Mode —
test tape
P-4-L300
(315 Hz, 0 dB)
VTVM
set
Output level measurement poin
(See page 8)
+
–
Deck A is RV311 (L-CH) and RV411 (R-CH), Deck B is RV301
(L-CH) and RV401 (R-CH) so that adjustment within adjustment
level as follows.
Adjustment Level:
LINE OUT level : –8.2 to –7.2 dB (301.5 to 338.3 mV)
Level Difference between Channels : within 0.5 dB
Confirm the OUTPUT level does not change in playback mode
while changing the mode from playback to stop several times.
Adjustment Location: AUDIO board (See page 10)
— 9 —
Page 10
Record Bias AdjustmentDECK B
)
Procedure:
1.Record mode
1) 315 Hz
2) 10 kHz
AF OSC
attenuator
50.1mV (–23.8dBs)
set
blank tape
CS-123
Adjustment Level:
OUTPUT level: –23.8 dB ± 1.0 dB (56.1 to 44.6 mV)
Adjustment Location: MAIN board
Adjustment Location :
[AUDIO BOARD] — Component Side —
RV301 : Playback Level (Deck B L-CH)
RV401 : Palyback Level
(Deck B R-CH)
RV651 : Tape Speed (Normal)
Input point (See page 8)
2.Mode: Playback
3. Confirm playback the signal recorded in step 1 become
adjustment level as follows.
4.If these levels do not adjustment level, adjustment the RV341
(L-CH) and RV441 (R-CH) to repeat steps 1 and 4.
Adjustment level: Playback output of 315 Hz to playback output
of 10 kHz: 0 ± 1.0 dB (0 ± 4.5mV).
Adjustment Location: AUDIO board
Record Level Adjustment DECK B
Procedure:
1.Record mode
RV341 : Record Bias (L-CH)
RV441 : Record Bias (R-CH)
RV411 : Playback Level (Deck A R-CH)
[MAIN BOARD] — Component Side —
RV451 Record Level (R
CNB108
RV401 Record Level (L)
RV652 : Tape Speed
(Hight)
RV311 : Playback Level
(Deck A L-CH)
2.Playback mode
3. Confirm playback the signal recorded in step 1 become
adjustment level as follows.
4.If these levels do not adjustment level, adjustment the RV401
(L-CH) and RV451 (R-CH) to repeat steps 1 and 4.
— 10 —
Page 11
CD SECTION
BD board
Oscilloscope
TP (RF)
TP (VC)
Note :
1.CD Block is basically designed to operate without adjustment.
Therefore, check each item in order given.
3.Use an oscilloscope with more than 10MΩ impedance.
4.Clean the object lens by an applicator with neutral detergent
when the signal level is low than specified value with the
following checks.
S Curve Check
Oscilloscope
BD board
TP (FE)
TP (VC)
RF Level Check
Procedure :
1.Connect oscilloscope to test point TP (RF) on BD board.
2.Turned Power switch on.
3.Put disc (YEDS-18) in to play the number five track.
4.Confirm that oscilloscope waveform is clear and check RF
signal level is correct or not.
Note : A clear RF signal waveform means that the shape “◊” can
be clearly distinguished at the center of the waveform.
RF signal waveform
Procedure :
1.Connect oscilloscope to test point TP (FE) on BD board.
2.Connect between test point TP (FEI) and TP (VC) by lead wire.
3.Turned Power switch on.
4.Put disc (YEDS-18) in and turned Power switch on again and
actuate the focus search. (actuate the focus search when disc
table is moving in and out.)
5.Check the oscilloscope waveform (S-curve) is symmetrical
between A and B. And confirm peak to peak level within 3 ± 1
Vp-p.
S-curve waveform
Symmetry
A
Within 3
B
±
1 Vp-p
6.After check, remove the lead wire connected in step 2.
Note : • Try to measure several times to make sure than the ratio
of A : B or B : A is more than 10 : 7.
• Take sweep time as long as possible and light up the
brightness to obtain best waveform.
VOLT/DIV : 200mV
TIME/DIV : 500ns
Level : 1.3 Vp-p
+0.25
–0.20
— 11 —
Page 12
RF PLL Free-run Frequency Check
r
r
Procedure :
1.Connect frequency counter to TP (PLCK) with lead wire.
VIDEO SECTION
Frequency adjustment
BD baord
TP (PLCK)
frequency counte
2.Turned Power switch on.
3.Put the disc (YEDS-18) in to play the number five track.Conf irm
that reading on frequency counter is 4.3218 MHz.
Adjustment Location :
[BD BOARD] — SIDE A —
(FEI)
(FE)
(TE)
(PLCK)
IC103
(RF)
(VC)
1.Connect the frequency counter to check point of the VIDEO
board.
frequency counte
VIDEO board
TP410 (DCLK)
2.Adjust CT401 of the VIDEO board so that the frequency counter
read 13.5 MHz ± 40 Hz at STOP condition.
[VIDEO BOARD] — SIDE B —
SL703 (AFADJ)
SL702 (ADJ)
IC751
IC251
SL701 (CAL BAR)
CT401
Frequency
TP410 (DCLK)
IC101
— 12 —
Page 13
6-1. BLOCK DIAGRAM — CD SECTION —
HCD-V5500
SECTION 6
DIAGRAMS
OPTICAL PICK-UP
BLOCK (KSS-213B/S-N)
LASER
DIODE
POWER
PD
LD
DETECTOR
E
AC
BD
F
TRACKING
COIL
FOCUS
COIL
IC107
RF AMP
APC LD
2
AMP
1
3
4
SUMMING
5
6
TRACKING
8
9
FOCUS/TRACKING COIL DRIVE
SPINDLE/SLED MOTOR DRIVE
1
2
16
17
13
12
27
26
AMP
ERROR
AMP
IC103
RF
FOCUS
ERROR
BUFFER
19
RF
RF FQ
16
AMP
AMP
VC
IC102
15
13
1110
VC
12
4
5
19
20
10
9
23
24
INTEGRATOR
INTE-
GRATOR
LD
LD
DRIVE
Q101
4
1
VC
T+
T–
F+
F–
M102
SLED
M
MOTOR
M101
SPINDLE
M
MOTOR
DIGITAL SERVO
DIGITAL SIGNAL PROCESSOR
IC101
ASY0
39
RF AC
36
ASY1
ASYMMETRY
38
CORRECTION
RF DC
26
TE
27
28
29
4
6
8
10
2
100
96
SE
FE
TFDR
TRDR
FFDR
FRDR
SRDR
SFDR
MDP
A/D
CONVERTER
MIRR
DFCT
FOK
DETECTOR
62
XTAL
CLOCK
GENERATOR
DIGITAL
PLL
EFM
DEMODULATOR
SYNC
PROTECTOR
TIMING
GENERATOR 1
CLV SERVO
PROCESSOR
1B TIMS
OVERSAMPLING
FILTER
NOISE
SHAPER
REGISTER
CORRECTOR
GENERATOR 2
MIX
FOK
DFCT
MIRR
SERVO DSP
FOCUS
SERVO
TRACKING
SERVO
SLED
SERVO
PWM
GENERATOR
TRACKING
PWM
GENERATOR
FOCUS
PWM
GENERATOR
SLED
PWM
GENERATOR
ERROR
TIMING
DATA BUS
PRIORITY
EMCODER
ADDRESS
GENERATOR
32K
RAM
D/A
DATA
PROCESSOR
79 54
MUTE
+5V
MD2
70
DOUT
DIGITAL
OUT
PEAK
DETECTOR
SERIAL/PARALLEL
PROCESSOR
GFS
S STOP
99
+5V
SERVO
INTERFACE
S101
LIMIT
SWITCH
SUBCODE
P-W
PROCESSOR
SUBCODE
Q
PROCESSOR
INTERFACE
SEQUENCER
CPU
SERVO
AUTO
EXCK
SBSO
SUBQ
SQCK
SCLK
DATA
LRCK
BCLK
SCOR
WFCK
DATA
SENS
C2PO
DFCT
MIRR
XRST
71
76
75
77
78
83
46
45
47
74
73
86
XLT
87
CLK
88
80
56
FOK
93
92
91
81
DIGITAL
OUT
OPTICAL
1
LDON
384BD
EXCK
SUBQ
SUBQ
SQCK
SCLK
ADATA
LRCK
BCLK
SCOR
B
DATA
VIDEO
XLT
SECTION
CLK
(Page 15 )
SENS
C2PO
XRST
AMUTE
16
15MUTE
• SIGNAL PATH
: CD
: DIGITAL OUT
: VIDEO
— 13 —— 14 —
Page 14
HCD-V5500
6-2. BLOCK DIAGRAM — VIDEO SECTION —
BUFFER
X202
X201
9
8
7
6
5
IC501 (1/2)
XTL0O
2
XTL01
3
106
XTL2O
107
XTL2I
73
DATA
78
CLK
74
AMUTE
11
SQCK
10
SUBQ
77
SCLK
XLT
76
75
LDON
71
SCOR
62
SENS
RESET
48
112
11
111
12
110
13
109
14
103
15
100
101
102
D-RAM INTERFACE
38–43 46–55•
2–5 7–10 35–38 40–43
•
•
•
DQ1
A0
I/O8
I/O1
2–10 21 23–25
•11–13 15–19
21–29 • 31–3513 – 20
D7
D0
CD-ROM
DECODER
MPEG
AUDIO
DECODER
17–21 23 24 32 33••••
18–21 24–28•
A0
DQ16
D-RAM
IC251
S-RAM
IC751
A12
••
55
A0
A12
B
CD
SECTION
(Page 14 )
IC501
(2/2)
B
CD
SECTION
(Page 14 )
16
BCK
ADATA
LRCK
C2PO
384FS
ADATA
LRCK
BCLK
DATA
CLK
AMUTE
384FS
416
384FS
DATA
CLK
AMUTE
SQCK
SUBQ
SCLK
XLT
LDON
SCOR
SENS
XRST
LED control.
LED control.
LED control.
Not used.
Communciation data.
Comunicaton clock.
CD reset.
CD latch.
Focus switch.
Table-L.
Table-R.
Not used.
Load out.
I
I
I
I
I
I
I
I
I
I
I
Load in.
LED control.
LED control.
LED control.
LED control.
LED control.
LED control.
Ground.
LED control.
LED control.
BD status input.
Disc sensor.
Table sensor.
Not used.
Encoder input for CDM38.
Encoder input for CDM38.
Encoder input for CDM38.
Encoder input for CDM38.
Capstan motor H/N selection.
Mechanism timing output control.
Mechanism timing output control.
Mechanism timing output control.
Capstan motor ON/OFF switch.
Playback A/B selection.
Equalizer H/L selection.
Bias ON/OFF.
REC mute.
NR ON/OFF.
REC/PB/PASS select.
TC mute.
Mechanism PLAY switch.
Mechanism PLAY switch.
Head selection.
Cassette half detection.
Not used.
Not used.
Not used.
Data input/output signal pin. Connect to the DRAM data pin so that the lower and upper bytes of
I/O
the data correspond to the CAS0 to CAS3 controls.
I/O
—
+5V power supply
—
Ground
I/O
I/O
I/O
I/O
I/O
Data input/output signal pin. Connect to the DRAM data pin so that the lower and upper bytes of
I/O
the data correspond to the CAS0 to CAS3 controls.
I/O
I/O
I/O
I/O
I
OSD enable signal
I
OSD data input pin. When the XOSDEN input is “L”, the color registered in the register specified by
I
this 3 inputs (3 bits) is output as the image data.
I
—
+5V power supply
—
Ground
Video output enable signal pin. When set to “L”, enables the image data output and DCLK output. When set to
I
“H”, disables (high impedance). Output control can also be performed by writing in the register. (Connected to
ground)
O
O
O
O
Output pin of the R or Cr signal of the image data. MSB is R/Cr7. Synchronizes with DCLK.
O
O
O
O
O
O
Output pin of the G or Y signal of the image data. MSB is G/Y7. Synchronizes with DCLK.
O
—
+5V power supply
—
Ground
O
O
Output pin of the G or Y signal of the image data. MSB is G/Y7. Synchronizes with DCLK.
O
O
O
Description
— 60 —
Page 23
Pin No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Pin Name
B/Cb0
B/Cb1
B/Cb2
B/Cb3
B/Cb4
B/Cb5
B/Cb6
B/Cb7
DCLK
VDD
VSS
HSYNC
VSYNC
FID/FHREF
CBLNK/FSC
CSYNC
XSGRST
CLK0O
DOUT
DATO
LRCO
BCKO
FSXI
VDD
VSS
I/O
O
O
O
O
Output pin of the B or Cb signal of the image data. MSB is B/Cb7. Synchronizes with DCLK. (Not used)
O
O
O
O
Dot clock (DCLK) signal pin. The DCLK frequency is normally 13.5MHz. The DCLK can be input from this pin
I
or can be made by frequency-dividing (1/integer) the clock input from XTL0I.
—
+5V power supply
—
Ground
Horizontal sync signal pin. When using the built-in sync generator, a signal is made by frequency-dividing the
I
dot clock (DCLK). Serves as the input when not using the built-in sync generator.
Vertical sync signal pin. When using the built-in sync generator, a signal is made by frequency-dividing the
I
DCLK. Serves as the input when not using the built-in sync generator.
Field determination signal. Odd field correspond to “H” and even field correspond to “L”. Serves as an output
when the built-in sync generator is used, and as an input when not.
I
/ Signal obtained by frequency-dividing the clock input from XTL0I or XTLI. When the input clock is 8 fsc, it
can be used as the horizontal sync signal phase comparison reference signal.
Composite blanking signal pin. Serves as an output when the built-in sync generator is used, and as an input
I
when not. / Signal obtained by frequency-dividing the clock input from XTL0I or XTLI. When the input clock is
8 fsc, it can be used as the fsc signal.
O
Composite sync signal pin. A signal is made by frequency-dividing the DCLK. Cannot be input. (Not used)
I
Sync generator reset signal pin. The signal generator is initialized by setting this pin to “L”.
Outputs the frequency-divided clock of the clock input to XTL0I. The frequency dividing ratio can be selected
O
from 1/2, 1/4, and 1/8. (Not used)
O
Digital output (Not used)
O
Audio serial data output to Audio D/A converter (IC101)
CD-ROM decoder, audio decoder master clock. Input a clock to the XTL21 or connect an oscillator between
XTL2I and XTL2O. The recommended frequency is 45 MHz. This clock is for the internal circuit. Does not
I
synchronize with inputs and outputs.
—
+5V power supply
I
C2 pointer input (CXD2545Q)
I
LR clock input (CXD2545Q)
I
Serial data input (CXD2545Q)
I
Bit clock input (CXD2545Q)
I
Digital input signal (Not used)
I
Register access chip select signal pin.
I/O
Data acknowledge/wait signal pin for DMA transmission, register access, transparent memory access.
I
Register access control signal pin.
O
Interrupt request signal
I
Hardware reset input pin. When set to “L”, all registers and operations are reset and initialized.
I
Address input pin. In some cases, serves as the control signal and data input according to the setting
NR feedback coefficient user processor select (Connect to +5V)
I
Power on reset
—
Ground
I
Composit SYNC input (Connect to ground)
I
Composit blanking input (Connect to +5V)
I
V SYNC input
I
H SYNC input
—
Power supply (+5V)
I
Dot clock input (13.5MHz)
Description
— 63 —
Page 26
• IC401 10 BIT VIDEO D/A CONVERTER (CXD1913Q)/VIDEO board
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Pin Name
Y7
Y6
Y5
Y4
VSS
Y3
Y2
Y1
Y0
VDD
C7
C6
C5
C4
C3
C2
C1
C0
VSS
IREF
VREF
AVDD1
AVSS1
COMPO
VB
VG
AVDD2
AVSS2
YOUT
AVDD3
AVSS3
COUT
TD10
VDD
TD9
TD8
XTEST1
XTEST2
XTEST3
VSS
TRST
VDD
TDI
TMS
I/O
I
8-bit pixel data input pins (PD0 to 7).
I
When control register bit “PIF MODE”=“0”, serve as input pins for multiplexed Y, Cb, Cr signals.
I
When control register bit “PIF MODE”=“1”, serve as input pins for Y signal.
I
—
Digital ground
I
8-bit pixel data input pins (PD0 to 7).
I
When control register bit “PIF MODE”=“0”, serve as input pins for multiplexed Y, Cb, Cr signals.
I
When control register bit “PIF MODE”=“1”, serve as input pins for Y signal.
I
—
Digital power supply
I
I
8-bit pixel data input pins/test data bus.
I
When control register bit “PIF MODE”=“0”, these input pins cannot be used.
I
When control register bit “PIF MODE”=“1”, serve as input pins for multiplexed Cb, Cr signals.
I
In the test mode, used for internal circuit test data bus.
I
The test mode is allowed to use only for device vendors.
I
I
—
Digital ground
O
Reference current output pin. Connect a resistor ×16 times (“16R”) of the output resistance value “R”
I
Voltage reference input pin. Sets the output full-scale value
—
Analog power supply
—
Analog ground
10-bit D/A converter output.
O
When control register bit “YC/YUV”=“1”, outputs the composite signal.
When control register bit “YC/YUV”=“0”, outputs the color difference (V) signal.
I
Connect to Vss with an approx. 0.1 µF capacitor
I
Connect to AVDD with an approx. 0.1 µF capacitor
—
Analog power supply
—
Analog ground
O
10 bit D/A converter output. (Luminance (Y) signal output.)
—
Analog power supply
—
Analog ground
10-bit D/A converter output.
O
When control register bit “YC/YUV”=“1”, outputs the chroma (C) signal.
When control register bit “YC/YUV”=“0”, outputs the color difference (U) signal.
Test data bus. In the test mode, used for internal circuit test data bus.
O
The test mode is allowed to use only for device vendors (Not used).
—
Digital power supply
O
Test data bus. In the test mode, used for internal circuit test data bus.
O
The test mode is allowed to use only for device vendors (Not used)
I
Test mode control input pin. Pulled-up.
I
When these pins are “H”, CXD1913Q is not in the test mode.
I
The test mode is allowed to use only for device vendors
—
Digital ground
I
Test mode reset input pin. During power on/reset, set to “L” for more than 40 clocks (SYSCLK) (Not used)
—
Digital power supply
I
Test mode control input pin. (Not used)
I
Description
— 64 —
Page 27
Pin No.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin Name
TCK
TDO
VSS
SI
SCK
XCS
XVRST
F1
VDD
XTEST4
XRST
SYSCLK
PDCLK
VSS
VSYNC
HSYNC
SO
FID
VDD
XIICEN
I/O
I
Test mode control input pin. Fix at “H”
O
Test data bus pin. (Not used)
—
Digital ground
Description
The functions of this pin are selected by Pin 64 XIICEN.
I
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes the SI serial data input pin.
When the XIICEN pin is “L”, sets into the I2C-BUS mode, and becomes the SDA input/output pin
The functions of this pin are selected by Pin 64 XIICEN.
I
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes the SCK serial clock input pin.
When the XIICEN pin is “L”, sets into the I2C-BUS mode, and becomes the SCL input pin
The functions of this pin are selected by Pin 64 XIICEN. Pulled-up.
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes the XCK chip select input pin.
I
When the XIICEN pin is “L”, sets into the I
2
C-BUS mode, and becomes the SA slave address selection input
signal which selects the I2C-BUS slave address
Active “L” vertical sync reset input pin. Pulled-up.
I
Used for synchronizing external vertical sync and internal vertical sync.
When XVRST is “L”, the internal digital sync generator is reset according to the F1 state
Field ID input pin.
When externally synchronizing with the XVRST signal, the field to be reset is determined by this signal.
I
“H” indicates the first field.
“L” indicates the second field
—
Digital power supply
Test mode control input pin. Pulled-up.
I
When these pins are “H”, CXD1913Q is not s test mode.
The test mode is allowed to use only for device vendors
System reset input pin when active “L”.
I
During power on/reset, set to “L” for more than 40 clocks (SYSCLK)
I
System clock input pin.
To generate the correct sub carrier frequency, precisely 27MHz is required
13.5MHz pixel data clock output pin. This clock is obtained by 1/2 frequency-dividing SYSCLK.
O
Used only in the 16-bit pixel data mode
—
Digital ground
O
V.sync signal output
O
H.sync signal output
The functions of this pin are selected by Pin 64 XIICEN.
O
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes the S0 serial-out output pin.
When the XIICEN pin is “L”, this pin is not used and sets into high impedance (Not used)
Field ID output.
O
When control register bit “FDS”=“1”, “L” indicates the first field and “H” indicates the second field.
When control register bit “FDS”=“0”, “H” indicates the first field and “L” indicates the second field
—
Digital power supply
Serial interface mode selection input pin. Pulled-up.
I
When “L”, Pins 48 to 50, and 61 set into the I
2
C-BUS mode.
When “H”, Pins 48 to 50, and 61 set into the SONY SOP mode
— 65 —
Page 28
• IC701 MECHANISM CONTROL (HD6433032SK12F)/VIDEO board
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13 to 20
21
22 to 29
30
31 to 35
36 to 39
40, 41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
Pin Name
CMD0
CMD1
CMD2
CMD3
SACK
QINT
VDAC-XLAT
DF-XLAT
P90/TXD
SUBQ
SQCK
VSS
D0 to D7
VCC
A0 to A7
VSS
A8 to A12
A13 to A16
A17, A18
A19
W AIT
MD0
MD1
φ
STBY
RESET
NM1
VSS
EXT AL
XT AL
VCC
AS
RD
WR
RESO
A VSS
TEST0
TEST1
TE
SENS
DA C-SELECT
NPIN
VSS
VREQ
VREF
I/O
I/O
Input/output terminal exchanging data bus 0 with IIC interface (IC901)
I/O
Input/output terminal exchanging data bus 1 with IIC interface (IC901)
I/O
Input/output terminal exchanging data bus 2 with IIC interface (IC901)
I/O
Input/output terminal exchanging data bus 3 with IIC interface (IC901)
O
Outputs command acknowledge to IIC interface (IC901)
O
Outputs command output pulses to IIC interface (IC901)
O
Serial data latch pulse output to Video D/A converter (IC401)
O
Serial data latch pulse output to Audio D/A converter (IC101)
—
Not used
I
Sub Q 80bit input (CXD2545Q)
O
SQSO readout clock output (CXD2545Q)
—
Ground
I/O
Data bus input/output (IC201, 751)
—
Connect to the power supply (+5V)
O
Address bus output (IC201, 751)
—
Ground
O
Address bus output (IC201, 751)
O
Address bus output (Not used)
O
Addres bus output (IC772)
O
Address bus output (Not used)
I
BUS control wait input (IC201)
I
Operation mode setting terminal (Connected to +5V)
I
Operation mode setting terminal (Connected to ground)
O
System clock output (Not used)
Shifts to the hardware standby mode when the standby terminal becomes “Low”.
I
(Unable to use H level fixed) (Connected to +5V)
I
Set into reset when the reset input pin becomes “Low”. (IC901)
I
Requests mask disable interruption. (Unable to use H level fixed) (Connected to +5V)
—
Ground
I
Connected to the Crystal oscillator. The EXTAL pin is also able to input external clocks. (10 MHz)
I
Connected to the Crystal oscillator. (10 MHz)
—
Power supply (+5V)
O
When the address strobe pin is “Low”, indicates that address outputs on the address bus are valid. (IC772)
O
When the read pin is “Low”, indicates that the external addresses space is in the read state. (IC201, 751)
When the read pin is “Low”, indicates that the external addresses space is in the write state and the data bus are
O
valid. (IC201, 751)
O
Reset output (Not used)
—
A/D converter (Pin62-69) ground
I
Color-bar test input (“L” = test)
I
AFADJ test input (“L” = test)
I
ADJ test input (“L” = test)
I
Internal state (SENSE) monitor input (CXD2545Q)
I
Audio D/A converter select mode setting terminal (Connected to +5V)
R6011-249-409-11CARBON2205%1/4W F
R6021-249-409-11CARBON2205%1/4W F
R6081-249-409-11CARBON2205%1/4W F
R6091-249-433-11CARBON22K5%1/4W
R6111-249-409-11CARBON2205%1/4W F
• RESISTORS
All resistors are in ohms.
METAL: metal-film resistor
METAL OXIDE: Metal Oxide-film resistor
F: nonflammable
• COILS
uH: µH
• SEMICONDUCTORS
In each case, u: µ, for example:
uA...: µA... , uPA... , µPA... ,
uPB... , µPB... , uPC... , µPC... ,
uPD..., µPD...
R4331-249-425-11CARBON4.7K5%1/4W F
R4341-249-425-11CARBON4.7K5%1/4W F
R4351-249-425-11CARBON4.7K5%1/4W F
R4361-249-417-11CARBON1K5%1/4W F
R4371-249-436-11CARBON39K5%1/4W
R4481-249-427-11CARBON6.8K5%1/4W F
R4491-249-429-11CARBON10K5%1/4W
R4501-249-425-11CARBON4.7K5%1/4W F
R4531-249-426-11CARBON5.6K5%1/4W
R4541-249-417-11CARBON1K5%1/4W F
R4551-247-840-00CARBON2.4K5%1/4W
R4561-249-421-11CARBON2.2K5%1/4W F
R4571-249-428-11CARBON8.2K5%1/4W F
R4591-249-433-11CARBON22K5%1/4W
(MY,SP,KR,HK,CH)
R4691-249-433-11CARBON22K5%1/4W
(MY,SP,KR,HK,CH)
R4701-249-425-11CARBON4.7K5%1/4W F
R4801-249-430-11CARBON12K5%1/4W
R7041-249-417-11CARBON1K5%1/4W F
R7051-249-438-11CARBON56K5%1/4W
R7061-249-417-11CARBON1K5%1/4W F
R7541-249-417-11CARBON1K5%1/4W F
R7551-249-438-11CARBON56K5%1/4W
R7561-249-417-11CARBON1K5%1/4W F
R8551-249-417-11CARBON1K5%1/4W F
R8591-249-417-11CARBON1K5%1/4W F
! R8611-212-853-00FUSIBLE6.85%1/4W F
! R8621-212-853-00FUSIBLE6.85%1/4W F
R1491-247-807-31CARBON1005%1/4W
R1501-247-807-31CARBON1005%1/4W
R1511-247-807-31CARBON1005%1/4W
R1521-247-807-31CARBON1005%1/4W
R1531-249-419-11CARBON1.5K5%1/4W F
R1541-249-419-11CARBON1.5K5%1/4W F
R1551-249-427-11CARBON6.8K5%1/4W F
R1561-249-427-11CARBON6.8K5%1/4W F
R1571-249-429-11CARBON10K5%1/4W
R1581-249-429-11CARBON10K5%1/4W
R1611-247-807-31CARBON1005%1/4W
R1621-247-807-31CARBON1005%1/4W
R4031-249-426-11CARBON5.6K5%1/4W
R4041-249-417-11CARBON1K5%1/4W F
R4051-247-840-00CARBON2.4K5%1/4W
R4061-249-421-11CARBON2.2K5%1/4W F
R4071-249-428-11CARBON8.2K5%1/4W F
R4091-249-433-11CARBON22K5%1/4W