Siemens TLE4279GL, TLE4279G, TLE4279A, TLE4279GM Datasheet
5-V Low-Drop Fixed Voltage Regulator
Features
• Output voltage tolerance ≤ ± 2 %
• Very low current consumption
• Early warning
V
• Reset output low down to
• Overtemperature protection
• Reverse polarity proof
• Settable reset threshold
• Very low-drop voltage
• Wide temperature range
Type Ordering Code Package
TLE 4279 A on request P-DIP-8-4
= 1 V
Q
TLE 4279
P-DIP-8-4
TLE 4279 G Q67006-A9225 P-DSO-8-1 (SMD)
▼ TLE 4279 GM Q67006-A9307 P-DSO-14-4 (SMD)
TLE 4279 GL Q67006-A9306 P-DSO-20-6 (SMD)
▼ New type
Functional Description
This device is a voltage regulator with a fixed 5-V output,
e.g. in a P-DSO-8-1 package. The maximum operating
voltage is 45 V. The output is able to drive a 150 mA
load. It is short circuit protected and the thermal
shutdown switches the output off if the junction
temperature is in excess of 150 °C. A reset signal is
V
generated for an output voltage of
< 4.6 V. The reset
Q
threshold voltage can be decreased by external
connection of a voltage divider. The reset delay time can
be set by an external capacitor. If the application
requires pull up resistors at the logic outputs (Reset,
Sense Out) the TLE 4269 with integrated resi stors can
P-DSO-8-1
P-DSO-20-6
P-DSO-14-4
be used. It is also possible to supervise the input voltage by using an integrated
comparator to give a low voltage warning.
Semiconductor Group 1 1998-11-01
Pin Configuration
(top view)
P-DIP-8-4 P-DSO-8-1
18
Ι Q
S
Ι
RE
AEP01813
SO72
R63
GNDD54
TLE 4279
1
Ι
2
ΙS
RE
3
D5
4
8
7
6
AEP01668
Q
SO
R
GND
Pin Definitions and Functions (TLE 4279 A and TLE 4279 G)
Pin No. Symbol Function
1I Input; block directly to GND on the IC with a ceramic capacitor.
2SISense input; if not needed connect to Q.
3REReset threshold; if not needed connect to ground.
4DReset delay; to select the delay time, connect to GND via
external capacitor.
5 GND Ground
6RReset output; open-collector output
7SOSense output; open-collector output
8Q5-V output; connect to GND with a 10 µF capacitor, ESR < 10 Ω.
Semiconductor Group 2 1998-11-01
Pin Configuration
(top view)
TLE 4279
P-DSO-20-6
RE
D
N.C.
GND
GND
GND
GND
N.C.
N.C.
R
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AEP01802
Ι
S
Ι
N.C.
GND
GND
GND
GND
N.C.
Q
SO
Pin Definitions and Functions (TLE 4279 GL)
Pin No. Symbol Function
1REReset threshold; if not needed connect to ground.
2DReset delay; to select delay time connect to GND via
external capacitor.
4-7, 14-17 GND Ground
10 R Reset output; open-collector output
11 SO Sense output; open-collector output
12 Q Output; connect to GND with 10 µF capacitor, ESR < 10 Ω
19 I Input; block directly to GND at the IC by a ceramic capacitor
20 SI Sense input; if not needed connect to Q
Semiconductor Group 3 1998-11-01
Pin Configuration
(top view)
TLE 4279
P-DSO-14-4
RE
GND
GND
GND
GND
114
2
D
3
4
5
6
R
7
13
12
11
10
9
8
AEP02254
SI
Ι
GND
GND
GND
Q
SO
Pin Definitions and Functions (TLE 4279 GM)
Pin No. Symbol Function
1REReset threshold; if not needed connect to GND
2DReset delay; connect to GND via external delay capacitor for
setting delay time
3, 4, 5, 6 GND Ground
7RReset output; open-collector output
8SOSense output; open-collector output
9Q5-V output; connect to GND with 10 µF capacitor, ESR < 10 Ω
10, 11, 12 GND Ground
13 I Input; block to ground directly at the IC by a ceramic capacitor
14 SI Sense input; if not needed connect to Q
Semiconductor Group 4 1998-11-01
TLE 4279
Circuit Description
The control amplifier compares a reference voltage, made highly accurate by resistance
balancing, with a voltage proportional to the output volta ge and drives the base of the
series PNP transistor via a bu ffer. Saturation control as a function of the load current
prevents any over-saturation of the power element.
In the reset generator block a comparator compares a reference voltage independent of
the input voltage with the scaled-down output voltage. If the output voltage reaches 4.6 V
the reset delay capacitor is discharged and the reset output is se t to low. This low is
guaranteed down to a n output voltage of 1 V. As the output voltage increases again,
from 4.6 V onward the reset delay capacitor is charged with constant current. When the
V
capacitor voltage reaches the upper switching threshold
choosing the val ue of this capacito r, the reset delay ti me can be selecte d over a wide
range. With the reset thre sho ld inp ut RE it i s pos sib le to lower the reset threshold
pin RE is connected to pin Q via a voltage divider, for examp le, the reset condition is
reached when this voltage is decreased below the switching threshold
, the reset returns to high. By
dt
V
V
of 1.35 V.
re
rt
. If
Another comparator compares the signal of the pin SI, normally fed by a voltage divider
from the input voltage, with the reference and gives an early warning on the pin SO. It is
also possible to superwise an other voltage e.g. of a second regulator, or to build a
watchdog circuit with few external components.
Application Description
C
The input capacitor
approx. 1 Ω in series wit h
capacitance can be damped. The output capacitor C
is necessary for compensating line influences. Using a resistor of
I
C
, the oscillating circuit consisting of input inductivity and input
I
is necessary for the stability of the
Q
regulating circuit. Stability is guaranteed at values ≥ 10 µF and an ESR ≤ 10 Ω within the
operating temperature range. Both reset output and sense output are open collector
outputs and have to be connected to 5 V output via external pull-up res istors ≥ 10 kΩ.
For small tolerances of the reset delay the spread of the capacitance of the delay
capacitor and its temperature coefficient should be noted.
Semiconductor Group 5 1998-11-01
TLE 4279
D
RE
Ι
Q
Error
Amplifier
Reference
Current and
Saturation
Control
Trimming
R
Reference
SO
SI
AEB01955
Block Diagram
Semiconductor Group 6 1998-11-01
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