Siemens HYB3118165BSJ-50, HYB3118165BSJ-60, HYB3118165BST-50, HYB3118165BST-60, HYB5118165BSJ-50 Datasheet

1M × 16-Bit Dynamic RAM
1k Refresh
(Hyper Page Mode-EDO)

Advanced Information

• 1 048 576 words by 16-bit organization

• 0 to 70 °C operating temperature

• Hyper Page Mode-EDO-operation

• Performance:

HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60

-50 -60

t
t
t
t
t

• Power Dissipation, Refresh & Addressing:

Power Supply 5 V ± 10 % 3.3 V ± 0.3 V
Addressing 10/10 10/10
Refresh 1024 cycles / 16 ms
Active 715 632 468 414 mW
TTL Standby 11 7.2 mW
CMOS Standby 5.5 3.6 mW

RAS access time 50 60 ns

RAC

CAS access time 13 15 ns

CAC

Access time from address 25 30 ns

AA

Read/Write cycle time 84 104 ns

RC

Hyper page mode (EDO) cycle time 20 25 ns

HPC

HYB5118165 HYB3118165

-50 -60 -50 -60

• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh and hidden refresh

• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible

• Plastic Package: P-SOJ-42-1 400 mil
P-TSOPII-50/44-1 400 mil

Semiconductor Group 1 1998-10-01

HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60

1M × 16 EDO-DRAM

The HYB 5(3)118165 are 16 MBit dynamic RAMs based on die revisions “G” & “F” and organized
as 1 048 576 words by 16-bits. The HYB 5(3)118165 utilizes a submicron CMOS silicon gate
process technology, as well as advanced circuit techniques to provide wide operating margins, both
internally and for the system user. Multiplexed address inputs permit the HYB 5(3)18165 to be
packaged in a standard SOJ-42 and TSOPII-50/44 plastic package with 400 mil width. These
packages provide high system bit densities and are compatible with commonly used automatic
testing and insertion equipment.

Ordering Information
Type Ordering Code Package Descriptions

HYB 5118165BSJ-50 Q67100-Q1107 P-SOJ-42-1 400 mil 5 V 50 ns EDO-DRAM
HYB 5118165BSJ-60 Q67100-Q1108 P-SOJ-42-1 400 mil 5 V 60 ns EDO-DRAM
HYB 3118165BSJ-50 on request P-SOJ-42-1 400 mil 3.3 V 50 ns EDO-DRAM
HYB 3118165BSJ-60 on request P-SOJ-42-1 400 mil 3.3 V 60 ns EDO-DRAM
HYB 5118165BST-50 on request P-TSOPII-50/44-1 400 mil 5 V 50 ns EDO-DRAM
HYB 5118165BST-60 on request P-TSOPII-50/44-1 400 mil 5 V 60 ns EDO-DRAM
HYB 3118165BST-50 on request P-TSOPII-50/44-1 400 mil 3.3 V 50 ns EDO-DRAM
HYB 3118165BST-60 on request P-TSOPII-50/44-1 400 mil 3.3 V 60 ns EDO-DRAM

Semiconductor Group 2 1998-10-01

Pin Names and Configuration

HYB 5(3)118165

Row Address Inputs A0 - A9
Column Address Inputs A0 - A9
Row Address Strobe RAS
Upper Column Address Strobe UCAS
Lower Column Address Strobe LCAS
Output Enable OE
Data Input/Output I/O1 - I/O16
Read/Write Input WE

HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60

1M × 16 EDO-DRAM

Power Supply V
Ground (0 V) V

CC

SS

Not Connected N.C.

P-SOJ-42-1 (400 mil)

V

1

CC

I/O1

2

I/O2

3
4

I/O3

5

I/O4

V

6

CC

7

I/O5

8

I/O6

9

I/O7
I/O8

10

N.C.

11

N.C.

12

WE

13

RAS

14

N.C.

15

N.C.

16

A0

17

A1

18

A2

19

A3 A4

20

V

21

CC

42

41
40
39
38
37
36
35
34
33
32

31
30
29
28
27
26
25
24
23
22

SPP02812

V

SS

I/O16
I/O15
I/O14
I/O13

V

SS

I/O12
I/O11
I/O10
I/O9
N.C.
LCAS
UCAS
OE
A9
A8
A7
A6
A5

V

SS

P-TSOPII-50/44-1 (400 mil)

V

1

CC

2

I/O1

3

I/O2
I/O3

4
5

I/O4

V

6

CC

I/O5

7

I/O6

8
9

I/O7
I/O8

10
11

N.C.

N.C.

15

N.C.

16

WE

17

RAS
A11 / N.C.
A10 / N.C.

A02221
A1
A2

V

CC

18
19
20

23
24
25

50
49
48
47
46
45
44
43
42
41
40

36
35
34
33
32
31
30
29
28
27
26

SPP03457

V

SS

I/O16
I/O15
I/O14
I/O13

V

SS

I/O12
I/O11
I/O10
I/O9
N.C.

N.C.
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4A3

V

SS

Semiconductor Group 3 1998-10-01

HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60

1M × 16 EDO-DRAM

WE
UCAS
LCAS

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

10

10

&

No.2 Clock

Generator

Column

Address

Buffers (10)

Refresh

Controller

Refresh

Counter (10)

10

Row

Address

Buffers (10)

10

I/O1 I/O2 I/O16

Data In

Buffer

16

Row

Decoder

...

....

10

.

.

.

1024

.

.

.

Data Out

Buffer

16

Column
Decoder

Sense Amplifier

I/O Gating

1024

...

16x

Memory Array

1024 x 1024 x

OE

16

...

16

RAS

No.1 Clock

Generator

Voltage Down

Generator

V

CC

V

CC

(internal)

SPB02826

Block Diagram for HYB 5118165BSJ

Semiconductor Group 4 1998-10-01

HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60

1M × 16 EDO-DRAM

Absolute Maximum Ratings

Operating temperature range ........................................................................................... 0 to 70 °C

Storage temperature range........................................................................................ – 55 to 150 °C

Input/output voltage (5 V versions)....................................................– 0.5 to min (VCC+ 0.5, 7.0) V

Input/output voltage (3.3 V versions).................................................– 0.5 to min (VCC+ 0.5, 4.6) V

Power supply voltage (5 V versions) ....................................................................... – 1.0 V to 7.0 V

Power supply voltage (3.3 V versions) .................................................................... – 1.0 V to 4.6 V

Power dissipation (5 V versions) .............................................................................................1.0W

Power dissipation (3.3 V versions) ..........................................................................................0.5 W

Data out current (short circuit) ................................................................................................50mA

Note: Stresses above those listed under“Absolute Maximum Ratings” may cause permanent

damage of the device. Exposure to absolute maximum rating conditions for extended periods
may

affect device reliability.

DC Characteristics

T

= 0 to 70 °C, VSS = 0 V, tT = 2 ns

A

Parameter Symbol Limit Values Unit Test

min. max.

Condition

5 V Versions

Power supply voltage V
Input high voltage V
Input low voltage V
Output high voltage (I
Output low voltage (I

= – 5 mA) V

OUT

= 4.2 mA) V

OUT

CC

IH

IL

OH

OL

4.5 5.5 V

2.4 VCC+ 0.5 V
– 0.5 0.8 V

2.4 – V
– 0.4 V

1

1

1

1

3.3 V Versions

Power supply voltage V
Input high voltage V
Input low voltage V
TTL Output high voltage (I
TTL Output low voltage (I
CMOS Output high voltage (I
CMOS Output low voltage (I

= – 2 mA) V

OUT

= 2 mA) V

OUT

= – 100 µA) V

OUT

= 100 µA) V

OUT

CC

IH

IL

OH

OL

OH

OL

3.0 3.6 V

2.0 VCC+ 0.5 V
– 0.5 0.8 V

2.4 – V
– 0.4 V

V

– 0.2 – V

CC

– 0.2 V

1

1

1

1

Semiconductor Group 5 1998-10-01

HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60

1M × 16 EDO-DRAM

DC Characteristics (cont’d)

T

= 0 to 70 °C, VSS = 0 V, tT = 2 ns

A

Parameter Symbol Limit Values Unit Notes

min. max.

Common Parameters

Input leakage current
(0 V ≤ VIH≤ VCC + 0.3 V, all other pins = 0 V)

Output leakage current
(DO is disabled, 0 V ≤ V

≤ VCC+ 0.3 V)

OUT

Average VCC supply current

-50 ns version

-60 ns version

(RAS, CAS, address cycling: tRC = t

RC MIN.

)
Standby VCC supply current (RAS = CAS = VIH) I
Average VCC supply current, during RAS-only refresh

cycles -50 ns version

-60 ns version

(RAS cycling, CAS = VIH, tRC = t

RC MIN.

)

Average VCC supply current, during hyper page mode
(EDO) -50 ns version

-60 ns version

(RAS = VIL, CAS, address cycling: tPC = t

PC MIN.

)

Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)

I

I

I

I

I

I

I(L)

O(L)

CC1

CC2

CC3

CC4

CC5

– 10 10 µA

– 10 10 µA

–
–

130
115mAmA

– 2 mA –

–
–

–
–

130
115mAmA

50
40

mA
mA

–1mA

1

1

2, 3, 4
2, 3, 4

2, 4
2, 4

2, 3, 4
2, 3, 4

1

Average VCC supply current, during CAS-before-RAS
refresh mode -50 ns version

-60 ns version

(RAS, CAS cycling: tRC = t

RC MIN.

)

I

CC6

–
–

130
115mAmA

2, 4
2, 4

Semiconductor Group 6 1998-10-01

HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60

1M × 16 EDO-DRAM

Capacitance

T

= 0 to 70 °C, f = 1 MHz

A

Parameter Symbol Limit Values Unit

min. max.

Input capacitance (A0 to A11) C
Input capacitance (RAS, UCAS, LCAS, WE, OE) C
I/O capacitance (I/O1 - I/O16) C

AC Characteristics

T

= 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns

A

5, 6

I1

I2

IO

–5pF
–7pF
–7pF

Parameter Symbol Limit Values Unit Note

-50 -60

min. max. min. max.

Common Parameters

Random read or write cycle time t
RAS precharge time t
RAS pulse width t
CAS pulse width t
Row address setup time t
Row address hold time t
Column address setup time t
Column address hold time t
RAS to CAS delay time t
RAS to column address delay t
RAS hold time t
CAS hold time t
CAS to RAS precharge time t
Transition time (rise and fall) t
Refresh period for 1k-refresh version t

RC

RP

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

RSH

CSH

CRP

T

REF

84 – 104 – ns
30 – 40 – ns
50 10k 60 10k ns
8 10k 10 10k ns
0–0–ns
8 – 10 – ns
0–0–ns
8 – 10 – ns
12 37 14 45 ns
10 25 12 30 ns
13 – 15 – ns
40 – 50 – ns
5–5–ns
1 50 1 50 ns
– 16 – 16 ms

7

Read Cycle

Access time from RAS t
Access time from CAS t
Access time from column address t
OE access time t

RAC

CAC

AA

OEA

– 50 – 60 ns
– 13 – 15 ns
– 25 – 30 ns
– 13 – 15 ns

8, 9

8, 9

8, 10

Semiconductor Group 7 1998-10-01

HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60

1M × 16 EDO-DRAM

AC Characteristics (cont’d)

T

= 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns

A

5, 6

Parameter Symbol Limit Values Unit Note

-50 -60

min. max. min. max.

Column address to RAS lead time t
Read command setup time t
Read command hold time t
Read command hold time referenced to RAS t
CAS to output in low-Z t
Output buffer turn-off delay t
Output turn-off delay from OE t
Data to CAS low delay t
Data to OE low delay t
CAS high to data delay t
OE high to data delay t

RAL

RCS

RCH

RRH

CLZ

OFF

OEZ

DZC

DZO

CDD

ODD

25 – 30 – ns
0–0–ns
0–0–ns
0–0–ns
0–0–ns
0 13 0 15 ns
0 13 0 15 ns
0–0–ns
0–0–ns
10 – 13 – ns
10 – 13 – ns

11

11

8

12

12

13

13

14

14

Write Cycle

Write command hold time t
Write command pulse width t
Write command setup time t
Write command to RAS lead time t
Write command to CAS lead time t
Data setup time t
Data hold time t

Read-Modify-Write Cycle

Read-write cycle time t
RAS to WE delay time t
CAS to WE delay time t
Column address to WE delay time t
OE command hold time t

WCH

WP

WCS

RWL

CWL

DS

DH

RWC

RWD

CWD

AWD

OEH

8 – 10 – ns
8 – 10 – ns
0–0–ns
8 – 10 – ns
8 – 10 – ns
0–0–ns
8 – 10 – ns

113 – 138 – ns
64 – 77 – ns
27 – 32 – ns
39 – 47 – ns
10 – 13 – ns

15

16

16

15

15

15

Hyper Page Mode (EDO) Cycle

Hyper page mode (EDO) cycle time t
CAS precharge time t

HPC

CP

20 – 25 – ns
8 – 10 – ns

Semiconductor Group 8 1998-10-01