Siemens HYB3118160BSJ-70, HYB3118160BST-50, HYB3118160BST-60, HYB3118160BST-70, HYB3116160BST-70 Datasheet

1M x 16-Bit Dynamic RAM
(1k & 4k -Refresh)

HYB3116160BSJ/BST(L)-50/-60/-70
HYB3118160BSJ/BST(L)-50/-60/-70

Advanced Information

• 1 048 576 words by 16-bit organization

• 0 to 70 °C operating temperature

• Performance:

-50 -60 -70

t

RAC

t

CAC

t

AA

t

RC

t

PC

• Single + 3.3 V (± 0.3 V) supply

• Low power dissipation

RAS access time 50 60 70 ns
CAS access time 13 15 20 ns
Access time from address 25 30 35 ns
Read/Write cycle time 90 110 130 ns
Fast page mode cycle time 35 40 45 ns

max. 720 active mW ( HYB3118160BSJ/BST-50)
max. 648 active mW ( HYB3118160BSJ/BST-60)
max. 576 active mW ( HYB3118160BSJ/BST-70)
max. 360 active mW ( HYB3116160BSJ/BST-50)
max. 324 active mW ( HYB3116160BSJ/BST-60)
max. 288 active mW ( HYB3116160BSJ/BST-70)

7.2 mW standby (LV-TTL)

3.6 mW standby (LV-CMOS)
720 µW standby for L-version

• Output unlatched at cycle end allows two-dimensional chip selection

• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,

self refresh

• Fast page mode capability

• 2 CAS / 1 WE

• All inputs, outputs and clocks fully LV-TTL-compatible

• 1024 refresh cycles / 16 ms for HYB 3118160BSJ

• 4096 refresh cycles / 64 ms for HYB 3116160BSJ

• Plastic Package: P-SOJ-42-1 400 mil

P-TSOPII-50/44-1 400mil

Semiconductor Group 1 1.96

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

The HYB 3116(8)160BSJ/BST is a 16 MBit dynamic RAM organized as 1 048 576 words by 16 bits.
The HYB 3116(8)160BSJ/BST utilizes a submicron CMOS silicon gate process technology, as well
as advanced circuit techniques to provide wide operating m argins, both internally and for the system
user. Multiplexed address inputs permit the HYB 3116(8)160BSJ/ BST to be packaged in standard
SOJ-42 and TSOPII-50/44 plastic package with 400mil width. These packages provide high s ystem
bit densities and are compatible with commonl y used automatic testing and insertion equipment.
System-oriented features include single + 3.3 V (± 0.3 V) power su pply, direct interfac ing with high­performance logic device families.The HYB3116160BSTL parts have a very low power „sleep
mode“ suppported by Self Refresh.

Ordering Information
Type Ordering Code Package Descriptions

HYB 3116160BSJ-50 on request P-SOJ-42 400 mil DRAM (access time 50 ns)
HYB 3116160BSJ-60 on request P-SOJ-42 400 mil DRAM (access time 60 ns)
HYB 3116160BSJ-70 on request P-SOJ-42 400 mil DRAM (access time 70 ns)
HYB 3118160BSJ-50 on request P-SOJ-42 400 mil DRAM (access time 50 ns)
HYB 3118160BSJ-60 on request P-SOJ-42 400 mil DRAM (access time 60 ns)
HYB 3118160BSJ-70 on request P-SOJ-42 400 mil DRAM (access time 70 ns)
HYB 3116160BST-50 on request P-TSOPII-50/44 400 mil DRAM (access time 50 ns)
HYB 3116160BST-60 on request P-TSOPII-50/44 400 mil DRAM (access time 60 ns)
HYB 3116160BST-70 on request P-TSOPII-50/44 400 mil DRAM (access time 70 ns)
HYB 3118160BST-50 on request P-TSOPII-50/44 400 mil DRAM (access time 50 ns)
HYB 3118160BST-60 on request P-TSOPII-50/44 400 mil DRAM (access time 60 ns)
HYB 3118160BST-70 on request P-TSOPII-50/44 400 mil DRAM (access time 70 ns)

Pin Names

A0 to A9 Row Address Inputs for 1k-refresh version HYB3118160BSJ/BST
A0 to A9 Column Addess Inputs for 1k-refresh version HYB3118160BSJ/BST
A0 to A11 Row Address Inputs for 4k-refresh version HYB3116160BSJ/BST
A0 to A7 Column Address Inputs for 4k-refresh version HYB3116160BSJ/BST
RAS
OE
I/O1-I/O16 Data Input/Output
UCAS
LCAS
WE

V

CC

V

SS

N.C. not connected

Row Address Strobe
Output Enable

Upper Column Address Strobe
Lower Column Address Strobe
Read/Write Input
Power Supply (+ 3.3 V)
Ground (0 V)

Semiconductor Group 2

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
N.C.
N.C.
WE
RAS

A11/NC
A10/NC

A0
A1
A2
A3
Vcc

P-SOJ-42 (400 mil)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
N.C.
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
Vss

Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
N.C.

N.C.
N.C.
WE
RAS

A11/N.C.
A10.N.C.

A0
A1
A2
A3
Vcc

P-TSOPII-50/44 (400mil)

1
2
3
4
5
6
7
8
9
10
11

15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40

36
35
34
33
32
31
30
29
28
27
26

Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
N.C.

N.C.
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
Vss

*) A11 and A10 are not connected for HYB3118160BSJ/BST (1k-refresh version)

Truth Table
RAS

H

L

L

L

L

L

L

L

LCAS UCAS WE OE I/O1-I/O8 I/O9-I/O16 Operation

H

H

L

H

L

L

H

L

H

H

H

L

L

H

L

L

H

H

H

H

H

L

L

L

H

H

L

L

L

H

H

H

High-Z

High-Z

Dout

High-Z

Dout

Din

Don't care

Din

High-Z

High-Z

High-Z

Dout

Dout

Don't care

Din

Din

Standby

Refresh

Lower byte read

Upper byte read

Word read

Lower byte write

Upper byte write

Word write

L

L

L

H

H

High-Z

Semiconductor Group 3

High-Z

NOP

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

WE

UCAS
LCAS

A0

A1

A2
A3
A4
A5
A6
A7
A8
A9

A10
A11

.

&

.

No. 2 Clock

Generator

Column

8

12 12

Address

Buffer(8)

Refresh

Controller

Refresh

Counter (12)

Row

Address

Buffers(12)

12

I/O1 I/O2

Data in
Buffer

Row

Decoder

16

8

4096

I/O16

Data out

Buffer

16

Column

Decoder

Sense Amplifier

I/O Gating

256

x16

Memory Array

4096x256x16

OE

16

RAS

Block Diagram for HYB 3116160BSJ

Semiconductor Group 4

No. 1 Clock

Generator

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

WE

UCAS
LCAS

A0

A1

A2
A3
A4
A5
A6
A7
A8
A9

.

10

.

No. 2 Clock

Generator

Column
Buffer(10)

Controller

Counter (10)

&

Address

Refresh

Refresh

10

I/O1 I/O2

Data in
Buffer

16

10

Sense Amplifier

I/O16

Data out

Buffer

16

Column

Decoder

I/O Gating

1024

x16

OE

16

Row

10 10

RAS

Block Diagram for HYB 3118160BSJ

Semiconductor Group 5

Address

Buffers(10)

No. 1 Clock

Generator

Row

Decoder

1024

Memory Array

1024x1024x16

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

Absolute Maximum Ratings

Operating temperature range .......................................... ............ ............ ................... .......0 to 70 °C

Storage temperature range.................................... ........ ........ ........ ........ ........... ........ ..– 55 to 150 °C

Soldering time..................................................................................................................... ........10 s

Input/output volt age..................... .... .. .... .... .... .... .... .. .... .... .... .... .. .... .... .... .-0.5 to min (Vcc+0.5,4.6) V

Power supply voltage....................... .............. .............. ............ .............. ................... ..-0.5 V to 4.6 V

Power dissipation..................... ...... ...... .... ...... ...... ...... ...... ...... ...... .... ...... ......... ...... ...... ...... .... ...1.0 W

Data out current (short circuit)................................................................................................50 mA

Note:

Stresses above those list ed under “Absolute M aximum Ratings ” ma y cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

DC Characteristics (values in brackets for HYB3116160BSJ)

T

= 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 5 ns

A

Parameter Symbol Limit Values Unit Test

mA
mA
mA

Condition

1)

1)

1)

1)

1)

1)

1)

1)

2) 3) 4)

2) 3) 4)

2) 3) 4)

Input high voltage
Input low voltage V
TTL Output high voltage (I
TTL Output low voltage (I
CMOS Output high voltage (I
CMOS Output low voltage (I

= – 2 mA) V

OUT

= 2 mA) V

OUT

= – 100 µA) V

OUT

= 100 µA) V

OUT

Input leakage current,any input
(0 V ≤

V

≤ Vcc + 0.3V, all other pins = 0 V)

IH

Output leakage current

V

(DO is disabled, 0 V ≤

≤ Vcc + 0.3V)

OUT

Average VCC supply current:

-50 ns version

-60 ns version

-70 ns version

V

I

I

I

IH

IL

OH

OL

OH

OL

I(L)

O(L)

CC1

min. max.

2.0 Vcc+0.5 V
– 0.5 0.8 V

2.4 – V
– 0.4 V
Vcc-0.2 – V
– 0.2 V
– 10 10 µA

– 10 10 µA

–
–
–

200(100)
180 (90)
160 (80)

(RAS

, CAS, address cycling, tRC = tRC min.)

Standby VCC supply current (RAS =CAS= VIH) I

Semiconductor Group 6

CC2

–2mA–

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

DC Characteristics (values in brackets for HYB3116160BSJ)

T

= 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 5 ns

A

(cont’d)

Parameter Symbol Limit Values Unit Test

mA
mA
mA

mA
mA
mA

Condition

2) 4)

2) 4)

2) 4)

2) 3) 4)

2) 3) 4)

2) 3) 4)

1)

1)

Average

V

supply current, during RAS-only

CC

refresh cycles: -50 ns version

-60 ns version

-70 ns version

(RAS

cyc ling: CAS = VIH, tRC = tRC min.)

Average VCC supply current,
during fast page mode: -50 ns version

-60 ns version

-70 ns version

(RAS

= VIL, CAS, address cycling, tPC = t

PC

min.)

Standby VCC supply current

= CAS = VCC – 0.2 V)

(RAS
Standby VCC supply current (L-version)

(RAS

= CAS = VCC – 0.2 V)

I

I

I

I

CC3

CC4

CC5

CC5

min. max.

–
–
–

–
–
–

200(100)
180 (90)
160 (80)

55 (40)
50 (35)
45 (30)

–1mA

– 200 µA

Average VCC supply current, during CAS­before-RAS refresh mode: -50 ns version

-60 ns version

-70 ns version

(RAS

, CAS cycling, tRC = t

RC

min.)

Average Self Refresh Current

(CBR cycle with tRAS>TRASSmin., CAS held low,

=Vcc-0.2V, Address and Din=Vcc--0.2V or 0.2V)

WE

I

I

CC6

CC7

–
–
–

200(100)
180 (90)
160 (80)

_1

250

2) 4)

mA

2) 4)

mA

2) 4)

mA

mA
µA L-version

Capacitance

T

= 0 to 70 °C,VCC = 3.3 V ± 0.3 V, f = 1 MHz

A

Parameter Symbol Limit Values Unit

min. max.

Input capacitance (A0 to A11)
Input capacitance (RAS

, UCAS, LCAS, WE, OE) C

I/O capacitance (I/O1-I/O16)

C

I1

I2

C

IO

–5pF
–7pF
–7pF

Semiconductor Group 7

HYB3116(8)160BSJ/BST(L)-50/-60/-70

3.3V 1M x 16-DRAM

AC Characteristics

T

= 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 5 ns

A

Parameter

5)6)

Symbol

common parameters

Random read or write cycle time t

precharge time t

RAS

pulse width t

RAS

pulse width t

CAS
Row address setup time t
Row address hold time t
Column address setup time t
Column address hold time t

to CAS delay time t

RAS

to column address delay

RAS

t

RC

RP

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

time

Limit Values

Unit Note

-50 -60 -70

min. max. min. max. min. max.

90 – 110 – 130 – ns
30 – 40 – 50 – ns
50 10k 60 10k 70 10k ns
13 10k 15 10k 20 10k ns
0–0–0–ns
8 – 10 – 10 – ns
0–0–0–ns
10 – 15 – 15 – ns
18 37 20 45 20 50
13 25 15 30 15 35 ns

16F

hold time t

RAS

hold time t

CAS

to RAS precharge time t

CAS
Transition time (rise and fall) t
Refresh period for HYB3118160 t
Refresh period for HYB3116160 t
Refresh period for L-versions t

Read Cycle

Access time from RAS t
Access time from CAS
Access time from colum n address t

access time t

OE
Column address to RAS

lead time t
Read command setup time t
Read command hold time t
Read command hold time

referenced to RAS

t

t

RSH

CSH

CRP

T

REF

REF

REF

RAC

CAC

AA

OEA

RAL

RCS

RCH

RRH

13 15 – 20 – ns
50 60 – 70 – ns
5–5–5–ns
350350350ns7
– 16 – 16 – 16 ms
– 64 – 64 – 64 ms
– 256 – 256 – 256 ms

– 50 – 60 – 70 ns 8, 9
– 13 – 15 – 20 ns 8, 9
– 25 – 30 – 35 ns 8,10
– 13 – 15 – 20 ns
25 – 30 – 35 – ns
0–0–0–ns
0–0–0–ns11
0–0–0–ns11

Semiconductor Group 8