Samsung S3C8639, S3C863A, S3P863A Datasheet
S3C8639/C863A/P863A PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide
range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned
to specific interrupt levels.
S3C8639/C863A/P863A MICROCONTROLLERS
S3C8639/C863A/P863A single-chip 8-bit
microcontrollers are based on the powerful SAM8
CPU architecture. The internal register file is logically
expanded to increase the on-chip register space.
S3C8639/C863A/P863A contain 32/48 Kbytes of onchip program ROM.
In line with Samsung's modular design approach, the
following peripherals are integrated with the SAM8
core:
— Four programmable I/O ports (total 27 pins)
— One 8-bit basic timer for oscillation stabilization
and watchdog functions
— One 8-bit general-purpose timer/counter with
selectable clock sources
— One interval timer
OTP
S3C8639/C863A microcontrollers are also available in OTP (One Time Programmable) version named,
S3P863A. S3P863A microcontroller has an on-chip 48-Kbyte one-time-programmable EPROM instead of
masked ROM. S3P863A is comparable to S3C8639/C863A, both in function and pin configuration except its
ROM size.
— One 12-bit counter with selectable clock sources,
including Hsync or Csync input
— PWM block with seven 8-bit PWM circuits
— Sync processor block (for Vsync and Hsync I/O,
Csync input, and Clamp signal output)
— DDC Multi-master and slave-only IIC-Bus
— 4-channel A/D converter (8-bit resolution)
S3C8639/C863A/P863A are a versatile
microcontrollers which are ideal for use in multi-sync
monitors or in general-purpose applications that
require sophisticated timer/counter, PWM, sync
signal processing, A/D converter, and multi-master
IIC-bus support with DDC. They are available in a
42-pin SDIP or a 44-pin QFP package.
1-1
PRODUCT OVERVIEW S3C8639/C863A/P863A
FEATURES
CPU
• SAM88RC CPU core
Memory
• S3C8639: 32-Kbyte internal program memory
(ROM)
S3C863A: 48-Kbyte internal program memory
(ROM)
• S3C8639: 784-byte general-purpose
register area
S3C863A: 1040-byte general-purpose
register area
Instruction Set
• 78 instructions
• IDLE and STOP instructions added for
power-down modes
Instruction Execution Time
• Minimum 333 ns (with 12 MHz CPU clock)
Interrupts
• Ten interrupt sources/vectors
• Eight interrupt level
• Fast interrupt feature
General I/O
• Four I/O Ports (total 27pins)
8-Bit Basic Timer
• Programmable timer for oscillation stabilization
interval control or watchdog timer function
• Three selective internal clock frequencies
Low Voltage Reset (LVR)
• LVR level is 2.4 V ± 200 mV
Pulse Width Modulator (PWM)
• 8-bit PWM: 7-CH
(6-bit basic frame with 2-bit extension)
Sync-Processor Block
• Vsync-I, Hsync-I, Csync-I input and Vsync-O,
Hsync-O, Clamp-O output pins
• Programmable Pseudo sync signal generation
• Auto SOG detection
• Auto H-/V-sync polarity detection
• Composite sync detection
DDC Multi-Master IIC-Bus 1-Ch
• Serial Peripheral Interface
• Support for Display Data Channel
(DDC1/DDC2B/DDC2Bi/DDC2B+)
Slave Only IIC-Bus 1-Ch
• Serial Peripheral Interface
A/D Converter
• 4-channel; 8-bit resolution
Oscillator Frequency
• 8 MHz to 12 MHz crystal operation
• Internal Max. 12 MHz CPU clock
Operating Temperature Range
• – 40 °C to + 85 °C
Timer/Counters
• One 8-bit Timer/Counter with several clock
sources (Capture mode)
• One 12-bit Counter with H-/C-sync and several
clock sources
• One Interval Timer
1-2
Operating Voltage Range
• 3.0 V to 5.5 V
Package Types
• 42-pin SDIP, 44-pin QFP
S3C8639/C863A/P863A PRODUCT OVERVIEW
BLOCK DIAGRAM
X
X
OUT
PWM0
PWM6
Vsync-I
Hsync-I
Csync-I
Vsync-O
Hsync-O
Clamp-O
TM0CAP
P0.0-P0.7/INT0-INT2
RESET
Port 0
INT0-INT2
IN
Main
Osc
P2.0-P2.7
Port 2
V
DD1
V
SS1
TEST
Port 1
, V
, V
DD2
SS2
P1.0-P1.2
I/O Port and Interrupt
Control
8-Bit
PWM
(7-Ch)
Port 3
P3.0-P3.7
SAM8 CPU
Sync-
Processor
8-Bit
Counter
(Timer M0)
32/48-
Kbyte
ROM
784/1040-
Byte
Register File
ADC
Slave
Only
IIC-Bus
AD0-AD3
SCL1
SDA1
* S3C8639
- 32 Kbyte ROM
- 784 Byte RAM
* S3C863A
- 48 Kbyte ROM
- 1040 Byte RAM
12-Bit
Counter
(Timer M1)
Interval
Timer
(Timer M2)
Figure 1-1. Block Diagram
Multi-master IIC-Bus
and DDC1/2B/2Bi/2B+
SCL0 SDA0
1-3
PRODUCT OVERVIEW S3C8639/C863A/P863A
PIN ASSIGNMENTS
P3.7
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.4/TM0CAP
TEST (GND)
P0.3
P0.5
P0.6
P0.7
P1.0/SDA1
P1.1/SCL1
V
DD1
V
SS1
X
OUT
X
SDA0
SCL0
RESET
P1.2
P2.0/PWM0
P2.1/PWM1
1
2
3
4
5
6
7
8
9
10
11
12
13
IN
14
15
16
17
18
19
20
21
S3C8639
/C863A
(42-SDIP)
42
P3.6
41
P3.5
40
P3.4
39
P3.3/AD3
38
P3.2/AD2
37
P3.1/AD1
36
P3.0/AD0
35
V
34
33
32
31
30
29
28
27
26
25
24
23
22
DD2
V
SS2
P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2
1-4
NOTE: The TEST pin must connect to VSS (GND) in the normal operation mode.
Figure 1-2. S3C8639/C863A 42-SDIP Pin Assignment
S3C8639/C863A/P863A PRODUCT OVERVIEW
P0.4/TM0CAP
P0.3
P0.2/INT2
P0.1/INT1
N.C.
P0.0/INT0
P3.7
P3.6
P3.5
P3.4
P3.3/AD3
4443424140393837363534
P0.5
P0.6
P0.7
P1.0/SDA1
P1.1/SCL1
DD1
V
V
SS1
OUT
X
X
TEST (GND)
SDA0
1
2
3
4
5
6
7
8
IN
9
S3C8639
/C863A
44-QFP
(Top View)
10
11
33
32
31
30
29
28
27
26
25
24
23
P3.2/AD2
P3.1/AD1
P3.0/AD0
DD2
V
V
SS2
P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
Clamp-O
1213141516171819202122
SCL0
RESET
P1.2
N.C.
P2.0/PWM0
P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5
P2.6/PWM6
NOTE: The TEST pin must connect to VSS (GND) in the normal operation mode.
Figure 1-3. S3C8639/C863A 44-QFP Pin Assignment
1-5
PRODUCT OVERVIEW S3C8639/C863A/P863A
PIN DESCRIPTIONS
Table 1-1. S3C8639/C863A Pin Descriptions
Pin
Names
P0.0
P0.1
P0.2
P0.3
P0.4
Pin
Type
Description
I/O General-purpose, 8-bit I/O port. Shared
functions include three external interrupt inputs
and I/O for timer M0. Selective configuration of
port 0 pins to input or output mode is
supported.
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
I/O General-purpose, 8-bit I/O port. Selective
configuration is available for port 1 pins to
input, push-pull output, n-channel open-drain
mode, or IIC-bus clock and data I/O.
P2.0
P2.1
P2.2
P2.3
P2.4
I/O General-purpose, 8-bit I/O port Selective
configuration of port 2 pins to input or output
mode is supported. The port 2 pin circuits are
designed to push-pull PWM output and Csync
(SOG) signal input.
P2.5
P2.6
P2.7
P3.0–P3.3
P3.4–P3.7
I/O General-purpose, 8-bit I/O port Selective
configuration port 3 pins to input or output
mode is supported. Multiplexed for alternative
use as A/D converter inputs AD0–AD3.
Hsync-I
Vsync-I
Clamp-O
Hsync-O
Vsync-O
SDA0
SCL0
V
, V
DD1
V
, V
DD2
XIN, X
OUT
RESET
SS1
SS2
,
I
The pins are sync processor signal I/O and IIC-
I
bus clock and data I/O.
O
O
O
I/O
I/O
– Power pins –
– System clock I/O pins – 14, 13 –
I System RESET pin B 18 –
TEST I Factory test pin input
0 V: Normal operation, 5 V: Factory test mode
Pin
Circuit
Type
D-1
D-1
D-1
D-1
D-1
D-1
D-1
D-1
E-1
E-1
E-1
D-1
D-1
D-1
D-1
E-1
E-1
E-1
D-1
E-1
E
A-3
A-3
A
A
A
G-3
G-3
SDIP Pin
Numbers
1
2
3
4
5
6
7
8
9
10
19
20
21
22
23
24
25
26
32
35–38
39–42
31
30
27
28
29
16
17
11, 12
–
34, 33
– 15 –
Shared
Functions
INT0
INT1
INT2
TM0CAP
SDA1
SCL1
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Csync-I
AD0–AD3
–
–
1-6
S3C8639/C863A/P863A PRODUCT OVERVIEW
PIN CIRCUITS DIAGRAM
DD
V
VDD
Data
Output
VSS
Figure 1-4. Pin Circuit Type A
VDD
280 k
Ω
RESET
Noise
Filter
Input
Figure 1-5. Pin Circuit Type A-3
Data or
Other
Function
Output
Disable
Digital Input,
TTL Input
Output
300 k
Ω
Typical
SS
V
VSS
DD
V
Output
VSS
Figure 1-6. Pin Circuit Type B (RESET)
NOTE: The noise filter must be built in the
external interrupts.
Figure 1-7. Pin Circuit Type D-1
1-7
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