Samsung M393B2G70DB0-YK0 User Manual
Preliminary
240pin Registered DIMM
based on 4Gb D-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
Rev. 0.6, Apr. 2013
M393B2G70DB0
M393B4G70DM0
1.35V
CAUTION :
This document includes some items still under discussion in JEDEC.
Therefore, those may be changed without pre-notice based on JEDEC progress.
In addition, it is highly recommended that you not send specs without Samsung’s permission.
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or otherwise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2013 Samsung Electronics Co., Ltd. All rights reserved.
- 1 -
Preliminary
Rev. 0.6
Registered DIMM
datasheet DDR3L SDRAM
Revision History
Revision No. History Draft Date Remark Editor
0.5 - Preliminary SPEC. Release Jul. 2012 - J.Y.Lee
0.6 - Update TBD based on JESD79-3F Apr. 2013 - S.H.Kim
- Delete product line-up (4GB, 8GB)
- 2 -
Preliminary
Rev. 0.6
Registered DIMM
datasheet DDR3L SDRAM
Table Of Contents
240pin Registered DIMM based on 4Gb D-die
1. DDR3L Registered DIMM Ordering Information ...........................................................................................................4
2. Key Features.................................................................................................................................................................4
3. Address Configuration ..................................................................................................................................................4
4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................5
5. Pin Description .............................................................................................................................................................6
6. ON DIMM Thermal Sensor ...........................................................................................................................................6
7. Input/Output Functional Description..............................................................................................................................7
8. Pinout Comparison Based On Module Type.................................................................................................................8
9. Registering Clock Driver Specification..........................................................................................................................9
9.1 Timing & Capacitance values .................................................................................................................................. 9
9.2 Clock driver Characteristics.....................................................................................................................................9
10. Function Block Diagram:.............................................................................................................................................10
10.1 16GB, 2Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)....................................................................10
10.2 32GB, 4Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs)....................................................................12
11. Absolute Maximum Ratings ........................................................................................................................................17
11.1 Absolute Maximum DC Ratings............................................................................................................................. 17
11.2 DRAM Component Operating Temperature Range ..............................................................................................17
12. AC & DC Operating Conditions...................................................................................................................................17
12.1 Recommended DC Operating Conditions .............................................................................................................17
13. AC & DC Input Measurement Levels ..........................................................................................................................18
13.1 AC & DC Logic Input Levels for Single-ended Signals..........................................................................................18
13.2 V
13.3 AC and DC Logic Input Levels for Differential Signals ..........................................................................................21
13.3.1. Differential Signals Definition ......................................................................................................................... 21
13.3.2. Differential Swing Requirement for Clock (CK -
13.3.3. Single-ended Requirements for Differential Signals ......................................................................................23
13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 24
13.4 Slew Rate Definition for Single Ended Input Signals.............................................................................................25
13.5 Slew rate definition for Differential Input Signals ................................................................................................... 25
14. AC & DC Output Measurement Levels .......................................................................................................................25
14.1 Single Ended AC and DC Output Levels...............................................................................................................25
14.2 Differential AC and DC Output Levels ................................................................................................................... 25
14.3 Single-ended Output Slew Rate ............................................................................................................................ 26
14.4 Differential Output Slew Rate ................................................................................................................................ 27
15. IDD specification definition..........................................................................................................................................28
16. IDD SPEC Table .........................................................................................................................................................30
17. Input/Output Capacitance ...........................................................................................................................................31
18. Electrical Characteristics and AC timing .....................................................................................................................32
18.1 Refresh Parameters by Device Density................................................................................................................. 32
18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................32
18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................32
18.3.1. Speed Bin Table Notes .................................................................................................................................. 35
19. Timing Parameters by Speed Grade ..........................................................................................................................36
19.1 Jitter Notes ............................................................................................................................................................39
19.2 Timing Parameter Notes........................................................................................................................................ 40
20. Physical Dimensions...................................................................................................................................................41
20.1 1Gbx4 based 2Gx72 Module (2 Ranks) - M393B2G70DB0..................................................................................41
20.1.1. x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs...............................................................41
20.2 2Gbx4(DDP) based 4Gx72 Module (4 Ranks) - M393B4G70DM0 .......................................................................42
20.2.1. x72 DIMM, populated as four physical ranks of x4 DDR3 SDRAMs..............................................................42
20.2.2. Heat Spreader Design Guide ......................................................................................................................... 43
Tolerances.................................................................................................................................................... 20
REF
CK) and Strobe (DQS - DQS) ............................................. 21
- 3 -
Preliminary
Rev. 0.6
Registered DIMM
datasheet DDR3L SDRAM
1. DDR3L Registered DIMM Ordering Information
Part Number
M393B2G70DB0-YH9/K0 16GB 2Gx72 1Gx4(K4B4G0446D-BY##)*36 2 30mm
M393B4G70DM0-YF8/H9 32GB 4Gx72 DDP 2Gx4(K4B8G0446D-MY##)*36 4 30mm
NOTE :
1. "##" - F8/H9/K0
2. F8(1066Mbps 7-7-7) / H9(1333Mbps 9-9-9) / K0(1600Mbps 11-11-11)
- DDR3L-1600(11-11-11) is backward compatible to DDR3L-1333(9-9-9), DDR3L-1066(7-7-7)
- DDR3L-1333(9-9-9) is backward compatible to DDR3L-1066(7-7-7)
2
Density Organization
Component Composition
1
Number of
Rank
2. Key Features
Speed
tCK(min) 2.5 1.875 1.5 1.25 ns
CAS Latency 6 7 9 11 nCK
tRCD(min) 15 13.125 13.5 13.75 ns
tRP(min) 15 13.125 13.5 13.75 ns
tRAS(min) 37.5 37.5 36 35 ns
tRC(min) 52.5 50.625 49.5 48.75 ns
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
6-6-6 7-7-7 9-9-9 11-11-11
Height
Unit
• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply
•V
• 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9,10,11
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333) and 8(DDR3-1600)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then T
• Asynchronous Reset
= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
DDQ
write [either On the fly using A12 or MRS]
85°C, 3.9us at 85°C < T
CASE
CASE
≤ 95°C
3. Address Configuration
Organization Row Address Column Address Bank Address Auto Precharge
1Gx4(4Gb) based Module A0-A15 A0-A9, A11 BA0-BA2 A10/AP
2Gx4(8Gb DDP) based Module A0-A15 A0-A9, A11 BA0-BA2 A10/AP
- 4 -
Preliminary
Rev. 0.6
Registered DIMM
datasheet DDR3L SDRAM
4. Registered DIMM Pin Configurations (Front side/Back side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1
2
V
REFDQ
V
121
SS
122 DQ4 43 DQS8 163
3 DQ0 123 DQ5 44
4 DQ1 124
5
6
V
SS
125
DQS0 126
7 DQS0 127
8
V
SS
128 DQ6 KEY 89
9 DQ2 129 DQ7 49
10 DQ3 130
11
V
SS
131 DQ12 51
12 DQ8 132 DQ13 52 BA2 172 A14 93
13 DQ9 133
14
15
V
SS
134
DQS1 135
16 DQS1 136
17
V
SS
137 DQ14 57
18 DQ10 138 DQ15 58 A5 178 A6 99 DQ48 219 DQ53
19 DQ11 139
20
V
SS
140 DQ20 60
21 DQ16 141 DQ21 61 A2 181 A1 102
22 DQ17 142
23
24
V
SS
143
DQS2 144
25 DQS2 145
26
V
SS
146 DQ22 66
27 DQ18 147 DQ23 67
28 DQ19 148
29
V
SS
149 DQ28 69
30 DQ24 150 DQ29 70 A10/AP 190 BA1 111
31 DQ25 151
32
33
V
SS
152
DQS3 153
34 DQS3 154
35
V
SS
155 DQ30 75
36 DQ26 156 DQ31 76 S1,NC 196 A13 117 SA0 237 SA1
37 DQ27 157
38
V
SS
158 CB4,NC 78
39 CB0,NC 159 CB5,NC 79 S2,NC 199
40 CB1,NC 160
41
V
SS
161
NOTE : NC = No internal Connection
V
SS
V
SS
DM0,DQS9
,TDQS9
DQS9
NC,
TDQS9
,
V
SS
V
SS
V
SS
DM1,DQS10
,TDQS10
DQS10
NC,
TDQS10
,
V
SS
V
SS
V
SS
DM2,DQS11
,TDQS11
DQS11
NC,
TDQS11
,
V
SS
V
SS
V
SS
DM3,DQS12
,TDQS12
DQS12
NC,
TDQS12
,
V
SS
V
SS
V
SS
DM8,DQS17
TDQS17,NC
42 DQS8 162
V
SS
164 CB6,NC 84 DQS4 204
45 CB2,NC 165 CB7,NC 85 DQS4 205
46 CB3,NC 166
47
48
V
SS
V
, NC
TT
V
, NC
TT
167 NC(TEST) 87 DQ34 207 DQ39
168
169 CKE1, NC 90 DQ40 210 DQ45
50 CKE0 170
V
DD
171 A15 92
53 Err_Out/NC 173
54
V
DD
174 A12/BC 95
55 A11 175 A9 96 DQ42 216 DQ47
56 A7 176
V
DD
177 A8 98
59 A4 179
V
DD
62
V
DD
180 A3 101
182
63 NC, CK1 183
64 NC,
65
CK1 184 CK0 105 DQ50 225 DQ55
V
V
V
REFCA
DD
DD
185 CK0 106 DQ51 226
186
187 EVENT,NC 108 DQ56 228 DQ61
68 NC/Par_In 188 A0 109 DQ57 229
V
DD
189
71 BA0 191
72
73
V
DD
WE 193 S0 114 DQ58 234 DQ63
192 RAS 113
74 CAS 194
V
DD
195 ODT0 116
77 ODT1,NC 197
V
DD
80
V
SS
198 S3,NC 119 SA2 239
200 DQ36
81 DQ32 201 DQ37
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
NC,DQS17
,
TDQS17
V
SS
V
SS
82 DQ33 202
83
86
V
SS
V
SS
RESET 88 DQ35 208
V
SS
V
DD
91 DQ41 211
V
SS
DQS5 213
V
DD
V
DD
V
DD
94 DQS5 214
V
SS
97 DQ43 217
V
SS
100 DQ49 220
V
SS
DQS6 222
V
DD
V
DD
V
DD
V
DD
103 DQS6 223
104
107
110
V
SS
V
SS
V
SS
DQS7 231
V
DD
V
DD
V
DD
V
SS
112 DQS7 232
V
SS
115 DQ59 235
V
SS
118 SCL 238 SDA
120
V
TT
203
DM4,DQS13
206 DQ38
209 DQ44
212
DM5,DQS14
215 DQ46
218 DQ52
221
DM6,DQS15
224 DQ54
227 DQ60
230
DM7/DQS16
DM7,
233 DQ62
236
240
V
SS
,TDQS13
DQS13
NC,
TDQS13
,
V
SS
V
SS
V
SS
,TDQS14
DQS14
NC,
TDQS14
,
V
SS
V
SS
V
SS
,TDQS15
DQS15
NC,
TDQS15
,
V
SS
V
SS
V
SS
TDQS16
DQS16
,TDQS16
V
SS
V
SS
V
DDSPD
V
SS
V
TT
- 5 -
Preliminary
Rev. 0.6
Registered DIMM
datasheet DDR3L SDRAM
5. Pin Description
Pin Name Description Number Pin Name Description Number
CK0 Clock Input, positive line 1 ODT[1:0] On Die Termination Inputs 2
CK0 Clock Input, negative line 1 DQ[63:0] Data Input/Output 64
CKE[1:0] Clock Enables 2 CB[7:0] Data check bits Input/Output 8
RAS Row Address Strobe 1 DQS[8:0] Data strobes 9
CAS Column Address Strobe 1 DQS[8:0] Data strobes, negative line 9
DM[8:0]/
WE Write Enable 1
S[3:0] Chip Selects 4
A[9:0],A11,
A[15:13]
A10/AP Address Input/Autoprecharge 1 EVENT
A12/BC Address Input/Burst chop 1 TEST
BA[2:0] SDRAM Bank Addresses 3 RESET Register and SDRAM control pin 1
SCL Serial Presence Detect (SPD) Clock Input 1
SDA SPD Data Input/Output 1
SA[2:0] SPD Address Inputs 3
Par_In Parity bit for the Address and Control bus 1
Err_Out
NOTE :
*The V
and V
DD
Address Inputs 2\14 RFU Reserved for Future Use 2
Parity error found on the Address and Control
bus
pins are tied common to a single power-plane on these designs.
DDQ
1
DQS[17:9]
TDQS[17:9]
DQS[17:9]
TDQS[17:9]
V
DD
V
SS
V
REFDQ
V
REFCA
V
TT
V
DDSPD
Data Masks/ Data strobes,
Termination data strobes
Data strobes, negative line, Termination data
strobes
Reserved for optional hardware temperature
sensing
Memory bus test toll (Not Connected and Not
Usable on DIMMs)
Power Supply 22
Ground 59
Reference Voltage for DQ 1
Reference Voltage for CA 1
Termination Voltage 4
SPD Power 1
Total 240
9
9
1
1
6. ON DIMM Thermal Sensor
EVENT
NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM
2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not.
When only the SPD is placed on the module, R2 is placed but R1 is not.
[ Table 1 ] Temperature Sensor Characteristics
Grade Range
75 < Ta < 95 - +/- 0.5 +/- 1.0
B
40 < Ta < 125 - +/- 1.0 +/- 2.0 -
-20 < Ta < 125 - +/- 2.0 +/- 3.0 -
Resolution 0.25 °C /LSB -
SCL
R1
0 Ω
WP/EVENT
SA0 SA1 SA2
R2
0 Ω
SA0 SA1 SA2
Min. Typ. Max.
SDA
Temperature Sensor Accuracy
Units NOTE
-
°C
- 6 -
Preliminary
Rev. 0.6
Registered DIMM
datasheet DDR3L SDRAM
7. Input/Output Functional Description
Symbol Type Polarity Function
CK0 Input
CK0 Input
CKE[1:0] Input Active High
S[3:0] Input Active Low
ODT[1:0] Input Active High On-Die Termination control signals
RAS, CAS, WE Input Active Low
V
REFDQ
V
REFCA
BA[2:0] Input
A[15:13,
12/BC,11,
10/AP,9:0]
DQ[63:0],
CB[7:0]
DM[8:0]
DQS[17:0] I/O Positive Edge Positive line of the differential data strobe for input and output data.
DQS[17:0] I/O Negative Edge Negative line of the differential data strobe for input and output data.
TDQS[17:9],
TDQS[17:9] OUT
SA[2:0] IN
SDA I/O
SCL IN
EVENT
V
DDSPD
RESET IN
Par_In IN Parity bit for the Address and Control bus. ("1 " : Odd, "0 ": Even)
Err_Out
TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Supply Reference voltage for DQ0-DQ63 and CB0-CB7
Supply Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1.
Input
I/O Data and Check Bit Input/Output pins
OUT
(open
drain)
Supply
OUT
(open
drain)
Positive
Edge
Negative
Edge
Active Low
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers
and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder when high.
When decoder is disabled, new commands are ignored and previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both
inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in
the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of register outputs.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM.
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank
address also determines mode register is to be accessed during an MRS cycle.
Provided the row address for Active commands and the column address and Auto Precharge bit for Read/
Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8
identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during
Mode Register Set commands.
Active High Masks write data when high, issued concurrently with input data.
, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic.
V
DD
V
Supply Termination Voltage for Address/Command/Control/Clock nets.
TT
TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will
enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.
X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1
These signals are tied at the system planar to either VSS or V
address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to V
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to V
This signal indicates that a thermal event has been detected in the thermal sensing device.The system
should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part.
Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from
3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When
low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set
to low level (the Clock Driver will remain synchronized with the input clock)
Parity error detected on the Address and Control bus. A resistor may be connected from
bus line to VDD on the system planar to act as a pull up.
on the system planar to act as a pull-up.
DDSPD
on the system planar to act as a pull-up.
DDSPD
to configure the serial SPD EEPROM
DDSPD
Err_Out
- 7 -
Preliminary
Rev. 0.6
Registered DIMM
datasheet DDR3L SDRAM
8. Pinout Comparison Based On Module Type
Pin
48, 49
120, 240
53 Err_Out
63 NC
64 NC CK1
68 Par_In Connected to the register on all RDIMMs NC Not used on RDIMMs
76 S1 Connected to the register on all RDIMMs S1
77 ODT1, NC
79
167 NC TEST input used only on bus analysis probes NC
169 CKE1
171 A15
172 A14 A14
196 A13 A13
198
39, 40, 45, 46,
158, 159, 164,
165
125, 134, 143,
152, 161, 203,
212, 221, 230
126, 135, 144,
153, 162, 204,
213, 222, 231
187
NOTE : NC = No internal Connection
Signal NOTE Signal NOTE
V
TT
VTT
S2, NC
S3, NC
CBn Used on all RDIMMs; (n = 0...7) NC, CBn
DQSn,
TDQSn
DQSn,
TDQSn
EVENT
NC
Additional connection for Termination Voltage for
Address/Command/Control/Clock nets.
Termination Voltage for Address/Command/Control/Clock nets.
Connected to the register on all RDIMMs NC Not
used on UDIMMs
Not used on RDIMMs
Connected to the register on dual- and quadrank
RDIMMs; NC on single-rank RDIMMs
Connected to the register on quad-rank
RDIMMs, not connected on single or dual rank
RDIMMs
Connected to the register on dual- and quadrank
RDIMMs; NC on single-rank RDIMMs
Connected to the register on all RDIMMs
Connected to the register on quad-rank
RDIMMs, not connected on single-or dual-rank
RDIMMs
Connected to DQS on x4 SDRAMs,
TDQS on x8 SDRAMs on RDIMMs; (n = 9...17)
Connected to DQS on x4 DRAMs, TDQS on x8
SDRAMs on RDIMMs; (n=9...17)
Connected to optional thermal sensing component.
NC on Modules without a thermal sensing
component.
RDIMM UDIMM
NC Not used on UDIMMs
V
TT
NC NC Not used on UDIMMs
CK1
ODT1,NC
NC Not used on UDIMMs
CKE1,
NC
A15, NC Depending on device density, may not be
NC Not used on UDIMMs
DMn
NC Not used on UDIMMs
NC Not used on UDIMMs
Termination Voltage for Address/Command/Control/Clock nets.
Used for 2 rank UDIMMs, not used on single-rank
UDIMMs, but terminated
Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs
Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs
TEST input used only on bus analysis
probes
Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs
connected to SDRAMs on UDIMMs. However,
these signals are terminated on
UDIMMs. A15 not routed on some RCs
Used on x72 UDIMMs, (n = 0...7); not
used on x64 UDIMMs
Connected to DM on x8 DRAMs, UDM or
LDM on x16 DRAMs on UDIMMs;
(n = 0...8)
- 8 -
Preliminary
Rev. 0.6
Registered DIMM
datasheet DDR3L SDRAM
9. Registering Clock Driver Specification
9.1 Timing & Capacitance values
TC = TBD
= 1.35V(1.28V~1.45V)
V
Symbol Parameter Conditions
fclock Input Clock Frequency application frequency 300 670 MHz
tCH/t
t
ACT
t
SU
t
H
t
PDM
t
DIS
t
EN
CIN(DATA)
CIN(CLOCK)
(RST)
C
IN
Pulse duration, CK, CK HIGH or LOW 0.4 -
CL
Inputs active time4 before RESET is taken HIGH
Setup time Input valid before CK/CK 100 - ps
Hold time
Propagation delay, single-bit switching CK/CK to output 0.65 1.0 ns
output disable time(1/2-Clock pre-launch)
output disable time(3/4-Clock pre-launch) 0.25 -
output enable time(1/2-Clock pre-launch)
output enable time(3/4-Clock pre-launch) - 0.25
Data Input Capacitance 1.5 2.5
Data Input Capacitance 2 3
Reset Input Capacitance - 3
DCKE0/1 = LOW and
DCS0/1 = HIGH
Input to remain Valid after CK/
CK
CK/CK to output float
CK/CK to output driving
DD
& 1.5V(1.425~1.575V)
Min Max
8-
175 -
0.5 -
- 0.5
Units Notes
t
CK
t
CK
t
CK
t
CK
pF
9.2 Clock driver Characteristics
Symbol Parameter Conditions
t
jit
t
t
t
jit
t
jit
t
t
t
(cc)
STAB
t
fdyn
CKsk
(per)
(hper)
Qsk1
Qsk1
dynoff
Cycle-to-cycle period jitter 0 40 ps
Stabilization time -6us
Dynamic phase offset -50 50 ps
Clock Output skew 50 ps
Yn Clock Period jitter -40 40 ps
Half period jitter -50 50 ps
Qn Output to clock tolerance (Standard 1/2 -Clock
Pre-Launch)
Output clock tolerance (3/4 Clock Pre-Launch)
Maximum re-driven dynamic clock off-set -80 80 ps
Output Inversion enabled -100 200
OUtput Inversion disabled -100 300
Output Inversion enabled -100 200
OUtput Inversion disabled -100 300
TC = TBD
VDD = 1.35V(1.28V~1.45V)
& 1.5V(1.425~1.575V)
Min Max
Units Notes
ps
ps
- 9 -
Preliminary
Rev. 0.6
Registered DIMM
datasheet DDR3L SDRAM
10. Function Block Diagram:
10.1 16GB, 2Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)
RS0A
RRASA
RCASA
RWEA
PCK0A
RCKE0A
RODT0A
A[N:0]A
DQS17
DQS17
VSS
CB[7:4]
DQS12
DQS12
VSS
DQ[31:28]
DQS11
DQS11
VSS
DQ[23:20]
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
PCK0A
D17
RAS
CASWECKCKCKE
D12
RAS
CASWECKCKCKE
D11
RAS
CASWECKCKCKE
/BA[N:0]A
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
RS1A
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
PCK1A
D17B
RAS
CASWECKCKCKE
D12B
RAS
CASWECKCKCKE
D11B
RAS
CASWECKCKCKE
PCK1A
RCKE1A
RODT1A
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
DQS8
DQS8
VSS
CB[3:0]
DQS3
DQS3
VSS
DQ[27:24]
DQS2
DQS2
VSS
DQ[19:16]
RS0A
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
RRASA
RAS
RAS
RAS
RCASA
RWEA
PCK0A
RCKE0A
PCK0A
D8
CASWECKCKCKE
D3
CASWECKCKCKE
D2
CASWECKCKCKE
RODT0A
A[N:0]A
/BA[N:0]A
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
RS1A
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
PCK1A
D8B
RAS
CASWECKCKCKE
D3B
RAS
CASWECKCKCKE
D2B
RAS
CASWECKCKCKE
PCK1A
RCKE1A
RODT1A
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
DQS10
DQS10
VSS
DQ[15:12]
DQS0
DQS0
VSS
DQ[3:0]
DQS
DQS
DM
D10
DQ[3:0]
CS
RAS
CASWECKCKCKE
DQS
DQS
DM
DQ[3:0]
CS
RAS
CASWECKCKCKE
Vtt
ODT
D0
ODT
DQS
DQS
DM
DQ[3:0]
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
A[N:0]/BA[N:0]
CS
RAS
CASWECKCKCKE
CS
RAS
CASWECKCKCKE
D10B
D0B
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
DQS1
DQS1
VSS
DQ[11:8]
DQS9
DQS9
VSS
DQ[7:4]
DQS
DQS
DM
D1
DQ[3:0]
CS
RAS
CASWECKCKCKE
DQS
DQS
DM
DQ[3:0]
CS
RAS
CASWECKCKCKE
Vtt
ODT
D9
ODT
DQS
DQS
DM
DQ[3:0]
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
A[N:0]/BA[N:0]
D1B
CS
RAS
CASWECKCKCKE
D9B
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
- 10 -
Preliminary
Rev. 0.6
Registered DIMM
RS0B
DQS4
DQS4
VSS
CB[35:32]
DQS5
DQS5
VSS
DQ[43:40]
DQS6
DQS6
VSS
DQ[51:48]
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
RRASB
RCASB
RWEB
PCK0B
D4
RAS
CASWECKCKCKE
D5
RAS
CASWECKCKCKE
D6
RAS
CASWECKCKCKE
PCK0B
RCKE0B
RODT0B
/BA[N:0]B
A[N:0]B
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
RS1B
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
datasheet DDR3L SDRAM
PCK1B
PCK1B
RCKE1B
D4B
RAS
CASWECKCKCKE
D5B
RAS
CASWECKCKCKE
D6B
RAS
CASWECKCKCKE
RODT1B
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
DQS13
DQS13
VSS
CB[39:36]
DQS14
DQS14
VSS
DQ[47:44]
DQS15
DQS15
VSS
DQ[55:52]
RS0B
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
RRASB
RCASB
RWEB
PCK0B
D13
RAS
CASWECKCKCKE
D14
RAS
CASWECKCKCKE
D15
RAS
CASWECKCKCKE
PCK0B
RCKE0B
RODT0B
/BA[N:0]B
A[N:0]B
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
RS1B
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
PCK1B
D13B
RAS
CASWECKCKCKE
D14B
RAS
CASWECKCKCKE
D15B
RAS
CASWECKCKCKE
PCK1B
RCKE1B
RODT1B
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
DQS7
DQS7
VSS
DQ[59:56]
DQS
DQS
DM
DQ[3:0]
CS
D7
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
CS
D7B
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS16
DQS16
DQ[63:60]
Vtt
Integrated Thermal sensor in SPD
SCL
EVENT EVENT
A0
A1 A2
SDA
SA0 SA1 SA2
Serial PD w/ integrated Thermal sensor
V
DDSPD
V
DD
V
TT
V
REFCA
V
REFDQ
V
SS
Serial PD
D0 - D35
D0 - D35
D0 - D35
D0 - D35
NOTE:
1. See wiring diagrams for resistor values.
2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240 +/-1%)ohms...
VSS
DQS
DQS
DM
DQ[3:0]
CS
D16
RAS
CASWECKCKCKE
ODT
DQS
DQS
DM
DQ[3:0]
A[N:0]/BA[N:0]
D16B
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
Vtt
RS0A -> CS0 : SDRAMs D[3:0], D[12:8], D17
RS0B -> CS0 : SDRAMs D[7:4]B, D[16:13] B
RS1A -> CS1 : SDRAMs D[3:0]B, D[12:8]B, D17B
RS1B -> CS1 : SDRAMs D[7:4], D[16:13]
RBA[N:0]A -> BA[N:0]: SDRAMs D[3:0], D[12:8], D17,D[3:0]B, D[12:8]B, D17B
RBA[N:0]B -> BA[N:0]: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B
RA[N:0]A -> A[N:0]: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B
RA[N:0]B -> A[N:0]: SDRAMs D[7:4], D[16:13], D[7:4], D[16:13]B
RRASA -> RAS: SDRAMs D[3:0], D[12:8],D17, D[3:0]B, D[12:8]B, D17B
RRASB -> RAS: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B
RCASA -> CAS: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B
RCASB -> CAS: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B
1:2
RWEA -> WE: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B
R
RWEB -> WE: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B
E
RCKE0A -> CKE0: SDRAMs D[3:0], D[12:8], D17
G
RCKE0B -> CKE0: SDRAMs D[7:4]B, D[16:13]B
I
RCKE1A -> CKE1: SDRAMs D[3:0], D[12:8]B, D17B
S
RCKE1B -> CKE1: SDRAMs D[7:4], D[16:13]
T
RODT0A -> ODT0: SDRAMs D[3:0], D[12:8], D17
E
RODT0B -> ODT0: SDRAMs D[7:4]B, D[16:13]B
R
RODT1A -> ODT1: SDRAMs D[3:0]B, D[12:8]B, D17B
RODT1B -> ODT1: SDRAMs D[7:4], D[16:13]
PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4]B, D[16:13]B
PCK1A -> CK: SDRAMs D[3:0]B, D[12:8]B, D17B
PCK1B -> CK: SDRAMs D[7:4], D[16:13]
PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4]B, D[16:13]B
PCK1A -> CK: SDRAMs D[3:0]B, D[12:8]B, D17B
PCK1B -> CK: SDRAMs D[7:4], D[16:13]
ERR_OUT
RST
RST : SDRAMs D[17:0], D[17:0]B
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
S0
S1
CK0
CK0
CK1
CK1
PAR_IN
RESET
120
Ω
- 11 -
Preliminary
Rev. 0.6
Registered DIMM
datasheet DDR3L SDRAM
10.2 32GB, 4Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs)
APCK0A
ARS0A
ARRASA
ARCASA
ARWEA
APCK0A
ARCKE0A
ARODT0A
ARA[N:0]A
VSS VSSZQ
DQS8
DQS8
VSS
CB[3:0]
VSS VSSZQ
DQS3
DQS3
VSS
DQ[27:24]
VSS VSSZQ
DQS2
DQS2
VSS
DQ[19:16]
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
D9
RAS
CASWECKCKCKE
D7
RAS
CASWECKCKCKE
D5
RAS
CASWECKCKCKE
/ARBA[N:0]A
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ARS1A
ZQ
DQS
DQS
DM
DQ[3:0]
CS
ZQ
DQS
DQS
DM
DQ[3:0]
CS
ZQ
DQS
DQS
DM
DQ[3:0]
CS
D8
RAS
CASWECKCKCKE
D6
RAS
CASWECKCKCKE
D4
RAS
CASWECKCKCKE
ARCKE1A
VDD
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
BRS2A
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
BRRASA
BRCASA
BRWEA
BPCK0A
D45
RAS
CASWECKCKCKE
D47
RAS
CASWECKCKCKE
D49
RAS
CASWECKCKCKE
BPCK0A
BRCKE0A
BRODT1A
ODT
ODT
ODT
BRA[N:0]A
/BRBA[N:0]A
VSSZQ
A[N:0]/BA[N:0]
VSSZQ
A[N:0]/BA[N:0]
VSSZQ
A[N:0]/BA[N:0]
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
BRS3A
D44
RAS
CASWECKCKCKE
D46
RAS
CASWECKCKCKE
D48
RAS
CASWECKCKCKE
BRCKE1A
VDD
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS1
DQS1
VSS
DQ[11:8]
VSS VSSZQ
DQS0
DQS0
VSS
DQ[3:0]
Vtt
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
D3
RAS
CASWECKCKCKE
D1
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
CS
ZQ
DQS
DQS
DM
DQ[3:0]
CS
D2
RAS
CASWECKCKCKE
D0
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
D51
RAS
CASWECKCKCKE
D53
RAS
CASWECKCKCKE
VSSZQ
ODT
A[N:0]/BA[N:0]
VSSZQ
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
D50
RAS
CASWECKCKCKE
D52
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
- 12 -
Preliminary
Rev. 0.6
Registered DIMM
VSS VSSZQ
DQS17
DQS17
VSS
CB[7:4]
VSS VSSZQ
DQS12
DQS12
VSS
DQ[31:28]
VSS VSSZQ
DQS11
DQS11
VSS
DQ[23:20]
ARS0A
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
APCK0A
ARRASA
ARCASA
ARWEA
D27
RAS
CASWECKCKCKE
D25
RAS
CASWECKCKCKE
D23
RAS
CASWECKCKCKE
APCK0A
ARCKE0A
ARODT0A
ODT
ODT
ODT
ARA[N:0]A
/ARBA[N:0]A
A[N:0]/BA[N:0]
A[N:0]/BA[N:0]
A[N:0]/BA[N:0]
datasheet DDR3L SDRAM
ARS1A
ZQ
DQS
DQS
DM
DQ[3:0]
CS
ZQ
DQS
DQS
DM
DQ[3:0]
CS
ZQ
DQS
DQS
DM
DQ[3:0]
CS
RAS
RAS
RAS
ARCKE1A
D26
CASWECKCKCKE
D24
CASWECKCKCKE
D22
CASWECKCKCKE
VDD
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
BRS2A
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
BRRASA
BRCASA
BRWEA
BPCK0A
D63
RAS
CASWECKCKCKE
D65
RAS
CASWECKCKCKE
D67
RAS
CASWECKCKCKE
BPCK0A
BRCKE0A
BRODT1A
ODT
ODT
ODT
BRA[N:0]A
/BRBA[N:0]A
VSSZQ
A[N:0]/BA[N:0]
VSSZQ
A[N:0]/BA[N:0]
VSSZQ
A[N:0]/BA[N:0]
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
BRS3A
D62
RAS
CASWECKCKCKE
D64
RAS
CASWECKCKCKE
D66
RAS
CASWECKCKCKE
BRCKE1A
VDD
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS10
DQS10
VSS
DQ[15:12]
VSS VSSZQ
DQS9
DQS9
VSS
DQ[7:4]
Vtt
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
D21
RAS
CASWECKCKCKE
D19
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
CS
ZQ
DQS
DQS
DM
DQ[3:0]
CS
D20
RAS
CASWECKCKCKE
D18
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
D69
RAS
CASWECKCKCKE
D71
RAS
CASWECKCKCKE
VSSZQ
ODT
A[N:0]/BA[N:0]
VSSZQ
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
D68
RAS
CASWECKCKCKE
D70
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
- 13 -
Preliminary
Rev. 0.6
Registered DIMM
VSS VSSZQ
DQS4
DQS4
VSS
DQ[35:32]
VSS VSSZQ
DQS5
DQS5
VSS
DQ[43:40]
VSS VSSZQ
DQS6
DQS6
VSS
DQ[51:48]
ARS0B
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
APCK0B
ARRASB
ARCASB
ARWEB
D11
RAS
CASWECKCKCKE
D13
RAS
CASWECKCKCKE
D15
RAS
CASWECKCKCKE
APCK0B
ARCKE0B
ARODT0B
ODT
ODT
ODT
ARA[N:0]B
/ARBA[N:0]B
A[N:0]/BA[N:0]
A[N:0]/BA[N:0]
A[N:0]/BA[N:0]
datasheet DDR3L SDRAM
ARS1B
ZQ
DQS
DQS
DM
DQ[3:0]
CS
ZQ
DQS
DQS
DM
DQ[3:0]
CS
ZQ
DQS
DQS
DM
DQ[3:0]
CS
RAS
RAS
RAS
ARCKE1B
D10
CASWECKCKCKE
D12
CASWECKCKCKE
D14
CASWECKCKCKE
VDD
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
BRS2B
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
DQS
DQS
DM
DQ[3:0]
CS
BRRASB
BRCASB
BRWEB
BPCK0B
D43
RAS
CASWECKCKCKE
D41
RAS
CASWECKCKCKE
D39
RAS
CASWECKCKCKE
BPCK0B
BRCKE0B
BRODT1B
ODT
ODT
ODT
BRA[N:0]B
/BRBA[N:0]B
VSSZQ
A[N:0]/BA[N:0]
VSSZQ
A[N:0]/BA[N:0]
VSSZQ
A[N:0]/BA[N:0]
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
BRS3B
D42
RAS
CASWECKCKCKE
D40
RAS
CASWECKCKCKE
D38
RAS
CASWECKCKCKE
BRCKE1B
VDD
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS7
DQS7
VSS
DQ[59:56]
Vtt
DQS
DQS
DM
DQ[3:0]
CS
D17
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
CS
D16
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
CS
D37
RAS
CASWECKCKCKE
VSSZQ
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS
DQS
DM
DQ[3:0]
CS
D36
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
- 14 -
Loading...