Samsung M393B1K70QB0-CMA User Manual

Rev.1.1, Aug. 2013

240pin Registered DIMM

based on 2Gb Q-die

78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)

M393B1K70QB0

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other­wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

2013 Samsung Electronics Co., Ltd. All rights reserved.

- 1 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

Revision History

Revision No. History Draft Date Remark Editor

1.0 - First SPEC. Release Jun. 2013 - S.H.Kim

1.1 - Deleted by changing line-up (4GB : 1Rx4, 2Rx8) Aug. 2013 - S.H.Kim

- 2 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

Table Of Contents

240pin Registered DIMM based on 2Gb Q-die

1. DDR3 Registered DIMM Ordering Information .............................................................................................................4

2. Key Features.................................................................................................................................................................4

3. Address Configuration ..................................................................................................................................................4

4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................5

5. Pin Description .............................................................................................................................................................6

6. ON DIMM Thermal Sensor ...........................................................................................................................................6

7. Input/Output Functional Description..............................................................................................................................7

8. Pinout Comparison Based On Module Type.................................................................................................................8

9. Registering Clock Driver Specification..........................................................................................................................9

9.1 Timing & Capacitance values .................................................................................................................................. 9

9.2 Clock driver Characteristics.....................................................................................................................................9

10. Function Block Diagram:.............................................................................................................................................10

10.1 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)......................................................................10

11. Absolute Maximum Ratings ........................................................................................................................................12

11.1 Absolute Maximum DC Ratings............................................................................................................................. 12

11.2 DRAM Component Operating Temperature Range ..............................................................................................12

12. AC & DC Operating Conditions...................................................................................................................................12

12.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................ 12

13. AC & DC Input Measurement Levels ..........................................................................................................................13

13.1 AC & DC Logic Input Levels for Single-ended Signals..........................................................................................13

13.2 V

13.3 AC and DC Logic Input Levels for Differential Signals ..........................................................................................16

13.3.1. Differential Signals Definition ......................................................................................................................... 16

13.3.2. Differential Swing Requirement for Clock (CK -

13.3.3. Single-ended Requirements for Differential Signals ......................................................................................18

13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 19

13.4 Slew Rate Definition for Single Ended Input Signals.............................................................................................19

13.5 Slew rate definition for Differential Input Signals ................................................................................................... 19

14. AC & DC Output Measurement Levels .......................................................................................................................20

14.1 Single Ended AC and DC Output Levels...............................................................................................................20

14.2 Differential AC and DC Output Levels ................................................................................................................... 20

14.3 Single-ended Output Slew Rate ............................................................................................................................ 20

14.4 Differential Output Slew Rate ................................................................................................................................ 21

15. DIMM IDD specification definition ...............................................................................................................................22

16. IDD SPEC Table .........................................................................................................................................................24

17. Input/Output Capacitance ...........................................................................................................................................25

18. Electrical Characteristics and AC timing .....................................................................................................................26

18.1 Refresh Parameters by Device Density................................................................................................................. 26

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................26

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 26

18.3.1. Speed Bin Table Notes .................................................................................................................................. 30

19. Timing Parameters by Speed Grade ..........................................................................................................................31

19.1 Jitter Notes ............................................................................................................................................................37

19.2 Timing Parameter Notes........................................................................................................................................ 38

20. Physical Dimensions...................................................................................................................................................39

20.1 512Mbx4 based 1Gx72 Module (2 Ranks) - M393B1K70QB0..............................................................................39

20.1.1. x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs...............................................................39

Tolerances.................................................................................................................................................... 15

REF

CK) and Strobe (DQS - DQS) ............................................. 16

- 3 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

1. DDR3 Registered DIMM Ordering Information

Part Number

M393B1K70QB0-CK0/MA 8GB 1Gx72 512Mx4(K4B2G0446Q-BC##)*36 2 30mm

NOTE :

1. "##" - K0/MA

2. K0(1600Mbps 11-11-11) / MA(1866Mbps 13-13-13)

- DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11)

3. Please contact Samsung for product availability.

2

Density Organization

Component Composition

1

Number of

Rank

2. Key Features

Speed

tCK(min) 2.5 1.875 1.5 1.25 1.071 ns

CAS Latency 6 7 9 11 13 nCK

tRCD(min) 15 13.125 13.5 13.75 13.91 ns

tRP(min) 15 13.125 13.5 13.75 13.91 ns

tRAS(min) 37.5 37.5 36 35 34 ns

tRC(min) 52.5 50.625 49.5 48.75 47.91 ns

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

6-6-6 7-7-7 9-9-9 11-11-11 13-13-13

Height

Unit

• JEDEC standard 1.5V ± 0.075V Power Supply

•V

= 1.5V ± 0.075V

DDQ

• 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin,
933MHz fCK for 1866Mb/sec/pin

• 8 independent internal bank

• Programmable CAS Latency: 6,7,8,9,10,11,13

• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9 (DDR3-1866)

• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or

write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

• Asynchronous Reset

85C, 3.9us at 85C < T

CASE

CASE

95C

3. Address Configuration

Organization Row Address Column Address Bank Address Auto Precharge

512Mx4(2Gb) based Module A0-A14 A0-A9, A11 BA0-BA2 A10/AP

- 4 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

4. Registered DIMM Pin Configurations (Front side/Back side)

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1

2

V

REFDQ

V

121

SS

122 DQ4 43 DQS8 163

3 DQ0 123 DQ5 44

4 DQ1 124

5

6

V

SS

125

DQS0 126

7 DQS0 127

8

V

SS

128 DQ6 KEY 89

9 DQ2 129 DQ7 49

10 DQ3 130

11

V

SS

131 DQ12 51

12 DQ8 132 DQ13 52 BA2 172 A14 93

13 DQ9 133

14

15

V

SS

134

DQS1 135

16 DQS1 136

17

V

SS

137 DQ14 57

18 DQ10 138 DQ15 58 A5 178 A6 99 DQ48 219 DQ53

19 DQ11 139

20

V

SS

140 DQ20 60

21 DQ16 141 DQ21 61 A2 181 A1 102

22 DQ17 142

23

24

V

SS

143

DQS2 144

25 DQS2 145

26

V

SS

146 DQ22 66

27 DQ18 147 DQ23 67

28 DQ19 148

29

V

SS

149 DQ28 69

30 DQ24 150 DQ29 70 A10/AP 190 BA1 111

31 DQ25 151

32

33

V

SS

152

DQS3 153

34 DQS3 154

35

V

SS

155 DQ30 75

36 DQ26 156 DQ31 76 S1,NC 196 A13 117 SA0 237 SA1

37 DQ27 157

38

V

SS

158 CB4,NC 78

39 CB0,NC 159 CB5,NC 79 S2,NC 199

40 CB1,NC 160

41

V

SS

161

NOTE : NC = No internal Connection

V

SS

V

SS

DM0,DQS9

,TDQS9

DQS9

NC,

TDQS9

,

V

SS

V

SS

V

SS

DM1,DQS10

,TDQS10

DQS10

NC,

TDQS10

,

V

SS

V

SS

V

SS

DM2,DQS11

,TDQS11

DQS11

NC,

TDQS11

,

V

SS

V

SS

V

SS

DM3,DQS12

,TDQS12

DQS12

NC,

TDQS12

,

V

SS

V

SS

V

SS

DM8,DQS17
TDQS17,NC

42 DQS8 162

V

SS

164 CB6,NC 84 DQS4 204

45 CB2,NC 165 CB7,NC 85 DQS4 205

46 CB3,NC 166

47

48

V

SS

, NC

V

TT

V

, NC

TT

167 NC(TEST) 87 DQ34 207 DQ39

168

169 CKE1, NC 90 DQ40 210 DQ45

50 CKE0 170

V

DD

171 NC 92

53 Err_Out/NC 173

54

V

DD

174 A12/BC 95

55 A11 175 A9 96 DQ42 216 DQ47

56 A7 176

V

DD

177 A8 98

59 A4 179

V

DD

62

V

DD

180 A3 101

182

63 NC, CK1 183

64 NC,

65

CK1 184 CK0 105 DQ50 225 DQ55

V

V

V

REFCA

DD

DD

185 CK0 106 DQ51 226

186

187 EVENT,NC 108 DQ56 228 DQ61

68 NC/Par_In 188 A0 109 DQ57 229

V

DD

189

71 BA0 191

72

73

V

DD

WE 193 S0 114 DQ58 234 DQ63

192 RAS 113

74 CAS 194

V

DD

195 ODT0 116

77 ODT1,NC 197

V

DD

80

V

SS

198 S3,NC 119 SA2 239

200 DQ36

81 DQ32 201 DQ37

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

DQS17

NC,

TDQS17

,

V

V

SS

SS

82 DQ33 202

83

86

V

SS

V

SS

RESET 88 DQ35 208

V

SS

V

DD

91 DQ41 211

V

SS

DQS5 213

V

DD

V

DD

V

DD

94 DQS5 214

V

SS

97 DQ43 217

V

SS

100 DQ49 220

V

SS

DQS6 222

V

DD

V

DD

V

DD

V

DD

103 DQS6 223

104

107

110

V

SS

V

SS

V

SS

DQS7 231

V

DD

V

DD

V

DD

V

SS

112 DQS7 232

V

SS

115 DQ59 235

V

SS

118 SCL 238 SDA

120

V

TT

203

DM4,DQS13

206 DQ38

209 DQ44

212

DM5,DQS14

215 DQ46

218 DQ52

221

DM6,DQS15

224 DQ54

227 DQ60

230

DM7/DQS16

DM7,

233 DQ62

236

240

V

SS

,TDQS13

DQS13

NC,

,

TDQS13

V

SS

V

SS

V

SS

,TDQS14

DQS14

NC,

TDQS14

,

V

SS

V

SS

V

SS

,TDQS15

DQS15

NC,

TDQS15

,

V

SS

V

SS

V

SS

TDQS16

DQS16

,TDQS16

V

SS

V

SS

V

DDSPD

V

SS

V

TT

- 5 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

5. Pin Description

Pin Name Description Number Pin Name Description Number

CK0 Clock Input, positive line 1 ODT[1:0] On Die Termination Inputs 2

CK0 Clock Input, negative line 1 DQ[63:0] Data Input/Output 64

CKE[1:0] Clock Enables 2 CB[7:0] Data check bits Input/Output 8

RAS Row Address Strobe 1 DQS[8:0] Data strobes 9

CAS Column Address Strobe 1 DQS[8:0] Data strobes, negative line 9

DM[8:0]/

WE Write Enable 1

S[3:0] Chip Selects 4

A[9:0],A11,

A[15:13]

A10/AP Address Input/Autoprecharge 1 EVENT

A12/BC Address Input/Burst chop 1 TEST

BA[2:0] SDRAM Bank Addresses 3 RESET Register and SDRAM control pin 1

SCL Serial Presence Detect (SPD) Clock Input 1

SDA SPD Data Input/Output 1

SA[2:0] SPD Address Inputs 3

Par_In Parity bit for the Address and Control bus 1

Err_Out

NOTE :
* The V

DD

Address Inputs 2\14 RFU Reserved for Future Use 2

Parity error found on the Address and Control
bus

and V

pins are tied common to a single power-plane on these designs.

DDQ

1

DQS[17:9]

TDQS[17:9]

DQS[17:9]

TDQS[17:9]

V

DD

V

SS

V

REFDQ

V

REFCA

V

TT

V

DDSPD

Data Masks/ Data strobes,
Termination data strobes

Data strobes, negative line, Termination data
strobes

Reserved for optional hardware temperature
sensing

Memory bus test toll (Not Connected and Not
Usable on DIMMs)

Power Supply 22

Ground 59

Reference Voltage for DQ 1

Reference Voltage for CA 1

Termination Voltage 4

SPD Power 1

Total 240

9

9

1

1

6. ON DIMM Thermal Sensor

EVENT

NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM

2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not.

When only the SPD is placed on the module, R2 is placed but R1 is not.

[ Table 1 ] Temperature Sensor Characteristics

Grade Range

75 < Ta < 95 - +/- 0.5 +/- 1.0

B

40 < Ta < 125 - +/- 1.0 +/- 2.0 -

-20 < Ta < 125 - +/- 2.0 +/- 3.0 -

Resolution 0.25 C /LSB -

SCL

R1
0 

EVENT

WP/

SA0 SA1 SA2
R2
0 

SA0 SA1 SA2

Min. Typ. Max.

SDA

Temperature Sensor Accuracy

Units NOTE

-

C

- 6 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

7. Input/Output Functional Description

Symbol Type Polarity Function

CK0 Input

CK0 Input

CKE[1:0] Input Active High

S[3:0] Input Active Low

ODT[1:0] Input Active High On-Die Termination control signals

RAS, CAS, WE Input Active Low

V

REFDQ

V

REFCA

BA[2:0] Input

A[15:13,

12/BC,11,

10/AP,9:0]

DQ[63:0],

CB[7:0]

DM[8:0]

DQS[17:0] I/O Positive Edge Positive line of the differential data strobe for input and output data.

DQS[17:0] I/O Negative Edge Negative line of the differential data strobe for input and output data.

TDQS[17:9],

TDQS[17:9] OUT

SA[2:0] IN

SDA I/O

SCL IN

EVENT

V

DDSPD

RESET IN

Par_In IN Parity bit for the Address and Control bus. ("1 " : Odd, "0 ": Even)

Err_Out

TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)

Supply Reference voltage for DQ0-DQ63 and CB0-CB7

Supply Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1.

Input

I/O Data and Check Bit Input/Output pins

OUT
(open
drain)

Supply

OUT
(open
drain)

Positive

Edge

Negative

Edge

Active Low

Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver.

Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers
and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)

Enables the associated SDRAM command decoder when low and disables decoder when high.
When decoder is disabled, new commands are ignored and previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both
inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in
the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of reg­ister outputs.

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be exe­cuted by the SDRAM.

Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank
address also determines mode register is to be accessed during an MRS cycle.

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/
Write commands to select one location out of the memory array in the respective bank. A10 is sampled dur­ing a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8
identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during
Mode Register Set commands.

Active High Masks write data when high, issued concurrently with input data.

, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic.

V

DD

Supply Termination Voltage for Address/Command/Control/Clock nets.

V

TT

TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will
enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When dis­abled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.
X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1

These signals are tied at the system planar to either VSS or V
address range.

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to V

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to V

This signal indicates that a thermal event has been detected in the thermal sensing device.The system
should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part.

Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from

3.0 Volt to 3.6 Volt (nominal 3.3V) operation.

The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When
low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set
to low level (the Clock Driver will remain synchronized with the input clock)

Parity error detected on the Address and Control bus. A resistor may be connected from
bus line to VDD on the system planar to act as a pull up.

on the system planar to act as a pull-up.

DDSPD

on the system planar to act as a pull-up.

DDSPD

to configure the serial SPD EEPROM

DDSPD

Err_Out

- 7 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

8. Pinout Comparison Based On Module Type

Pin

48, 49

120, 240

53 Err_Out

63 NC

64 NC CK1

68 Par_In Connected to the register on all RDIMMs NC Not used on RDIMMs

76 S1 Connected to the register on all RDIMMs S1

77 ODT1, NC

79 S2, NC

167 NC TEST input used only on bus analysis probes NC

169 CKE1

171 A15

172 A14 A14

196 A13 A13

198 S3, NC

39, 40, 45, 46,
158, 159, 164,

165

125, 134, 143,
152, 161, 203,
212, 221, 230

126, 135, 144,
153, 162, 204,
213, 222, 231

187

NOTE : NC = No internal Connection

Signal NOTE Signal NOTE

V

TT

VTT

CBn Used on all RDIMMs; (n = 0...7) NC, CBn

DQSn,

TDQSn

DQSn,

TDQSn

EVENT

NC

Additional connection for Termination Voltage for
Address/Command/Control/Clock nets.

Termination Voltage for Address/Command/Con­trol/Clock nets.

Connected to the register on all RDIMMs NC Not
used on UDIMMs

Not used on RDIMMs

Connected to the register on dual- and quadrank
RDIMMs; NC on single-rank RDIMMs

Connected to the register on quad-rank
RDIMMs, not connected on single or dual rank
RDIMMs

Connected to the register on dual- and quadrank
RDIMMs; NC on single-rank RDIMMs

Connected to the register on all RDIMMs

Connected to the register on quad-rank
RDIMMs, not connected on single-or dual-rank
RDIMMs

Connected to DQS on x4 SDRAMs,
TDQS on x8 SDRAMs on RDIMMs; (n = 9...17)

Connected to DQS on x4 DRAMs, TDQS on x8
SDRAMs on RDIMMs; (n=9...17)

Connected to optional thermal sensing compo­nent.
NC on Modules without a thermal sensing
component.

RDIMM UDIMM

NC Not used on UDIMMs

V

TT

NC NC Not used on UDIMMs

CK1

ODT1,NC

NC Not used on UDIMMs

CKE1,

NC

A15, NC Depending on device density, may not be

NC Not used on UDIMMs

DMn

NC Not used on UDIMMs

NC Not used on UDIMMs

Termination Voltage for Address/Command/Con­trol/Clock nets.

Used for 2 rank UDIMMs, not used on single-rank
UDIMMs, but terminated

Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs

Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs

TEST input used only on bus analysis
probes

Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs

connected to SDRAMs on UDIMMs. However,
these signals are terminated on
UDIMMs. A15 not routed on some RCs

Used on x72 UDIMMs, (n = 0...7); not
used on x64 UDIMMs

Connected to DM on x8 DRAMs, UDM or
LDM on x16 DRAMs on UDIMMs;
(n = 0...8)

- 8 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

9. Registering Clock Driver Specification

9.1 Timing & Capacitance values

TC = TBD

= 1.5 0.075V

Symbol Parameter Conditions

fclock Input Clock Frequency application frequency 300 670 MHz

tCH/t

CL

t

ACT

t

SU

t

H

t

PDM

t

DIS

t

EN

CIN(DATA)

CIN(CLOCK)

C

(RST)

IN

Pulse duration, CK, CK HIGH or LOW 0.4 -

Inputs active time4 before RESET is taken HIGH

Setup time Input valid before CK/CK 100 - ps

Hold time

Propagation delay, single-bit switching CK/CK to output 0.65 1.0 ns

output disable time(1/2-Clock pre-launch)

output disable time(3/4-Clock pre-launch) 0.25 -

output enable time(1/2-Clock pre-launch)

output enable time(3/4-Clock pre-launch) - 0.25

Data Input Capacitance 1.5 2.5

Data Input Capacitance 2 3

Reset Input Capacitance - 3

DCKE0/1 = LOW and
DCS0/1 = HIGH

Input to remain Valid after CK/
CK

CK/CK to output float

CK/CK to output driving

V

DD

Min Max

8-

175 -

0.5 -

- 0.5

Units Notes

t

CK

t

CK

t

CK

t

CK

pF

9.2 Clock driver Characteristics

Symbol Parameter Conditions

t

jit

t

t

t

jit

t

jit

t

t

t

(cc)

STAB

t

fdyn

CKsk

(per)

(hper)

Qsk1

Qsk1

dynoff

Cycle-to-cycle period jitter 0 40 ps

Stabilization time -6us

Dynamic phase offset -50 50 ps

Clock Output skew 50 ps

Yn Clock Period jitter -40 40 ps

Half period jitter -50 50 ps

Qn Output to clock tolerance (Standard 1/2 -Clock
Pre-Launch)

Output clock tolerance (3/4 Clock Pre-Launch)

Maximum re-driven dynamic clock off-set -80 80 ps

Output Inversion enabled -100 200

OUtput Inversion disabled -100 300

Output Inversion enabled -100 200

OUtput Inversion disabled -100 300

TC = TBD

VDD = 1.5 0.075V

Min Max

Units Notes

ps

ps

- 9 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

10. Function Block Diagram:

10.1 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)

RS0A

RRASA

RCASA

RWEA

PCK0A

RCKE0A

RODT0A

A[N:0]A

DQS17
DQS17

VSS

CB[7:4]

DQS12
DQS12

VSS

DQ[31:28]

DQS11
DQS11

VSS

DQ[23:20]

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

PCK0A

D17

RAS

CASWECKCKCKE

D12

RAS

CASWECKCKCKE

D11

RAS

CASWECKCKCKE

/BA[N:0]A

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

RS1A

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

PCK1A

D17B

RAS

CASWECKCKCKE

D12B

RAS

CASWECKCKCKE

D11B

RAS

CASWECKCKCKE

PCK1A

RCKE1A

RODT1A

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

DQS8
DQS8

VSS

CB[3:0]

DQS3
DQS3

VSS

DQ[27:24]

DQS2
DQS2

VSS

DQ[19:16]

RS0A

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

RRASA

RCASA

RWEA

PCK0A

D8

RAS

CASWECKCKCKE

D3

RAS

CASWECKCKCKE

D2

RAS

CASWECKCKCKE

PCK0A

RCKE0A

RODT0A

A[N:0]A

/BA[N:0]A

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

RS1A

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

PCK1A

D8B

RAS

CASWECKCKCKE

D3B

RAS

CASWECKCKCKE

D2B

RAS

CASWECKCKCKE

PCK1A

RCKE1A

RODT1A

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

DQS10
DQS10

VSS

DQ[15:12]

DQS0
DQS0

VSS

DQ[3:0]

DQS
DQS
DM

D10

DQ[3:0]

CS

RAS

CASWECKCKCKE

DQS
DQS
DM
DQ[3:0]

CS

RAS

CASWECKCKCKE

Vtt

ODT

D0

ODT

DQS
DQS
DM
DQ[3:0]

A[N:0]/BA[N:0]

DQS
DQS
DM
DQ[3:0]

A[N:0]/BA[N:0]

CS

RAS

CASWECKCKCKE

CS

RAS

CASWECKCKCKE

D10B

D0B

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

DQS1
DQS1

VSS

DQ[11:8]

DQS9
DQS9

VSS

DQ[7:4]

DQS
DQS
DM

D1

DQ[3:0]

CS

RAS

CASWECKCKCKE

DQS
DQS
DM
DQ[3:0]

CS

RAS

CASWECKCKCKE

Vtt

ODT

D9

ODT

DQS
DQS
DM
DQ[3:0]

A[N:0]/BA[N:0]

DQS
DQS
DM
DQ[3:0]

A[N:0]/BA[N:0]

D1B

CS

RAS

CASWECKCKCKE

D9B

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

- 10 -

Rev. 1.1

Registered DIMM

RS0B

DQS4
DQS4

VSS

CB[35:32]

DQS5
DQS5

VSS

DQ[43:40]

DQS6
DQS6

VSS

DQ[51:48]

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

RRASB

RCASB

RWEB

PCK0B

D4

RAS

CASWECKCKCKE

D5

RAS

CASWECKCKCKE

D6

RAS

CASWECKCKCKE

PCK0B

RCKE0B

RODT0B

/BA[N:0]B

A[N:0]B

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

RS1B

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

datasheet DDR3 SDRAM

PCK1B

PCK1B

RCKE1B

D4B

RAS

CASWECKCKCKE

D5B

RAS

CASWECKCKCKE

D6B

RAS

CASWECKCKCKE

RODT1B

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

DQS13
DQS13

VSS

CB[39:36]

DQS14
DQS14

VSS

DQ[47:44]

DQS15
DQS15

VSS

DQ[55:52]

RS0B

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

RRASB

RCASB

RWEB

PCK0B

D13

RAS

CASWECKCKCKE

D14

RAS

CASWECKCKCKE

D15

RAS

CASWECKCKCKE

PCK0B

RCKE0B

RODT0B

/BA[N:0]B

A[N:0]B

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

RS1B

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

PCK1B

D13B

RAS

CASWECKCKCKE

D14B

RAS

CASWECKCKCKE

D15B

RAS

CASWECKCKCKE

PCK1B

RCKE1B

RODT1B

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

DQS7
DQS7

VSS

DQ[59:56]

DQS
DQS
DM
DQ[3:0]

CS

D7

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS
DQS
DM
DQ[3:0]

CS

D7B

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS16
DQS16

DQ[63:60]

Vtt

Integrated Thermal sensor in SPD

SCL

EVENT EVENT

A0

A1 A2

SDA

SA0 SA1 SA2

Serial PD w/ integrated Thermal sensor

V

DDSPD

V

DD

V

TT

V

REFCA

V

REFDQ

V

SS

Serial PD

D0 - D35

D0 - D35

D0 - D35

D0 - D35

NOTE:

1. See wiring diagrams for resistor values.

2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240 +/-1%)ohms...

VSS

DQS
DQS
DM
DQ[3:0]

CS

D16

RAS

CASWECKCKCKE

ODT

DQS
DQS
DM
DQ[3:0]

A[N:0]/BA[N:0]

D16B

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

Vtt

RS0A -> CS0 : SDRAMs D[3:0], D[12:8], D17
RS0B -> CS0 : SDRAMs D[7:4]B, D[16:13] B

RS1A -> CS1 : SDRAMs D[3:0]B, D[12:8]B, D17B
RS1B -> CS1 : SDRAMs D[7:4], D[16:13]

RBA[N:0]A -> BA[N:0]: SDRAMs D[3:0], D[12:8], D17,D[3:0]B, D[12:8]B, D17B
RBA[N:0]B -> BA[N:0]: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B

RA[N:0]A -> A[N:0]: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B
RA[N:0]B -> A[N:0]: SDRAMs D[7:4], D[16:13], D[7:4], D[16:13]B

RRASA -> RAS: SDRAMs D[3:0], D[12:8],D17, D[3:0]B, D[12:8]B, D17B
RRASB -> RAS: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B

RCASA -> CAS: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B
RCASB -> CAS: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B

1:2

RWEA -> WE: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B

R

RWEB -> WE: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B

E

RCKE0A -> CKE0: SDRAMs D[3:0], D[12:8], D17

G

RCKE0B -> CKE0: SDRAMs D[7:4]B, D[16:13]B

I

RCKE1A -> CKE1: SDRAMs D[3:0], D[12:8]B, D17B

S

RCKE1B -> CKE1: SDRAMs D[7:4], D[16:13]

T

RODT0A -> ODT0: SDRAMs D[3:0], D[12:8], D17

E

RODT0B -> ODT0: SDRAMs D[7:4]B, D[16:13]B

R

RODT1A -> ODT1: SDRAMs D[3:0]B, D[12:8]B, D17B

RODT1B -> ODT1: SDRAMs D[7:4], D[16:13]
PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4]B, D[16:13]B

PCK1A -> CK: SDRAMs D[3:0]B, D[12:8]B, D17B
PCK1B -> CK: SDRAMs D[7:4], D[16:13]

PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4]B, D[16:13]B

PCK1A -> CK: SDRAMs D[3:0]B, D[12:8]B, D17B
PCK1B -> CK: SDRAMs D[7:4], D[16:13]



ERR_OUT

RST

RST : SDRAMs D[17:0], D[17:0]B

BA[N:0]

A[N:0]

RAS

CAS

WE

CKE0

CKE1

ODT0

ODT1

S0

S1

CK0

CK0

CK1
CK1

PAR_IN

RESET

120

- 11 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

10. Absolute Maximum Ratings

10.1 Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

V

DD

Voltage on V

V

DDQ

V

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. VDD and V

equal to or less than 300mV.

Voltage on any pin relative to V

IN, VOUT

T

Storage Temperature -55 to +100 C 1, 2

STG

DDQ

10.2 DRAM Component Operating Temperature Range

Symbol Parameter rating Unit NOTE

T

OPER

NOTE :

1. Operating Temperature T
JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main­tained between 0-85C under all operating conditions

3. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature

Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.

Voltage on VDD pin relative to V

pin relative to V

DDQ

must be within 300mV of each other at all times; and V

SS

SS

SS

Operating Temperature Range 0 to 95 C 1, 2, 3

is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document

OPER

-0.4 V ~ 1.975 V V 1,3

-0.4 V ~ 1.975 V V 1,3

-0.4 V ~ 1.975 V V 1

must be not greater than 0.6 x V

REF

, When VDD and V

DDQ

are less than 500mV; V

DDQ

REF

may be

11. AC & DC Operating Conditions

11.1 Recommended DC Operating Conditions (SSTL-15)

Symbol Parameter

V

DD

V

DDQ

NOTE:

1. Under all conditions V

tracks with VDD. AC parameters are measured with VDD and V

2. V

DDQ

Supply Voltage 1.425 1.5 1.575 V 1,2

Supply Voltage for Output 1.425 1.5 1.575 V 1,2

must be less than or equal to VDD.

DDQ

tied together.

DDQ

Min. Typ. Max.

Rating

Units NOTE

- 13 -