Samsung M393B1K70QB0-CMA User Manual

Rev.1.1, Aug. 2013

240pin Registered DIMM

based on 2Gb Q-die

78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)

M393B1K70QB0

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other­wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

2013 Samsung Electronics Co., Ltd. All rights reserved.

- 1 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

Revision History

Revision No. History Draft Date Remark Editor

1.0 - First SPEC. Release Jun. 2013 - S.H.Kim

1.1 - Deleted by changing line-up (4GB : 1Rx4, 2Rx8) Aug. 2013 - S.H.Kim

- 2 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

Table Of Contents

240pin Registered DIMM based on 2Gb Q-die

1. DDR3 Registered DIMM Ordering Information .............................................................................................................4

2. Key Features.................................................................................................................................................................4

3. Address Configuration ..................................................................................................................................................4

4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................5

5. Pin Description .............................................................................................................................................................6

6. ON DIMM Thermal Sensor ...........................................................................................................................................6

7. Input/Output Functional Description..............................................................................................................................7

8. Pinout Comparison Based On Module Type.................................................................................................................8

9. Registering Clock Driver Specification..........................................................................................................................9

9.1 Timing & Capacitance values .................................................................................................................................. 9

9.2 Clock driver Characteristics.....................................................................................................................................9

10. Function Block Diagram:.............................................................................................................................................10

10.1 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)......................................................................10

11. Absolute Maximum Ratings ........................................................................................................................................12

11.1 Absolute Maximum DC Ratings............................................................................................................................. 12

11.2 DRAM Component Operating Temperature Range ..............................................................................................12

12. AC & DC Operating Conditions...................................................................................................................................12

12.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................ 12

13. AC & DC Input Measurement Levels ..........................................................................................................................13

13.1 AC & DC Logic Input Levels for Single-ended Signals..........................................................................................13

13.2 V

13.3 AC and DC Logic Input Levels for Differential Signals ..........................................................................................16

13.3.1. Differential Signals Definition ......................................................................................................................... 16

13.3.2. Differential Swing Requirement for Clock (CK -

13.3.3. Single-ended Requirements for Differential Signals ......................................................................................18

13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 19

13.4 Slew Rate Definition for Single Ended Input Signals.............................................................................................19

13.5 Slew rate definition for Differential Input Signals ................................................................................................... 19

14. AC & DC Output Measurement Levels .......................................................................................................................20

14.1 Single Ended AC and DC Output Levels...............................................................................................................20

14.2 Differential AC and DC Output Levels ................................................................................................................... 20

14.3 Single-ended Output Slew Rate ............................................................................................................................ 20

14.4 Differential Output Slew Rate ................................................................................................................................ 21

15. DIMM IDD specification definition ...............................................................................................................................22

16. IDD SPEC Table .........................................................................................................................................................24

17. Input/Output Capacitance ...........................................................................................................................................25

18. Electrical Characteristics and AC timing .....................................................................................................................26

18.1 Refresh Parameters by Device Density................................................................................................................. 26

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................26

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 26

18.3.1. Speed Bin Table Notes .................................................................................................................................. 30

19. Timing Parameters by Speed Grade ..........................................................................................................................31

19.1 Jitter Notes ............................................................................................................................................................37

19.2 Timing Parameter Notes........................................................................................................................................ 38

20. Physical Dimensions...................................................................................................................................................39

20.1 512Mbx4 based 1Gx72 Module (2 Ranks) - M393B1K70QB0..............................................................................39

20.1.1. x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs...............................................................39

Tolerances.................................................................................................................................................... 15

REF

CK) and Strobe (DQS - DQS) ............................................. 16

- 3 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

1. DDR3 Registered DIMM Ordering Information

Part Number

M393B1K70QB0-CK0/MA 8GB 1Gx72 512Mx4(K4B2G0446Q-BC##)*36 2 30mm

NOTE :

1. "##" - K0/MA

2. K0(1600Mbps 11-11-11) / MA(1866Mbps 13-13-13)

- DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11)

3. Please contact Samsung for product availability.

2

Density Organization

Component Composition

1

Number of

Rank

2. Key Features

Speed

tCK(min) 2.5 1.875 1.5 1.25 1.071 ns

CAS Latency 6 7 9 11 13 nCK

tRCD(min) 15 13.125 13.5 13.75 13.91 ns

tRP(min) 15 13.125 13.5 13.75 13.91 ns

tRAS(min) 37.5 37.5 36 35 34 ns

tRC(min) 52.5 50.625 49.5 48.75 47.91 ns

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

6-6-6 7-7-7 9-9-9 11-11-11 13-13-13

Height

Unit

• JEDEC standard 1.5V ± 0.075V Power Supply

•V

= 1.5V ± 0.075V

DDQ

• 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin,
933MHz fCK for 1866Mb/sec/pin

• 8 independent internal bank

• Programmable CAS Latency: 6,7,8,9,10,11,13

• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9 (DDR3-1866)

• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or

write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

• Asynchronous Reset

85C, 3.9us at 85C < T

CASE

CASE

95C

3. Address Configuration

Organization Row Address Column Address Bank Address Auto Precharge

512Mx4(2Gb) based Module A0-A14 A0-A9, A11 BA0-BA2 A10/AP

- 4 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

4. Registered DIMM Pin Configurations (Front side/Back side)

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1

2

V

REFDQ

V

121

SS

122 DQ4 43 DQS8 163

3 DQ0 123 DQ5 44

4 DQ1 124

5

6

V

SS

125

DQS0 126

7 DQS0 127

8

V

SS

128 DQ6 KEY 89

9 DQ2 129 DQ7 49

10 DQ3 130

11

V

SS

131 DQ12 51

12 DQ8 132 DQ13 52 BA2 172 A14 93

13 DQ9 133

14

15

V

SS

134

DQS1 135

16 DQS1 136

17

V

SS

137 DQ14 57

18 DQ10 138 DQ15 58 A5 178 A6 99 DQ48 219 DQ53

19 DQ11 139

20

V

SS

140 DQ20 60

21 DQ16 141 DQ21 61 A2 181 A1 102

22 DQ17 142

23

24

V

SS

143

DQS2 144

25 DQS2 145

26

V

SS

146 DQ22 66

27 DQ18 147 DQ23 67

28 DQ19 148

29

V

SS

149 DQ28 69

30 DQ24 150 DQ29 70 A10/AP 190 BA1 111

31 DQ25 151

32

33

V

SS

152

DQS3 153

34 DQS3 154

35

V

SS

155 DQ30 75

36 DQ26 156 DQ31 76 S1,NC 196 A13 117 SA0 237 SA1

37 DQ27 157

38

V

SS

158 CB4,NC 78

39 CB0,NC 159 CB5,NC 79 S2,NC 199

40 CB1,NC 160

41

V

SS

161

NOTE : NC = No internal Connection

V

SS

V

SS

DM0,DQS9

,TDQS9

DQS9

NC,

TDQS9

,

V

SS

V

SS

V

SS

DM1,DQS10

,TDQS10

DQS10

NC,

TDQS10

,

V

SS

V

SS

V

SS

DM2,DQS11

,TDQS11

DQS11

NC,

TDQS11

,

V

SS

V

SS

V

SS

DM3,DQS12

,TDQS12

DQS12

NC,

TDQS12

,

V

SS

V

SS

V

SS

DM8,DQS17
TDQS17,NC

42 DQS8 162

V

SS

164 CB6,NC 84 DQS4 204

45 CB2,NC 165 CB7,NC 85 DQS4 205

46 CB3,NC 166

47

48

V

SS

, NC

V

TT

V

, NC

TT

167 NC(TEST) 87 DQ34 207 DQ39

168

169 CKE1, NC 90 DQ40 210 DQ45

50 CKE0 170

V

DD

171 NC 92

53 Err_Out/NC 173

54

V

DD

174 A12/BC 95

55 A11 175 A9 96 DQ42 216 DQ47

56 A7 176

V

DD

177 A8 98

59 A4 179

V

DD

62

V

DD

180 A3 101

182

63 NC, CK1 183

64 NC,

65

CK1 184 CK0 105 DQ50 225 DQ55

V

V

V

REFCA

DD

DD

185 CK0 106 DQ51 226

186

187 EVENT,NC 108 DQ56 228 DQ61

68 NC/Par_In 188 A0 109 DQ57 229

V

DD

189

71 BA0 191

72

73

V

DD

WE 193 S0 114 DQ58 234 DQ63

192 RAS 113

74 CAS 194

V

DD

195 ODT0 116

77 ODT1,NC 197

V

DD

80

V

SS

198 S3,NC 119 SA2 239

200 DQ36

81 DQ32 201 DQ37

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

DQS17

NC,

TDQS17

,

V

V

SS

SS

82 DQ33 202

83

86

V

SS

V

SS

RESET 88 DQ35 208

V

SS

V

DD

91 DQ41 211

V

SS

DQS5 213

V

DD

V

DD

V

DD

94 DQS5 214

V

SS

97 DQ43 217

V

SS

100 DQ49 220

V

SS

DQS6 222

V

DD

V

DD

V

DD

V

DD

103 DQS6 223

104

107

110

V

SS

V

SS

V

SS

DQS7 231

V

DD

V

DD

V

DD

V

SS

112 DQS7 232

V

SS

115 DQ59 235

V

SS

118 SCL 238 SDA

120

V

TT

203

DM4,DQS13

206 DQ38

209 DQ44

212

DM5,DQS14

215 DQ46

218 DQ52

221

DM6,DQS15

224 DQ54

227 DQ60

230

DM7/DQS16

DM7,

233 DQ62

236

240

V

SS

,TDQS13

DQS13

NC,

,

TDQS13

V

SS

V

SS

V

SS

,TDQS14

DQS14

NC,

TDQS14

,

V

SS

V

SS

V

SS

,TDQS15

DQS15

NC,

TDQS15

,

V

SS

V

SS

V

SS

TDQS16

DQS16

,TDQS16

V

SS

V

SS

V

DDSPD

V

SS

V

TT

- 5 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

5. Pin Description

Pin Name Description Number Pin Name Description Number

CK0 Clock Input, positive line 1 ODT[1:0] On Die Termination Inputs 2

CK0 Clock Input, negative line 1 DQ[63:0] Data Input/Output 64

CKE[1:0] Clock Enables 2 CB[7:0] Data check bits Input/Output 8

RAS Row Address Strobe 1 DQS[8:0] Data strobes 9

CAS Column Address Strobe 1 DQS[8:0] Data strobes, negative line 9

DM[8:0]/

WE Write Enable 1

S[3:0] Chip Selects 4

A[9:0],A11,

A[15:13]

A10/AP Address Input/Autoprecharge 1 EVENT

A12/BC Address Input/Burst chop 1 TEST

BA[2:0] SDRAM Bank Addresses 3 RESET Register and SDRAM control pin 1

SCL Serial Presence Detect (SPD) Clock Input 1

SDA SPD Data Input/Output 1

SA[2:0] SPD Address Inputs 3

Par_In Parity bit for the Address and Control bus 1

Err_Out

NOTE :
* The V

DD

Address Inputs 2\14 RFU Reserved for Future Use 2

Parity error found on the Address and Control
bus

and V

pins are tied common to a single power-plane on these designs.

DDQ

1

DQS[17:9]

TDQS[17:9]

DQS[17:9]

TDQS[17:9]

V

DD

V

SS

V

REFDQ

V

REFCA

V

TT

V

DDSPD

Data Masks/ Data strobes,
Termination data strobes

Data strobes, negative line, Termination data
strobes

Reserved for optional hardware temperature
sensing

Memory bus test toll (Not Connected and Not
Usable on DIMMs)

Power Supply 22

Ground 59

Reference Voltage for DQ 1

Reference Voltage for CA 1

Termination Voltage 4

SPD Power 1

Total 240

9

9

1

1

6. ON DIMM Thermal Sensor

EVENT

NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM

2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not.

When only the SPD is placed on the module, R2 is placed but R1 is not.

[ Table 1 ] Temperature Sensor Characteristics

Grade Range

75 < Ta < 95 - +/- 0.5 +/- 1.0

B

40 < Ta < 125 - +/- 1.0 +/- 2.0 -

-20 < Ta < 125 - +/- 2.0 +/- 3.0 -

Resolution 0.25 C /LSB -

SCL

R1
0 

EVENT

WP/

SA0 SA1 SA2
R2
0 

SA0 SA1 SA2

Min. Typ. Max.

SDA

Temperature Sensor Accuracy

Units NOTE

-

C

- 6 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

7. Input/Output Functional Description

Symbol Type Polarity Function

CK0 Input

CK0 Input

CKE[1:0] Input Active High

S[3:0] Input Active Low

ODT[1:0] Input Active High On-Die Termination control signals

RAS, CAS, WE Input Active Low

V

REFDQ

V

REFCA

BA[2:0] Input

A[15:13,

12/BC,11,

10/AP,9:0]

DQ[63:0],

CB[7:0]

DM[8:0]

DQS[17:0] I/O Positive Edge Positive line of the differential data strobe for input and output data.

DQS[17:0] I/O Negative Edge Negative line of the differential data strobe for input and output data.

TDQS[17:9],

TDQS[17:9] OUT

SA[2:0] IN

SDA I/O

SCL IN

EVENT

V

DDSPD

RESET IN

Par_In IN Parity bit for the Address and Control bus. ("1 " : Odd, "0 ": Even)

Err_Out

TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)

Supply Reference voltage for DQ0-DQ63 and CB0-CB7

Supply Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1.

Input

I/O Data and Check Bit Input/Output pins

OUT
(open
drain)

Supply

OUT
(open
drain)

Positive

Edge

Negative

Edge

Active Low

Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver.

Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers
and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)

Enables the associated SDRAM command decoder when low and disables decoder when high.
When decoder is disabled, new commands are ignored and previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both
inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in
the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of reg­ister outputs.

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be exe­cuted by the SDRAM.

Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank
address also determines mode register is to be accessed during an MRS cycle.

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/
Write commands to select one location out of the memory array in the respective bank. A10 is sampled dur­ing a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8
identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during
Mode Register Set commands.

Active High Masks write data when high, issued concurrently with input data.

, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic.

V

DD

Supply Termination Voltage for Address/Command/Control/Clock nets.

V

TT

TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will
enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When dis­abled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.
X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1

These signals are tied at the system planar to either VSS or V
address range.

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to V

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to V

This signal indicates that a thermal event has been detected in the thermal sensing device.The system
should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part.

Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from

3.0 Volt to 3.6 Volt (nominal 3.3V) operation.

The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When
low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set
to low level (the Clock Driver will remain synchronized with the input clock)

Parity error detected on the Address and Control bus. A resistor may be connected from
bus line to VDD on the system planar to act as a pull up.

on the system planar to act as a pull-up.

DDSPD

on the system planar to act as a pull-up.

DDSPD

to configure the serial SPD EEPROM

DDSPD

Err_Out

- 7 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

8. Pinout Comparison Based On Module Type

Pin

48, 49

120, 240

53 Err_Out

63 NC

64 NC CK1

68 Par_In Connected to the register on all RDIMMs NC Not used on RDIMMs

76 S1 Connected to the register on all RDIMMs S1

77 ODT1, NC

79 S2, NC

167 NC TEST input used only on bus analysis probes NC

169 CKE1

171 A15

172 A14 A14

196 A13 A13

198 S3, NC

39, 40, 45, 46,
158, 159, 164,

165

125, 134, 143,
152, 161, 203,
212, 221, 230

126, 135, 144,
153, 162, 204,
213, 222, 231

187

NOTE : NC = No internal Connection

Signal NOTE Signal NOTE

V

TT

VTT

CBn Used on all RDIMMs; (n = 0...7) NC, CBn

DQSn,

TDQSn

DQSn,

TDQSn

EVENT

NC

Additional connection for Termination Voltage for
Address/Command/Control/Clock nets.

Termination Voltage for Address/Command/Con­trol/Clock nets.

Connected to the register on all RDIMMs NC Not
used on UDIMMs

Not used on RDIMMs

Connected to the register on dual- and quadrank
RDIMMs; NC on single-rank RDIMMs

Connected to the register on quad-rank
RDIMMs, not connected on single or dual rank
RDIMMs

Connected to the register on dual- and quadrank
RDIMMs; NC on single-rank RDIMMs

Connected to the register on all RDIMMs

Connected to the register on quad-rank
RDIMMs, not connected on single-or dual-rank
RDIMMs

Connected to DQS on x4 SDRAMs,
TDQS on x8 SDRAMs on RDIMMs; (n = 9...17)

Connected to DQS on x4 DRAMs, TDQS on x8
SDRAMs on RDIMMs; (n=9...17)

Connected to optional thermal sensing compo­nent.
NC on Modules without a thermal sensing
component.

RDIMM UDIMM

NC Not used on UDIMMs

V

TT

NC NC Not used on UDIMMs

CK1

ODT1,NC

NC Not used on UDIMMs

CKE1,

NC

A15, NC Depending on device density, may not be

NC Not used on UDIMMs

DMn

NC Not used on UDIMMs

NC Not used on UDIMMs

Termination Voltage for Address/Command/Con­trol/Clock nets.

Used for 2 rank UDIMMs, not used on single-rank
UDIMMs, but terminated

Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs

Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs

TEST input used only on bus analysis
probes

Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs

connected to SDRAMs on UDIMMs. However,
these signals are terminated on
UDIMMs. A15 not routed on some RCs

Used on x72 UDIMMs, (n = 0...7); not
used on x64 UDIMMs

Connected to DM on x8 DRAMs, UDM or
LDM on x16 DRAMs on UDIMMs;
(n = 0...8)

- 8 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

9. Registering Clock Driver Specification

9.1 Timing & Capacitance values

TC = TBD

= 1.5 0.075V

Symbol Parameter Conditions

fclock Input Clock Frequency application frequency 300 670 MHz

tCH/t

CL

t

ACT

t

SU

t

H

t

PDM

t

DIS

t

EN

CIN(DATA)

CIN(CLOCK)

C

(RST)

IN

Pulse duration, CK, CK HIGH or LOW 0.4 -

Inputs active time4 before RESET is taken HIGH

Setup time Input valid before CK/CK 100 - ps

Hold time

Propagation delay, single-bit switching CK/CK to output 0.65 1.0 ns

output disable time(1/2-Clock pre-launch)

output disable time(3/4-Clock pre-launch) 0.25 -

output enable time(1/2-Clock pre-launch)

output enable time(3/4-Clock pre-launch) - 0.25

Data Input Capacitance 1.5 2.5

Data Input Capacitance 2 3

Reset Input Capacitance - 3

DCKE0/1 = LOW and
DCS0/1 = HIGH

Input to remain Valid after CK/
CK

CK/CK to output float

CK/CK to output driving

V

DD

Min Max

8-

175 -

0.5 -

- 0.5

Units Notes

t

CK

t

CK

t

CK

t

CK

pF

9.2 Clock driver Characteristics

Symbol Parameter Conditions

t

jit

t

t

t

jit

t

jit

t

t

t

(cc)

STAB

t

fdyn

CKsk

(per)

(hper)

Qsk1

Qsk1

dynoff

Cycle-to-cycle period jitter 0 40 ps

Stabilization time -6us

Dynamic phase offset -50 50 ps

Clock Output skew 50 ps

Yn Clock Period jitter -40 40 ps

Half period jitter -50 50 ps

Qn Output to clock tolerance (Standard 1/2 -Clock
Pre-Launch)

Output clock tolerance (3/4 Clock Pre-Launch)

Maximum re-driven dynamic clock off-set -80 80 ps

Output Inversion enabled -100 200

OUtput Inversion disabled -100 300

Output Inversion enabled -100 200

OUtput Inversion disabled -100 300

TC = TBD

VDD = 1.5 0.075V

Min Max

Units Notes

ps

ps

- 9 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

10. Function Block Diagram:

10.1 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)

RS0A

RRASA

RCASA

RWEA

PCK0A

RCKE0A

RODT0A

A[N:0]A

DQS17
DQS17

VSS

CB[7:4]

DQS12
DQS12

VSS

DQ[31:28]

DQS11
DQS11

VSS

DQ[23:20]

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

PCK0A

D17

RAS

CASWECKCKCKE

D12

RAS

CASWECKCKCKE

D11

RAS

CASWECKCKCKE

/BA[N:0]A

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

RS1A

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

PCK1A

D17B

RAS

CASWECKCKCKE

D12B

RAS

CASWECKCKCKE

D11B

RAS

CASWECKCKCKE

PCK1A

RCKE1A

RODT1A

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

DQS8
DQS8

VSS

CB[3:0]

DQS3
DQS3

VSS

DQ[27:24]

DQS2
DQS2

VSS

DQ[19:16]

RS0A

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

RRASA

RCASA

RWEA

PCK0A

D8

RAS

CASWECKCKCKE

D3

RAS

CASWECKCKCKE

D2

RAS

CASWECKCKCKE

PCK0A

RCKE0A

RODT0A

A[N:0]A

/BA[N:0]A

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

RS1A

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

PCK1A

D8B

RAS

CASWECKCKCKE

D3B

RAS

CASWECKCKCKE

D2B

RAS

CASWECKCKCKE

PCK1A

RCKE1A

RODT1A

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

DQS10
DQS10

VSS

DQ[15:12]

DQS0
DQS0

VSS

DQ[3:0]

DQS
DQS
DM

D10

DQ[3:0]

CS

RAS

CASWECKCKCKE

DQS
DQS
DM
DQ[3:0]

CS

RAS

CASWECKCKCKE

Vtt

ODT

D0

ODT

DQS
DQS
DM
DQ[3:0]

A[N:0]/BA[N:0]

DQS
DQS
DM
DQ[3:0]

A[N:0]/BA[N:0]

CS

RAS

CASWECKCKCKE

CS

RAS

CASWECKCKCKE

D10B

D0B

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

DQS1
DQS1

VSS

DQ[11:8]

DQS9
DQS9

VSS

DQ[7:4]

DQS
DQS
DM

D1

DQ[3:0]

CS

RAS

CASWECKCKCKE

DQS
DQS
DM
DQ[3:0]

CS

RAS

CASWECKCKCKE

Vtt

ODT

D9

ODT

DQS
DQS
DM
DQ[3:0]

A[N:0]/BA[N:0]

DQS
DQS
DM
DQ[3:0]

A[N:0]/BA[N:0]

D1B

CS

RAS

CASWECKCKCKE

D9B

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

- 10 -

Rev. 1.1

Registered DIMM

RS0B

DQS4
DQS4

VSS

CB[35:32]

DQS5
DQS5

VSS

DQ[43:40]

DQS6
DQS6

VSS

DQ[51:48]

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

RRASB

RCASB

RWEB

PCK0B

D4

RAS

CASWECKCKCKE

D5

RAS

CASWECKCKCKE

D6

RAS

CASWECKCKCKE

PCK0B

RCKE0B

RODT0B

/BA[N:0]B

A[N:0]B

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

RS1B

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

datasheet DDR3 SDRAM

PCK1B

PCK1B

RCKE1B

D4B

RAS

CASWECKCKCKE

D5B

RAS

CASWECKCKCKE

D6B

RAS

CASWECKCKCKE

RODT1B

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

DQS13
DQS13

VSS

CB[39:36]

DQS14
DQS14

VSS

DQ[47:44]

DQS15
DQS15

VSS

DQ[55:52]

RS0B

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

RRASB

RCASB

RWEB

PCK0B

D13

RAS

CASWECKCKCKE

D14

RAS

CASWECKCKCKE

D15

RAS

CASWECKCKCKE

PCK0B

RCKE0B

RODT0B

/BA[N:0]B

A[N:0]B

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

RS1B

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

DQS
DQS
DM
DQ[3:0]

CS

PCK1B

D13B

RAS

CASWECKCKCKE

D14B

RAS

CASWECKCKCKE

D15B

RAS

CASWECKCKCKE

PCK1B

RCKE1B

RODT1B

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

DQS7
DQS7

VSS

DQ[59:56]

DQS
DQS
DM
DQ[3:0]

CS

D7

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS
DQS
DM
DQ[3:0]

CS

D7B

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

DQS16
DQS16

DQ[63:60]

Vtt

Integrated Thermal sensor in SPD

SCL

EVENT EVENT

A0

A1 A2

SDA

SA0 SA1 SA2

Serial PD w/ integrated Thermal sensor

V

DDSPD

V

DD

V

TT

V

REFCA

V

REFDQ

V

SS

Serial PD

D0 - D35

D0 - D35

D0 - D35

D0 - D35

NOTE:

1. See wiring diagrams for resistor values.

2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240 +/-1%)ohms...

VSS

DQS
DQS
DM
DQ[3:0]

CS

D16

RAS

CASWECKCKCKE

ODT

DQS
DQS
DM
DQ[3:0]

A[N:0]/BA[N:0]

D16B

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

Vtt

RS0A -> CS0 : SDRAMs D[3:0], D[12:8], D17
RS0B -> CS0 : SDRAMs D[7:4]B, D[16:13] B

RS1A -> CS1 : SDRAMs D[3:0]B, D[12:8]B, D17B
RS1B -> CS1 : SDRAMs D[7:4], D[16:13]

RBA[N:0]A -> BA[N:0]: SDRAMs D[3:0], D[12:8], D17,D[3:0]B, D[12:8]B, D17B
RBA[N:0]B -> BA[N:0]: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B

RA[N:0]A -> A[N:0]: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B
RA[N:0]B -> A[N:0]: SDRAMs D[7:4], D[16:13], D[7:4], D[16:13]B

RRASA -> RAS: SDRAMs D[3:0], D[12:8],D17, D[3:0]B, D[12:8]B, D17B
RRASB -> RAS: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B

RCASA -> CAS: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B
RCASB -> CAS: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B

1:2

RWEA -> WE: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B

R

RWEB -> WE: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B

E

RCKE0A -> CKE0: SDRAMs D[3:0], D[12:8], D17

G

RCKE0B -> CKE0: SDRAMs D[7:4]B, D[16:13]B

I

RCKE1A -> CKE1: SDRAMs D[3:0], D[12:8]B, D17B

S

RCKE1B -> CKE1: SDRAMs D[7:4], D[16:13]

T

RODT0A -> ODT0: SDRAMs D[3:0], D[12:8], D17

E

RODT0B -> ODT0: SDRAMs D[7:4]B, D[16:13]B

R

RODT1A -> ODT1: SDRAMs D[3:0]B, D[12:8]B, D17B

RODT1B -> ODT1: SDRAMs D[7:4], D[16:13]
PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4]B, D[16:13]B

PCK1A -> CK: SDRAMs D[3:0]B, D[12:8]B, D17B
PCK1B -> CK: SDRAMs D[7:4], D[16:13]

PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4]B, D[16:13]B

PCK1A -> CK: SDRAMs D[3:0]B, D[12:8]B, D17B
PCK1B -> CK: SDRAMs D[7:4], D[16:13]



ERR_OUT

RST

RST : SDRAMs D[17:0], D[17:0]B

BA[N:0]

A[N:0]

RAS

CAS

WE

CKE0

CKE1

ODT0

ODT1

S0

S1

CK0

CK0

CK1
CK1

PAR_IN

RESET

120

- 11 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

10. Absolute Maximum Ratings

10.1 Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

V

DD

Voltage on V

V

DDQ

V

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. VDD and V

equal to or less than 300mV.

Voltage on any pin relative to V

IN, VOUT

T

Storage Temperature -55 to +100 C 1, 2

STG

DDQ

10.2 DRAM Component Operating Temperature Range

Symbol Parameter rating Unit NOTE

T

OPER

NOTE :

1. Operating Temperature T
JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main­tained between 0-85C under all operating conditions

3. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature

Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.

Voltage on VDD pin relative to V

pin relative to V

DDQ

must be within 300mV of each other at all times; and V

SS

SS

SS

Operating Temperature Range 0 to 95 C 1, 2, 3

is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document

OPER

-0.4 V ~ 1.975 V V 1,3

-0.4 V ~ 1.975 V V 1,3

-0.4 V ~ 1.975 V V 1

must be not greater than 0.6 x V

REF

, When VDD and V

DDQ

are less than 500mV; V

DDQ

REF

may be

11. AC & DC Operating Conditions

11.1 Recommended DC Operating Conditions (SSTL-15)

Symbol Parameter

V

DD

V

DDQ

NOTE:

1. Under all conditions V

tracks with VDD. AC parameters are measured with VDD and V

2. V

DDQ

Supply Voltage 1.425 1.5 1.575 V 1,2

Supply Voltage for Output 1.425 1.5 1.575 V 1,2

must be less than or equal to VDD.

DDQ

tied together.

DDQ

Min. Typ. Max.

Rating

Units NOTE

- 13 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

12. AC & DC Input Measurement Levels

12.1 AC & DC Logic Input Levels for Single-ended Signals

[ Table 2 ] Single-ended AC & DC input levels for Command and Address

Symbol Parameter

V

(DC100)

IH.CA

V

(DC100)

IL.CA

V

(AC175)

IH.CA

V

(AC175)

IL.CA

(AC150)

V

IH.CA

V

(AC150)

IL.CA

(AC135)

V

IH.CA

V

(AC135)

IL.CA

V

(AC125)

IH.CA

V

(AC125)

IL.CA

V

REFCA

NOTE :

1. For input only pins except

2. See ’Overshoot/Undershoot Specification’ on Component Datasheet.

3. The AC peak noise on V

4. For reference : approx. V

5. V

(dc) is used as a simplified symbol for V

IH

6. V

(dc) is used as a simplified symbol for V

IL

7. V

(ac) is used as a simplified symbol for V

IH

, V

(AC150) value is used when VREF + 150mV is referenced, V

IH.CA

VREF + 125mV is referenced.

(ac) is used as a simplified symbol for V

8. V

IL

enced, V
when V

9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device

REF

DC input logic high

DC input logic low

AC input logic high

AC input logic low Note 2

AC input logic high

AC input logic low Note 2

AC input logic high - -

AC input logic low - - Note 2

AC input logic high - -

AC input logic low - - Note 2

Reference Voltage for ADD,

(DC)

CMD inputs

RESET, V

may not allow V

REF

/2 ± 15mV

DD

(AC150) value is used when V

IL.CA

- 125mV is referenced.

REF

= V

(DC)

REFCA

to deviate from V

REF

(DC100)

IH.CA

(DC100)

IL.CA

(AC175), V

IH.CA

(AC175) and V

IL.CA

- 150mV is referenced, V

REF

DDR3-800/1066/1333/1600 DDR3-1866

Min. Max. Min. Max.

V

+ 100 V

REF

V

REF

V

REF

0.49*V

IH.CA

V

SS

+ 175

+150

DD

(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

REF

(AC150), V

IH.CA

(AC150), V

IL.CA

(AC135) and V

IH.CA

(AC135) value is used when VREF + 135mV is referenced and V

IL.CA

(AC135) value is used when V

IL.CA

DD

V

- 100 V

REF

Note 2 - - mV 1,2,7

V

- 175

REF

Note 2 - - mV 1,2,7

V

-150

REF

0.51*V

DD

(AC135) and V

IH.CA

(AC125); V

(AC125); V

IL.CA

V

+ 100 V

REF

SS

DD

V

- 100

REF

- - mV 1,2,8

- - mV 1,2,8

V

+ 135

REF

V

+125

REF

0.49*V

DD

(AC175) value is used when V

IH.CA

(AC175) value is used when V

IL.CA

- 135mV is referenced and V

REF

Note 2 mV 1,2,7

V

- 135

REF

Note 2 mV 1,2,7

V

-125

REF

0.51*V

DD

+ 175mV is referenced

REF

(AC125) value is used when

IH.CA

- 175mV is refer-

REF

(AC125) value is used

IL.CA

Unit NOTE

mV 1,5

mV 1,6

mV 1,2,8

mV 1,2,8

V 3,4,9

- 14 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

[ Table 3 ] Single-ended AC & DC input levels for DQ and DM

Symbol Parameter

V

(DC100)

IH.DQ

V

(DC100)

IL.DQ

V

(AC175)

IH.DQ

V

(AC175)

IL.DQ

V

(AC150)

IH.DQ

V

(AC150)

IL.DQ

(AC135)

V

IH.DQ

V

(AC135)

IL.DQ

V

REF

DQ

NOTE :

1. For input only pins except

2. See ’Overshoot/Undershoot Specification’ on Component Datasheet.

3. The AC peak noise on V

4. For reference : approx. V

(dc) is used as a simplified symbol for V

5. V

IH

6. V

(dc) is used as a simplified symbol for V

IL

(ac) is used as a simplified symbol for V

7. V

IH

(AC150) value is used when V

V

IH.DQ

8. V

(ac) is used as a simplified symbol for V

IL

- 150mV is referenced.

V

REF

9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device

10. Optional in DDR3 SDRAM for DDR3-800/1066/1333/1600: Users should refer to the DRAM supplier data sheetand/or the DIMM SPDto determine if DDR3 SDRAM devices

support this option.

DC input logic high

DC input logic low

AC input logic high

AC input logic low NOTE 2

AC input logic high

AC input logic low NOTE 2

AC input logic high

AC input logic low NOTE 2

Reference Voltage for DQ,

(DC)

DM inputs

RESET, V

may not allow V

REF

/2 ± 15mV

DD

= V

REF

IL.DQ

+ 150mV is referenced.

REF

IL.DQ

REFDQ

REF

IH.DQ

(DC100)

(AC175), V

IH.DQ

DDR3-800/1066 DDR3-1333/1600 DDR3-1866

Min. Max. Min. Max. Min. Max.

V

+ 100 V

REF

V

SS

V

+ 175

REF

V

+ 150

REF

V

+ 135

REF

0.49*V

DD

(DC)

to deviate from V

(DC100)

(AC175), V

IL.DQ

DD

V

- 100 V

REF

NOTE 2 - - - - mV 1,2,7

V

- 175

REF

NOTE 2

V

- 150

REF

NOTE 2

V

- 135

REF

0.51*V

(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

REF

(AC150) and V

IH.DQ

(AC150) ; V

IL.DQ

V

+ 100 V

REF

SS

V

- - - - mV 1,2,8

V

+ 150

REF

DD

V

V

0.51*V

IH.DQ

NOTE 2

V

+ 135

REF

NOTE 2

0.49*V

DD

(AC135) ; V

IH.DQ

(AC175) value is used when V

V

DD

- 100 V

REF

+ 100 V

REF

SS

NOTE 2 - - mV 1,2,7

- 150

REF

NOTE 2

- 135

REF

DD

(AC175) value is used when V

- 175mV is referenced, V

REF

- - mV 1,2,8

V

+ 135

REF

NOTE 2

0.49*V

DD

V

- 100

REF

NOTE 2 mV 1,2,7,10

V

- 135

REF

0.51*V

DD

DD

+ 175mV is referenced,

REF

(AC150) value is used when

IL.DQ

Unit NOTE

mV 1,5

mV 1,6

mV 1,2,8,10

V 3,4,9

- 15 -

Rev. 1.1

Registered DIMM

12.2 V

The dc-tolerance limits and ac-noise limits for the reference voltages V

(t) as a function of time. (V

V

REF

V

(DC) is the linear average of V

REF

thermore V

Tolerances.

REF

REF

(t) may temporarily deviate from V

REF

voltage

stands for V

(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V

REF

REFCA

REF

datasheet DDR3 SDRAM

and V

(DC) by no more than ± 1% VDD.

REFDQ

likewise).

REFCA

and V

are illustrate in Figure 2. It shows a valid reference voltage

REFDQ

REF

V

DD

V

SS

. Fur-

time

Figure 2. Illustration of VREF(DC) tolerance and VREF ac-noise limits

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on V

" shall be understood as V

"V

REF

This clarifies, that dc-variations of V

which setup and hold is measured. System timing and voltage budgets need to account for V

data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

Timing and voltage effects due to ac-noise on V

(DC), as defined in Figure 2.

REF

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

REF

(DC) deviations from the optimum position within the

REF

up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

REF

REF

.

ac-noise.

REF

- 16 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

12.3 AC and DC Logic Input Levels for Differential Signals

12.3.1 Differential Signals Definition

tDVAC

VIH.DIFF.AC.MIN

.DIFF.MIN

V

IH

0.0
half cycle

.DIFF.MAX

V

IL

.DIFF.AC.MAX

V

IL

Differential Input Voltage (i.e. DQS-DQS, CK-CK)

tDVAC

time

Figure 3. Definition of differential ac-swing and "time above ac level" tDVAC

12.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

Symbol Parameter

V

IHdiff

V

ILdiff

V

(AC)

IHdiff

(AC)

V

ILdiff

NOTE :

1. Used to define a differential signal slew-rate.

2. for CK -

3. These values are not defined, however they single-ended signals CK,

CK use VIH/VIL(AC) of ADD/CMD and V

then the reduced level applies also here.

ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"

differential input high +0.2 NOTE 3 V 1

differential input low NOTE 3 -0.2 V 1

differential input high ac

differential input low ac NOTE 3

; for DQS - DQS use VIH/VIL(AC) of DQs and V

REFCA

2 x (VIH(AC) - V

DDR3-800/1066/1333/1600/1866

min max

)

REF

CK, DQS, DQS, DQSL need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-

NOTE 3 V 2

2 x (VIL(AC) - V

; if a reduced ac-high or ac-low level is used for a signal group,

REFDQ

REF

unit NOTE

)

V2

- 17 -

Rev. 1.1

Registered DIMM

[ Table 4 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS

DDR3-800/1066/1333/1600 DDR3-1866

Slew Rate [V/ns]

> 4.0 75 - 175 - 214 - 134 - 139 -

4.0 57 - 170 - 214 - 134 - 139 -

3.0 50 - 167 - 191 - 112 - 118 -

2.0 38 - 119 - 146 - 67 - 77 -

1.8 34 - 102 - 131 - 52 - 63 -

1.6 29 - 81 - 113 - 33 - 45 -

1.4 22 - 54 - 88 - 9 - 23 -

1.2 note - 19 - 56 - note - note -

1.0 note - note - 11 - note - note -

< 1.0 note - note - note - note - note -

NOTE : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VILdiff(ac)
level.

tDVAC [ps]

@ V

(AC)= 350mV

IH/Ldiff

min max min max min max min max min max

@ V

datasheet DDR3 SDRAM

tDVAC [ps]

(AC)= 300mV

IH/Ldiff

tDVAC [ ps ]

@ VIH/L diff(ac)

=270mV

(DQS - DQS#) only

(Optional)

tDVAC [ps]

@ V

IH/Ldiff

= 270mV

(AC)

tDVAC [ps]

@ V

=250mV(CK - CK#) only

IH/Ldiff

(AC)

- 18 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

12.3.3 Single-ended Requirements for Differential Signals

Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.

CK and CK have to approximately reach V

half-cycle.

DQS, DQS have to reach V

SEH

min / V

ing a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V

signals, then these ac-levels apply also for the single-ended signals CK and

VDD or V

V

SEH

VDD/2 or V

DDQ

min / V

SEH

max (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle proceeding and follow-

SEL

max (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every

SEL

150(AC)/VIL150(AC) is used for ADD/CMD

IH

CK .

DDQ

min

V

SEH

/2

CK or DQS

max

V

SEL

V

VSS or V

SSQ

Figure 4. Single-ended requirement for differential signals

Note that while ADD/CMD and DQ signal requirements are with respect to V

with respect to V

ended components of differential signals the requirement to reach V

/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-

DD

SEL

, the single-ended components of differential signals have a requirement

REF

max, V

min has no bearing on timing, but adds a restriction on the common

SEH

mode characteristics of these signals.

[ Table 5 ] Single ended levels for CK, DQS,

Symbol Parameter

V

SEH

V

SEL

NOTE :

1. For CK,

2. V

3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-

CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.

(AC)/VIL(AC) for DQs is based on V

IH

reduced level applies also here

nals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"

Single-ended high-level for strobes

Single-ended high-level for CK, CK

Single-ended low-level for strobes NOTE 3

Single-ended low-level for CK, CK NOTE 3

REFDQ

CK, DQS

Min Max

(VDD/2)+0.175

/2)+0.175

(V

DD

; VIH(AC)/VIL(AC) for ADD/CMD is based on V

DDR3-800/1066/1333/1600/1866

; if a reduced ac-high or ac-low level is used for a signal group, then the

REFCA

SEL

time

NOTE 3 V 1, 2

NOTE 3 V 1, 2

/2)-0.175

(V

DD

(VDD/2)-0.175

Unit NOTE

V 1, 2

V 1, 2

- 19 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

12.3.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual

cross point of true and complement signal to the mid level between of VDD and VSS.

V

DD

CK, DQS

V

IX

VDD/2

V

IX

Figure 5. VIX Definition

[ Table 6 ] Cross point voltage for differential input signals (CK, DQS)

Symbol Parameter

V

V

NOTE :

1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V
±250 mV, and the differential slew rate of CK-

2. The relation between V

(V

DD

V

SEH

Differential Input Cross Point Voltage relative to VDD/2 for CK,CK

IX

Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS

IX

Min/Max and V

/2) + VIX(Min) - V

- ((VDD/2) + VIX(Max)) 25mV

IX

SEL

25mV

CK is larger than 3 V/ ns.

should satisfy following.

SEL/VSEH

V

IX

CK, DQS

V

SS

DDR3-800/1066/1333/1600/1866

Min Max

-150 150 mV 2

-175 175 mV 1

-150 150 mV 2

/ V

SEL

Unit NOTE

of at least VDD/2

SEH

12.4 Slew Rate Definition for Single Ended Input Signals

See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.

12.5 Slew rate definition for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.

[ Table 7 ] Differential input slew rate definition

Description

Differential input slew rate for rising edge (CK-

CK and DQS-DQS)

Differential input slew rate for falling edge (CK-CK and DQS-DQS)

NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds

delta TFdiff

Figure 6. Differential input slew rate definition for DQS, DQS and CK, CK

Measured

From To

V

ILdiffmax

V

IHdiffmin

delta TRdiff

V

V

IHdiffmin

ILdiffmax

V

0

V

IHdiffmin

ILdiffmax

[V

IHdiffmin

[V

IHdiffmin

Defined by

- V

ILdiffmax] /

- V

ILdiffmax] /

Delta TRdiff

Delta TFdiff

- 20 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

13. AC & DC Output Measurement Levels

13.1 Single Ended AC and DC Output Levels

[ Table 8 ] Single Ended AC and DC output levels

Symbol Parameter DDR3-800/1066/1333/1600/1866 Units NOTE

VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x V

VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x V

(DC) DC output low measurement level (for IV curve linearity) 0.2 x V

V

OL

V

(AC) AC output high measurement level (for output SR) VTT + 0.1 x V

OH

VOL(AC) AC output low measurement level (for output SR) VTT - 0.1 x V

NOTE : 1. The swing of +/-0.1 x V

load of 25 to V

TT=VDDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test

DDQ

/2.

DDQ

DDQ

DDQ

DDQ

DDQ

13.2 Differential AC and DC Output Levels

[ Table 9 ] Differential AC and DC output levels

Symbol Parameter DDR3-800/1066/1333/1600/1866 Units NOTE

V

(AC) AC differential output high measurement level (for output SR) +0.2 x V

OHdiff

V

(AC) AC differential output low measurement level (for output SR) -0.2 x V

OLdiff

NOTE : 1. The swing of +/-0.2xV

load of 25 to V

TT=VDDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test

DDQ

/2 at each of the differential outputs.

DDQ

DDQ

V

V

V

V1

V1

V1

V1

13.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)

for single ended signals as shown in below.

[ Table 10 ] Single ended Output slew rate definition

Description

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 11 ] Single ended output slew rate

Parameter Symbol

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Min Max Min Max Min Max Min Max Min Max

Single ended output slew rate SRQse 2.5 5 2.5 5 2.5 5 2.5 5 2.5

Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals

For Ron = RZQ/7 setting

NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ
signals in the same byte lane are static (i.e they stay at either high or low).

- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the
remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.

Measured

From To

Defined by

VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / Delta TRse

(AC) VOL(AC) [VOH(AC)-VOL(AC)] / Delta TFse

V

OH

V

OH(AC)

Units

1)

V/ns

5

VTT

V

OL(AC)

delta TRsedelta TFse

Figure 7. Single-ended Output Slew Rate Definition

- 21 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

13.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V

(AC) for differential signals as shown in below.

diff

[ Table 12 ] Differential Output slew rate definition

Description

Differential output slew rate for rising edge

Differential output slew rate for falling edge

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 13 ] Differential Output slew rate

Parameter Symbol

Differential output slew rate SRQdiff 5 10 5 10 5 10 5 10 5 12 V/ns

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

diff : Differential Signals

For Ron = RZQ/7 setting

V

V

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Min Max Min Max Min Max Min Max Min Max

Measured

From To

(AC) V

OLdiff

(AC) V

OHdiff

OHdiff

OLdiff

(AC) [V

(AC) [V

OHdiff

OHdiff

(AC)-V

(AC)-V

Defined by

(AC)] / Delta TRdiff

OLdiff

(AC)] / Delta TFdiff

OLdiff

OLdiff

(AC) and V

Units

OH-

V

OHdiff

VTT

V

OLdiff

delta TRdiffdelta TFdiff

Figure 8. Differential output slew rate definition

(AC)

(AC)

- 22 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

14. DIMM IDD specification definition

Symbol Description

Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8

IDD0

IDD1

IDD2N

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDD4W

IDD5B

IDD6

IDD6ET

IDD7

IDD8

Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

2)

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

tern

Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8

and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

2)

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

tern

Precharge Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode

2)

Registers

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit

3)

Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit

3)

Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

ODT Signal: stable at 0

Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode

2)

Registers

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers

Signal: stable at 0

Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

at

HIGH; Pattern Details: Refer to Component Datasheet for detail pattern

Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8

Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and
RTT: Enabled in Mode Registers

2)

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and CK:

LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8

1)

; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and CK:

LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8

6)

1)

; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: CL-1; CS: High

between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and
the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:

Enabled in Mode Registers

2)

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

RESET Low Current
RESET : Low; External clock : off; CK and

CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :

FLOATING

1)

; AL: 0; CS: High between ACT and PRE;

1)

; AL: 0; CS: High between ACT, RD

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

1)

; AL: 0; CS: High between RD; Command, Address,

2)

; ODT Signal: stable

1)

; AL: 0; CS: High between WR; Command, Address,

2)

; ODT Signal: stable

1)

; AL: 0; CS: High between REF; Command,

2)

; ODT Signal: FLOATING

2)

; ODT Signal: FLOATING

2)

; ODT

2)

;

2)

;

2)

;

- 23 -

Rev. 1.1

Registered DIMM

NOTE :

1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device

7) IDD current measure method and detail patterns are described on DDR3 component datasheet

8) VDD and VDDQ are merged on module PCB.

9) DIMM IDD SPEC is measured with Qoff condition

(IDDQ values are not considered)

datasheet DDR3 SDRAM

- 24 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

16. IDD SPEC Table

M393B1K70QB0 : 8GB(1Gx72) Module

Symbol

IDD0 1890 1980 mA 1

IDD1 2070 2160 mA 1

IDD2P0(slow exit) 1062 1062 mA

IDD2P1(fast exit) 1170 1242 mA

IDD2N 1410 1410 mA

IDD2Q 1390 1390 mA

IDD3P 1350 1350 mA

IDD3N 1940 2012 mA

IDD4R 2340 2700 mA 1

IDD4W 2620 2800 mA 1

IDD5B 3200 3200 mA 1

IDD6 462 462 mA

IDD7 3420 3510 mA 1

IDD8 462 462 mA

.NOTE :

1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.

(DDR3-1600@CL=11)

CK0

(DDR3-1866@CL=13)

CMA

Unit NOTE

- 24 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

17. Input/Output Capacitance

[ Table 14 ] Input/Output Capacitance

Parameter Symbol

Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)

Input capacitance
(CK and

Input capacitance delta
(CK and

Input capacitance
(All other input-only pins)

Input capacitance delta
(DQS and

Input capacitance delta
(All control input-only pins)

Input capacitance delta
(all ADD and CMD input-only pins)

Input/output capacitance delta
(DQ, DM, DQS,

Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 - 3 - 3 pF 2, 3, 12

NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance.

1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS

2. This parameter is not subject to production test. It is verified by design and characterization.
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4. Absolute value of CCK-CCK

5. Absolute value of CIO(DQS)-CIO(DQS)

6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.

7. CDI_CTRL applies to ODT, CS and CKE

8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))

9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE

10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))

11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))

12. Maximum external load capacitance on ZQ pin: 5pF

CK)

CK)

DQS)

V

, V

, VSS, V

DD

DDQ

termination off.

DQS, TDQS, TDQS)

applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=V

SSQ

CIO 1.4 3.0 1.4 2.7 1.4 2.5 1.4 2.3 1.4 2.2 pF 1,2,3

CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 pF 2,3

CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4

CI 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 pF 2,3,6

CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 pF 2,3,5

CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8

CDI_ADD_CMD -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,9,10

CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Min Max Min Max Min Max Min Max Min Max

=1.5V, V

DDQ

BIAS=VDD

Units NOTE

/2 and on-die

- 25 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

17. Electrical Characteristics and AC timing

(0 C<T

17.1 Refresh Parameters by Device Density

All Bank Refresh to active/refresh cmd time tRFC 110 160 260 350 ns

Average periodic refresh interval tREFI

NOTE :

1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in
this material.

17.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Parameter min min min min min

CL 6 7 91113tCK

tRCD 15 13.13 13.5 13.75 13.91 ns

tRP 15 13.13 13.5 13.75 13.91 ns

tRAS 37.5 37.5 36 35 34 ns

tRC 52.5 50.63 49.5 48.75 47.91 ns

tRRD 10 7.5 6.0 6.0 5.0 ns

tFAW 40 37.5 30 30 27 ns

95 C, V

CASE

Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units NOTE

= 1.5V  0.075V; VDD = 1.5V  0.075V)

DDQ

0CT

CASE

85CT

CASE

 85C

 95C

7.8 7.8 7.8 7.8 s

3.9 3.9 3.9 3.9 s 1

Units NOTEBin (CL - tRCD - tRP) 6-6-6 7-7-7 9-9-9 11-11-11 13-13-13

17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

[ Table 15 ] DDR3-800 Speed Bins

Speed DDR3-800

Units NOTECL-nRCD-nRP 6 - 6 - 6

Parameter Symbol min max

Internal read command to first data tAA 15 20 ns

ACT to internal read or write delay time tRCD 15 - ns

PRE command period tRP 15 - ns

ACT to ACT or REF command period tRC 52.5 - ns

ACT to PRE command period tRAS 37.5 9*tREFI ns

CL = 6 / CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3

Supported CL Settings 6 nCK

Supported CWL Settings 5 nCK

- 28 -

Rev. 1.1

Registered DIMM

[ Table 16 ] DDR3-1066 Speed Bins

Speed DDR3-1066

Parameter Symbol min max

Internal read command to first data tAA 13.125 20 ns

ACT to internal read or write delay time tRCD 13.125 - ns

PRE command period tRP 13.125 - ns

ACT to ACT or REF command period tRC 50.625 - ns

ACT to PRE command period tRAS 37.5 9*tREFI ns

CL = 6

CL = 7

CL = 8

Supported CL Settings 6,7,8 nCK

Supported CWL Settings 5,6 nCK

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,5

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,9

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3

datasheet DDR3 SDRAM

Units NOTECL-nRCD-nRP 7 - 7 - 7

[ Table 17 ] DDR3-1333 Speed Bins

Speed DDR3-1333

Units NOTECL-nRCD-nRP 9 -9 - 9

Parameter Symbol min max

Internal read command to first data tAA 13.5 (13.125)

ACT to internal read or write delay time tRCD 13.5 (13.125)

PRE command period tRP 13.5 (13.125)

ACT to ACT or REF command period tRC 49.5 (49.125)

ACT to PRE command period tRAS 36 9*tREFI ns

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,6

CL = 6

CL = 7

CL = 8

CL = 9

CL = 10

Supported CL Settings 6,7,8,9,10 nCK

Supported CWL Settings 5,6,7 nCK

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,6

CWL = 7 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,6

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,6

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,9

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3

9

9

9

9

20 ns

- ns

- ns

- ns

- 29 -

Rev. 1.1

Registered DIMM

[ Table 18 ] DDR3-1600 Speed Bins

Speed DDR3-1600

Parameter Symbol min max

Intermal read command to first data tAA

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to ACT or REF command period tRC

ACT to PRE command period tRAS 35 9*tREFI ns

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7

CL = 6

CL = 7

CL = 8

CL = 9

CL = 10

CL = 11

Supported CL Settings 6,7,8,9,10,11 nCK

Supported CWL Settings 5,6,7,8 nCK

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,7

CWL = 7, 8 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,7

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,7

CWL = 8 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,7

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,7

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,7

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,7

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6,7 tCK(AVG) Reserved ns 4

CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3,9

datasheet DDR3 SDRAM

Units NOTECL-nRCD-nRP 11-11-11

13.75

(13.125)

13.75

(13.125)

13.75

(13.125)

48.75

(48.125)

9

9

9

9

20 ns

- ns

- ns

- ns

- 30 -

Rev. 1.1

Registered DIMM

[ Table 19 ] DDR3-1866 Speed Bins

Speed DDR3-1866

Parameter Symbol min max

Internal read command to first data tAA

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to ACT or REF command period tRC

ACT to PRE command period tRAS 34 9*tREFI ns

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,8

CL = 6

CL = 7

CL = 8

CL = 9

CL = 10

CL = 11

CL = 12

CL = 13

Supported CL Settings 6,7,8,9,10,11,13 nCK

Supported CWL Settings 5,6,7,8,9 nCK

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 7,8,9 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 2.5 ns 1,2,3,4,8

CWL = 7,8,9 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,8

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 8,9 tCK(AVG) Reserved ns 4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 1.875 ns 1,2,3,4,8

CWL = 8 tCK(AVG) Reserved ns 4

CWL = 9 tCK(AVG) Reserved ns 4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,8

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 5,6,7 tCK(AVG) Reserved ns 4

CWL = 8 tCK(AVG) 1.25 1.5 ns 1,2,3,4,8

CWL = 9 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6,7,8 tCK(AVG) Reserved ns 4

CWL = 9 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6,7,8 tCK(AVG) Reserved ns 4

CWL = 9 tCK(AVG) 1.071 <1.25 ns 1,2,3,9

datasheet DDR3 SDRAM

Units NOTECL-nRCD-nRP 13-13-13

13.91

(13.125)

13.91

(13.125)

13.91

(13.125)

47.91

(47.125)

10

10

10

10

20 ns

- ns

- ns

- ns

- 31 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

17.3.1 Speed Bin Table Notes

Absolute Specification (T

NOTE :

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements

from CL setting as well as requirements from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-

anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],
rounding up to the next "SupportedCL".

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or

1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.

4. "Reserved" settings are not allowed. User must program a different value.

5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,

DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte

20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte

18), and tRPmin (Byte 20). DDR3-1866(CL13) devices supporting downshift to DDR3-1600(CL11) or DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in
SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 devices supporting down binning to DDR3-1333 or DDR3-1066 should program

13.125ns in SPD byte for tAAmin (Byte 16), tRCDmin (Byte 18) and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be
programmed accodingly. For example, 49.125ns, (tRASmin + tRPmin = 36ns + 13.125ns) for DDR3-1333 and 48.125ns (tRASmin + tRPmin = 35ns + 13.125ns) for DDR3-

1600.

10. For devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting must be programed to match. For example,

DDR3-1866 devices supporting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for tAAmin(byte16), tRCDmin(Byte18) and tRP­min (byte20). Once tRP (Byte20) is programmed to 13.125ns, tRCmin (Byte21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin =
34ns + 13.125ns)

OPER

; V

= VDD = 1.5V +/- 0.075 V);

DDQ

- 32 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

18. Timing Parameters by Speed Grade

[ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.)

Speed DDR3-800 DDR3-1066 DDR3-1333

Parameter Symbol MIN MAX MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - 8 - ns 6

Average Clock Period tCK(avg)

Clock Period tCK(abs)

Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)

Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)

Clock Period Jitter tJIT(per) -100 100 -90 90 -80 80 ps

Clock Period Jitter during DLL locking period tJIT(per, lck) -90 90 -80 80 -70 70 ps

Cycle to Cycle Period Jitter tJIT(cc) 200 180 160 ps

Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 180 160 140 ps

Cumulative error across 2 cycles tERR(2per) - 147 147 - 132 132 - 118 118 ps

Cumulative error across 3 cycles tERR(3per) - 175 175 - 157 157 - 140 140 ps

Cumulative error across 4 cycles tERR(4per) - 194 194 - 175 175 - 155 155 ps

Cumulative error across 5 cycles tERR(5per) - 209 209 - 188 188 - 168 168 ps

Cumulative error across 6 cycles tERR(6per) - 222 222 - 200 200 - 177 177 ps

Cumulative error across 7 cycles tERR(7per) - 232 232 - 209 209 - 186 186 ps

Cumulative error across 8 cycles tERR(8per) - 241 241 - 217 217 - 193 193 ps

Cumulative error across 9 cycles tERR(9per) - 249 249 - 224 224 - 200 200 ps

Cumulative error across 10 cycles tERR(10per) - 257 257 - 231 231 - 205 205 ps

Cumulative error across 11 cycles tERR(11per) - 263 263 - 237 237 - 210 210 ps

Cumulative error across 12 cycles tERR(12per) - 269 269 - 242 242 - 215 215 ps

Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper)

Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - 0.43 - tCK(avg) 25

Absolute clock Low pulse width tCL(abs) 0.43 - 0.43 - 0.43 - tCK(avg) 26

Data Timing

DQS,DQS to DQ skew, per group, per access tDQSQ - 200 - 150 - 125 ps 13

DQ output hold time from DQS, DQS tQH 0.38 - 0.38 - 0.38 - tCK(avg) 13, g

DQ low-impedance time from CK, CK tLZ(DQ) -800 400 -600 300 -500 250 ps 13,14, f

DQ high-impedance time from CK, CK tHZ(DQ) - 400 - 300 - 250 ps 13,14, f

tDS(base)

Data setup time to DQS, DQS referenced

(AC)VIL(AC) levels

to V

IH

Data hold time to DQS, DQS referenced

(DC)VIL(DC) levels

to V

IH

DQ and DM Input pulse width for each input tDIPW 600

Data Strobe Timing

DQS, DQS differential READ Preamble tRPRE 0.9 NOTE 19 0.9 NOTE 19 0.9 NOTE 19 tCK(avg) 13, 19, g

DQS, DQS differential READ Postamble tRPST 0.3 NOTE 11 0.3 NOTE 11 0.3 NOTE 11 tCK(avg) 11, 13, b

DQS, DQS differential output high time tQSH 0.38 - 0.38 - 0.4 - tCK(avg) 13, g

DQS, DQS differential output low time tQSL 0.38 - 0.38 - 0.4 - tCK(avg) 13, g

DQS, DQS differential WRITE Preamble tWPRE 0.9 - 0.9 - 0.9 - tCK(avg)

DQS, DQS differential WRITE Postamble tWPST 0.3 - 0.3 - 0.3 - tCK(avg)

DQS, DQS rising edge output access time from rising CK, CK tDQSCK -400 400 -300 300 -255 255 ps 13,f

DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS) -800 400 -600 300 -500 250 ps 13,14,f

DQS, DQS high-impedance time (Referenced from RL+BL/2) tHZ(DQS) - 400 - 300 - 250 ps 12,13,14

DQS, DQS differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) 29, 31

DQS, DQS differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) 30, 31

DQS, DQS rising edge to CK, CK rising edge tDQSS -0.25 0.25 -0.25 0.25 -0.25 0.25 tCK(avg) c

DQS,DQS falling edge setup time to CK, CK rising edge tDSS 0.2 - 0.2 - 0.2 - tCK(avg) c, 32

DQS,DQS falling edge hold time to CK, CK rising edge tDSH 0.2 - 0.2 - 0.2 - tCK(avg) c, 32

AC175

tDS(base)

AC150

tDH(base)

DC100

tCK(avg)min +

tJIT(per)min

75

125

150

tCK(avg)max +

tJIT(per)max

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min

tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max

-

-

-

-

See Speed Bins Table

tCK(avg)min +

tJIT(per)min

25

75

100

490

tCK(avg)max +

tJIT(per)max

tCK(avg)min +

tJIT(per)min

-

-

-

-

400

tCK(avg)max +

tJIT(per)max

- - ps d, 17

30 - ps d, 17

65 - ps d, 17

-

Units NOTE

ps

ps

ps 24

ps 28

- 33 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

[ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.)

Speed DDR3-800 DDR3-1066 DDR3-1333

Parameter Symbol MIN MAX MIN MAX MIN MAX

Command and Address Timing

DLL locking time tDLLK 512 - 512 - 512 - nCK

internal READ Command to PRECHARGE Command delay tRTP

Delay from start of internal write transaction to internal read com­mand

WRITE recovery time tWR 15 - 15 - 15 - ns e

Mode Register Set command cycle time tMRD 4 - 4 - 4 - nCK

Mode Register Set command update delay tMOD

CAS to CAS command delay tCCD 4 - 4 - 4 - nCK

Auto precharge write recovery + precharge time tDAL(min) WR + roundup (tRP / tCK(AVG)) nCK

Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - nCK 22

ACTIVE to PRECHARGE command period tRAS See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42 ns e

ACTIVE to ACTIVE command period for 1KB page size tRRD

ACTIVE to ACTIVE command period for 2KB page size tRRD

Four activate window for 1KB page size tFAW 40 - 37.5 - 30 - ns e

Four activate window for 2KB page size tFAW 50 - 50 - 45 - ns e

Command and Address setup time to CK, CK referenced to

(AC) / VIL(AC) levels

V

IH

Command and Address hold time from CK, CK referenced to

(DC) / VIL(DC) levels

V

IH

Control & Address Input pulse width for each input tIPW 900

Calibration Timing

Power-up and RESET calibration time tZQinitI 512 - 512 - 512 - nCK

Normal operation Full calibration time tZQoper 256 - 256 - 256 - nCK

Normal operation short calibration time tZQCS 64 - 64 - 64 - nCK 23

Reset Timing

Exit Reset from CKE HIGH to a valid command tXPR

Self Refresh Timing

Exit Self Refresh to commands not requiring a locked DLL tXS

Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - tDLLK(min) - tDLLK(min) - nCK

Minimum CKE low width for Self refresh entry to exit timing tCKESR

Valid Clock Requirement after Self Refresh Entry (SRE) or Power­Down Entry (PDE)

Valid Clock Requirement before Self Refresh Exit (SRX) or Power­Down Exit (PDX) or Reset Exit

tWTR

tIS(base)

AC175

tIS(base)

AC150

tIH(base)

DC100

tCKSRE

tCKSRX

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(12nCK,15ns)

max

(4nCK,10ns)

max

(4nCK,10ns)

200

200+150

275

max(5nCK,

tRFC + 10ns)

max(5nCK,tRF

C + 10ns)

tCKE(min) +

1tCK

max(5nCK,

10ns)

max(5nCK,

10ns)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(12nCK,15ns)

max

(4nCK,7.5ns)

max

(4nCK,10ns)

125

125+150

200

780

max(5nCK,

tRFC + 10ns)

max(5nCK,tRF

C + 10ns)

tCKE(min) +

1tCK

max(5nCK,

10ns)

max(5nCK,

10ns)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(12nCK,15ns)

max

(4nCK,6ns)

max

(4nCK,7.5ns)

65 - ps b,16

65+125 - ps b,16,27

140 - ps b,16

620 - ps 28

max(5nCK,

tRFC + 10ns)

max(5nCK,tRF

C + 10ns)

tCKE(min) +

1tCK

max(5nCK,

10ns)

max(5nCK,

10ns)

- e

- e,18

-

- e

- e

-

-

-

-

-

Units NOTE

- 34 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

[ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333

Speed DDR3-800 DDR3-1066 DDR3-1333

Parameter Symbol MIN MAX MIN MAX MIN MAX

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit Pre­charge Power Down with DLL
frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands re­quiring a locked DLL

CKE minimum pulse width tCKE

Command pass disable delay tCPDED 1 - 1 - 1 - nCK

Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK(avg) 15

Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - 1 - nCK 20

Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - 1 - nCK 20

Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 - RL + 4 +1 - RL + 4 +1 -

Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)

Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)

Timing of WR command to Power Down entry
(BC4MRS)

Timing of WRA command to Power Down entry
(BC4MRS)

Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 1 - 20,21

Timing of MRS command to Power Down entry tMRSPDEN tMOD(min) - tMOD(min) - tMOD(min) -

ODT Timing

ODT high time without write command or with write command
and BC4

ODT high time with Write command and BL8 ODTH8 6 - 6 - 6 - nCK

Asynchronous RTT turn-on delay (Power-Down with DLL fro­zen)

Asynchronous RTT turn-off delay (Power-Down with DLL fro­zen)

RTT turn-on tAON -400 400 -300 300 -250 250 ps 7,f

RTT_NOM and RTT_WR turn-off time from ODTLoff reference tAOF 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) 8,f

RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) f

Write Leveling Timing

First DQS/DQS rising edge after write leveling mode is pro­grammed

DQS/DQS delay after write leveling mode is programmed tWLDQSEN 25 - 25 - 25 - tCK(avg) 3

Write leveling setup time from rising CK, CK crossing to rising

DQS crossing

DQS,

Write leveling hold time from rising DQS, DQS crossing to rising

CK crossing

CK,

Write leveling output delay tWLO 0 9 0 9 0 9 ns

Write leveling output error tWLOE 0 2 0 2 0 2 ns

tXP

tXPDLL

tWRPDEN

tWRAPDEN WL+4+WR +1 - WL+4+WR+1 - WL+4+WR+1 - nCK 10

tWRPDEN

tWRAPDEN

ODTH4 4 - 4 - 4 - nCK

tAONPD 2 8.5 2 8.5 2 8.5 ns

tAOFPD 2 8.5 2 8.5 2 8.5 ns

tWLMRD 40 - 40 - 40 - tCK(avg) 3

tWLS 325 - 245 - 195 - ps

tWLH 325 - 245 - 195 - ps

max

(3nCK,

7.5ns)

max

(10nCK,

24ns)

max

(3nCK,

7.5ns)

WL + 4
+(tWR/

tCK(avg))

WL + 2
+(tWR/

tCK(avg))

WL +2 +WR

+1

-

-

-

-

-

-

max

(3nCK,

7.5ns)

max

(10nCK,

24ns)

max

(3nCK,

5.625ns)

WL + 4
+(tWR/

tCK(avg))

WL + 2
+(tWR/

tCK(avg))

WL +2 +WR

+1

-

-

-

-

-

-

max

(3nCK,6ns)

max

(10nCK,

24ns)

max

(3nCK,

5.625ns)

WL + 4
+(tWR/

tCK(avg))

WL + 2
+(tWR/

tCK(avg))

WL +2 +WR

+1

-

- 2

-

- nCK 9

- nCK 9

- nCK 10

Units NOTE

- 35 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

[ Table 21 ] Timing Parameters by Speed Bins for DDR3-1600 to DDR3-1866 (Cont.)

Speed DDR3-1600 DDR3-1866

Parameter Symbol MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - ns 6

Average Clock Period tCK(avg) See Speed Bins Table ps

Clock Period tCK(abs)

Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 tCK(avg)

Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 tCK(avg)

Clock Period Jitter tJIT(per) -70 70 -60 60 ps

Clock Period Jitter during DLL locking period tJIT(per, lck) -60 60 -50 50 ps

Cycle to Cycle Period Jitter tJIT(cc) 140 120 ps

Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 120 100 ps

Cumulative error across 2 cycles tERR(2per) -103 103 -88 88 ps

Cumulative error across 3 cycles tERR(3per) -122 122 -105 105 ps

Cumulative error across 4 cycles tERR(4per) -136 136 -117 117 ps

Cumulative error across 5 cycles tERR(5per) -147 147 -126 126 ps

Cumulative error across 6 cycles tERR(6per) -155 155 -133 133 ps

Cumulative error across 7 cycles tERR(7per) -163 163 -139 139 ps

Cumulative error across 8 cycles tERR(8per) -169 169 -145 145 ps

Cumulative error across 9 cycles tERR(9per) -175 175 -150 150 ps

Cumulative error across 10 cycles tERR(10per) -180 180 -154 154 ps

Cumulative error across 11 cycles tERR(11per) -184 184 -158 158 ps

Cumulative error across 12 cycles tERR(12per) -188 188 -161 161 ps

Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper)

Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - tCK(avg) 25

Absolute clock Low pulse width tCL(abs) 0.43 - 0.43 - tCK(avg) 26

Data Timing

DQS,DQS to DQ skew, per group, per access tDQSQ - 100 - 85 ps 13

DQ output hold time from DQS, DQS tQH 0.38 - 0.38 - tCK(avg) 13, g

DQ low-impedance time from CK, CK tLZ(DQ) -450 225 -390 195 ps 13,14, f

DQ high-impedance time from CK, CK tHZ(DQ) - 225 - 195 ps 13,14, f

tDS(base)

Data setup time to DQS, DQS referenced to VIH(AC)VIL(AC) lev­els

Data hold time to DQS, DQS referenced to VIH(DC)VIL(DC) levels

DQ and DM Input pulse width for each input tDIPW 360

Data Strobe Timing

DQS, DQS differential READ Preamble tRPRE 0.9 NOTE 19 0.9 NOTE 19 tCK(avg) 13, 19, g

DQS, DQS differential READ Postamble tRPST 0.3 NOTE 11 0.3 NOTE 11 tCK(avg) 11, 13, b

DQS, DQS differential output high time tQSH 0.4 - 0.4 - tCK(avg) 13, g

DQS, DQS differential output low time tQSL 0.4 - 0.4 - tCK(avg) 13, g

DQS, DQS differential WRITE Preamble tWPRE 0.9 - 0.9 - tCK(avg)

DQS, DQS differential WRITE Postamble tWPST 0.3 - 0.3 - tCK(avg)

DQS, DQS rising edge output access time from rising CK, CK tDQSCK -225 225 -195 195 ps 13,f

DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS) -450 225 -390 195 ps 13,14,f

DQS, DQS high-impedance time (Referenced from RL+BL/2) tHZ(DQS) - 225 - 195 ps 12,13,14

DQS, DQS differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 tCK(avg) 29, 31

DQS, DQS differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 tCK(avg) 30, 31

DQS, DQS rising edge to CK, CK rising edge tDQSS -0.27 0.27 -0.27 0.27 tCK(avg) c

DQS,DQS falling edge setup time to CK, CK rising edge tDSS 0.18 - 0.18 - tCK(avg) c, 32

DQS,DQS falling edge hold time to CK, CK rising edge tDSH 0.18 - 0.18 - tCK(avg) c, 32

AC150

tDS(base)

AC135

tDH(base)

DC100

tCK(avg)min + tJIT(per)min

10 - -

- - 0

45 - 20

tCK(avg)max +

tJIT(per)max

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min

tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max

-

tCK(avg)min +

tJIT(per)min

320

tCK(avg)max +

tJIT(per)max

-

-

-

-

Units NOTE

ps

ps 24

ps d, 17

ps d, 17

ps d, 17

ps 28

- 36 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

[ Table 21 ] Timing Parameters by Speed Bins for DDR3-1600 to DDR3-1866 (Cont.)

Speed DDR3-1600 DDR3-1866

Parameter Symbol MIN MAX MIN MAX

Command and Address Timing

DLL locking time tDLLK 512 - 512 - nCK

internal READ Command to PRECHARGE Command delay tRTP

Delay from start of internal write transaction to internal read com­mand

WRITE recovery time tWR 15 - 15 - ns e

Mode Register Set command cycle time tMRD 4 - 4 - nCK

Mode Register Set command update delay tMOD

CAS to CAS command delay tCCD 4 - 4 - nCK

Auto precharge write recovery + precharge time tDAL(min)

Multi-Purpose Register Recovery Time tMPRR 1 - 1 - nCK 22

ACTIVE to PRECHARGE command period tRAS See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42 ns e

ACTIVE to ACTIVE command period for 1KB page size tRRD

ACTIVE to ACTIVE command period for 2KB page size tRRD

Four activate window for 1KB page size tFAW 30 - 27 - ns e

Four activate window for 2KB page size tFAW 40 - 35 - ns e

Command and Address setup time to CK, CK referenced to

(AC) / VIL(AC) levels

V

IH

Command and Address hold time from CK, CK referenced to

(DC) / VIL(DC) levels

V

IH

Control & Address Input pulse width for each input tIPW 560 - 535

Calibration Timing

Power-up and RESET calibration time tZQinitI 512 - max(512nCK,640ns) - nCK

Normal operation Full calibration time tZQoper 256 - max(256nCK,320ns) - nCK

Normal operation short calibration time tZQCS 64 - max(64nCK,80ns) - nCK 23

Reset Timing

Exit Reset from CKE HIGH to a valid command tXPR

Self Refresh Timing

Exit Self Refresh to commands not requiring a locked DLL tXS

Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - tDLLK(min) - nCK

Minimum CKE low width for Self refresh entry to exit timing tCKESR tCKE(min) + 1tCK - tCKE(min) + 1nCK -

Valid Clock Requirement after Self Refresh Entry (SRE) or Power­Down Entry (PDE)

Valid Clock Requirement before Self Refresh Exit (SRX) or Power­Down Exit (PDX) or Reset Exit

tWTR

tIS(base)

AC175

tIS(base)

AC150

tIS(base)

AC135

tIS(base)

AC125

tIH(base)

DC100

tCKSRE

tCKSRX

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(12nCK,15ns)

max

(4nCK,6ns)

max

(4nCK,7.5ns)

45 - -

170 - -

- - 65 ps b,16

- - 150

120 - 100

max(5nCK, tRFC +

10ns)

max(5nCK,tRFC +

10ns)

max(5nCK,

10ns)

max(5nCK,

10ns)

-

-

-

-

-

-

-

-

-

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(12nCK,15ns)

WR + roundup (tRP /

tCK(AVG))

max

(4nCK, 5ns)

max

(4nCK, 6ns)

max(5nCK, tRFC +

10ns)

max(5nCK,tRFC +

10ns)

max(5nCK,

10ns)

max(5nCK,

10ns)

- e

- e,18

-

- e

- e

-

-

-

-

-

-

-

-

-

Units NOTE

nCK

ps b,16

ps b,16

ps b,16,27

ps b,16

ps 28

- 37 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

[ Table 21 ] Timing Parameters by Speed Bins for DDR3-1600 to DDR3-1866

Speed DDR3-1600 DDR3-1866

Parameter Symbol MIN MAX MIN MAX

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit Pre­charge Power Down with DLL
frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands re­quiring a locked DLL

CKE minimum pulse width tCKE

Command pass disable delay tCPDED 1 - 2 - nCK

Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK(avg) 15

Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - nCK 20

Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - nCK 20

Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 - RL + 4 +1 -

Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)

Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)

Timing of WR command to Power Down entry
(BC4MRS)

Timing of WRA command to Power Down entry
(BC4MRS)

Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 20,21

Timing of MRS command to Power Down entry tMRSPDEN tMOD(min) - tMOD(min) -

ODT Timing

ODT high time without write command or with write command
and BC4

ODT high time with Write command and BL8 ODTH8 6 - 6 - nCK

Asynchronous RTT turn-on delay (Power-Down with DLL fro­zen)

Asynchronous RTT turn-off delay (Power-Down with DLL fro­zen)

RTT turn-on tAON -225 225 -195 195 ps 7,f

RTT_NOM and RTT_WR turn-off time from ODTLoff reference tAOF 0.3 0.7 0.3 0.7 tCK(avg) 8,f

RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 tCK(avg) f

Write Leveling Timing

First DQS/DQS rising edge after write leveling mode is pro­grammed

DQS/DQS delay after write leveling mode is programmed tWLDQSEN 25 - 25 - tCK(avg) 3

Write leveling setup time from rising CK, CK crossing to rising

DQS crossing

DQS,

Write leveling hold time from rising DQS, DQS crossing to rising

CK crossing

CK,

Write leveling output delay tWLO 0 7.5 0 7.5 ns

Write leveling output error tWLOE 0 2 0 2 ns

tXP

tXPDLL

tWRPDEN

tWRAPDEN WL + 4 +WR +1 - WL + 4 +WR +1 - nCK 10

tWRPDEN

tWRAPDEN WL +2 +WR +1 - WL +2 +WR +1 - nCK 10

ODTH4 4 - 4 - nCK

tAONPD 2 8.5 2 8.5 ns

tAOFPD 2 8.5 2 8.5 ns

tWLMRD 40 - 40 - tCK(avg) 3

tWLS 165 - 140 - ps

tWLH 165 - 140 - ps

max

(3nCK,6ns)

max

(10nCK,

24ns)

max

(3nCK,5ns)

WL + 4 +(tWR/

tCK(avg))

WL + 2 +(tWR/

tCK(avg))

- max(3nCK,6ns) -

- max(10nCK,24ns) - 2

- max(3nCK,5ns) -

-

-

WL + 4 +(tWR/

tCK(avg))

WL + 2 +(tWR/

tCK(avg))

- nCK 9

- nCK 9

Units NOTE

- 38 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

18.1 Jitter Notes

Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the

input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,
another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.

Specific Note b These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition

edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,
these parameters should be met whether clock jitter is present or not.

Specific Note c These parameters are measured from a data strobe signal (DQS, DQS) crossing to its respective clock signal (CK, CK) crossing.

The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.

Specific Note d These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal

(DQS, DQS) crossing.

Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},
which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the
device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge com­mand at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.

Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input

clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +
193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and
tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800
derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution
on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.

Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input

clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has
tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +
tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =
tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/
max usage!)

- 39 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

18.2 Timing Parameter Notes

1. Actual value dependant upon measurement level definitions see "Device Operation & Timing Diagram Datasheet".

2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

3. The max values are system dependent.

4. WR as programmed in mode register

5. Value must be rounded-up to next higher integer value

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"

8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".

9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.

10. WR in clock cycles as programmed in MR0

11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing

Diagram Datasheet.

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated

by 18.1-Jitter Notes on page 39

13. Value is only valid for RON34

14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.

15. tREFI depends on T

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,

V

(DC) = V

REF

See "Address/Command Setup, Hold and Derating" on component datasheet.

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS,

V

(DC)= V

REF

See "Data Setup, Hold and Slew Rate Derating" on component datasheet.

18. Start of internal write transaction is defined as follows ;

For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL

19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram Data-

sheet"

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down

IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time

such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming

the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-

ject to in the application, is illustrated. The interval could be defined by the following formula:

OPER

DQ(DC). For input only pins except RESET, V

REF

DQ(DC). For input only pins except RESET, V

REF

REF

REF

(DC)=V

(DC)=V

REF

REF

CA(DC).

DQS differential slew rate. Note for DQ and DM signals,

CA(DC).

ZQCorrection

(TSens x Tdriftrate) + (VSens x Vdriftrate)

where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.

For example, if TSens = 1.5% /C, VSens = 0.15% / mV, Tdriftrate = 1C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu­lated as:

0.5

(1.5 x 1) + (0.15 x 15)

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.

26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125 ps for DDR3-800/1066 or 100ps for DDR3-

1333/1600 of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mv - 150
mV) / 1 V/ns].

28. Pulse width of a input signal is defined as the width between the first crossing of V

29. tDQSL describes the instantaneous differential input low pulse width on DQS-

30. tDQSH describes the instantaneous differential input high pulse width on DQS-

31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

33. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75ps for DDR3-1866 to accommodate for the

lower alternate threshold of 125mV and another 10ps to account for the earlier reference point [(135mv - 125mV) / 1 V/ns].

= 0.133

DQS, as measured from one falling edge to the next consecutive rising edge.

DQS, as measured from one rising edge to the next consecutive falling edge.

~

128ms

~

(DC) and the consecutive crossing of V

REF

REF

(DC)

- 40 -

Rev. 1.1

Registered DIMM

datasheet DDR3 SDRAM

20. Physical Dimensions

20.1 512Mbx4 based 1Gx72 Module (2 Ranks) - M393B1K70QB0

133.35 ± 0.15

C

54.675

47.00

128.95

Register

AB

71.00

Units : Millimeters

Max 4.0

30.00 ± 0.15

1.0 max

1.27 ± 0.10

5.00

2.50 ± 0.20

3.80

2.50

Detail A

1.50±0.10

Detail B

20.1.1 x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs

VTTVTT

VTTVTT

Register

1.00

0.80 ± 0.05

0.2 ± 0.15

VTT

VTT

VTTVTT

10.9

R 0.50

Detail C

2x 2.10 ± 0.15

0.4

Address, Command and Control lines

The used device is 512M x4 DDR3 SDRAM, Flip-Chip
DDR3 SDRAM Part NO : K4B2G0446Q-BC**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

- 39 -