Rev. 1.2, Aug. 2011
240pin Registered DIMM
1.35V
based on 2Gb D-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
M393B5773DH0
M393B5273DH0
M393B5270DH0
M393B1K70DH0
M393B1K73DH0
M393B2K70DM0
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or otherwise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
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may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2011 Samsung Electronics Co., Ltd. All rights reserved.
- 1 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
Revision History
Revision No. History Draft Date Remark Editor
1.0 - First Release Sep. 2010 - S.H.Kim
1.01 - Corrected typo. Dec. 2010 - S.H.Kim
1.1 - Corrected typo. Feb. 2011 - J.Y.Lee
1.11 - Corrected typo. May. 2011 - J.Y.Lee
1.12 - Corrected typo. Jun. 2011 - J.Y.Lee
1.13 - Corrected typo. Jul. 2011 - J.Y.Lee
1.2 - Changed input/output capacitance for 1333/1600Mbps of 1.35V Aug. 2011 - J.Y.Lee
- Changed module thickness with Heat Spreader.
- 2 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
Table Of Contents
240pin Registered DIMM based on 2Gb D-die
1. DDR3L Registered DIMM Ordering Information ...........................................................................................................5
2. Key Features................................................................................................................................................................. 5
3. Address Configuration ..................................................................................................................................................5
4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................6
5. Pin Description ............................................................................................................................................................. 7
6. ON DIMM Thermal Sensor ........................................................................................................................................... 7
7. Input/Output Functional Description..............................................................................................................................8
8. Pinout Comparison Based On Module Type.................................................................................................................9
9. Registering Clock Driver Specification..........................................................................................................................10
9.1 Timing & Capacitance values ..................................................................................................................................10
9.2 Clock driver Characteristics..................................................................................................................................... 10
10. Function Block Diagram:.............................................................................................................................................11
10.1 2GB, 256Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ................................................................... 11
10.2 4GB, 512Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................. 12
10.3 4GB, 512Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) ................................................................... 13
10.4 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) ..................................................................... 14
10.5 8GB, 1Gx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs) .................................................................... 16
10.6 16GB, 2Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs) ................................................................... 17
11. Absolute Maximum Ratings ........................................................................................................................................ 22
11.1 Absolute Maximum DC Ratings............................................................................................................................. 22
11.2 DRAM Component Operating Temperature Range .............................................................................................. 22
12. AC & DC Operating Conditions...................................................................................................................................22
12.1 Recommended DC Operating Conditions .......................................................................................
13. AC & DC Input Measurement Levels ..........................................................................................................................23
13.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 23
13.2 V
13.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 26
13.3.1. Differential Signals Definition .........................................................................................................................26
13.3.2. Differential Swing Requirement for Clock (CK - CK
13.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 28
13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 29
13.4 Slew Rate Definition for Single Ended Input Signals .............................................................................................30
13.5 Slew rate definition for Differential Input Signals ...................................................................................................30
14. AC & DC Output Measurement Levels .......................................................................................................................30
14.1 Single Ended AC and DC Output Levels............................................................................................................... 30
14.2 Differential AC and DC Output Levels ................................................................................................................... 30
14.3 Single-ended Output Slew Rate ............................................................................................................................ 31
14.4 Differential Output Slew Rate ................................................................................................................................ 32
15. IDD specification definition..........................................................................................................................................33
16. IDD SPEC Table .........................................................................................................................................................35
17. Input/Output Capacitance ...........................................................................................................................................38
18. Electrical Characteristics and AC timing .....................................................................................................................39
18.1 Refresh Parameters by Device Density................................................................................................................. 39
18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 39
18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 39
18.3.1. Speed Bin Table Notes .................................................................................................................................. 42
19. Timing Parameters by Speed Grade ..........................................................................................................................43
19.1 Jitter Notes ............................................................................................................................................................ 46
19.2 Timing Parameter Notes........................................................................................................................................ 47
20. Physical Dimensions................................................................................................................................................... 48
20.1 256Mbx8 based 256Mx72 Module (1 Rank) - M393B5773DH0 ............................................................................ 48
20.1.1. x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs................................................................ 48
Tolerances.................................................................................................................................................... 25
REF
) and Strobe (DQS - DQS) .............................................26
...................... 22
- 3 -
Rev. 1.2
Registered DIMM
20.2 256Mbx8 based 512Mx72 Module (2 Ranks) - M393B5273DH0 .......................................................................... 49
20.2.1. x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs .............................................................. 49
20.3 512Mbx4 based 512Mx72 Module (1 Rank) - M393B5270DH0 ............................................................................ 50
20.3.1. x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs................................................................ 50
20.4 512Mbx4 based 1Gx72 Module (2 Ranks) - M393B1K70DH0 .............................................................................. 51
20.4.1. x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs .............................................................. 51
20.5 256Mbx8 based 1Gx72 Module (4 Ranks) - M393B1K73DH0 .............................................................................. 52
20.5.1. x72 DIMM, populated as four physical ranks of x8 DDR3 SDRAMs .............................................................. 52
20.6 1Gbx4(DDP) based 2Gx72 Module (4 Ranks) - M393B2K70DM0........................................................................ 53
20.6.1. x72 DIMM, populated as four physical ranks of x4 DDR3 SDRAMs .............................................................. 53
20.6.2. Heat Spreader Design Guide ......................................................................................................................... 54
datasheet DDR3L SDRAM
- 4 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
1. DDR3L Registered DIMM Ordering Information
Part Number
M393B5773DH0-YF8/H9/K0 2GB 256Mx72 256Mx8(K4B2G0846D-HY##)*9 1 30mm
M393B5273DH0-YF8/H9/K0 4GB 512Mx72 256Mx8(K4B2G0846D-HY##)*18 2 30mm
M393B5270DH0-YF8/H9/K0 4GB 512Mx72 512Mx4(K4B2G0446D-HY##)*18 1 30mm
M393B1K70DH0-YF8/H9/K0 8GB 1Gx72 512Mx4(K4B2G0446D-HY##)*36 2 30mm
M393B1K73DH0-YF8/H9 8GB 1Gx72 256Mx8(K4B2G0846D-HY##)*36 4 30mm
M393B2K70DM0-YF8/H9 16GB 2Gx72 DDP 1Gx4(K4B4G0446D-MY##)*36 4 30mm
NOTE :
1. "##" - F8/H9/K0
2. F8(1066Mbps 7-7-7) / H9(1333Mbps 9-9-9) / K0(1600Mbps 11-11-11)
- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
2
Density Organization Component Composition
Number of
Rank
2. Key Features
Speed
tCK(min) 2.5 1.875 1.5 1.25 ns
CAS Latency 6 7 9 11 nC K
tRCD(min) 15 13.125 13.5 13.75 ns
tRP(min) 15 13.125 13.5 13.75 ns
tRAS(min) 37.5 37.5 36 35 ns
tRC(min) 52.5 50.625 49.5 48.75 ns
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
6-6-6 7-7-7 9-9-9 11-11- 11
Height
Unit
• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply
•V
= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
DDQ
• 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9,10,11
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333) and 8(DDR3-1600)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then T
• Asynchronous Reset
85°C, 3.9us at 85°C < T
CASE
CASE
≤ 95°C
3. Address Configuration
Organization Row Address Column Address Bank Address Auto Precharge
512Mx4(2Gb) based Module A0-A14 A0-A9, A11 BA0-BA2 A10/AP
256Mx8(2Gb) based Module A0-A14 A0-A9 BA0-BA2 A10/AP
1Gx4(4Gb DDP) based Module A0-A14 A0-A9, A11 BA0-BA2 A10/AP
- 5 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
4. Registered DIMM Pin Configurations (Front side/Back side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1
2
V
REFDQ
V
121
SS
122 DQ4 43 DQS8 163
3 DQ0 123 DQ5 44
4DQ1124
5
6DQS
V
SS
125
0126
7DQS0127
8
V
SS
128 DQ6 KEY 89
9 DQ2 129 DQ7 49
10 DQ3 130
11
V
SS
131 DQ12 51
12 DQ8 132 DQ13 52 BA2 172 A14 93 DQS
13 DQ9 133
14
15 DQS
V
SS
134
1135
16 DQS1 136
17
V
SS
137 DQ14 57
18 DQ10 138 DQ15 58 A5 178 A6 99 DQ48 219 DQ53
19 DQ11 139
20
V
SS
140 DQ20 60
21 DQ16 141 DQ21 61 A2 181 A1 102 DQS
22 DQ17 142
23
24 DQS
V
SS
143
2144
25 DQS2 145
26
V
SS
146 DQ22 66
27 DQ18 147 DQ23 67
28 DQ19 148
29
V
SS
149 DQ28 69
30 DQ24 150 DQ29 70 A10/AP 190 BA1 111 DQS
31 DQ25 151
32
33 DQS
V
SS
152
3153
34 DQS3 154
35
V
SS
155 DQ30 75
36 DQ26 156 DQ31 76 S1,NC 196 A13 117 SA0 237 SA1
37 DQ27 157
38
V
SS
158 CB4,NC 78
39 CB0,NC 159 CB5,NC 79 S2,NC 199
40 CB1,NC 160
41
V
SS
161
NOTE : NC = No internal Connection
V
SS
V
SS
DM0,DQS9
,TDQS9
NC,DQS
9
9
,TDQS
V
SS
V
SS
V
SS
DM1,DQS10
,TDQS10
NC,DQS
10
10
,TDQS
V
SS
V
SS
V
SS
DM2,DQS11
,TDQS11
NC,DQS
11
11
,TDQS
V
SS
V
SS
V
SS
DM3,DQS12
,TDQS12
NC,DQS12
12
,TDQS
V
SS
V
SS
V
SS
DM8,DQS17
TDQS17,NC
42 DQS8162
V
SS
164 CB6,NC 84 DQS4 204
45 CB2,NC 165 CB7,NC 85 DQS4 205
46 CB3,NC 166
47
48
V
SS
, NC
V
TT
, NC
V
TT
167 NC(TEST) 87 DQ34 207 DQ39
168 RESET
169 CKE1, NC 90 DQ40 210 DQ45
50 CKE0 170
V
DD
171 NC 92
53 Err_Out/NC 173
54
V
DD
174 A12/BC 95
55 A11 175 A9 96 DQ42 216 DQ47
56 A7 176
V
DD
177 A8 98
59 A4 179
V
DD
62
V
DD
180 A3 101
182
63 NC, CK1 183
64 NC, CK
65
1 184 CK0 105 DQ50 225 DQ55
V
V
V
REFCA
DD
DD
185 CK0 106 DQ51 226
186
187 EVENT,NC 108 DQ56 228 DQ61
68 NC/Par_In 188 A0 109 DQ57 229
V
DD
189
71 BA0 191
72
73 WE
V
DD
192 RAS 113
193 S0 114 DQ58 234 DQ63
74 CAS 194
V
DD
195 ODT0 116
77 ODT1,NC 197
V
DD
80
V
SS
198 S3,NC 119 SA2 239
200 DQ36
81 DQ32 201 DQ37
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
NC,DQS
,TDQS
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
17
17
82 DQ33 202
83
86
V
SS
V
SS
203
206 DQ38
DM4,DQS13
88 DQ35 208
V
SS
209 DQ44
91 DQ41 211
V
SS
212
DM5,DQS14
5 213
94 DQS5 214
V
SS
215 DQ46
97 DQ43 217
V
SS
218 DQ52
100 DQ49 220
V
SS
221
DM6,DQS15
6 222
103 DQS6 223
104
107
110
V
SS
V
SS
V
SS
7 231
224 DQ54
227 DQ60
230
DM7/DQS16
DM7,DQS
112 DQS7 232
V
SS
233 DQ62
115 DQ59 235
V
SS
236
118 SCL 238 SDA
120
V
TT
240
V
SS
,TDQS13
NC,DQS
,TDQS
V
SS
V
SS
V
SS
,TDQS14
NC,DQS
,TDQS
V
SS
V
SS
V
SS
,TDQS15
NC,DQS
,TDQS
V
SS
V
SS
V
SS
TDQS16
,TDQS
V
SS
V
SS
V
DDSPD
V
SS
V
TT
13
13
14
14
15
15
16
16
- 6 -
Rev. 1.2
SCL
SDA
WP/EVENT
SA0 SA1 SA2
SA0 SA1 SA2
EVENT
R1
0 Ω
R2
0 Ω
Registered DIMM
datasheet DDR3L SDRAM
5. Pin Description
Pin Name Description Number Pin Name Description Number
CK0 Clock Input, positive line 1 ODT[1:0] On Die Termination Inputs 2
CK0
CKE[1:0] Clock Enables 2 CB[7:0] Data check bits Input/Output 8
RAS
CAS
WE
S
[3:0] Chip Selects 4
A[9:0],A11,
A[15:13]
A10/AP Address Input/Autoprecharge 1 EVENT
A12/BC
BA[2:0] SDRAM Bank Addresses 3 RESET
SCL Serial Presence Detect (SPD) Clock Input 1
SDA SPD Data Input/Output 1
SA[2:0] SPD Address Inputs 3
Par_In Parity bit for the Address and Control bus 1
Err_Out
NOTE :
*The V
and V
DD
Clock Input, negative line 1 DQ[63:0] Data Input/Output 64
Row Address Strobe 1 DQS[8:0] Data strobes 9
Column Address Strobe 1 DQS[8:0] Data strobes, negative line 9
DM[8:0]/
Write Enable 1
Address Inputs 2\14 RFU Reserved for Future Use 2
Address Input/Burst chop 1 TEST
Parity error found on the Address and Control
bus
pins are tied common to a single power-plane on these designs.
DDQ
1
DQS[17:9]
TDQS[17:9]
DQS
[17:9]
TDQS
V
DD
V
SS
V
REFDQ
V
REFCA
V
TT
V
DDSPD
Data Masks/ Data strobes,
Termination data strobes
Data strobes, negative line, Termination data
[17:9]
strobes
Reserved for optional hardware temperature
sensing
Memory bus test toll (Not Connected and Not
Usable on DIMMs)
Register and SDRAM control pin 1
Power Supply 22
Ground 59
Reference Voltage for DQ 1
Reference Voltage for CA 1
Termination Voltage 4
SPD Power 1
Total 240
9
9
1
1
6. ON DIMM Thermal Sensor
[ Table 1 ] Temperature Sensor Characteristics
Grade Range
B
Resolution 0.25 °C /LSB -
NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM
2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not.
When only the SPD is placed on the module, R2 is placed but R1 is not.
Temperature Sensor Accuracy
Min. Typ . Max.
75 < Ta < 95 - +/- 0.5 +/- 1.0
40 < Ta < 125 - +/- 1.0 +/- 2.0 -
-20 < Ta < 125 - +/- 2.0 +/- 3.0 -
- 7 -
Units NOTE
°C
-
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
7. Input/Output Functional Description
Symbol Typ e Polarity Function
CK0 Input
CK0
CKE[1:0] Input Active High
S
[3:0] Input Active Low
ODT[1:0] Input Active High On-Die Termination control signals
R
AS, CAS, WE Input Active Low
V
REFDQ
V
REFCA
BA[2:0] Input
A[15:13,
12/BC,11,
10/AP,9:0]
DQ[63:0],
CB[7:0]
DM[8:0]
DQS[17:0] I/O Positive Edge Positive line of the differential data strobe for input and output data.
[17:0] I/O Negative Edge Negative line of the differential data strobe for input and output data.
DQS
TDQS[17:9],
TDQS
[17:9]
SA[2:0] IN
SDA I/O
SCL IN
EVENT
V
DDSPD
RESET
Par_In IN Parity bit for the Address and Control bus. ("1" : Odd, "0" : Even)
Err_Out
TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Input
Supply Reference voltage for DQ0-DQ63 and CB0-CB7
Supply Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1.
Input
I/O Data and Check Bit Input/Output pins
OUT
OUT
(open
drain)
Supply
IN
OUT
(open
drain)
Positive
Edge
Negative
Edge
Active Low
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers
and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder when high.
When decoder is disabled, new commands are ignored and previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both
inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in
the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of register outputs.
When sampled at the positive rising edge of the clock, CAS
cuted by the SDRAM.
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank
address also determines mode register is to be accessed during an MRS cycle.
Provided the row address for Active commands and the column address and Auto Precharge bit for Read/
Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8
identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during
Mode Register Set commands.
Active High Masks write data when high, issued concurrently with input data.
V
, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic.
DD
V
Supply Termination Voltage for Address/Command/Control/Clock nets.
TT
TDQS/TDQS
enable the same termination resistance function on TDQS/TDQS
abled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.
X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1
These signals are tied at the system planar to either V
address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to V
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to V
This signal indicates that a thermal event has been detected in the thermal sensing device.The system
should guarantee the electrical level requirement is met for the EVENT
Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from
3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
The RESET
low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set
to low level (the Clock Driver will remain synchronized with the input clock)
Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out
bus line to VDD on the system planar to act as a pull up.
is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will
on the system planar to act as a pull-up.
DDSPD
on the system planar to act as a pull-up.
DDSPD
pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When
, RAS, and WE define the operation to be exe-
that is applied to DQS/DQS. When dis-
SS
or V
to configure the serial SPD EEPROM
DDSPD
pin on TS/SPD part.
- 8 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
8. Pinout Comparison Based On Module Type
Pin
48, 49
120, 240
53 Err_Out
63 NC
64 NC CK1
68 Par_In Connected to the register on all RDIMMs NC Not used on RDIMMs
76 S
77 ODT1, NC
79 S
167 NC TEST input used only on bus analysis probes NC
169 CKE1
171 A15
172 A14 A14
196 A13 A13
198 S
39, 40, 45, 46,
158, 159, 164,
165
125, 134, 143,
152, 161, 203,
212, 221, 230
126, 135, 144,
153, 162, 204,
213, 222, 231
187
NOTE : NC = No internal Connection
Signal NOTE Signal NOTE
V
TT
V
TT
1 Connected to the register on all RDIMMs S1
2, NC
3, NC
CBn Used on all RDIMMs; (n = 0...7) NC, CBn
DQSn,
TDQSn
DQS
TDQS
EVENT
NC
Additional connection for Termination Voltage for
Address/Command/Control/Clock nets.
Termination Voltage for Address/Command/Control/Clock nets.
Connected to the register on all RDIMMs NC Not
used on UDIMMs
Not used on RDIMMs
Connected to the register on dual- and quadrank
RDIMMs; NC on single-rank RDIMMs
Connected to the register on quad-rank
RDIMMs, not connected on single or dual rank
RDIMMs
Connected to the register on dual- and quadrank
RDIMMs; NC on single-rank RDIMMs
Connected to the register on all RDIMMs
Connected to the register on quad-rank
RDIMMs, not connected on single-or dual-rank
RDIMMs
Connected to DQS on x4 SDRAMs,
TDQS on x8 SDRAMs on RDIMMs; (n = 9...17)
n,
Connected to DQS
SDRAMs on RDIMMs; (n=9...17)
n
Connected to optional thermal sensing component.
NC on Modules without a thermal sensing
component.
RDIMM UDIMM
NC Not used on UDIMMs
Termination Voltage for Address/Command/Control/Clock nets.
Used for 2 rank UDIMMs, not used on single-rank
UDIMMs, but terminated
Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs
Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs
TEST input used only on bus analysis
probes
Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs
connected to SDRAMs on UDIMMs. However,
these signals are terminated on
UDIMMs. A15 not routed on some RCs
Used on x72 UDIMMs, (n = 0...7); not
used on x64 UDIMMs
Connected to DM on x8 DRAMs, UDM or
LDM on x16 DRAMs on UDIMMs;
(n = 0...8)
on x4 DRAMs, TDQS on x8
V
TT
NC NC Not used on UDIMMs
CK1
ODT1,NC
NC Not used on UDIMMs
CKE1,
NC
A15, NC Depending on device density, may not be
NC Not used on UDIMMs
DMn
NC Not used on UDIMMs
NC Not used on UDIMMs
- 9 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
9. Registering Clock Driver Specification
9.1 Timing & Capacitance values
TC = TBD
= 1.35V(1.28V~1.45V)
V
Symbol Parameter Conditions
fclock Input Clock Frequency application frequency 300 670 MHz
t
C
IN
C
IN
C
IN
CH/tCL
t
ACT
t
SU
t
H
t
PDM
t
DIS
t
EN
(DATA)
(CLOCK)
(RST)
Pulse duration, CK, CK HIGH or LOW 0.4 -
Inputs active time4 before RESET is taken HIGH
Setup time Input valid before CK/CK 100 - ps
Hold time
Propagation delay, single-bit switching CK/CK to output 0.65 1.0 ns
output disable time(1/2-Clock pre-launch)
output disable time(3/4-Clock pre-launch) 0.25 -
output enable time(1/2-Clock pre-launch)
output enable time(3/4-Clock pre-launch) - 0.25
Data Input Capacitance 1.5 2.5
Data Input Capacitance 2 3
Reset Input Capacitance - 3
DCKE0/1 = LOW and
DCS0/1
= HIGH
Input to remain Valid after CK/
CK
to output float
CK/CK
to output driving
CK/CK
DD
& 1.5V(1.425~1.575V)
Min Max
8-
175 -
0.5 -
-0.5
Units Notes
t
CK
t
CK
t
CK
t
CK
pF
9.2 Clock driver Characteristics
Symbol Parameter Conditions
(cc)
t
jit
t
t
t
jit
t
jit
t
t
t
STAB
t
fdyn
CKsk
(per)
(hper)
Qsk1
Qsk1
dynoff
Cycle-to-cycle period jitter 0 40 ps
Stabilization time -6us
Dynamic phase offset -50 50 ps
Clock Output skew 50 ps
Yn Clock Period jitter -40 40 ps
Half period jitter -50 50 ps
Qn Output to clock tolerance (Standard 1/2 -Clock
Pre-Launch)
Output clock tolerance (3/4 Clock Pre-Launch)
Maximum re-driven dynamic clock off-set -80 80 ps
Output Inversion enabled -100 200
OUtput Inversion disabled -100 300
Output Inversion enabled -100 200
OUtput Inversion disabled -100 300
TC = TBD
V
= 1.35V(1.28V~1.45V)
DD
& 1.5V(1.425~1.575V)
Min Max
Units Notes
ps
ps
- 10 -
Rev. 1.2
A0
Thermal sensor with SPD
A1 A2
SA0 SA1 S A2
SCL
SDA
DQS8
DQS8
DM8/DQS17
DQS17
CB[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D8
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
RS0A
RRASA
RCASA
RWEA
PCK0A
PCK0A
RCLE0A
RODT0A
A[N:0]A
/BA[N:0]A
DQS3
DQS
3
DM3/DQS12
DQS
12
DQ[31:24]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D3
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS2
DQS2
DM2/DQS11
DQS11
DQ[23:16]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D2
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS1
DQS1
DM1/DQS10
DQS10
DQ[15:8]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D1
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS0
DQS0
DM0/DQS9
DQS9
DQ[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D0
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
Vtt
DQS4
DQS4
DM4/DQS13
DQS13
DQ[39:32]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D4
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
RS0B
RRASB
RCASB
RWEB
PCK0B
PCK0B
RCLE0B
RODT0B
A[N:0]B
/BA[N:0]B
DQS5
DQS
5
DM5/DQS14
DQS
14
DQ[47:40]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D5
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS6
DQS6
DM6/DQS15
DQS15
DQ[55:48]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D6
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS7
DQS7
DM7/DQS16
DQS16
DQ[63:56]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D7
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
Vtt
V
SS
V
DD
D0 - D8
V
REFCA
V
DDSPD
Serial PD
1:2
R
E
G
I
S
T
E
R
S1*
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CK0
RESET
**
RST
** : SDRAMs D[8:0]
RS0B-> CS0 : SDRAMs D[7:4]
RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D8
RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D8
RRASA
-> RAS : SDRAMs D[3:0], D8
RCASA
-> CAS : SDRAMs D[3:0], D8
RCKE0A -> CKE0 : SDRAMs D[3:0], D8
ODT0
PAR_IN
RODT0A -> ODT0 : SDRAMs D[3:0], D8
S0* RS0A-> CS0 : SDRAMs D[3:0], D8
EVENT EVENT
V
TT
V
REFDQ
D0 - D8
D0 - D8
D0 - D8
NOTE :
1. ZQ resistors are 240 ± 1% For all other resistor values refer to the appropriate wiring diagram.
RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4]
RA[N:0]B -> A[N:0] : SDRAMs D[7:4]
RRASB
-> RAS : SDRAMs D[7:4]
RCASB
-> CAS : SDRAMs D[7:4]
RWEA
-> WE : SDRAMs D[3:0], D8
RWEB
-> WE : SDRAMs D[7:4]
RCKE0B -> CKE0 : SDRAMs D[7:4]
RODT0B -> ODT0 : SDRAMs D[7:4]
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0A -> CK : SDRAMs D[7:4]
PCK
0A -> CK : SDRAMs D[3:0], D8
PCK
0A -> CK : SDRAMs D[7:4]
Err_out
QERR
RST
CK0
*S[3:2], CKE1, ODT1, CK1 and CK1 are NC
(Unused register inputs ODT1 and CKE1 have a 330 ohm resistor to ground)
Registered DIMM
datasheet DDR3L SDRAM
10. Function Block Diagram:
10.1 2GB, 256Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)
- 11 -
Rev. 1.2
A0
Thermal sensor with SPD
A1 A2
SA0 SA1 SA2
SCL
SDA
DQS8
DQS8
DM8/DQS17
DQS17
CB[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D8
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
RS0A
RRASA
RCASA
RWEA
PCK0A
PCK0A
RCKE0A
RODT0A
A[N:0]A
/BA[N:0]A
Vtt
V
SS
V
DD
D0 - D17
V
REFCA
V
DDSPD
Serial PD
EVENT EVENT
V
TT
V
REFDQ
D0 - D17
D0 - D17
D0 - D17
NOTE :
1. Unless otherwise noted, resistor values are 15Ω ± 5%.
2. RS0 and RS1 alternate between the back and front sides of the DIMM.
3. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate
wiring diagram.
4. See the wiring diagrams for all resistors associated with the command, address
and control bus.
DQS
DQS
TDQS
TDQS
DQ[7:0]
D17
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
RS1A
PCK1A
PCK1A
RCKE1A
RODT1A
DQS3
DQS3
DM3/DQS12
DQS12
DQ[31:24]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D3
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
D12
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS2
DQS2
DM2/DQS11
DQS11
DQ[23:16]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D2
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
D11
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS1
DQS1
DM1/DQS10
DQS10
DQ[15:8]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D1
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
D10
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS0
DQS0
DM0/DQS9
DQS9
DQ[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D0
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
D9
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS4
DQS4
DM4/DQS13
DQS13
DQ[39:32]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D4
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
RS0B
RRASB
RCASB
RWEB
PCK0B
PCK0B
RCKE0B
RODT0B
A[N:0]B
/BA[N:0]B
Vtt
DQS
DQS
TDQS
TDQS
DQ[7:0]
D13
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
RS1B
PCK1B
PCK1B
RCKE1B
RODT1B
DQS5
DQS5
DM5/DQS14
DQS14
DQ[47:40]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D5
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
D14
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS6
DQS6
DM6/DQS15
DQS15
DQ[55:48]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D6
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
D15
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS7
DQS7
DM7/DQS16
DQS16
DQ[63:56]
DQS
DQS
TDQS
TDQS
DQ[7:0]
D7
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
D16
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
1:2
R
E
G
I
S
T
E
R
S1*
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
RESET
**
RST
** : SDRAMs D[8:0]
RS1B-> CS1 : SDRAMs D[16:13]
RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17
RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17
RRASA
-> RAS : SDRAMs D[3:0], D[12:8], D17
RCASA
-> CAS : SDRAMs D[3:0], D[12:8], D17
RCKE0A -> CKE0 : SDRAMs D[3:0], D8
PAR_IN
S0* RS0A-> CS0 : SDRAMs D[3:0], D8
RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]
RA[N:0]B -> A[N:0] : SDRAMs D[7:4, D[16:13]]
RRASB
-> RAS : SDRAMs D[7:4], D[16:13]
RCASB
-> CAS : SDRAMs D[7:4], D[16:13]
RWEA
-> WE : SDRAMs D[3:0], D[12:8], D17
RWEB
-> WE : SDRAMs D[7:4], D[16:13]
RCKE0B -> CKE0 : SDRAMs D[7:4]
PCK1A -> CK : SDRAMs D[12:9], D17
PCK1B -> CK : SDRAMs D[16:13]
PCK
0A -> CK : SDRAMs D[3:0], D8
PCK
0B -> CK : SDRAMs D[7:4]
Err_out
QERR
RST
CK0
*S[3:2], CKE1, ODT1, CK1 and CK1 are NC
CKE1
RCKE1A -> CKE1 : SDRAMs D[12:9], D17
RCKE1B -> CKE1 : SDRAMs D[16:13]
ODT0
RODT0A -> ODT0 : SDRAMs D[3:0], D8
RODT0B -> ODT0 : SDRAMs D[7:4]
ODT1
RODT1A -> ODT1 : SDRAMs D[12:9], D17
RODT1A -> ODT1 : SDRAMs D[16:13]
CK0
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0B -> CK : SDRAMs D[7:4]
PCK1A -> CK : SDRAMs D[12:9], D17
PCK
1B -> CK : SDRAMs D[16:13]
RS
0B-> CS0 : SDRAMs D[7:4]
RS
1A-> CS1 : SDRAMs D[12:9], D17
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
Registered DIMM
datasheet DDR3L SDRAM
10.2 4GB, 512Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
- 12 -
Rev. 1.2
DQ[27:24]
DQ[19:16]
DQS8
DQS8
CB[3:0]
DQS
DQS
DQ[3:0]
D8
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
RS0A
RRAS
A
RCASARWE
A
PCK0A
PCK0
A
RCKE0A
RODT0A
A[N:0]A
/BA[N:0]A
VSS
VSS
DQS17
DQS17
CB[7:4]
DQS
DQS
D17
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DM
DQ[3:0]
DM
DQS3
DQS3
DQ[27:24]
DQS
DQS
DQ[3:0]
D3
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DQS17
DQS17
DQ[31:28]
DQS
DQS
D12
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DM
DQ[3:0]
DM
DQS8
DQS8
DQ[19:16]
DQS
DQS
DQ[3:0]
D2
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DQS17
DQS17
DQ[23:20]
DQS
DQS
D11
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DM
DQ[3:0]
DM
DQS8
DQS8
DQ[11:8]
DQS
DQS
DQ[3:0]
D1
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DQS17
DQS17
DQ[15:12]
DQS
DQS
D10
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DM
DQ[3:0]
DM
DQS8
DQS
8
DQ[3:0]
DQS
DQS
DQ[3:0]
D0
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DQS17
DQS
17
DQ[7:4]
DQS
DQS
D9
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DM
DQ[3:0]
DM
DQS8
DQS8
DQ[35:32]
DQS
DQS
DQ[3:0]
D4
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
RS0B
RRAS
B
RCASBRWE
B
PCK0B
PCK0
B
RCKE0B
RODT0B
A[N:0]B
/BA[N:0]B
VSS
VSS
DQS17
DQS17
DQ[39:36]
DQS
DQS
D13
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DM
DQ[3:0]
DM
DQS8
DQS8
DQ[43:40]
DQS
DQS
DQ[3:0]
D5
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DQS17
DQS17
DQ[47:44]
DQS
DQS
D14
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DM
DQ[3:0]
DM
DQS8
DQS8
DQ[51:48]
DQS
DQS
DQ[3:0]
D6
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DQS17
DQS17
DQ[55:52]
DQS
DQS
D15
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DM
DQ[3:0]
DM
DQS8
DQS8
DQ[59:56]
DQS
DQS
DQ[3:0]
D7
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DQS17
DQS17
DQ[63:60]
DQS
DQS
D16
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
VSS
VSS
DM
DQ[3:0]
DM
Vtt
Vtt
V
SS
V
DD
D0 - D17
V
REFCA
V
DDSPD
Serial PD
V
TT
V
REFDQ
D0 - D17
D0 - D17
D0 - D17
NOTE :
1. Unless otherwise noted, resistor values are 15Ω ± 5%.
2. See the wiring diagrams for all resistors associated with the command, address
and control bus.
3. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate
wiring diagram.
1:2
R
E
G
I
S
T
E
R
S1*
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
RESET
**
RST
** : SDRAMs D[17:0]
RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17
RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17
RRASA
-> RAS : SDRAMs D[3:0], D[12:8], D17
RCASA
-> CAS : SDRAMs D[3:0], D[12:8], D17
RCKE0A -> CKE0 : SDRAMs D[3:0], D[12:8], D17
PAR_IN
S0* RS0A-> CS0 : SDRAMs D[3:0], D[12:8], D17
RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]
RA[N:0]B -> A[N:0] : SDRAMs D[7:4], D[16:13]
RRASB
-> RAS : SDRAMs D[7:4], D[16:13]
RCASB
-> CAS : SDRAMs D[7:4], D[16:13]
RWEA
-> WE : SDRAMs D[3:0], D[12:8], D17
RWEB
-> WE : SDRAMs D[7:4], D[16:13]
RCKE0B -> CKE0 : SDRAMs D[7:4], D[16:13]
PCK
0A -> CK : SDRAMs D[3:0], D[12:8], D17
PCK
0B -> CK : SDRAMs D[7:4], D[16:13]
Err_out
QERR
RST
CK0
*S[3:2], CKE1, ODT1, CK1 and CK1 are NC
ODT0
RODT0A -> ODT0 : SDRAMs D[3:0], D[12:8], D17
RODT0B -> ODT0 : SDRAMs D[7:4], D[16:13]
CK0
PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK : SDRAMs D[7:4], D[16:13]
RS0B-> CS0 : SDRAMs D[7:4], D[16:13]]
(Unused register inputs ODT1 and CKE1 have a 330
Ω
resistor to ground)
A0
Thermal sensor with SPD
A1 A2
SA0 SA1 SA2
SCL
SDA
EVENT EVENT
Registered DIMM
datasheet DDR3L SDRAM
10.3 4GB, 512Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs)
- 13 -
Rev. 1.2
DQS17
DQS17
VSS
CB[7:4]
DQS
DQS
DM
DQ[3:0]
D17
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
RS0A
RRASA
RCASA
RWEA
PCK0A
PCK0A
RCKE0A
RODT0A
A[N:0]A
/BA[N:0]A
D35
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
RS1A
PCK1A
PCK1A
RCKE1A
RODT1A
DQS
DQS
DM
DQ[3:0]
DQS12
DQS12
VSS
DQ[31:28]
DQS
DQS
DM
DQ[3:0]
D12
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D30
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
DQS11
DQS11
VSS
DQ[23:20]
DQS
DQS
DM
DQ[3:0]
D11
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D29
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
DQS10
DQS10
VSS
DQ[15:12]
DQS
DQS
DM
DQ[3:0]
D10
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D28
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
DQS0
DQS0
VSS
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
D0
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D18
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
Vtt
DQS17
DQS17
VSS
CB[3:0]
DQS
DQS
DM
DQ[3:0]
D8
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
RS0A
RRASA
RCASA
RWEA
PCK0A
PCK0A
RCKE0A
RODT0A
A[N:0]A
/BA[N:0]A
D26
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
RS1A
PCK1A
PCK1A
RCKE1A
RODT1A
DQS
DQS
DM
DQ[3:0]
DQS12
DQS12
VSS
DQ[27:24]
DQS
DQS
DM
DQ[3:0]
D3
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D21
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
DQS11
DQS11
VSS
DQ[19:16]
DQS
DQS
DM
DQ[3:0]
D2
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D20
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
DQS10
DQS10
VSS
DQ[11:8]
DQS
DQS
DM
DQ[3:0]
D1
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D19
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
DQS0
DQS0
VSS
DQ[7:4]
DQS
DQS
DM
DQ[3:0]
D9
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D27
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
Vtt
Registered DIMM
datasheet DDR3L SDRAM
10.4 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)
- 14 -
Rev. 1.2
V
SS
V
DD
D0 - D35
V
REFCA
V
DDSPD
Serial PD
V
TT
V
REFDQ
D0 - D35
D0 - D35
D0 - D35
DQS14
DQS14
VSS
CB[47:44]
DQS
DQS
DM
DQ[3:0]
D14
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
RS0B
RRASB
RCASB
RWEB
PCK0B
PCK0B
RCKE0B
RODT0B
A[N:0]B
/BA[N:0]B
D32
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
RS1B
PCK1B
PCK1B
RCKE1B
RODT1B
DQS
DQS
DM
DQ[3:0]
DQS4
DQS4
VSS
DQ[35:32]
DQS
DQS
DM
DQ[3:0]
D4
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D22
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
DQS16
DQS16
VSS
DQ[63:60]
DQS
DQS
DM
DQ[3:0]
D16
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D34
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
DQS10
DQS10
VSS
DQ[59:56]
DQS
DQS
DM
DQ[3:0]
D7
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D25
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
Vtt
DQS13
DQS13
VSS
CB[39:36]
DQS
DQS
DM
DQ[3:0]
D13
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
RS0B
RRASB
RCASB
RWEB
PCK0B
PCK0B
RCKE0B
RODT0B
A[N:0]B
/BA[N:0]B
D31
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
RS1B
PCK1B
PCK1B
RCKE1B
RODT1B
DQS
DQS
DM
DQ[3:0]
DQS5
DQS5
VSS
DQ[43:40]
DQS
DQS
DM
DQ[3:0]
D5
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D23
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
DQS15
DQS15
VSS
DQ[55:52]
DQS
DQS
DM
DQ[3:0]
D15
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D33
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
DQS6
DQS6
VSS
DQ[51:48]
DQS
DQS
DM
DQ[3:0]
D6
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
D24
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
DQS
DQS
DM
DQ[3:0]
Vtt
A0
Integrated Thermal sensor in SPD
A1 A2
SA0 SA1 SA2
SCL
SDA
EVENT EVENT
Serial PD w/ integrated Thermal sensor
NOTE:
1. See wiring diagrams for resistor values.
2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240 ± 1%)ohms...
1:2
R
E
G
I
S
T
E
R
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
RESET
RST : SDRAMs D[35:0]
PAR_IN
S0
RS0A -> CS0 : SDRAMs D[3:0], D[12:0], D17
ERR_OUT
RST
CK0
ODT0
CK0
RS0B -> CS0 : SDRAMs D[7:4], D[16:13]
RS
1A -> CS1 : SDRAMs D[21:18], D[30:26], D35
RS
1B -> CS1 : SDRAMs D[25:22], D[34:31]
RBA[N:0]A -> BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RBA[N:0]B -> BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D [34:31]
RA[N:0]A -> A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RA[N:0]B -> A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RRAS
A -> RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RRAS
B -> RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCAS
A -> CAS: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
RCAS
B -> CAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
RWE
A -> WE: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
RWE
B -> WE: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
RCKE0A -> CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B -> CKE0: SDRAMs D[7:4], D[16:13]
RODT0A -> ODT0: SDRAMs D[3:0], D[12:8], D17
RODT0B -> ODT0: SDRAMs D[7:4], D[16:13]
PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4], D[16:13]
PCK1A -> CK: SDRAMs D[21:18], D[30:26], D35
PCK1B -> CK: SDRAMs D[25:22], D[34:31]
S1
CKE1
RCKE1A -> CKE1: SDRAMs D[21:18], D[30:26], D35
RCKE1B -> CKE1: SDRAMs D[25:22], D[34:31]
ODT1
RODT1A -> ODT1: SDRAMs D[21:18], D[30:26], D35
RODT1B -> ODT1: SDRAMs D[25:22], D[34:31]
PCK0
A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0
B -> CK: SDRAMs D[7:4], D[16:13]
PCK1
A -> CK: SDRAMs D[21:18], D[30:26], D35
PCK1
B -> CK: SDRAMs D[25:22], D[34:31]
CK0
CK0
120
Ω
±
3%
Registered DIMM
datasheet DDR3L SDRAM
- 15 -
Rev. 1.2
DQS0
DQS0
DQ[7:0]
DQS
DQS
DQ[7:0]
U0
CKCSCK
CKE
ODT
ZQ
PCK0
CS0
PCK0
WCKE0
WODT0
DQS
DQS
DQ[7:0]
U9
CKCSCK
CKE
ODT
ZQ
PCK0
CS1
PCK0
WCKE1
VDD
DQS
DQS
DQ[7:0]
U18
CKCSCK
CKE
ODT
ZQ
PCK2
CS2
PCK2
WCKE0
WODT1
DQS
DQS
DQ[7:0]
U27
CKCSCK
CKE
ODT
ZQ
PCK2
CS3
PCK2
WCKE1
VDD
DQS1
DQS1
DQ[15:8]
DQS
DQS
DQ[7:0]
U1
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U10
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U19
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U28
CKCSCK
CKE
ODT
ZQ
DQS2
DQS2
DQ[23:16]
DQS
DQS
DQ[7:0]
U2
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U11
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U20
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U29
CKCSCK
CKE
ODT
ZQ
DQS3
DQS3
DQ[31:24]
DQS
DQS
DQ[7:0]
U3
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U12
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U21
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U30
CKCSCK
CKE
ODT
ZQ
DQS8
DQS8
CB[7:0]
DQS
DQS
DQ[7:0]
U4
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U13
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U22
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U31
CKCSCK
CKE
ODT
ZQ
DQS4
DQS4
DQ[39:32]
DQS
DQS
DQ[7:0]
U5
CKCSCK
CKE
ODT
ZQ
PCK1
CS0
PCK1
ECKE0
EODT0
DQS
DQS
DQ[7:0]
U14
CKCSCK
CKE
ODT
ZQ
PCK1
CS1
PCK1
ECKE1
VDD
DQS
DQS
DQ[7:0]
U23
CKCSCK
CKE
ODT
ZQ
PCK3
CS2
PCK3
ECKE0
EODT1
DQS
DQS
DQ[7:0]
U32
CKCSCK
CKE
ODT
ZQ
PCK3
CS3
PCK3
ECKE1
VDD
DQS5
DQS5
DQ[47:40]
DQS
DQS
DQ[7:0]
U6
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U15
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U24
CKCSCK
CKE
ODT
ZQ
DQS6
DQS6
DQ[55:48]
DQS
DQS
DQ[7:0]
U7
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U16
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U25
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U34
CKCSCK
CKE
ODT
ZQ
DQS3
DQS3
DQ[31:24]
DQS
DQS
DQ[7:0]
U8
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U17
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U26
CKCSCK
CKE
ODT
ZQ
DQS
DQS
DQ[7:0]
U35
CKCSCK
CKE
ODT
ZQ
Vtt
V
SS
V
DD
D0 - D35
V
REFCA
V
DDSPD
Serial PD
V
TT
V
REFDQ
D0 - D35
D0 - D35
D0 - D35
NOTE :
1. Unless otherwise noted, resistor values are 15Ω ± 5%.
2. See the wiring diagrams for all resistors associated with the command, address and control bus.
3. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to
the appropriate wiring diagram.
A0
Thermal sensor with SPD
A1 A2
SA0 SA1 SA2
SCL
SDA
EVENT EVENT
Vtt
1:2
R
E
G
I
S
T
E
R
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
RESET
RST : SDRAMs D[35:0]
PAR_IN
S0 RS0-> CS0 : SDRAMs D[8:0]
Err_out
QERR
RST
CK0
ODT0
CK0
S1 RS1-> CS1 : SDRAMs D[17:9]
RS
2-> CS2 : SDRAMs D[26:18]
RS
3-> CS3 : SDRAMs D[35:27]
WBA[N:0] -> BA[N:0]: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27 ]
EBA[N:0] -> BA[N:0]: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
WA[N:0] -> A[N:0]: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
EA[N:0] -> A[N:0]: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
WRAS
-> RAS: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
ERAS
-> RAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
WCAS
-> CAS: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
ECAS
-> CAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
WWE
-> WE: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
EWE
-> WE: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
WCKE0 -> CKE0: SDRAMs D[4:0], D[22:18]
ECKE0 -> CKE0: SDRAMs D[8:5], D[26:23]
WODT0 -> ODT0: SDRAMs D[4:0]
EODT0 -> ODT0: SDRAMs D[8:5]
PCK0 -> CK: SDRAMs D[4:0], D[13:9]
PCK1 -> CK: SDRAMs D[8:5], D[26:23]
PCK2 -> CK: SDRAMs D[22:18], D[31:27]
PCK3 -> CK: SDRAMs D[17:14], D[35:32]
S2
S3
CKE1
WCKE1 -> CKE1: SDRAMs D[13:9], D[31:27]
ECKE1 -> CKE1: SDRAMs D[17:14], D[35:32]
ODT1
WODT1 -> ODT1: SDRAMs D[22:18]
EODT1 -> ODT1: SDRAMs D[26:23]
PCK0
-> CK: SDRAMs D[4:0], D[13:9]
PCK1
-> CK: SDRAMs D[8:5], D[26:23]
PCK2
-> CK: SDRAMs D[22:18], D[31:27]
PCK3 -> CK: SDRAMs D[17:14], D[35:32]
DQS
DQS
DQ[7:0]
U33
CKCSCK
CKE
ODT
ZQ
Registered DIMM
datasheet DDR3L SDRAM
10.5 8GB, 1Gx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs)
- 16 -
Rev. 1.2
DQS8
DQS8
VSS
CB[3:0]
DQS
DQS
DM
DQ[3:0]
D9
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ARS0A
ARRASA
ARCASA
ARWEA
APCK0A
APCK0A
ARCKE0A
ARODT0A
ARA[N:0]A
/ARBA[N:0]A
ARS1A
ARCKE1A
VDD
BRS2A
BRRASA
BRCASA
BRWEA
BPCK0A
BPCK0A
BRCKE0A
BRODT1A
BRA[N:0]A
/BRBA[N:0]A
BRS3A
BRCKE1A
VDD
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D8
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D45
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D44
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS3
DQS3
VSS
DQ[27:24]
DQS
DQS
DM
DQ[3:0]
D7
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D6
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D47
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D46
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS2
DQS2
VSS
DQ[19:16]
DQS
DQS
DM
DQ[3:0]
D5
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D4
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D49
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D48
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS1
DQS1
VSS
DQ[11:8]
DQS
DQS
DM
DQ[3:0]
D3
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D2
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D51
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D50
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS0
DQS0
VSS
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
D1
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D0
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D53
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D52
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
Vtt
Registered DIMM
datasheet DDR3L SDRAM
10.6 16GB, 2Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs)
- 17 -
Rev. 1.2
DQS17
DQS17
VSS
CB[7:4]
DQS
DQS
DM
DQ[3:0]
D27
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ARS0A
ARRASA
ARCASA
ARWEA
APCK0A
APCK0A
ARCKE0A
ARODT0A
ARA[N:0]A
/ARBA[N:0]A
ARS1A
ARCKE1A
VDD
BRS2A
BRRASA
BRCASA
BRWEA
BPCK0A
BPCK0A
BRCKE0A
BRODT1A
BRA[N:0]A
/BRBA[N:0]A
BRS3A
BRCKE1A
VDD
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D26
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D63
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D62
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS12
DQS12
VSS
DQ[31:28]
DQS
DQS
DM
DQ[3:0]
D25
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D24
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D65
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D64
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS11
DQS11
VSS
DQ[23:20]
DQS
DQS
DM
DQ[3:0]
D23
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D22
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D67
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D66
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS10
DQS10
VSS
DQ[15:12]
DQS
DQS
DM
DQ[3:0]
D21
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D20
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D69
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D68
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS9
DQS9
VSS
DQ[7:4]
DQS
DQS
DM
DQ[3:0]
D19
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D18
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D71
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D70
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
Vtt
Registered DIMM
datasheet DDR3L SDRAM
- 18 -
Rev. 1.2
DQS4
DQS4
VSS
DQ[35:32]
DQS
DQS
DM
DQ[3:0]
D11
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ARS0A
ARRASA
ARCASA
ARWEA
APCK0A
APCK0A
ARCKE0A
ARODT0A
ARA[N:0]A
/ARBA[N:0]A
ARS1A
ARCKE1A
VDD
BRS2A
BRRASA
BRCASA
BRWEA
BPCK0A
BPCK0A
BRCKE0A
BRODT1A
BRA[N:0]A
/BRBA[N:0]A
BRS3A
BRCKE1A
VDD
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D10
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D43
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D42
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS5
DQS5
VSS
DQ[43:40]
DQS
DQS
DM
DQ[3:0]
D13
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D12
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D41
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D40
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS6
DQS6
VSS
DQ[51:48]
DQS
DQS
DM
DQ[3:0]
D15
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D14
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D39
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D38
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS7
DQS7
VSS
DQ[59:56]
DQS
DQS
DM
DQ[3:0]
D17
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D16
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D37
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D36
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
Vtt
Registered DIMM
datasheet DDR3L SDRAM
- 19 -
Rev. 1.2
DQS13
DQS13
VSS
DQ[39:36]
DQS
DQS
DM
DQ[3:0]
D29
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ARS0A
ARRASA
ARCASA
ARWEA
APCK0A
APCK0A
ARCKE0A
ARODT0A
ARA[N:0]A
/ARBA[N:0]A
ARS1A
ARCKE1A
VDD
BRS2A
BRRASA
BRCASA
BRWEA
BPCK0A
BPCK0A
BRCKE0A
BRODT1A
BRA[N:0]A
/BRBA[N:0]A
BRS3A
BRCKE1A
VDD
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D28
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D61
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D60
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS14
DQS14
VSS
DQ[47:44]
DQS
DQS
DM
DQ[3:0]
D31
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D30
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D59
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D58
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS15
DQS15
VSS
DQ[55:52]
DQS
DQS
DM
DQ[3:0]
D33
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D32
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D57
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D56
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
DQS16
DQS16
VSS
DQ[63:60]
DQS
DQS
DM
DQ[3:0]
D35
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSS VSSZQ
DQS
DQS
DM
DQ[3:0]
D34
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQ
DQS
DQS
DM
DQ[3:0]
D55
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
VSSZQ
DQS
DQS
DM
DQ[3:0]
D54
CS
RAS
CASWECKCKCKE
ODT
A[N:0]/BA[N:0]
ZQVSS
Vtt
V
SS
V
DD
D0 - D71
V
REFCA
V
DDSPD
Serial PD
V
TT
V
REFDQ
D0 - D71
D0 - D71
D0 - D71
A0
Integrated Thermal sensor with SPD
A1 A2
SA0 SA1 SA2
SCL
SDA
EVENT_n EVENT_n
Serial PD w/integrated Thermal Sensor
NOTE :
1. Unless otherwise noted, resistor values are 15Ω ± 5%.
2. See the wiring diagrams for all resistors associated with the command, address and control bus.
3. ZQ resistors are 240Ω ± 1%. For all other resistor values refer to the appropriate wiring diagram.
Registered DIMM
datasheet DDR3L SDRAM
- 20 -
Rev. 1.2
1:2
R
E
G
I
S
T
E
R
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
RST
: SDRAMs D[71:0]
ARS1B-> CS0 : SDRAMs D10, D12, D14, D16
ARBA[N:0]A -> BA[N:0] : SDRAMs D[9:0], D[27:18]
ARA[N:0]A -> A[N:0] : SDRAMs D[9:0], D[27:18]
ARRASA
-> RAS : SDRAMs D[9:0], D[27:18]
ARCASA
-> CAS : SDRAMs D[9:0], D[27:18]
ARCKE0A -> CKE1 : SDRAMs D1, D3, D5, D7, D9
PAR_IN
S0 ARS0A-> CS1 : SDRAMs D1, D3, D5, D7, D9
ARBA[N:0]B -> BA[N:0] : SDRAMs D[17:10], D[35:28]
ARA[N:0]B -> A[N:0] : SDRAMs D[17:10], D[35:28]
ARRASB
-> RAS : SDRAMs D[17:10], D[35:28]
ARCASB
-> CAS : SDRAMs D[17:10], D[35:28]
ARWEA
-> WE : SDRAMs D[9:0], D[27:18]
ARWEB
-> WE : SDRAMs D[17:10], D[35:28]
ARCKE0B -> CKE1 : SDRAMs D11, D13, D15, D17
APCK1A -> CK : SDRAMs D[27:18]
APCK1B -> CK : SDRAMs D[35:28]
APCK
0A -> CK : SDRAMs D[9:0]
APCK
0B -> CK : SDRAMs D[17:10]
CKE1
ARCKE1A -> CKE0 : SDRAMs D0, D2, D4, D6, D8
ARCKE1B -> CKE0 : SDRAMs D10, D12, D14, D16
ODT0
ARODT0A -> ODT1 : SDRAMs D1, D3, D5, D7, D9
ARODT0B -> ODT1 : SDRAMs D11, D13, D15, D17
APCK0A -> CK : SDRAMs D[9:0]
APCK0B -> CK : SDRAMs D[17:10]
APCK1A -> CK : SDRAMs D[27:18]
APCK
1B -> CK : SDRAMs D[35:28]
ARS
0B-> CS1 : SDRAMs D11, D13, D15, D17
ARS
1A-> CS0 : SDRAMs D0, D2, D4, D6, D8
CK0_c
CK0_t
120Ω
CK1
CK1
120Ω
Err_out
RST_n
RESET
D19, D21, D23, D25, D27
D29, D31, D33, D35
D18, D20, D22, D24, D26
D28, D30, D32, D34
D19, D21, D23, D25, D27
D29, D31, D33, D35
D18, D20, D22, D24, D26
D28, D30, D32, D34
D19, D21, D23, D25
D29, D31, D33, D35
1:2
R
E
G
I
S
T
E
R
S3
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
BRS3B-> CS0 : SDRAMs D36, D38, D40, D42
BRBA[N:0]A -> BA[N:0] : SDRAMs D[53:44], D[71:62]
BRA[N:0]A -> A[N:0] : SDRAMs D[53:44], D[71:62]
BRRASA
-> RAS : SDRAMs D[53:44], D[71:62]
BRCASA
-> CAS : SDRAMs D[53:44], D[71:62]
BRCKE0A -> CKE1 : SDRAMs D45, D47, D49, D51, D53
PAR_IN
S2 BRS2A-> CS1 : SDRAMs D45, D47, D49, D51, D53
BRBA[N:0]B -> BA[N:0] : SDRAMs D[43:36], D[61:54]
BRA[N:0]B -> A[N:0] : SDRAMs D[43:36], D[61:54]
BRRASB
-> RAS : SDRAMs D[43:36], D[61:54]
BRCASB
-> CAS : SDRAMs D[43:36], D[61:54]
BRWEA
-> WE : SDRAMs D[53:44], D[71:62]
BRWEB
-> WE : SDRAMs D[43:36], D[61:54]
BRCKE0B -> CKE1 : SDRAMs D37, D39, D41, D43
BPCK1A -> CK : SDRAMs D[71:62]
BPCK1B -> CK : SDRAMs D[61:54]
BPCK
0A -> CK : SDRAMs D[53:44]
BPCK
0B -> CK : SDRAMs D[43:36]
CKE1
BRCKE1A -> CKE0 : SDRAMs D44, D46, D48, D50, D52
BRCKE1B -> CKE0 : SDRAMs D36, D38, D40, D42
ODT1
BRODT1A -> ODT1 : SDRAMs D45, D47, D49, D51, D53
BRODT1B -> ODT1 : SDRAMs D37, D39, D41, D43
BPCK0A -> CK : SDRAMs D[53:44]
BPCK0B -> CK : SDRAMs D[43:36]
BPCK1A -> CK : SDRAMs D[71:62]
BPCK
1B -> CK : SDRAMs D[61:54]
BRS
2B-> CS1 : SDRAMs D37, D39, D41, D43
BRS
3A-> CS0 : SDRAMs D44, D46, D48, D50, D52
CK0_c
CK0_t
120Ω
Err_out
RST_n
RESET
D63, D65, D67, D69, D71
D55, D57, D59, D61
D62, D64, D66, D68, D70
D54, D56, D58, D60
D63, D65, D67, D69, D71
D55, D57, D59, D61
D62, D64, D66, D68, D70
D54, D56, D58, D60
D63, D65, D67, D69, D71
D55, D57, D59, D61
A B
Registered DIMM
datasheet DDR3L SDRAM
- 21 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
11. Absolute Maximum Ratings
11.1 Absolute Maximum DC Ratings
Symbol Parameter Rating Units NOTE
V
DD
V
Voltage on V
DDQ
V
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and V
equal to or less than 300mV.
Voltage on any pin relative to V
IN, VOUT
T
Storage Temperature -55 to +100 °C 1, 2
STG
DDQ
Voltage on VDD pin relative to V
pin relative to V
DDQ
must be within 300mV of each other at all times;and V
SS
SS
SS
must be not greater than 0.6 x V
REF
11.2 DRAM Component Operating Temperature Range
Symbol Parameter rating Unit NOTE
T
OPER
NOTE :
1. Operating Temperature T
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
OPER
Operating Temperature Range 0 to 95 °C 1, 2, 3
-0.4 V ~ 1.975 V V 1,3
-0.4 V ~ 1.975 V V 1,3
-0.4 V ~ 1.975 V V 1
, When VDD and V
DDQ
are less than 500mV; V
DDQ
REF
may be
12. AC & DC Operating Conditions
12.1 Recommended DC Operating Conditions
Symbol Parameter Operation Voltage
V
DD
V
DDQ
NOTE:
1. Under all conditions V
tracks with VDD. AC parameters are measured with VDD and V
2. V
DDQ
3. V
& V
DD
DDQ
Supply Voltage
Supply Voltage for Output
must be less than or equal to VDD.
DDQ
rating are determinied by operation voltage.
1.35V 1.283 1.35 1.45 V 1, 2, 3
1.5V 1.425 1.5 1.575 V 1, 2, 3
1.35V 1.283 1.35 1.45 V 1, 2, 3
1.5V 1.425 1.5 1.575 V 1, 2, 3
DDQ
tied together.
Rating
Min. Typ . Max.
Units NOTE
- 22 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
13. AC & DC Input Measurement Levels
13.1 AC & DC Logic Input Levels for Single-ended Signals
[ Table 2 ] Single Ended AC and DC input levels for Command and Address
Symbol Parameter
(DC90)
V
IH.CA
V
(DC90)
IL.CA
V
(AC160)
IH.CA
V
(AC160)
IL.CA
V
(AC135)
IH.CA
V
(AC135)
IL.CA
V
REFCA
(DC100)
V
IH.CA
V
(DC100)
IL.CA
V
(AC175)
IH.CA
V
(AC175)
IL.CA
V
(AC150)
IH.CA
V
(AC150)
IL.CA
V
REFCA
NOTE :
1. For input only pins except RESET
2. See "Overshoot and Undershoot specifications" section.
3. The AC peak noise on V
4. For reference : approx. V
5. V
(dc) is used as a simplified symbol for V
IH
6. V
(dc) is used as a simplified symbol for V
IL
(ac) is used as a simplified symbol for V
7. V
IH
used when VREF + 150mV is referenced.
(ac) is used as a simplified symbol for V
8. V
IL
when V
DC input logic high
DC input logic low
AC input logic high
AC input logic low Note 2
AC input logic high
AC input logic lowM Note 2
Reference Voltage for ADD,
(DC)
CMD inputs
DC input logic high
DC input logic low
AC input logic high
AC input logic low Note 2
AC input logic high
AC input logic low Note 2
Reference Voltage for ADD,
(DC)
CMD inputs
, V
REF
DD
- 150mV is referenced.
REF
= V
REF
may not allow V
/2 ± 15mV
(DC)
REFCA
to deviate from V
REF
(a) 1.35V : DC90, b) 1.5V : DC100)
IH.CA
(a) 1.35V : DC90, b) 1.5V : DC100)
IL.CA
(AC175) and V
IH.CA
(AC175) and V
IL.CA
Min. Max.
V
REF
V
V
REF
V
REF
0.49*V
V
REF
V
V
REF
V
REF
0.49*V
(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
REF
(AC150); V
IH.CA
(AC150); V
IL.CA
DDR3-800/1066/1333/1600
1.35V
+ 90 V
SS
+ 160
+135
DD
1.5V
+ 100 V
SS
+ 175
+150
DD
(AC175) value is used when V
IH.CA
(AC175) value is used when V
IL.CA
DD
V
- 90
REF
Note 2 mV 1,2
V
- 160
REF
Note 2 mV 1,2
V
-135
REF
0.51*V
DD
DD
V
- 100
REF
Note 2 mV 1,2,7
V
- 175
REF
Note 2 mV 1,2,7
V
-150
REF
0.51*V
DD
+ 175mV is referenced and V
REF
- 175mV is referenced and V
REF
Unit NOTE
mV
mV
mV 1,2
mV 1,2
V3,4
mV
mV
mV 1,2,8
mV 1,2,8
V3,4
(AC150) value is
IH.CA
(AC150) value is used
IL.CA
1,5
1,6
1,5
1,6
a)
a)
b)
b)
- 23 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
[ Table 3 ] Single Ended AC and DC input levels for DQ and DM
Symbol Parameter
(DC90)
V
IH.DQ
V
(DC90)
IL.DQ
V
(AC160)
IH.DQ
V
(AC160)
IL.DQ
V
(AC135)
IH.DQ
V
(AC135)
IL.DQ
V
REF
DQ
V
(DC100)
IH.DQ
V
(DC100)
IL.DQ
V
(AC175)
IH.DQ
V
(AC175)
IL.DQ
V
(AC150)
IH.DQ
V
(AC150)
IL.DQ
V
REF
DQ
NOTE :
1. For input only pins except RESET
2. See ’Overshoot/Undershoot Specification’ on page 18.
3. The AC peak noise on V
4. For reference : approx. V
5. V
(dc) is used as a simplified symbol for V
IH
(dc) is used as a simplified symbol for V
6. V
IL
7. V
(ac) is used as a simplified symbol for V
IH
when V
(ac) is used as a simplified symbol for V
8. V
IL
V
REF
DC input logic high
DC input logic low
AC input logic high
AC input logic low Note 2
AC input logic high
AC input logic low Note 2
Reference Voltage for DQ,
(DC)
DM inputs
DC input logic high
DC input logic low
AC input logic high
AC input logic low NOTE 2
AC input logic high
AC input logic low NOTE 2
Reference Voltage for DQ,
(DC)
DM inputs
, V
= V
REF
REFDQ
may not allow V
REF
/2 ± 15mV
DD
+ 150mV is referenced.
REF
- 150mV is referenced.
REF
IH.CA
IL.CA
IH.DQ
IL.DQ
(DC)
to deviate from V
(a) 1.35V : DC90, b) 1.5V : DC100)
(a) 1.35V : DC90, b) 1.5V : DC100)
(AC175), V
(AC175), V
DDR3-800/1066 DDR3-1333/1600
Min. Max. Min. Max.
V
+ 90 V
REF
V
SS
V
+ 160
REF
V
+ 135
REF
0.49*V
DD
V
+ 100 V
REF
V
SS
V
+ 175
REF
V
+ 150
REF
0.49*V
DD
(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
REF
(AC150) ; V
IH.DQ
(AC150) ; V
IL.DQ
1.35V
DD
V
- 90 V
REF
Note 2 - - mV 1,2
V
- 160
REF
Note 2
V
- 135
REF
0.51*V
DD
1.5V
DD
V
- 100 V
REF
NOTE 2 - - mV 1,2,7
V
- 175
REF
NOTE 2
V
- 150
REF
0.51*V
DD
(AC175) value is used when V
IH.DQ
(AC175) value is used when V
IL.DQ
Unit NOTE
V
+ 90 V
REF
SS
DD
V
- 90
REF
mV
mV
1,5
1,6
a)
a)
--mV1,2
V
+ 135
REF
Note 2
0.49*V
DD
V
+ 100 V
REF
SS
Note 2 mV 1,2
V
REF
0.51*V
V
REF
- 135
DD
DD
- 100
mV 1,2
V3,4
mV
mV
1,5
1,6
b)
b)
--mV1,2,8
V
+ 150
REF
NOTE 2
0.49*V
DD
+ 175mV is referenced, V
REF
- 175mV is referenced, V
REF
NOTE 2 mV 1,2,7
V
- 150
REF
0.51*V
DD
IH.DQ
(AC150) value is used when
IL.DQ
mV 1,2,8
V3,4
(AC150) value is used
- 24 -
Rev. 1.2
voltage
V
DD
V
SS
time
Registered DIMM
13.2 V
The dc-tolerance limits and ac-noise limits for the reference voltages V
V
REF
V
REF
thermore V
Tolerances
REF
(t) as a function of time. (V
(DC) is the linear average of V
(t) may temporarily deviate from V
REF
REF
stands for V
REF
REFCA
(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V
REF
datasheet DDR3L SDRAM
and V
(DC) by no more than ± 1% VDD.
REFDQ
likewise).
REFCA
and V
are illustrate in Figure 1. It shows a valid reference voltage
REFDQ
REF
. Fur-
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on V
" shall be understood as V
"V
REF
This clarifies, that dc-variations of V
which setup and hold is measured. System timing and voltage budgets need to account for V
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V
Timing and voltage effects due to ac-noise on V
(DC), as defined in Figure 1.
REF
affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
REF
(DC) deviations from the optimum position within the
REF
up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
REF
REF
.
ac-noise.
REF
- 25 -
Rev. 1.2
0.0
tDVAC
V
IH
.DIFF.MIN
half cycle
Differential Input Voltage (i.e. DQS-DQS, CK-CK)
time
tDVAC
VIH.DIFF.AC.MIN
V
IL
.DIFF.MAX
V
IL
.DIFF.AC.MAX
Registered DIMM
datasheet DDR3L SDRAM
13.3 AC and DC Logic Input Levels for Differential Signals
13.3.1 Differential Signals Definition
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
DDR3-800/1066/1333/1600
Symbol Parameter
min max min max
V
IHdiff
V
ILdiff
V
(AC)
IHdiff
V
(AC)
ILdiff
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK
then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK
nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"
differential input high +0.18 NOTE 3 +0.20 NOTE 3 V 1
differential input low NOTE 3 -0.18 NOTE 3 -0.20 V 1
differential input high ac
2 x (VIH(AC) - V
differential input low ac NOTE 3
use VIH/VIL(AC) of ADD/CMD and V
REFCA
; for DQS - DQS use VIH/VIL(AC) of DQs and V
REF
)
NOTE 3
2 x (VIL(AC) - V
, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-
2 x (VIH(AC) - V
)
REF
REFDQ
unit NOTE1.35V 1.5V
)
REF
NOTE 3
; if a reduced ac-high or ac-low level is used for a signal group,
NOTE 3 V 2
2 x (VIL(AC) - V
REF
)
V2
- 26 -
Rev. 1.2
Registered DIMM
[ Table 4 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.35V)
Slew Rate [V/ns]
> 4.0 TBD - TBD -
4.0 TBD - TBD -
3.0 TBD - TBD -
2.0 TBD - TBD -
1.8 TBD - TBD -
1.6 TBD - TBD -
1.4 TBD - TBD -
1.2 TBD - TBD -
1.0 TBD - TBD -
< 1.0 TBD - TBD -
[ Table 5 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.5V)
Slew Rate [V/ns]
> 4.0 75 - 175 -
4.0 57 - 170 -
3.0 50 - 167 -
2.0 38 - 163 -
1.8 34 - 162 -
1.6 29 - 161 -
1.4 22 - 159 -
1.2 13 - 155 -
1.0 0 - 150 -
< 1.0 0 - 150 -
datasheet DDR3L SDRAM
tDVAC [ps] @ |V
min max min max
tDVAC [ps] @ |V
min max min max
(AC)| = 320mV tDVAC [ps] @ |V
IH/Ldiff
(AC)| = 350mV tDVAC [ps] @ |V
IH/Ldiff
(AC)| = 270mV
IH/Ldiff
(AC)| = 300mV
IH/Ldiff
- 27 -
Rev. 1.2
VDD or V
DDQ
V
SEH
min
V
DD
/2 or V
DDQ
/2
V
SEL
max
V
SEH
VSS or V
SSQ
V
SEL
CK or DQS
time
Registered DIMM
datasheet DDR3L SDRAM
13.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.
CK and CK
have to approximately reach V
half-cycle.
DQS, DQS
have to reach V
SEH
min / V
ing a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V
signals, then these ac-levels apply also for the single-ended signals CK and CK
min / V
SEH
max (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle proceeding and follow-
SEL
max (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every
SEL
150(AC)/VIL150(AC) is used for ADD/CMD
IH
.
Figure 3. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to V
with respect to V
ended components of differential signals the requirement to reach V
/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
DD
SEL
, the single-ended components of differential signals have a requirement
REF
max, V
min has no bearing on timing, but adds a restriction on the common
SEH
mode characteristics of these signals.
[ Table 6 ] Single ended levels for CK, DQS, CK
Symbol Parameter
V
SEH
V
SEL
NOTE :
1. For CK, CK
2. V
IH
reduced level applies also here
3. These values are not defined, however the single-ended signals CK, CK
nals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"
use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.
(AC)/VIL(AC) for DQs is based on V
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended low-level for strobes NOTE 3
Single-ended low-level for CK, CK
; VIH(AC)/VIL(AC) for ADD/CMD is based on V
REFDQ
, DQS
DDR3-800/1066/1333/1600
Min Max
/2)+0.175
(V
DD
(VDD/2)+0.175
NOTE 3
; if a reduced ac-high or ac-low level is used for a signal group, then the
REFCA
, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-
Unit NOTE
NOTE 3 V 1, 2
NOTE 3 V 1, 2
/2)-0.175
(V
(V
DD
/2)-0.175
DD
V1, 2
V1, 2
- 28 -
Rev. 1.2
V
DD
CK, DQS
VDD/2
CK, DQS
V
SS
V
IX
V
IX
V
IX
VSEH VSEL
Registered DIMM
datasheet DDR3L SDRAM
13.3.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK
cross point of true and complement signal to the mid level between of V
and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual
and VSS.
DD
Figure 4. VIX Definition
[ Table 7 ] Cross point voltage for differential input signals (CK, DQS) : 1.35V
Symbol Parameter
V
V
NOTE :
1. The relationbetween Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix(Min) - VSEL ≥ 25mV
VSEH - ((VDD/2) + Vix(Max)) ≥ 25mV
Differential Input Cross Point Voltage relative to VDD/2 for CK,CK
IX
Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS
IX
[ Table 8 ] Cross point voltage for differential input signals (CK, DQS) : 1.5V
Symbol Parameter
V
V
NOTE :
1. Extended range for V
±250 mV, and the differential slew rate of CK-CK
Differential Input Cross Point Voltage relative to VDD/2 for CK,CK
IX
Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS
IX
is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V
IX
is larger than 3 V/ ns.
DDR3L-800/1066/1333/1600
Min Max
Unit NOTE
-150 150 mV 1
-150 150 mV
DDR3-800/1066/1333/1600
Min Max
Unit NOTE
-150 150 mV
-175 175 mV 1
-150 150 mV
/ V
SEL
of at least VDD/2
SEH
- 29 -
Rev. 1.2
V
IHdiffmin
0
V
ILdiffmax
delta TRdiff
delta TFdiff
Registered DIMM
datasheet DDR3L SDRAM
13.4 Slew Rate Definition for Single Ended Input Signals
See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.
13.5 Slew rate definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.
[ Table 9 ] Differential input slew rate definition
Description
Differential input slew rate for rising edge (CK-CK
Differential input slew rate for falling edge (CK-CK
NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
and DQS-DQS)
and DQS-DQS)
Measured
From To
V
ILdiffmax
V
IHdiffmin
V
IHdiffmin
V
ILdiffmax
Defined by
V
IHdiffmin
Delta TRdiff
V
IHdiffmin
Delta TFdiff
- V
- V
ILdiffmax
ILdiffmax
Figure 5. Differential input slew rate definition for DQS, DQS and CK, CK
14. AC & DC Output Measurement Levels
14.1 Single Ended AC and DC Output Levels
[ Table 10 ] Single Ended AC and DC output levels
Symbol Parameter DDR3-800/1066/1333/1600 Units NOTE
(DC) DC output high measurement level (for IV curve linearity) 0.8 x V
V
OH
V
(DC) DC output mid measurement level (for IV curve linearity) 0.5 x V
OM
V
(DC) DC output low measurement level (for IV curve linearity) 0.2 x V
OL
V
(AC) AC output high measurement level (for output SR) VTT + 0.1 x V
OH
V
(AC) AC output low measurement level (for output SR) VTT - 0.1 x V
OL
NOTE : 1. The swing of +/-0.1 x V
load of 25Ω to V
TT=VDDQ
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
DDQ
/2.
DDQ
DDQ
DDQ
DDQ
DDQ
14.2 Differential AC and DC Output Levels
[ Table 11 ] Differential AC and DC output levels
Symbol Parameter DDR3-800/1066/1333/1600 Units NOTE
(AC) AC differential output high measurement level (for output SR) +0.2 x V
V
OHdiff
(AC) AC differential output low measurement level (for output SR) -0.2 x V
V
OLdiff
NOTE : 1. The swing of +/-0.2xV
load of 25Ω to V
TT=VDDQ
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
DDQ
/2 at each of the differential outputs.
DDQ
DDQ
V
V
V
V1
V1
V1
V1
- 30 -
Rev. 1.2
V
OHdiff
(AC)
V
OLdiff
(AC)
delta TRdiffdelta TFdiff
VTT
Registered DIMM
datasheet DDR3L SDRAM
14.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in below.
[ Table 12 ] Single ended Output slew rate definition
Description
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 13 ] Single ended output slew rate
Parameter Symbol
Single ended output slew rate SRQse
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ
signals in the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the
remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
Operation
Vol tag e
1.35V 1.75
1.5V 2.5 5 2.5 5 2.5 5 2.5 5 V/ns
Measured
From To
(AC) VOH(AC)
V
OL
V
(AC) VOL(AC)
OH
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Min Max Min Max Min Max Min Max
1)
5
1.75
1)
5
1.75
Defined by
(AC)-VOL(AC)
V
OH
Delta TRse
(AC)-VOL(AC)
V
OH
Delta TFse
1)
5
1.75
1)
5
Units
V/ns
Figure 6. Single-ended output slew rate definition
- 31 -
Rev. 1.2
V
OHdiff
(AC)
V
OLdiff
(AC)
delta TRdiffdelta TFdiff
VTT
Registered DIMM
datasheet DDR3L SDRAM
14.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
(AC) for differential signals as shown in below.
diff
[ Table 14 ] Differential Output slew rate definition
Description
Differential output slew rate for rising edge
Differential output slew rate for falling edge
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 15 ] Differential Output slew rate
Parameter Symbol
Differential output slew rate SRQdiff
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
diff : Differential Signals
For Ron = RZQ/7 setting
Operation
Vol tag e
1.35V 3.5 12 3.5 12 3.5 12 3.5 12 V/ns
1.5V 5 10 5 10 5 10 5 10 V/ns
V
V
Measured
From To
(AC) V
OLdiff
(AC) V
OHdiff
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Min Max Min Max Min Max Min Max
OHdiff
OLdiff
(AC)
(AC)
V
V
OHdiff
OHdiff
Defined by
(AC)-V
OLdiff
Delta TRdiff
(AC)-V
OLdiff
Delta TFdiff
(AC)
(AC)
OLdiff
(AC) and V
Units
OH-
Figure 7. Differential output slew rate definition
- 32 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
15. IDD specification definition
Symbol Description
Operating One Bank Active-Precharge Current
IDD0
IDD1
IDD2N
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
IDD8
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8
and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
2)
Registers
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit
3)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit
3)
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode
2)
Registers
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers
Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
; Pattern Details: Refer to Component Datasheet for detail pattern
at HIGH
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and
RTT: Enabled in Mode Registers
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
4)
; Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and CK:
1)
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8
6)
1)
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8
between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and
the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:
Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
RESET Low Current
RESET : Low; External clock : off; CK and CK
: LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
1)
; AL: 0; CS: High between ACT and PRE;
1)
; AL: 0; CS: High between ACT, RD
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
1)
; AL: 0; CS: High between RD; Command, Address,
2)
; ODT Signal: stable
1)
; AL: 0; CS: High between WR; Command, Address,
2)
; ODT Signal: stable
1)
; AL: 0; CS: High between REF; Command,
2)
; ODT Signal: FLOATING
2)
; ODT Signal: FLOATING
1)
; AL: CL-1; CS: High
2)
; ODT
2)
;
2)
;
2)
;
- 33 -
Rev. 1.2
Registered DIMM
NOTE :
1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
7) IDD current measure method and detail patterns are described on DDR3 component datasheet
8) VDD and VDDQ are merged on module PCB.
9) DIMM IDD SPEC is measured with Qoff condition
(IDDQ values are not considered)
datasheet DDR3L SDRAM
- 34 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
16. IDD SPEC Table
M393B5773DH0 : 2GB(256Mx72) Module
DDR3-1066 DDR3-1333 DDR3-1600
Symbol
1.35V 1.5V 1.35V 1.5V 1.35V 1.5V
IDD0 870 955 935 1030 1030 1125 mA
IDD1 960 1045 1027 1120 1120 1215 mA
IDD2P0(slow exit) 600 648 630 688 680 738 mA
IDD2P1(fast exit) 627 675 657 715 725 765 mA
IDD2N 705 763 735 830 793 870 mA
IDD2Q 685 743 725 810 773 850 mA
IDD3P 645 693 675 733 743 810 mA
IDD3N 785 870 825 955 900 995 mA
IDD4R 1095 1225 1250 1345 1390 1530 mA
IDD4W 1150 1280 1305 1400 1480 1585 mA
IDD5B 1550 1590 1635 1675 1665 1760 mA
IDD6 120 138 120 138 120 138 mA
IDD7 1500 1585 1745 1885 1830 1980 mA
IDD8 120 138 120 138 120 138 mA
Unit NOTE7-7-7 9-9-9 11-11-11
M393B5273DH0 : 4GB(512Mx72) Module
DDR3-1066 DDR3-1333 DDR3-1600
Symbol
1.35V 1.5V 1.35V 1.5V 1.35V 1.5V
IDD0 1005 1108 1070 1210 1183 1305 mA 1
IDD1 1095 1198 1162 1300 1273 1395 mA 1
IDD2P0(slow exit) 690 756 720 796 770 846 mA
IDD2P1(fast exit) 744 810 774 850 860 900 mA
IDD2N 840 916 870 1010 946 1050 mA
IDD2Q 820 896 860 990 926 1030 mA
IDD3P 780 846 810 886 896 990 mA
IDD3N 1010 1140 1050 1270 1170 1310 mA
IDD4R 1230 1378 1385 1525 1543 1710 mA 1
IDD4W 1285 1433 1440 1580 1633 1765 mA 1
IDD5B 1685 1743 1770 1855 1818 1940 mA 1
IDD6 210 246 210 246 210 246 mA
IDD7 1635 1738 1880 2065 1983 2160 mA 1
IDD8 210 246 210 246 210 246 mA
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
Unit NOTE7-7-7 9-9-9 11-11-11
- 35 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
M393B5270DH0 : 4GB(512Mx72) Module
DDR3-1066 DDR3-1333 DDR3-1600
Symbol
1.35V 1.5V 1.35V 1.5V 1.35V 1.5V
IDD0 1140 1270 1250 1390 1390 1530 mA
IDD1 1320 1450 1432 1570 1570 1710 mA
IDD2P0(slow exit) 690 756 720 796 770 846 mA
IDD2P1(fast exit) 744 810 774 850 860 900 mA
IDD2N 840 916 870 1010 946 1050 mA
IDD2Q 820 896 860 990 926 1030 mA
IDD3P 780 846 810 886 896 990 mA
IDD3N 1010 1140 1050 1270 1170 1310 mA
IDD4R 1500 1540 1700 1750 1840 1980 mA
IDD4W 1600 1730 1800 1940 2020 2260 mA
IDD5B 2540 2580 2670 2710 2700 2840 mA
IDD6 210 246 210 246 210 246 mA
IDD7 2310 2530 2780 2920 2910 3060 mA
IDD8 210 246 210 246 210 246 mA
Unit NOTE7-7-7 9-9-9 11-11-11
M393B1K70DH0 : 8GB(1Gx72) Module
DDR3-1066 DDR3-1333 DDR3-1600
Symbol
1.35V 1.5V 1.35V 1.5V 1.35V 1.5V
IDD0 1410 1576 1520 1750 1696 1890 mA 1
IDD1 1590 1756 1702 1930 1876 2070 mA 1
IDD2P0(slow exit) 870 972 900 1012 950 1062 mA
IDD2P1(fast exit) 978 1080 1008 1120 1130 1170 mA
IDD2N 1110 1222 1140 1370 1252 1410 mA
IDD2Q 1090 1202 1130 1350 1232 1390 mA
IDD3P 1050 1152 1080 1192 1202 1350 mA
IDD3N 1460 1680 1500 1900 1710 1940 mA
IDD4R 1770 1846 1970 2110 2146 2340 mA 1
IDD4W 1870 2036 2070 2300 2326 2620 mA 1
IDD5B 2810 2886 2940 3070 3006 3200 mA 1
IDD6 390 462 390 462 390 462 mA
IDD7 2580 2836 3050 3280 3216 3420 mA 1
IDD8 390 462 390 462 390 462 mA
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
Unit NOTE7-7-7 9-9-9 11-11-11
- 36 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
M393B1K73DH0 : 8GB(1Gx72) Module
DDR3-1066 DDR3-1333
Symbol
1.35V 1.5V 1.35V 1.5V
IDD0 1275 1414 1340 1570 mA 1
IDD1 1365 1504 1432 1660 mA 1
IDD2P0(slow exit) 870 972 900 1012 mA
IDD2P1(fast exit) 978 1080 1008 1120 mA
IDD2N 1110 1222 1140 1370 mA
IDD2Q 1090 1202 1130 1350 mA
IDD3P 1050 1152 1080 1192 mA
IDD3N 1460 1680 1500 1900 mA
IDD4R 1500 1684 1655 1885 mA 1
IDD4W 1555 1739 1710 1940 mA 1
IDD5B 1955 2049 2040 2215 mA 1
IDD6 390 462 390 462 mA
IDD7 1905 2044 2150 2425 mA 1
IDD8 390 462 390 462 mA
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
Unit NOTE7-7-7 9-9-9
M393B2K70DM0 : 16GB(2Gx72) Module
DDR3-1066 DDR3-1333
Symbol
1.35V 1.5V 1.35V 1.5V
IDD0 2430 2700 2556 3006 mA 1
IDD1 2610 2880 2739.6 3186 mA 1
IDD2P0(slow exit) 1638 1836 1692 1908 mA
IDD2P1(fast exit) 1854 2052 1908 2124 mA
IDD2N 2106 2322 2160 2610 mA
IDD2Q 2070 2286 2142 2574 mA
IDD3P 1998 2196 2052 2268 mA
IDD3N 2808 3240 2880 3672 mA
IDD4R 2790 2970 3006 3366 mA 1
IDD4W 2898 3168 3114 3564 mA 1
IDD5B 3798 3978 3960 4302 mA 1
IDD6 774 918 774 918 mA
IDD7 3600 3960 4086 4536 mA 1
IDD8 774 918 774 918 mA
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
Unit NOTE7-7-7 9-9-9
- 37 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
17. Input/Output Capacitance
[ Table 16 ] Input/Output Capacitance
Parameter Symbol
Input/output capacitance
(DQ, DM, DQS, DQS
Input capacitance
(CK and CK)
Input capacitance delta
(CK and CK)
Input capacitance
(All other input-only pins)
Input/Output capacitance delta
(DQS and DQS)
Input capacitance delta
(All control input-only pins)
Input capacitance delta
(all ADD and CMD input-only pins)
Input/output capacitance delta
(DQ, DM, DQS, DQS
Input/output capacitance of ZQ pin CZQ - 3 - 3 - . - 3 pF 2,3,12
Input/output capacitance
(DQ, DM, DQS, DQS
Input capacitance
(CK and CK)
Input capacitance delta
(CK and CK)
Input capacitance
(All other input-only pins)
Input capacitance delta
(DQS and DQS)
Input capacitance delta
(All control input-only pins)
Input capacitance delta
(all ADD and CMD input-only pins)
Input/output capacitance delta
(DQ, DM, DQS, DQS
Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 - 3 pF 2,3,12
NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance.
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with
, V
DD
DDQ
, VSS, V
V
die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
, TDQS, TDQS)
, TDQS, TDQS)
, TDQS, TDQS)
, TDQS, TDQS)
applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=V
SSQ
CIO 1.5 2.5 1.5 2.5 1.5 2.3 1.2 2.3 pF 1,2,3
CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pF 2,3
CDCK 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4
CI 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.3 pF 2,3,6
CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 pF 2,3,5
CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 pF 2,3,7,8
CDI_ADD_CMD -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 pF 2,3,9,10
CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11
CIO 1.5 3.0 1.5 2.7 1.5 2.5 1.4 2.3 pF 1,2,3
CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pF 2,3
CDCK 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4
CI 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 pF 2,3,6
CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 pF 2,3,5
CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 pF 2,3,7,8
CDI_ADD_CMD -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 pF 2,3,9,10
CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Min Max Min Max Min Max Min Max
1.35V
1.5V
=1.5V or 1.35V, V
DDQ
Units NOTE
/2 and on-
BIAS=VDD
- 38 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
18. Electrical Characteristics and AC timing
[0 °C<T
18.1 Refresh Parameters by Device Density
All Bank Refresh to active/refresh cmd time tRFC 110 160 260 350 ns
Average periodic refresh interval tREFI
NOTE :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in
this material.
18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
≤95 °C, V
CASE
Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units NOTE
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Parameter min min min min
CL 6 7911tCK
tRCD 15 13.13 13.5 13.75 ns
tRP 15 13.13 13.5 13.75 ns
tRAS 37.5 37.5 36 35 ns
tRC 52.5 50.63 49.5 48.75 ns
tRRD 10 7.5 6.0 6.0 ns
tFAW 40 37.5 30 30 ns
= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V); VDD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)]
DDQ
0 °C ≤ T
85 °C < T
CASE
CASE
≤ 85°C
≤ 95°C
7.8 7.8 7.8 7.8 μs
3.9 3.9 3.9 3.9 μs 1
Units NOTEBin (CL - tRCD - tRP) 6-6-6 7-7-7 9-9-9 11 -11-11
18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
[ Table 17 ] DDR3-800 Speed Bins
Speed DDR3-800
Units NOTECL-nRCD-nRP 6 - 6 - 6
Parameter Symbol min max
Internal read command to first data tAA 15 20 ns
ACT to internal read or write delay time tRCD 15 - ns
PRE command period tRP 15 - ns
ACT to ACT or REF command period tRC 52.5 - ns
ACT to PRE command period tRAS 37.5 9*tREFI ns
CL = 6 / CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3
Supported CL Settings 6 nCK
Supported CWL Settings 5 nCK
- 39 -
Rev. 1.2
Registered DIMM
[ Table 18 ] DDR3-1066 Speed Bins
Speed DDR3-1066
Parameter Symbol min max
Internal read command to first data tAA 13.125 20 ns
ACT to internal read or write delay time tRCD 13.125 - ns
PRE command period tRP 13.125 - ns
ACT to ACT or REF command period tRC 50.625 - ns
ACT to PRE command period tRAS 37.5 9*tREFI ns
CL = 6
CL = 7
CL = 8
Supported CL Settings 6,7,8 nCK
Supported CWL Settings 5,6 nCK
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,5
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,8
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3
datasheet DDR3L SDRAM
Units NOTECL-nRCD-nRP 7 - 7 - 7
[ Table 19 ] DDR3-1333 Speed Bins
Speed DDR3-1333
Units NOTECL-nRCD-nRP 9 -9 - 9
Parameter Symbol min max
Internal read command to first data tAA 13.5 (13.125)
ACT to internal read or write delay time tRCD 13.5 (13.125)
PRE command period tRP 13.5 (13.125)
ACT to ACT or REF command period tRC 49.5 (49.125)
ACT to PRE command period tRAS 36 9*tREFI ns
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,6
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
Supported CL Settings 6,7,8,9 nCK
Supported CWL Settings 5,6,7 nCK
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,6
CWL = 7 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,6
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,6
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,8
CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) Reserved ns 1,2,3
8
8
8
8
20 ns
- ns
- ns
- ns
- 40 -
Rev. 1.2
Registered DIMM
[ Table 20 ] DDR3-1600 Speed Bins
Speed DDR3-1600
Parameter Symbol min max
Intermal read command to first data tAA
ACT to internal read or write delay time tRCD
PRE command period tRP
ACT to ACT or REF command period tRC
ACT to PRE command period tRAS 35 9*tREFI ns
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
Supported CL Settings 6,7,8,9,10,11 nCK
Supported CWL Settings 5,6,7,8 nCK
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,7
CWL = 7, 8 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,7
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,7
CWL = 8 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,7
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,7
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,7
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,7
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5,6,7 tCK(AVG) Reserved ns 4
CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3,8
datasheet DDR3L SDRAM
Units NOTECL-nRCD-nRP 11-11-11
13.75
(13.125)
13.75
(13.125)
13.75
(13.125)
48.75
(48.125)
8
8
8
8
20 ns
- ns
- ns
- ns
- 41 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
18.3.1 Speed Bin Table Notes
Absolute Specification [T
NOTE :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-
anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],
rounding up to the next "SupportedCL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or
1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
8. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,
DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte
20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte
18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin
+ tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and 48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).
OPER
; V
= VDD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)];
DDQ
- 42 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
19. Timing Parameters by Speed Grade
[ Table 21 ] Timing Parameters by Speed Bin (Cont.)
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period tCK(avg) See Speed Bins Table ps
Clock Period tCK(abs)
Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Clock Period Jitter tJIT(per) -100 100 -90 90 -80 80 -70 70 ps
Clock Period Jitter during DLL locking period tJIT(per, lck) -90 90 -80 80 -70 70 -60 60 ps
Cycle to Cycle Period Jitter tJIT(cc) 200 180 160 140 ps
Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 180 160 140 120 ps
Cumulative error across 2 cycles tERR(2per) - 147 147 - 132 132 - 118 118 -103 103 ps
Cumulative error across 3 cycles tERR(3per) - 175 175 - 157 157 - 140 140 -122 122 ps
Cumulative error across 4 cycles tERR(4per) - 194 194 - 175 175 - 155 155 -136 136 ps
Cumulative error across 5 cycles tERR(5per) - 209 209 - 188 188 - 168 168 -147 147 ps
Cumulative error across 6 cycles tERR(6per) - 222 222 - 200 200 - 177 177 -155 155 ps
Cumulative error across 7 cycles tERR(7per) - 232 232 - 209 209 - 186 186 -163 163 ps
Cumulative error across 8 cycles tERR(8per) - 241 241 - 217 217 - 193 193 -169 169 ps
Cumulative error across 9 cycles tERR(9per) - 249 249 - 224 224 - 200 200 -175 175 ps
Cumulative error across 10 cycles tERR(10per) - 257 257 - 231 231 - 205 205 -180 180 ps
Cumulative error across 11 cycles tERR(11per) - 263 263 - 237 237 - 210 210 -184 184 ps
Cumulative error across 12 cycles tERR(12per) - 269 269 - 242 242 - 215 215 -188 188 ps
Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper)
Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - 0.43 - 0.43 - tCK(avg) 25
Absolute clock Low pulse width tCL(abs) 0.43 - 0.43 - 0.4 3 - 0.43 - tCK(avg) 26
Data Timing
DQS,DQS to DQ skew, per group, per access tDQSQ - 200 - 150 - 125 - 100 ps 13
DQ output hold time from DQS, DQS tQH 0.38 - 0.38 - 0.38 - 0.38 - tCK(avg) 13, g
DQ low-impedance time from CK, CK tLZ(DQ) -800 400 -60 0 300 -500 250 -450 225 ps 13,14, f
DQ high-impedance time from CK, CK tHZ(DQ) - 400 - 300 - 250 - 225 ps 13,14, f
Data setup time to DQS, DQS referenced to
(AC)VIL(AC) levels
V
IH
Data hold time from DQS, DQS referenced to
VIH(DC)VIL(DC) levels
Data setup time to DQS, DQS referenced to
VIH(AC)VIL(AC) levels
DQ and DM Input pulse width for each input tDIPW 600
tCK(DLL_OF
F)
tDS(base)
AC160
tDS(base)
AC175
tDH(base)
DC90
tDH(base)
DC100
tDS(base)
AC135
tDS(base)
AC150
8 - 8 - 8 - 8 - ns 6
tCK(avg)min +
tJIT(per)min
90
75
160
150
140
125
tCK(avg)max +
tJIT(per)max
-
-
-
-
-
-
-
tCK(avg)min +
tJIT(per)min
tCK(avg)max +
tJIT(per)max
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
40
25
110
100
90
75
490
-
-
-
-
-
-
-
tCK(avg)min +
tJIT(per)min
1.35V
----psd, 17
1.5V
- - - - ps d, 17
1.35V
75 - 55 - ps d, 17
1.5V
65 - 45 - ps d, 17
1.35V
45 - 25 - ps
1.5V
30 - 10 - ps
400
tCK(avg)max +
tJIT(per)max
-
tCK(avg)min +
tJIT(per)min
360
tCK(avg)max +
tJIT(per)max
-
Units NOTE
ps
ps 24
ps 28
- 43 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
[ Table 21] Timing Parameters by Speed Bin (Cont.)
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX
Data Strobe Timing
DQS, DQS differential READ Preamble tRPRE 0.9 Note 19 0.9 Note 19 0.9 Note 19 0.9 Note 19 tCK 13, 19, g
DQS, DQS differential READ Postamble tRPST 0.3 Note 11 0.3 Note 11 0.3 Note 11 0.3 Note 11 tCK 11, 13, b
DQS, DQS differential output high time tQSH 0.38 - 0.38 - 0.4 - 0.4 - tCK(avg) 13, g
DQS, DQS differential output low time tQSL 0.38 - 0.38 - 0.4 - 0.4 - tCK(avg) 13, g
DQS, DQS differential WRITE Preamble tWPRE 0.9 - 0.9 - 0.9 - 0.9 - tCK
DQS, DQS differential WRITE Postamble tWPST 0.3 - 0.3 - 0.3 - 0.3 - tCK
DQS, DQS rising edge output access time from rising
CK, CK
DQS, DQS low-impedance time (Referenced from RL-
1)
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
DQS, DQS differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 29, 31
DQS, DQS differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0. 55 tCK 30, 31
DQS, DQS rising edge to CK, CK rising edge tDQSS -0.25 0.25 -0.25 0.25 -0.25 0.25 -0.27 0.27 tCK(avg) c
DQS,DQS falling edge setup time to CK, CK rising edge tDSS 0.2 - 0.2 - 0.2 - 0.1 8 - tCK(avg) c, 32
DQS,DQS falling edge hold time to CK, CK rising edge tDSH 0.2 - 0.2 - 0.2 - 0.18 - tCK(avg) c, 32
Command and Address Timing
DLL locking time tDLLK 512 - 512 - 512 - 512 - nCK
internal READ Command to PRECHARGE Command
delay
Delay from start of internal write transaction to internal
read command
WRITE recovery time tWR 15 - 15 - 15 - 15 - ns e
Mode Register Set command cycle time tMRD 4 - 4 - 4 - 4 - nCK
Mode Register Set command updat e delay tMOD
CAS to CAS command delay tCCD 4 - 4 - 4 - 4 - nCK
Auto precharge write recovery + precharge time tDAL(min) WR + roundup (tRP / tCK(AVG)) nCK
Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - 1 - nCK 22
ACTIVE to PRECHARGE command period tRAS See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” ns e
ACTIVE to ACTIVE command period for 1KB page size tRRD
ACTIVE to ACTIVE command period for 2KB page size tRRD
Four activate window for 1KB page size tFAW 40 - 37.5 - 30 - 30 - ns e
Four activate window for 2KB page size tFAW 50 - 50 - 45 - 40 - ns e
Command and Address setup time to CK, CK referenced to V
Command and Address hold time from CK, CK referenced to VIH(DC) / VIL(DC) levels
Command and Address setup time to CK, CK referenced to V
Control & Address Input pulse width for each input tIPW 900
Calibration Timing
Power-up and RESET calibration time tZQinitI 512 - 512 - 512 - 512 - nCK
Normal operation Full calibration time tZQoper 256 - 256 - 256 - 256 - nCK
Normal operation short calibration time tZQCS 64 - 64 - 64 - 64 - nCK 23
(AC) / VIL(AC) levels
IH
(AC) / VIL(AC) levels
IH
tDQSCK -400 400 -300 300 -255 255 -225 225 ps 13,f
tLZ(DQS) -800 400 -600 300 -500 250 -450 225 ps 13,14,f
tHZ(DQS) - 400 - 300 - 250 - 225 ps 12,13,14
tRTP
tWTR
tIS(base)
AC160
tIS(base)
AC175
tIH(base)
DC90
tIH(base)
DC100
tIS(base)
AC135
tIS(base)
AC150
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(12nCK,15ns)
max
(4nCK,10ns)
max
(4nCK,10ns)
215
200
285
275 200 140 120 - ps b,16
365
350
-
-
-
-
-
-
-
-
-
-
-
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(12nCK,15ns)
max
(4nCK,7.5ns)
max
(4nCK,10ns)
140
125
210
290
275
780
-
-
-
-
-
-
-
-
-
-
-
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(12nCK,15ns)
max
(4nCK,6ns)
max
(4nCK,7.5ns)
1.35V
80 - 60 - ps b,16
1.5V
65 - 45 - ps b,16
1.35V
150 - 130 - ps b,16
1.5V
1.35V
205 - 185 - ps b,16,27
1.5V
190 - 170 - ps b,16,27
620 - 560 - ps 28
-
-
-
-
-
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(12nCK,15ns)
max
(4nCK,6ns)
max
(4nCK,7.5ns)
Units NOTE
- e
- e,18
-
- e
- e
- 44 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
[ Table 21 ] Timing Parameters by Speed Bin
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX
Reset Timing
tXS
tXP
max(5nCK,
tRFC +
10ns)
max(5nCK,t
RFC +
10ns)
tCKE(min) +
1tCK
max(5nCK,
10ns)
max(5nCK,
10ns)
max
(3nCK,
7.5ns)
max
(10nCK,
24ns)
max
(3nCK,
7.5ns)
WL + 4
+(tWR/
tCK(avg))
WL + 4
+WR +1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
Exit Reset from CKE HIGH to a valid command tXPR
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked
DLL
Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - tDLLK(min) - tDLLK(min) - tDLLK(min) - nCK
Minimum CKE low width for Self refresh entry to exit
timing
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL
CKE minimum pulse width tCKE
Command pass disable delay tCPDED 1 - 1 - 1 - 1 - nCK
Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK 15
Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - 1 - 1 - nCK 20
Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - 1 - 1 - nCK 20
Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 - RL + 4 +1 - RL + 4 +1 - RL + 4 +1 -
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WR command to Power Down entry
(BC4MRS)
Timing of WRA command to Power Down entry
(BC4MRS)
Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 1 - 1 - 20,21
Timing of MRS command to Power Down entry tMRSPDEN tMOD(min) - tMOD(min) - tMOD(min) - tMOD(min) -
ODT Timing
ODT high time without write command or with write
command and BC4
ODT high time with Write command and BL8 ODTH8 6 - 6 - 6 - 6 - nCK
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen)
RTT turn-on tAON -400 400 -300 300 -250 250 -225 225 ps 7,f
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tC K(avg) f
Write Leveling Timing
First DQS/DQS rising edge after write leveling mode
is programmed
DQS/DQS delay after write leveling mode is programmed
Write leveling setup time from rising CK, CK crossing
to rising DQS, DQS
Write leveling hold time from rising DQS, DQS crossing to rising CK, CK
Write leveling output delay tWLO 0 9 0 9 0 9 0 7.5 ns
Write leveling output error tWLOE 0 2 0 2 0 2 0 2 ns
crossing
crossing
tCKESR
tCKSRE
tCKSRX
tXPDLL
tWRPDEN
tWRAPDEN
tWRPDEN
tWRAPDEN
ODTH4 4 - 4 - 4 - 4 - nCK
tAONPD 2 8.5 2 8.5 2 8.5 2 8.5 ns
tAOFPD 2 8.5 2 8.5 2 8.5 2 8.5 ns
tAOF 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) 8,f
tWLMRD 40 - 40 - 40 - 40 - tCK 3
tWLDQSEN 25 - 25 - 25 - 25 - tCK 3
tWLH 325 - 245 - 195 - 165 - ps
tWLH 325 - 245 - 195 - 165 - ps
-
-
-
-
-
-
-
-
-
-
-
-
max(5nCK,
tRFC +
10ns)
max(5nCK,t
RFC +
10ns)
tCKE(min) +
1tCK
max(5nCK,
10ns)
max(5nCK,
10ns)
max
(3nCK,
7.5ns)
max
(10nCK,
24ns)
max
(3nCK,
5.625ns)
WL + 4
+(tWR/
tCK(avg))
WL + 4
+WR +1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
-
-
-
-
-
-
-
-
-
-
-
-
max(5nCK,
tRFC +
10ns)
max(5nCK,t
RFC +
10ns)
tCKE(min) +
1tCK
max(5nCK,
10ns)
max(5nCK,
10ns)
max
(3nCK,6ns)
max
(10nCK,
24ns)
max
(3nCK,
5.625ns)
WL + 4
+(tWR/
tCK(avg))
WL + 4
+WR +1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
-
-
-
-
-
-
-
-
-
-
-
-
max(5nCK,
tRFC +
10ns)
max(5nCK,t
RFC + 10ns)
tCKE(min) +
1tCK
max(5nCK,
10ns)
max(5nCK,
10ns)
max
(3nCK,6ns)
max
(10nCK,
24ns)
max
(3nCK,5ns)
WL + 4
+(tWR/
tCK(avg))
WL + 4 +WR
+1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
Units NOTE
-
-
-
-
-
-
- 2
-
- nCK 9
- nCK 10
- nCK 9
- nCK 10
- 45 -
Rev. 1.2
Registered DIMM
datasheet DDR3L SDRAM
19.1 Jitter Notes
Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the
input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,
another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b These parameters are measured from a command/address signal (CKE, CS
edge to its respective clock signal (CK/CK
tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,
these parameters should be met whether clock jitter is present or not.
Specific Note c These parameters are measured from a data strobe signal (DQS, DQS
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal
(DQS, DQS
Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},
which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the
device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.
) crossing.
) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition
) crossing to its respective clock signal (CK, CK) crossing.
Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input
clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +
193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to
tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the
min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12,
and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input
clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has
tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +
tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =
tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/
max usage!)
- 46 -
Rev. 1.2
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
0.5
(1.5 x 1) + (0.15 x 15)
= 0.133
~
~
128ms
Registered DIMM
datasheet DDR3L SDRAM
19.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"
8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing
Diagram Datasheet.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by TBD
13. Value is only valid for RON34
14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.
15. tREFI depends on T
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
V
(DC) = V
REF
See "Address/Command Setup, Hold and Derating" on component datasheet.
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
V
(DC)= V
REF
See "Data Setup, Hold and Slew Rate Derating" on component datasheet.
18. Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram
Datasheet"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-
ject to in the application, is illustrated. The interval could be defined by the following formula:
OPER
DQ(DC). For input only pins except RESET, V
REF
DQ(DC). For input only pins except RESET, V
REF
REF
REF
(DC)=V
(DC)=V
REF
REF
CA(DC).
CA(DC).
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as:
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-
nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of V
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
(DC) and the consecutive crossing of V
REF
, as measured from one falling edge to the next consecutive rising edge.
- 47 -
REF
(DC)
Rev. 1.2
1.00
0.2 ± 0.15
2.50 ± 0.20
Detail B
5.00
Detail A
1.50±0.10
0.80 ± 0.05
3.80
Units : Millimeters
9.50
128.95
(2X)3.00
17.30
AB
47.00
71.00
Register
1.27 ± 0.10
1.0 max
2.50
9.76 18.92 32.40 18.93 9.7410.9
C
Detail C
10.9
R
0.
50
0.4
2.30
133.35 ± 0.15
2.50
30.00 ± 0.15
Max 4.0
54.675
The used device is 256M x8 DDR3L SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0846D-HY**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
Register
Address, Command and Control lines
NOTE : DRAMs indicated with dotted outline are located on the backside of the module.
2x 2.10 ± 0.15
Registered DIMM
datasheet DDR3L SDRAM
20. Physical Dimensions
20.1 256Mbx8 based 256Mx72 Module (1 Rank) - M393B5773DH0
20.1.1 x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs
- 48 -
Rev. 1.2
133.35 ± 0.15
AB
47.00 71.00
Units : Millimeters
9.50
128.95
(2X)3.00
17.30
Register
1.27 ± 0.10
1.0 max
1.00
0.2 ± 0.15
2.50 ± 0.20
Detail B
5.00
Detail A
1.50±0.10
0.80 ± 0.05
3.80
2.50
9.76 18.92 32.40 18.93 9.74
10.9
C
Detail C
10.9
R 0.
5
0
0.4
2.30
2.50
30.00 ± 0.15
Max 4.0
54.675
The used device is 256M x8 DDR3L SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0846D-HY**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
Register
Address, Command and Control lines
2x 2.10 ± 0.15
Registered DIMM
datasheet DDR3L SDRAM
20.2 256Mbx8 based 512Mx72 Module (2 Ranks) - M393B5273DH0
20.2.1 x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs
- 49 -
Rev. 1.2
133.35 ± 0.15
AB
47.00 71.00
Units : Millimeters
9.50
128.95
(2X)3.00
17.30
Register
1.27 ± 0.10
1.0 max
1.00
0.2 ± 0.15
2.50 ± 0.20
Detail B
5.00
Detail A
1.50±0.10
0.80 ± 0.05
3.80
2.50
9.76 18.92 32.40 18.93 9.74
10.9
C
Detail C
10.9
R 0.
5
0
0.4
2.30
2.50
30.00 ± 0.15
Max 4.0
54.675
The used device is 512M x4 DDR3L SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0446D-HY**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
Register
Address, Command and Control lines
2x 2.10 ± 0.15
Registered DIMM
datasheet DDR3L SDRAM
20.3 512Mbx4 based 512Mx72 Module (1 Rank) - M393B5270DH0
20.3.1 x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs
- 50 -
Rev. 1.2
Units : Millimeters
9.50
128.95
(2X)3.00
1.27 ± 0.10
1.0 max
17.30
1.00
0.2 ± 0.15
2.50 ± 0.20
Detail B
5.00
Detail A
1.50±0.10
0.80 ± 0.05
3.80
2.50
Register
9.76 18.92 32.40 18.93 9.74
10.9
C
Detail C
10.9
R
0.
5
0
0.4
AB
2.50
2.30
133.35 ± 0.15
30.00 ± 0.15
Max 4.0
71.00
54.675
47.00
The used device is 512M x4 DDR3L SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0446D-HY**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
Address, Command and Control lines
VTTVTT
VTT
VTTVTT
VTTVTT
Register
2x 2.10 ± 0.15
VTT
Registered DIMM
datasheet DDR3L SDRAM
20.4 512Mbx4 based 1Gx72 Module (2 Ranks) - M393B1K70DH0
20.4.1 x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs
- 51 -
Rev. 1.2
Units : Millimeters
9.50
128.95
(2X)3.00
1.27 ± 0.10
1.0 max
17.30
1.00
0.2 ± 0.15
2.50 ± 0.20
Detail B
5.00
Detail A
1.50±0.10
0.80 ± 0.05
3.80
2.50
9.76 18.92 32.40 18.93 9.74
10.9
C
Detail C
10.9
R
0.
5
0
0.4
AB
47.00
71.00
Register
2.30
133.35 ± 0.15
2.50
30.00 ± 0.15
Max 4.0
54.675
The used device is 256M x8 DDR3L SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0846D-HY**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
Address, Command and Control lines
VTTVTT
VTTVTT
VTTVTT
VTTVTT
Register
2x 2.10 ± 0.15
Registered DIMM
datasheet DDR3L SDRAM
20.5 256Mbx8 based 1Gx72 Module (4 Ranks) - M393B1K73DH0
20.5.1 x72 DIMM, populated as four physical ranks of x8 DDR3 SDRAMs
- 52 -
Rev. 1.2
Units : Millimeters
9.50
128.95
(2X)3.00
1.27 ± 0.10
1.0 max
17.30
1.00
0.2 ± 0.15
2.50 ± 0.20
Detail B
5.00
Detail A
1.50±0.10
0.80 ± 0.05
3.80
2.50
9.76 18.92 32.40 18.93 9.74
10.9
C
Detail C
10.9
R
0.
5
0
0.4
AB
47.00
71.00
Register
2.30
133.35 ± 0.15
2.50
30.00 ± 0.15
Max 4.0
54.675
The used device is 1G x4(DDP) DDR3L SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B4G0446D-MY**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
Address, Command and Control lines
VTTVTT
VTTVTT
VTTVTT
VTTVTT
Register
2x 2.10 ± 0.15
Registered DIMM
datasheet DDR3L SDRAM
20.6 1Gbx4(DDP) based 2Gx72 Module (4 Ranks) - M393B2K70DM0
20.6.1 x72 DIMM, populated as four physical ranks of x4 DDR3 SDRAMs
- 53 -
Rev. 1.2
133.15 ± 0.2
4.65± 0.12
2
130.45 ± 0.15
127 ± 0.12
23.6 ± 0.15
25.6 ± 0.15
7.45
119.29
80.78
Green Line : TIM Attach Line
0.4
0.6 ± 0.15
0.65 ± 0.2
R
0
.
2
R0.
1
1
25.6 ± 0.15
0.15
1.3
2
2.8 ± 0.2
2.2 ± 0.1
1. FRONT PART
Reg. pedestal line
Outside
Inside
Green Line : TIM Attach Line
Outside
Inside
2. BACK PART
29.77
31.411. 9
9.26
128.35
0.6 ± 0.1
Registered DIMM
20.6.2 Heat Spreader Design Guide
datasheet DDR3L SDRAM
- 54 -
Rev. 1.2
19 ± 0.12
39.3 ± 0.2
7.3 ± 0.1
19 ± 0.12
Clip open size
2.6~3.8
D
text mark ’D’
punch press_stamp
7.3 ± 0.1
44.4
39.3 ± 0.2
29.77
R1.5
0.1 ~ 0.3
Upper Bending
Tilting Gap
0.5
3. CLIP PART
6.3
± 0.12
3.77
133.15
1.27
4. DDR3 RDIMM ASS’Y View
Reference thickness total (Maximum) : 7.55 (With Clip thickness)
Registered DIMM
datasheet DDR3L SDRAM
- 55 -
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