Samsung M393A2K40BB2-CTD User Manual

Rev. 1.6, Apr. 2016

M393A1K43BB0
M393A1K43BB1
M393A2K40BB0
M393A2K40BB1
M393A2K40BB2
M393A4K40BB0
M393A4K40BB1
M393A4K40BB2

288pin Registered DIMM

based on 8Gb B-die

78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other­wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

(c) 2016 Samsung Electronics Co., Ltd. All rights reserved.

- 1 -

Rev. 1.6

Registered DIMM

datasheet DDR4 SDRAM

Revision History

Revision No. History Draft Date Remark Editor

1.0 - First SPEC Release Nov. 2014 - J.Y.Lee

1.1

1.2

1.3

1.4

1.5

1.6

- Change of Part Number (Speed bin "RC")

- Addition of VDDSPD tolerance on page 8

- Addition of IDD value (M393A2K40BB0-CPB, M393A2K40BB1-CRC,
M393A4K40BB1-CRC) on page 25

- Change of IDD

- Addition of Module line up (8GB)

- Addition of DDR4-2666

Jan. 2015 - J.Y.Lee

Mar. 2015 - J.Y.Lee

Apr. 2015 - J.Y.Lee

16th Dec. 2015 - J.Y.Lee

3rd Feb. 2016 - J.Y.Lee

7th Apr. 2016 - J.Y.Lee

- 2 -

Rev. 1.6

Registered DIMM

datasheet DDR4 SDRAM

Table Of Contents

288pin Registered DIMM based on 8Gb B-die

1. DDR4 Registered DIMM Ordering Information ............................................................................................................. 4

2. Key Features................................................................................................................................................................. 4

3. Address Configuration .................................................................................................................................................. 4

4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................5

5. Pin Description ............................................................................................................................................................. 6

6. ON DIMM Thermal Sensor ........................................................................................................................................... 6

7. Input/Output Functional Description..............................................................................................................................7

8. Registering Clock Driver Specification..........................................................................................................................9

8.1 Timing & Capacitance Values .................................................................................................................................9

8.2 Clock Driver Characteristics .................................................................................................................................... 9

9. Function Block Diagram:............................................................................................................................................... 10

9.1 8GB, 1Gx72 Module (Populated as 1 rank of x8 DDR4 SDRAMs) ......................................................................... 10

9.2 16GB, 2Gx72 Module (Populated as 1 rank of x4 DDR4 SDRAMs) ....................................................................... 11

9.3 32GB, 4Gx72 Module (Populated as 2 ranks of x4 DDR4 SDRAMs) ..................................................................... 12

10. Absolute Maximum Ratings ........................................................................................................................................14

10.1 Absolute Maximum DC Ratings............................................................................................................................. 14

11. AC & DC Operating Conditions...................................................................................................................................14

11.1 Recommended DC Operating Conditions ............................................................................................................. 14

12. AC & DC Input Measurement Levels ..........................................................................................................................15

12.1 AC & DC Logic Input Levels for Single-Ended Signals ......................................................................................... 15

12.2 AC and DC Input Measurement Levels : VREF Tolerances.................................................................................. 15

12.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 16

12.3.1. Differential Signals Definition ......................................................................................................................... 16

12.3.2. Differential Swing Requirements for Clock (CK_t - CK_c) ............................................................................. 16

12.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 17

12.4 Slew Rate Definitions ............................................................................................................................................ 18

12.4.1. Slew Rate Definitions for Differential Input Signals ( CK ) ............................................................................. 18

12.5 Differential Input Cross Point Voltage.................................................................................................................... 19

12.6 Single-ended AC & DC Output Levels................................................................................................................... 20

12.7 Differential AC & DC Output Levels....................................................................................................................... 20

12.8 Single-ended Output Slew Rate ............................................................................................................................ 20

12.9 Differential Output Slew Rate ................................................................................................................................ 21

12.10 Single-ended AC & DC Output Levels of Connectivity Test Mode ...................................................................... 22

12.11 Test Load for Connectivity Test Mode Timing ..................................................................................................... 22

13. DIMM IDD Specification Definition..............................................................................................................................23

14. IDD SPEC Table ......................................................................................................................................................... 26

15. Input/Output Capacitance ........................................................................................................................................... 29

16. Electrical Characterisitics and AC Timing ...................................................................................................................30

16.1 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 30

16.2 Speed Bin Table Note ........................................................................................................................................... 35

17. Timing Parameters by Speed Grade ..........................................................................................................................36

18. Physical Dimensions................................................................................................................................................... 42

18.1 1Gx8 based 1Gx72 Module (1 Rank) - M393A1K43BB0/M393A1K43BB1........................................................... 42

18.1.1. x72 DIMM, populated as one physical rank of x8 DDR4 SDRAMs.............................................................

18.2 2Gx4 based 2Gx72 Module (1 Rank) - M393A2K40BB0/M393A2K40BB1/M393A2K40BB2 ............................... 43

18.2.1. 2Gx72 DIMM, populated as one physical rank of x4 DDR4 SDRAMs ........................................................... 43

18.3 2Gx4 based 4Gx72 Module (2 Ranks) - M393A4K40BB0/M393A4K40BB1/M393A2K40BB2 ............................. 44

18.3.1. 4Gx72 DIMM, populated as two physical ranks of x4 DDR4 SDRAMs.......................................................... 44

... 42

- 3 -

Rev. 1.6

Registered DIMM

datasheet DDR4 SDRAM

1. DDR4 Registered DIMM Ordering Information

Part Number

M393A1K43BB0-CPB/RC

M393A1K43BB1-CTD

M393A2K40BB0-CPB
M393A2K40BB1-CRC
M393A2K40BB2-CTD

M393A4K40BB0-CPB
M393A4K40BB1-CRC
M393A4K40BB2-CTD

NOTE :

1. "##" - PB/RC/TD

2. PB(2133Mbps 15-15-15)/RC(2400Mbps 17-17-17)/TD(2666Mbps 19-19-19)

- DDR4-2666(19-19-19) is backward compatible to DDR4-2400(17-17-17)

2

Density Organization

8GB 1Gx72 1Gx8(K4A8G085WB-BC##)*9 1 31.25mm

16GB 2Gx72 2Gx4(K4A8G045WB-BC##)*18 1 31.25mm

32GB 4Gx72 2Gx4(K4A8G045WB-BC##)*36 2 31.25mm

Component Composition

1

2. Key Features

Speed

tCK(min) 1.25 1.071 0.938 0.833 0.75 ns

CAS Latency 11 13 15 17 19 nCK

tRCD(min) 13.75 13.92 14.06 14.16 14.25 ns

tRP(min) 13.75 13.92 14.06 14.16 14.25 ns

tRAS(min) 35 34 33 32 32 ns

tRC(min) 48.75 47.92 47.06 46.16 46.25 ns

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

11-11-11 13-13-13 15-15-15 17-17-17 19-19-19

Number of

Rank

Height

Unit

• JEDEC standard 1.2V ± 0.06V Power Supply

•V

• 800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin, 1067MHz fCK for 2133Mb/sec/pin,1200MHz fCK for 2400Mb/sec/pin, 1333MHz

• 16 Banks (4 Bank Groups)

• Programmable CAS Latency: 10,11,12,13,14,15,16,17,18,19,20

• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency(CWL) = 9,11 (DDR4-1600) , 10,12 (DDR4-1866) , 11,14 (DDR4-2133), 12,16 (DDR4-2400) and 14,18 (DDR4-

• Burst Length: 8 , 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

• Asynchronous Reset

= 1.2V ± 0.06V

DDQ

for 2666Mb/sec/pin

f

CK

2666)

85C, 3.9us at 85C < T

CASE

CASE

95C

3. Address Configuration

Organization Row Address Column Address Bank Group Address Bank Address Auto Precharge

2Gx4(8Gb) based Module A0-A16 A0-A9 BG0-BG1 BA0-BA1 A10/AP

- 4 -

Rev. 1.6

Registered DIMM

datasheet DDR4 SDRAM

4. Registered DIMM Pin Configurations (Front side/Back side)

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1

2 VSS 146 VREFCA 41

3 DQ4 147 VSS 42 VSS 186 DQS3

4 VSS 148 DQ5 43 DQ30 187 VSS 81 BA0 225 A10/AP 120 VSS 264 DQ49

5 DQ0 149 VSS 44 VSS 188 DQ31 82 RAS

6 VSS 150 DQ1 45 DQ26 189 VSS 83 VDD 227 RFU 122

7

8

9 VSS 153 DQS0

10 DQ6 154 VSS 49 CB0 193 VSS 87 ODT0 231 VDD 126 DQ50 270 VSS

11 VSS 155 DQ7 50 VSS 194 CB1 88 VDD 232 A13 127 VSS 271 DQ51

12 DQ2 156 VSS 51

13 VSS 157 DQ3 52

14 DQ12 158 VSS 53 VSS 197 DQS8

15 VSS 159 DQ13 54 CB6 198 VSS 92 VDD 236 VDD 131 VSS 275 DQ57

16 DQ8 160 VSS 55 VSS 199 CB7 93 C0,CS2

17 VSS 161 DQ9 56 CB2 200 VSS 94 VSS 238 SA2 133

18

19

20 VSS 164 DQS1

21 DQ14 165 VSS 60 CKE0 204 VDD 98 VSS 242 DQ33 137 DQ58 281 VSS

22 VSS 166 DQ15 61 VDD 205 RFU 99

23 DQ10 167 VSS 62 ACT

24 VSS 168 DQ11 63 BG0 207 BG1 101 VSS 245 DQS4

25 DQ20 169 VSS 64 VDD 208 ALERT

26 VSS 170 DQ21 65 A12/BC

27 DQ16 171 VSS 66 A9 210 A11 104 DQ34 248 VSS 143 VPP 287 VPP

28 VSS 172 DQ17 67 VDD 211 A7 105 VSS 249 DQ35 144 RFU 288

29

30

31 VSS 175 DQS2

32 DQ22 176 VSS 71 A3 215 VDD 109 VSS 253 DQ41

33 VSS 177 DQ23 72 A1 216 A2 110

34 DQ18 178 VSS 73 VDD 217 VDD 111

35 VSS 179 DQ19 74 CK0_t 218 CK1_t 112 VS S 256 D QS5 _t

36 DQ28 180 VSS 75 CK0_c 219 CK1_c 113 D Q46 2 57 VS S

37 VSS 181 DQ29 76 VDD 220 VDD 114 VSS 258 DQ47

38 DQ24 182 VSS 77 VTT 221 VTT 115 DQ42 259 VSS

39 VSS 183 DQ25 KEY 116 VSS 260 DQ43

3

12V

,NC

TDQS9_t,

DQS9_t

TDQS9_c,

DQS9_c

TDQS10_t,

DQS10_t

TDQS10_c,

DQS10_c

TDQS11_t,

DQS11_t

TDQS11_c,

DQS11_c

145

12V3,NC

151 VSS 46 VSS 190 DQ27 84 S0_n 228 WE_n/A14 123 VSS 267 DQS6_t

152 DQS0_c 47 CB4 191 VSS 85 VDD 229 VDD 124 DQ54 268 VSS

_t 48 VSS 192 CB5 86 CAS_n/A15 230 NC 125 VSS 269 DQ55

162 VSS 57 VSS 201 CB3 95 DQ36 239 VSS 134 VSS 278 DQS7_t

163 DQS1_c 58 RESET_n 202 VSS 96 VSS 240 DQ37 135 DQ62 279 VSS

_t 59 VDD 203 CKE1 97 DQ32 241 VSS 136 VSS 280 DQ63

173 VSS 68 A8 212 VDD 106 DQ44 250 VSS

174 DQS2_c 69 A6 213 A5 107 VSS 251 DQ45

_t 70 VDD 214 A4 108 DQ40 252 VSS

TDQS12_t,

40

DQS12_t

TDQS12_c,

DQS12_c

TDQS17_t,

DQS17_t

TDQS17_c,

DQS17_c

184 VSS 78 EVENT_n 222 PARITY 117 DQ52 261 VSS

185 DQS3_c 79 A0 223 VDD 118 VSS 262 DQ53

_t 80 VDD 224 BA1 119 DQ48 263 VSS

_n/A16 226 VDD 121

TDQS15_t,

DQS15_t

TDQS15_c,

DQS15_c

265 VSS

266 DQS6_c

195 VSS 89 S1_n 233 VDD 128 DQ60 272 VSS

196 DQS8_c 90 VDD 234 A17 129 VSS 273 DQ61

_t 91 ODT1 235 NC,C2 130 DQ56 274 VSS

_n,NC 237 NC,CS3_c,C1 132

TDQS13_t,

DQS13_t

_n 206 VDD 100

_n 102 DQ38 246 VSS 141 SCL 285 SDA

_n 209 VDD 103 VSS 247 DQ39 142 VPP 286 VPP

TDQS13_c,

DQS13_c

TDQS14_t,

DQS14_t

TDQS14_c,

DQS14_c

243 VSS 138 VSS 282 DQ59

244 DQS4_c 139 SA0 283 VSS

_t 140 SA1 284 VDDSPD

254 VSS

255 DQS5_c

TDQS16_t,

DQS16_t

TDQS16_c,

DQS16_c

276 VSS

277 DQS7_c

VPP

4

NOTE:

1. VPP is 2.5V DC

2. Pin 230 is defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pin 230 is defined as SAVE_n for NVDIMMs.

3. Pins 1 and 145 are defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pins 1 and 145 are defined as 12V for Hybrid /NVDIMM

4. The 5th VPP is required on all modules. DIMMs.

- 5 -

Rev. 1.6

Thermal sensor

SA0 SA1 SA2

SCL

1K

EVENT_nEVENT_n

SCL

SDASDA

Serial PD with

SA0 SA1 SA2

VSSZQCAL

SCL

SDA

Register

SA0

SA1

SA2

Registered DIMM

datasheet DDR4 SDRAM

5. Pin Description

Pin Name Description Pin Name Description

1

A0–A17

BA0, BA1 Register bank select input SDA I

BG0, BG1 Register bank group select input SA0–SA2 I

RAS_n

CAS_n

WE_n

CS0_n, CS1_n,

CS2_n, CS3_n

CKE0, CKE1 Register clock enable lines input VSS Power supply return (ground)

ODT0, ODT1 Register on-die termination control lines input VDDSPD Serial SPD/TS positive power supply

ACT_n Register input for activate input ALERT_n Register ALERT_n output

DQ0–DQ63 DIMM memory data bus RESET_n Set Register and SDRAMs to a Known State

CB0–CB7 DIMM ECC check bits EVENT_n SPD signals a thermal event has occurred

DQS0_t–
DQS17_t

DQS0_c–
DQS17_c

CK0_t, CK1_t

CK0_c, CK1_c

Register address input SCL I2C serial bus clock for SPD/TS and register

2C serial bus data line for SPD/TS and register

2C slave address select for SPD/TS and register

2

Register row address strobe input PAR Register parity input

3

Register column address strobe input VDD SDRAM core power supply

4

Register write enable input VPP SDRAM activating power supply

DIMM Rank Select Lines input VREFCA SDRAM command/address reference supply

Data Buffer data strobes
(positive line of differential pair)

Data Buffer data strobes
(negative line of differential pair)

Register clock input (positive line of differential
pair)

Register clocks input (negative line of differential
pair)

VTT

RFU Reserved for future use

SDRAM I/O termination supply

NOTE :

1. Address A17 is only valid for 16 Gb x4 based SDRAMs.

2. RAS_n is a multiplexed function with A16.

3. CAS_n is a multiplexed function with A15.

4. WE_n is a multiplexed function with A14.

6. ON DIMM Thermal Sensor

NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM

[ Table 1 ] Temperature Sensor Characteristics

Grade Range

75 < Ta < 95 - +/- 0.5 +/- 1.0

B

40 < Ta < 125 - +/- 1.0 +/- 2.0 -

-20 < Ta < 125 - +/- 2.0 +/- 3.0 -

Resolution 0.25 C /LSB -

Temperature Sensor Accuracy

Min. Typ. Max.

- 6 -

Units NOTE

-

C

Rev. 1.6

Registered DIMM

datasheet DDR4 SDRAM

7. Input/Output Functional Description

Symbol Type Function

CK0_t, CK0_c,

CK1_t, CK1_c

CKE0, CKE1 Input

CS0_n, CS1_n,

CS2_n, CS3_n

C0, C1, C2 Input

ODT0, ODT1 Input

ACT_n Input

RAS_n/A16.
CAS_n/A15.

WE_n/A14

BG0 - BG1 Input

BA0 - BA1 Input

A0 - A17 Input

A10 / AP Input

A12 / BC_n Input

RESET_n

DQ

DQS0_t-DQS17_t,

DQS0_c-DQS17_c

PAR Input

ALERT_n

RFU Reserved for Future Use: No on DIMM electrical connection is present

NC No Connect: No on DIMM electrical connection is present

Input

Input

Input

CMOS

Input

Input/

Output

Input/

Output

Output
(Input)

Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of
the positive edge of CK_t and negative edge of CK_c.

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and
output drivers. Taking CKE LOW provides Precharge Power-Down and Self-Refresh operation (all banks idle), or
Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal
DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all
operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK_t, CK_c, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE, are disabled
during Self-Refresh.

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection.
CS_n is considered part of the command code.

Chip ID : Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of stacked component. Chip ID
is considered part of the command code.

On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM.
When enabled, ODT is only applied to each DQ, DQS_t, DQS_c, TDQS_t and TDQS_c signal. The ODT pin will be
ignored if MR1 is programmed to disable RTT_NOM.

Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The input into
RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14

Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being entered.
Those pins have multi function. For example, for activation with ACT_n Low, these are Addresses like A16, A15 and
A14 but for non-activation command with ACT_n High, these are Command pins for Read, Write and other command
defined in command truth table

Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write or Precharge command is being
applied. BG0 also determines which mode register is to be accessed during a MRS cycle.

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied.
Bank address also determines which mode register is to be accessed during a MRS cycle.

Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write
commands to select one location out of the memory array in the respective bank. A10/AP, A12/BC_n, RAS_n/A16,
CAS_n/A15 and WE_n/A14 have additional functions. See other rows. The address inputs also provide the op-code
during Mode Register Set commands. A17 is only defined for 16 Gb x4 SDRAM configurations.

Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be
performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10
is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.

Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst chop (on-thefly) will be
performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH.
RESET_n must be HIGH during normal operation.

Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of
Data Burst. Any DQ from DQ0-DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4
A4=High. Refer to vendor specific data sheets to determine which DQ is used.

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data
strobe DQS_t is paired with differential signals DQS_c, respectively, to provide differential pair signaling to the system
during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended.

Command and Address Parity Input: DDR4 Supports Even Parity check in SDRAMs with MR setting. Once it’s enabled
via Register in MR5, then SDRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1,
BA0-BA1, A17-A0. Input parity should be maintained at the rising edge of the clock and at the same time with
command & address with CS_n LOW

Alert : It has multi functions such as CRC error flag, Command and Address Parity error flag as Output signal. If there
is error in CRC, then ALERT_n goes LOW for the period time interval and goes back HIGH. If there is error in
Command Address Parity Check, then ALERT_n goes LOW for relatively long period until on going SDRAM internal
recovery transaction is complete. During Connectivity Test mode this pin functions as an input.
Using this signal or not is dependent on the system. If the SDRAM ALERT_n pins are not connected to the ALERT_n
pin on the edge connector is must still be connected to VDD on DIMM.

- 7 -

Rev. 1.6

Registered DIMM

Symbol Type Function

1

VDD

VSS Supply

VTT Supply

VPP Supply

VDDSPD Supply

VREFCA Supply

NOTE :

1. For PC4 VDD is 1.2V. For PC4L VDD is TBD.

Supply

Power Supply: 1.2 V ± 0.06 V

Ground

VDD/2

SDRAM Activating Power Supply: 2.5V ( 2.375V min, 2.75V max)

SPD and register supply voltage. Register requires the nominl volatge to be 2.5V ± 10%.

Reference voltage for CA

datasheet DDR4 SDRAM

- 8 -

Rev. 1.6

Registered DIMM

datasheet DDR4 SDRAM

8. Registering Clock Driver Specification

8.1 Timing & Capacitance Values

Symbol Parameter Conditions

fclock Input Clock Frequency application frequency 625 1080 625 1350 MHz

t

CH/tCL

t

ACT

t

PDM

t

DIS

t

C

C

C

Note:

1. This parameter does not include package capacitance

2. Data inputs are DCKE0/1, DODT0/1, DA0..DA17, DBA0..DBA1, DBG0..DBG1, DACT_n, DC0..DC2, DPAR, DCS0/1_n

Pulse duration, CK_t, CK_c HIGH or
LOW

Inputs active time4 before DRST_n is
taken HIGH

Propagation delay, single-bit switch­ing, CK_t/ CK_c to output

output disable time

output enable time

EN

Input capacitance, Data inputs

I

Input capacitance, CK_t, CK_c

CK

Input capacitance, DRST_n

IR

DCKE0/1 = LOW and DCS0/
1_n = HIGH

1.2V Operation 1 1.3 1 1.3 ns

Rising edge of Yn_t to out­put float

Output valid to rising edge of
Yn_t

1,2

NOTE

1,2

NOTE

or VSS ;

V

I=VDD

=1.2V

V

DD

DDR4-1600/1866/2133 DDR4-2400/2666

Min Max Min Max

0.4 - 0.4 -

16 - 16 -

0.5*tCK +

tQSK1(min)

0.5*tCK -

tQSK1(max)

0.8 1.1 0.8 1.0

0.8 1.1 0.8 1.0

0.5 2.0 0.5 2.0

-

-

0.5*tCK +

tQSK1(min)

0.5*tCK -

tQSK1(max)

-ps

-ps

Units Notes

t

CK

t

CK

pF

8.2 Clock Driver Characteristics

Symbol Parameter Conditions

t

jit

t

STAB

t

CKsk

t

jit

t

(hper)

jit

t

Qsk1

t

dynoff

(cc)

(per)

Cycle-to-cycle period jitter CK_t/CK_c stable 0

Stabilization time - 5 - 5 - 5 us

Clock Output skew - 10 - 10 - 10 ps

Yn Clock Period jitter

Half period jitter

Qn Output to clock tolerance

Maximum re-driven dynamic clock
off-set

DDR4-1600/1866/

2133

Min Max Min Max Min Max

0.025 x
tCK

-0.025 *
tCK

-0.032 *
tCK

-0.125 *
tCK

0.025 *
tCK

0.032 *
tCK

0.125 *
tCK

-50-45-45ps

DDR4-2400 DDR4-2666

0

-0.025 *
tCK

-0.032 *
tCK

-0.125 *
tCK

0.025 x
tCK

0.025 *
tCK

0.032 *
tCK

0.125 *
tCK

0

-0.025 *
tCK

-0.032 *
tCK

-0.1 * tCK 0.1 * tCK ps

0.025 x
tCK

0.025 *
tCK

0.032 *
tCK

Units Notes

ps

ps

ps

- 9 -

Rev. 1.6

DQS_t
DQS_c

D0

CKE

ODT

ZQ

DQ[7:0]

CS_n

DQS_t
DQS_c

D1

CKE

ODT

ZQ

DQ[7:0]

CS_n

DQS_t
DQS_c

D2

CKE

ODT

ZQ

DQ[7:0]

CS_n

DQS_t
DQS_c

D3

CKE

ODT

ZQ

DQ[7:0]

CS_n

DQS_t
DQS_c

D4

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS_t
DQS_c

D5

CKE

ODT

ZQ

DQ[7:0]

CS_n

DQS_t
DQS_c

D6

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS_t
DQS_c

D7

CKE

ODT

ZQ

DQ[7:0]

CS_n

DQS_t
DQS_c

D8

CKE

ODT

ZQ

DQ[7:0]

CS_n

CS0A_n

ODT0A
CKE0A

CS0B_n

ODT0B
CKE0B

VSS VSS VSSVSSVSS

VSS VSSVSSVSS

R
E
G

I
S
T
E
R

BA[1:0]

A[16:0]

PARITY, ACT_n

CKE0

RESET_n

BA1:0]A -> BA[1:0] : SDRAMs D[4:0]

A[16:0]A -> A[16:0] : SDRAMs D[4:0]

PARA -> PAR, ACT_n : SDRAMs D[4:0]

CKE0A -> CKE : SDRAMs D[4:0]

BG[1:0] BG[1:0]A -> BG[1:0] : SDRAMs D[4:0]

BA[1:0]B -> BA[1:0] : SDRAMs D[8:5]

A[16:0]B -> A[16:0] : SDRAMs D[8:5]

PARB -> PAR, ACT_n : SDRAMs D[8:5]

CKE0B -> CKE : SDRAMs D[8:5]

Y1

(_t

, _c) -> CK

1(_t, _c)

: SDRAMs D[4:0]

QRESET_n : All SDRAMs

CK0_c

ODT0

CK0_t

Y0

(_t

, _c) -> CK

0(_t, _c)

: SDRAMs D[8:5]

BG[1:0]B -> BG[1:0] : SDRAMs D[8:5]

CK1_c

CK1_t

CS0_n

ODT0A -> ODT : SDRAMs D[4:0]
ODT0B -> ODT : SDRAMs D[8:5]

CS0A_n -> CS_n : SDRAMs D[4:0]
CS0B_n -> CS_n : SDRAMs D[8:5]

V

SS

V

PP

D0 - D8

V

TT

V

DDSPD

Serial PD

V

DD

V

REFCA

NOTE :

1. Unless otherwise noted, resistor values are 15 5%.

2. See the Net Structure diagrams for all resistors associated with the command, address and control bus.

3. ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram.

D0 - D8

D0 - D8

D0 - D8

DQS0_t

DQS0_c

DQ[7:0]

DQS1_t

DQS1_c

DQ[15:8]

DQS2_t

DQS2_c

DQ[23:16]

DQS3_t

DQS3_c

DQ[31:24]

DQS8_t

DQS8_c

CB[7:0]

DQS4_t

DQS4_c

DQ[39:32]

DQS5_t

DQS5_c

DQ[47:40]

DQS6_t

DQS6_c

DQ[55:48]

DQS7_t

DQS7_c

DQ[63:56]

DBI_n/DM_nDBI0_n/DM0_n

DBI_n/DM_nDBI1_n/DM1_n

DBI_n/DM_nDBI2_n/DM2_n

DBI_n/DM_nDBI3_n/DM3_n

DBI_n/DM_nDBI8_n/DM8_n

DBI_n/DM_nDBI4_n/DM4_n

DBI_n/DM_nDBI5_n/DM5_n

DBI_n/DM_nDBI6_n/DM6_n

DBI_n/DM_nDBI7_n/DM7_n

Thermal sensor

SA0 SA1 SA2

SCL

1K

EVENT_nEVENT_n

SCL

SDASDA

Serial PD with

SA0 SA1 SA2

VSSZQCAL

SCL

SDA

Register

SA0

SA1

SA2

Registered DIMM

datasheet DDR4 SDRAM

9. Function Block Diagram:

9.1 8GB, 1Gx72 Module (Populated as 1 rank of x8 DDR4 SDRAMs)

- 10 -

Rev. 1.6

DQS0_t

DQS0_c

DQ[3:0]

DQS_t
DQS_c

D1

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS1_t

DQS1_c

DQ[11:8]

DQS_t
DQS_c

D2

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS2_t

DQS2_c

DQ[19:16]

DQS_t
DQS_c

D3

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS3_t

DQS3_c

DQ[27:24]

DQS_t
DQS_c

D4

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS8_t

DQS8_c

CB[3:0]

DQS_t
DQS_c

D5

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS_t
DQS_c

D6

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS_t
DQS_c

D7

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS_t
DQS_c

D8

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS_t
DQS_c

D9

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS_t
DQS_c

D10

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS_t
DQS_c

D15

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS_t
DQS_c

D16

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS_t
DQS_c

D17

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS_t
DQS_c

D18

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS4_t

DQS4_c

DQ[35:32]

DQS_t
DQS_c

D11

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS5_t

DQS5_c

DQ[43:40]

DQS_t
DQS_c

D12

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS6_t

DQS6_c

DQ[51:48]

DQS_t
DQS_c

D13

CKE

ODT

ZQ

DQ[3:0]

CS_n

DQS7_t

DQS7_c

DQ[59:56]

DQS_t
DQS_c

D14

CKE

ODT

ZQ

DQ[3:0]

CS_n

QACS0_n

QAODT0
QACKE0

QBCS0_n

QBODT0
QBCKE0

VSS VSS VSSVSSVSS

VSS VSS VSSVSSVSS

VSS VSSVSSVSS

VSS VSSVSSVSS

R
E
G

I

S
T
E
R

BA[1:0]

A[17:0]

ACT_n

PARITY

CKE0

RESET_n

QABA[1:0] -> BA[1:0] : SDRAMs D[10:1]

QAA[17:0] -> A[17:0] : SDRAMs D[10:1]

QAACT_n -> ACT_n : SDRAMs D[10:1]

QACKE0 -> CKE : SDRAMs D[10:1]

BG[1:0] QABG[1:0] -> BG[1:0] : SDRAMs D[10:1]

QBBA[1:0] -> BA[1:0] : SDRAMs D[18:11]

QBA[17:0] -> A[17:0] : SDRAMs D[18:11]

QBACT_n -> ACT_n : SDRAMs D[18:11]

QAPAR -> PAR : SDRAMs D[10:1]
QBPAR -> PAR : SDRAMs D[18:11]

QBCKE0 -> CKE : SDRAMs D[18:11]

Y0_c -> CK_c : SDRAMs D[18:11]
Y1_c -> CK_c : SDRAMs D[10:1]

QRST_n -> RESET_n : All SDRAMs

CK0_c

ODT0

CK0_t

Y0_t -> CK_t : SDRAMs D[18:11]
Y1

_t

-> CK_t : SDRAMs D[10:1]

QBBG[1:0] -> BG[1:0] : SDRAMs D[18:11]

CK1_c

CK1_t

CS0_n

ALERT_n

ERROR_IN_n -> ALERT_n : All SDRAMs

QAODT0 -> ODT : SDRAMs D[10:1]
QBODT0 -> ODT : SDRAMs D[18:11]

QACS0_n -> CS_n : SDRAMs D[10:1]
QBCS0_n -> CS_n : SDRAMs D[18:11]

V

SS

V

PP

D1 - D18

V

TT

V

DDSPD

Serial PD

V

DD

V

REFCA

NOTE :

1. Unless otherwise noted, resistor values are 15 5%.

2. See the Net Structure diagrams for all resistors associated with the command, address and control bus.

3. ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram.

Thermal sensor

SA0 SA1 SA2

SCL

1K

EVENT_nEVENT_n

SCL

SDASDA

Serial PD with

SA0 SA1 SA2

VSSZQCAL

SCL

SDA

Register

SA0

SA1

SA2

D1 - D18

D1 - D18

D1 - D18

DQS9_t

DQS9_c

DQ[7:4]

DQS10_t

DQS10_c

DQ[15:12]

DQS11_t

DQS11_c

DQ[23:20]

DQS12_t

DQS12_c

DQ[31:28]

DQS17_t

DQS17_c

CB[7:4]

DQS13_t
DQS13_c

DQ[39:36]

DQS14_t
DQS14_c

DQ[47:44]

DQS15_t
DQS15_c

DQ[55:52]

DQS16_t
DQS16_c

DQ[63:60]

Registered DIMM

datasheet DDR4 SDRAM

9.2 16GB, 2Gx72 Module (Populated as 1 rank of x4 DDR4 SDRAMs)

- 11 -

Rev. 1.6

DQS0_t

DQS0_c

DQ[3:0]

DQS_t
DQS_c

D6

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS1_t

DQS1_c

DQ[11:8]

DQS_t
DQS_c

D7

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS2_t

DQS2_c

DQ[19:16]

DQS_t
DQS_c

D8

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS3_t

DQS3_c

DQ[27:24]

DQS_t
DQS_c

D9

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D16

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D17

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D18

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D19

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D11

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D12

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D13

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D14

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS9_t

DQS9_c

DQ[7:4]

DQS_t
DQS_c

D1

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS10_t
DQS10_c
DQ[15:12]

DQS_t
DQS_c

D2

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS11_t

DQS11_c

DQ[23:20]

DQS_t
DQS_c

D3

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS12_t
DQS12_c
DQ[31:28]

DQS_t
DQS_c

D4

CKE

ODT

ZQ

DQ[3:0]

CS

_n

QACS0

_n

QAODT0
QACKE0

VSS VSSVSSVSS

VSS VSSVSSVSS

VSS VSSVSSVSS

VSS VSSVSSVSS

NOTE :

1. Unless otherwise noted, resistor values are 15 5%.

2. See the Net Structure diagrams for all resistors associated with the command, address and control bus.

3. ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram.

Thermal sensor

SA0 SA1 SA2

SCL

1K

EVENT_nEVENT_n

SCL

SDASDA

Serial PD with

SA0 SA1 SA2

VSSZQCAL

SCL

SDA

Register

SA0

SA1

SA2

QACS1

_n

QAODT1
QACKE1

DQS8_t

DQS8_c

CB[3:0]

DQS_t
DQS_c

D10

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D20

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D15

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS17_t
DQS17_c

CB[7:4]

DQS_t
DQS_c

D5

CKE

ODT

ZQ

DQ[3:0]

CS

_n

VSS

VSS

VSS

VSS

V

SS

V

PP

D1 - D36

V

TT

V

DDSPD

Serial PD

V

DD

V

REFCA

D1 - D36

D1 - D36

D1 - D36

Registered DIMM

datasheet DDR4 SDRAM

9.3 32GB, 4Gx72 Module (Populated as 2 ranks of x4 DDR4 SDRAMs)

- 12 -

Rev. 1.6

DQS4_t

DQS4_c

DQ[35:32]

DQS_t
DQS_c

D25

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS5_t

DQS5_c

DQ[43:40]

DQS_t
DQS_c

D26

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS6_t

DQS6_c

DQ[51:48]

DQS_t
DQS_c

D27

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS7_t

DQS7_c

DQ[59:56]

DQS_t
DQS_c

D28

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D33

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D34

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D35

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D36

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D29

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D30

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D31

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS_t
DQS_c

D32

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS13_t

DQS13_c

DQ[39:36]

DQS_t
DQS_c

D21

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS14_t

DQS14_c

DQ[47:44]

DQS_t
DQS_c

D22

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS15_t

DQS15_c

DQ[55:52]

DQS_t
DQS_c

D23

CKE

ODT

ZQ

DQ[3:0]

CS

_n

DQS16_t

DQS16_c

DQ[63:60]

DQS_t
DQS_c

D24

CKE

ODT

ZQ

DQ[3:0]

CS

_n

QBCS0_n

QBODT0
QBCKE0

VSS VSSVSSVSS

VSS VSSVSSVSS

VSS VSSVSSVSS

VSS VSSVSSVSS

QBCS1_n

QBODT1
QBCKE1

R
E

G

I
S
T
E
R

BA[1:0]

A[17:0]

ACT

_n

C[2:0]

PARITY

CKE0

CKE1

RESET

_n

QABA[1:0] -> BA[1:0] : SDRAMs D[20:1]

QAA[17:0] -> A[17:0] : SDRAMs D[20:1]

QAACT_n -> ACT_n : SDRAMs D[20:1]

QAC[2:0] -> C[2:0] : SDRAMs D[20:1]

QACKE0 -> CKE : SDRAMs D[10:1]

BG[1:0] QABG[1:0] -> BG[1:0] : SDRAMs D[20:1]

QBBA[1:0] -> BA[1:0] : SDRAMs D[36:21]

QBA[17:0] -> A[17:0] : SDRAMs D[36:21]

QBACT_n -> ACT_n : SDRAMs D[36:21]

QBC[2:0] -> C[2:0] : SDRAMs D[36:21]

QAPAR -> PAR : SDRAMs D[20:1]
QBPAR -> PAR : SDRAMs D[36:21]

QBCKE0 -> CKE : SDRAMs D[28:21]

Y0

_c

-> CK_c : SDRAMs D[24:21], D[32:29]

Y1

_c

-> CK_c: SDRAMs D[5:1], D[15:11]

QRST

_n

-> RESET_n : All SDRAMs

CK0

_c

ODT0

QACKE1 -> CKE : SDRAMs D[20:11]
QBCKE1 -> CKE : SDRAMs D[36:29]

CK0

_t

Y0_t -> CK_t : SDRAMs D[24:21], D[32:29]
Y1

_t

-> CK_t : SDRAMs D[5:1], D[15:11]

QBBG[1:0] -> BG[1:0] : SDRAMs D[36:21]

CK

1

_c

CK1

_t

ODT1

CS0

_n

CS1

_n

ALERT

_n

ERROR_IN_n - ALERT_n : All SDRAMs

QAODT0 -> ODT : SDRAMs D[10:1]
QBODT0 -> ODT : SDRAMs D[28:21]
QAODT1 -> ODT : SDRAMs D[20:11]
QBODT1 -> ODT : SDRAMs D[36:29]

QACS0_n -> CS_n : SDRAMs D[10:1]
QBCS0_n -> CS_n : SDRAMs D[28:21]

QACS1_n -> CS_n : SDRAMs D[20:11]
QBCS1_n -> CS_n : SDRAMs D[36:29]

Y2

_t

-> CK_t : SDRAMs D[28:25], D[36:33]

Y3

_t

-> CK_t : SDRAMs D[10:6], D[20:16]

Y2

_c

-> CK_c : SDRAMs D[28:25], D[36:33]

Y3

_c

-> CK_c : SDRAMs D[10:6], D[20:16]

NOTE :

1.

CK0_t, CK0_c terminated with 120 ± 5% resistor

.

2.

CK1_t, CK1_c terminated with 120 ± 5% resistor but not used.

3.

Unless otherwise noted resistors are 22 ± 5%.

Registered DIMM

datasheet DDR4 SDRAM

- 13 -

Rev. 1.6

Registered DIMM

datasheet DDR4 SDRAM

10. Absolute Maximum Ratings

10.1 Absolute Maximum DC Ratings

[ Table 2 ] Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

VDD Voltage on VDD pin relative to Vss -0.3 ~ 1.5 V 1,3

VDDQ Voltage on VDDQ pin relative to Vss -0.3 ~ 1.5 V 1,3

VPP Voltage on VPP pin relative to Vss -0.3 ~ 3.0 V 4

V

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA
may be equal to or less than 300 mV

4. VPP must be equal or greater than VDD/VDDQ at all times.

Voltage on any pin except VREFCA to Vss -0.3 ~ 1.5 V 1,3

IN, VOUT

T

Storage Temperature -55 to +100 °C 1,2

STG

11. AC & DC Operating Conditions

11.1 Recommended DC Operating Conditions

[ Table 3 ] Recommended DC Operating Conditions

Symbol Parameter

VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3

VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3

VPP Peak-to-Peak Voltage 2.375 2.5 2.75 V 3

NOTE:

1. Under all conditions V

2. V

tracks with VDD. AC parameters are measured with VDD and V

DDQ

3. DC bandwidth is limited to 20MHz.

must be less than or equal to VDD.

DDQ

Min. Typ. Max.

tied together.

DDQ

Rating

Unit NOTE

- 14 -