Samsung M393A2G40EB2-CTD User Manual

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Page 1

Rev. 1.41, Nov. 2016

M393A1G40EB1 M393A1G40EB2 M393A1G43EB1

M393A2G40EB1 M393A2G40EB2

288pin Registered DIMM

based on 4Gb E-die

78FBGA with Lead-Free & Halogen-Free (RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

- 1 -

Page 2

Rev. 1.41

Registered DIMM

datasheet DDR4 SDRAM

Revision History

Revision No. History Draft Date Remark Editor

1.0 - First SPEC Release 19th Oct.2015 - J.Y.Lee

1.1 - Change of IDD value on page 27~28 2nd Feb.2016 - J.Y.Lee

- Change of 8.1 Timing & Capacitance values (tACT) on page 9

- Change of Physical Dimensions (Module Thickness) on page 41~43

1.2 - Addition of DDR4-2666 7th Apr.2016 - J.Y.Lee

1.21 - Correction of Physical Dimensions on page 44~45 18th May.2016 - J.Y.Lee

1.3 - Correction of Typo 10th Sep.2016 - J.Y.Lee

1.4

1.41 - Correction of Typo 2nd Nov.2016 - J.Y.Lee

- Addition of IDD value on page 28~31 ( M393A5143EB0-CRC, M393A5143EB1-CTD, M393A1G40EB2-CTD, M393A1G43EB1-CTD, M393A2G40EB2-CTD)

20th Sep.2016 - J.Y.Lee

- 2 -

Page 3

Rev. 1.41

Registered DIMM

datasheet DDR4 SDRAM

Table Of Contents

288pin Registered DIMM based on 4Gb E-die

1. DDR4 Registered DIMM Ordering Information ............................................................................................................. 4

2. Key Features................................................................................................................................................................. 4

3. Address Configuration .................................................................................................................................................. 4

4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................5

5. Pin Description ............................................................................................................................................................. 6

6. ON DIMM Thermal Sensor ........................................................................................................................................... 6

7. Input/Output Functional Description..............................................................................................................................7

8. Registering Clock Driver Specification..........................................................................................................................9

8.1 Timing & Capacitance values .................................................................................................................................. 9

8.2 Clock driver Characteristics..................................................................................................................................... 9

9. Function Block Diagram:............................................................................................................................................... 10

9.1 8GB, 1Gx72 Module (Populated as 1 rank of x4 DDR4 SDRAMs) ......................................................................... 10

9.2 8GB, 1Gx72 Module (Populated as 2 ranks of x8 DDR4 SDRAMs) ....................................................................... 11

9.3 16GB, 2Gx72 Module (Populated as 2 ranks of x4 DDR4 SDRAMs) ..................................................................... 13

10. Absolute Maximum Ratings ........................................................................................................................................15

10.1 Absolute Maximum DC Ratings............................................................................................................................. 15

11. AC & DC Operating Conditions...................................................................................................................................15

11.1 Recommended DC Operating Conditions ............................................................................................................. 15

12. AC & DC Input Measurement Levels ..........................................................................................................................16

12.1 AC & DC Logic Input Levels for Single-Ended Signals ......................................................................................... 16

12.2 AC and DC Input Measurement Levels : VREF Tolerances.................................................................................. 16

12.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 17

12.3.1. Differential Signals Definition ......................................................................................................................... 17

12.3.2. Differential Swing Requirements for Clock (CK_t - CK_c) ............................................................................. 17

12.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 18

12.4 Slew Rate Definitions ............................................................................................................................................ 19

12.4.1. Slew Rate Definitions for Differential Input Signals ( CK ) ............................................................................. 19

12.5 Differential Input Cross Point Voltage.................................................................................................................... 20

12.6 Single-ended AC & DC Output Levels................................................................................................................... 21

12.7 Differential AC & DC Output Levels....................................................................................................................... 21

12.8 Single-ended Output Slew Rate ............................................................................................................................ 21

12.9 Differential Output Slew Rate ................................................................................................................................ 22

12.10 Single-ended AC & DC Output Levels of Connectivity Test Mode ...................................................................... 23

12.11 Test Load for Connectivity Test Mode Timing ..................................................................................................... 23

13. DIMM IDD Specification Definition..............................................................................................................................24

14. IDD SPEC Table ......................................................................................................................................................... 27

15. Input/Output Capacitance ........................................................................................................................................... 31

16. Electrical Characterisitics and AC Timing ...................................................................................................................32

16.1 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 32

16.2 Speed Bin Table Note ........................................................................................................................................... 37

17. Timing Parameters by Speed Grade ..........................................................................................................................38

18. Physical Dimensions................................................................................................................................................... 44

18.1 1Gx4 based 1Gx72 Module (1 Rank) - M393A1G40EB1/M393A1G40EB2.......................................................... 44

18.1.1. x72 DIMM, populated as one physical rank of x4 DDR4 SDRAMs.............................................................

18.2 512Mx8 based 1Gx72 Module (2 Ranks) - M393A1G43EB1................................................................................45

18.2.1. x72 DIMM, populated as two physical ranks of x8 DDR4 SDRAMs .............................................................. 45

18.3 1Gbx4 based 2Gx72 Module (2 Ranks) - M393A2G40EB1/M393A2G40EB2 ...................................................... 46

18.3.1. x72 DIMM, populated as two physical ranks of x4 DDR4 SDRAMs .............................................................. 46

... 44

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Page 4

Rev. 1.41

Registered DIMM

datasheet DDR4 SDRAM

1. DDR4 Registered DIMM Ordering Information

Part Number

M393A1G40EB1-CPB/RC

M393A1G40EB2-CTD

M393A1G43EB1-CPB/RC/TD 8GB 1Gx72 512Mx8(K4A4G085WE-BC##)*18 2 31.25mm

M393A2G40EB1-CPB/RC

M393A2G40EB2-CTD

NOTE:

1. "##" - PB/RC/TD

2. PB(2133Mbps 15-15-15)/RC(2400Mbps 17-17-17)/TD(2666Mbps 19-19-19)

- DDR4-2666(19-19-19) is backward compatible to DDR4-2400(17-17-17)

Density Organization

8GB 1Gx72 1Gx4(K4A4G045WE-BC##)*18 1 31.25mm

16GB 2Gx72 1Gx4(K4A4G045WE-BC##)*36 2 31.25mm

Component Composition

Number of

Rank

2. Key Features

Speed

tCK(min) 1.25 1.071 0.938 0.833 0.75 ns

CAS Latency 11 13 15 17 19 nCK

tRCD(min) 13.75 13.92 14.06 14.16 14.25 ns

tRP(min) 13.75 13.92 14.06 14.16 14.25 ns

tRAS(min) 35 34 33 32 32 ns

tRC(min) 48.75 47.92 47.06 46.16 46.25 ns

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

11-11- 11 13-13-13 15-15-15 17-17-17 19-19-19

Height

Unit

• JEDEC standard 1.2V ± 0.06V Power Supply

•V

• 800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin, 1067MHz fCK for 2133Mb/sec/pin,1200MHz fCK for 2400Mb/sec/pin,1333MHz

• 16 Banks (4 Bank Groups)

• Programmable CAS Latency: 10,11,12,13,14,15,16,17,18,19,20

• Programmable Additive Latency (Posted CAS): 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600) , 10,12 (DDR4-1866), 11,14 (DDR4-2133),12,16 (DDR4-2400) and 14,18 (DDR4-

• Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

• Asynchronous Reset

= 1.2V ± 0.06V

DDQ

for 2666Mb/sec/pin

2666)

85C, 3.9us at 85C < T

CASE

95C

3. Address Configuration

Organization Row Address Column Address Bank Group Address Bank Address Auto Precharge

1Gx4(4Gb) based Module A0-A15 A0-A9 BG0-BG1 BA0-BA1 A10/AP

512Mx8(4Gb) based Module A0-A14 A0-A9 BG0-BG1 BA0-BA1 A10/AP

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Page 5

Rev. 1.41

Registered DIMM

datasheet DDR4 SDRAM

4. Registered DIMM Pin Configurations (Front side/Back side)

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

2 VSS 146 VREFCA 41

3 DQ4 147 VSS 42 VSS 186 DQS3

4 VSS 148 DQ5 43 DQ30 187 VSS 81 BA0 225 A10/AP 120 VSS 264 DQ49

5 DQ0 149 VSS 44 VSS 188 DQ31 82 RAS

6 VSS 150 DQ1 45 DQ26 189 VSS 83 VDD 227 RFU 122

9 VSS 153 DQS0

10 DQ6 154 VSS 49 CB0 193 VSS 87 ODT0 231 VDD 126 DQ50 270 VSS

11 VSS 155 DQ7 50 VSS 194 CB1 88 VDD 232 A13 127 VSS 271 DQ51

12 DQ2 156 VSS 51

13 VSS 157 DQ3 52

14 DQ12 158 VSS 53 VSS 197 DQS8

15 VSS 159 DQ13 54 CB6 198 VSS 92 VDD 236 VDD 131 VSS 275 DQ57

16 DQ8 160 VSS 55 VSS 199 CB7 93 C0,CS2

17 VSS 161 DQ9 56 CB2 200 VSS 94 VSS 238 SA2 133

20 VSS 164 DQS1

21 DQ14 165 VSS 60 CKE0 204 VDD 98 VSS 242 DQ33 137 DQ58 281 VSS

22 VSS 166 DQ15 61 VDD 205 RFU 99

23 DQ10 167 VSS 62 ACT

24 VSS 168 DQ11 63 BG0 207 BG1 101 VSS 245 DQS4

25 DQ20 169 VSS 64 VDD 208 ALERT

26 VSS 170 DQ21 65 A12/BC

27 DQ16 171 VSS 66 A9 210 A11 104 DQ34 248 VSS 143 VPP 287 VPP

28 VSS 172 DQ17 67 VDD 211 A7 105 VSS 249 DQ35 144 RFU 288

31 VSS 175 DQS2

32 DQ22 176 VSS 71 A3 215 VDD 109 VSS 253 DQ41

33 VSS 177 DQ23 72 A1 216 A2 110

34 DQ18 178 VSS 73 VDD 217 VDD 111

35 VSS 179 DQ19 74 CK0_t 218 CK1_t 112 VS S 256 D QS5 _t

36 DQ28 180 VSS 75 CK0_c 219 CK1_c 113 D Q46 2 57 VS S

37 VSS 181 DQ29 76 VDD 220 VDD 114 VSS 258 DQ47

38 DQ24 182 VSS 77 VTT 221 VTT 115 DQ42 259 VSS

39 VSS 183 DQ25 KEY 116 VSS 260 DQ43

12V

,NC

TDQS9_t,

DQS9_t

TDQS9_c,

DQS9_c

TDQS10_t,

DQS10_t

TDQS10_c,

DQS10_c

TDQS11_t,

DQS11_t

TDQS11_c,

DQS11_c

145

12V3,NC

151 VSS 46 VSS 190 DQ27 84 S0_n 228 WE_n/A14 123 VSS 267 DQS6_t

152 DQS0_c 47 CB4 191 VSS 85 VDD 229 VDD 124 DQ54 268 VSS

_t 48 VSS 192 CB5 86 CAS_n/A15 230 NC 125 VSS 269 DQ55

162 VSS 57 VSS 201 CB3 95 DQ36 239 VSS 134 VSS 278 DQS7_t

163 DQS1_c 58 RESET_n 202 VSS 96 VSS 240 DQ37 135 DQ62 279 VSS

_t 59 VDD 203 CKE1 97 DQ32 241 VSS 136 VSS 280 DQ63

173 VSS 68 A8 212 VDD 106 DQ44 250 VSS

174 DQS2_c 69 A6 213 A5 107 VSS 251 DQ45

_t 70 VDD 214 A4 108 DQ40 252 VSS

TDQS12_t,

DQS12_t

TDQS12_c,

DQS12_c

TDQS17_t,

DQS17_t

TDQS17_c,

DQS17_c

184 VSS 78 EVENT_n 222 PARITY 117 DQ52 261 VSS

185 DQS3_c 79 A0 223 VDD 118 VSS 262 DQ53

_t 80 VDD 224 BA1 119 DQ48 263 VSS

_n/A16 226 VDD 121

TDQS15_t,

DQS15_t

TDQS15_c,

DQS15_c

265 VSS

266 DQS6_c

195 VSS 89 S1_n 233 VDD 128 DQ60 272 VSS

196 DQS8_c 90 VDD 234 A17 129 VSS 273 DQ61

_t 91 ODT1 235 NC,C2 130 DQ56 274 VSS

_n,NC 237 NC,CS3_c,C1 132

TDQS13_t,

DQS13_t

_n 206 VDD 100

_n 102 DQ38 246 VSS 141 SCL 285 SDA

_n 209 VDD 103 VSS 247 DQ39 142 VPP 286 VPP

TDQS13_c,

DQS13_c

TDQS14_t,

DQS14_t

TDQS14_c,

DQS14_c

243 VSS 138 VSS 282 DQ59

244 DQS4_c 139 SA0 283 VSS

_t 140 SA1 284 VDDSPD

254 VSS

255 DQS5_c

TDQS16_t,

DQS16_t

TDQS16_c,

DQS16_c

276 VSS

277 DQS7_c

VPP

NOTE:

1. VPP is 2.5V DC

2. Pin 230 is defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pin 230 is defined as SAVE_n for NVDIMMs.

3. Pins 1 and 145 are defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pins 1 and 145 are defined as 12V for Hybrid /NVDIMM

4. The 5th VPP is required on all modules. DIMMs.

- 5 -

Page 6

Rev. 1.41

Thermal sensor

SA0 SA1 SA2

SCL

EVENT_nEVENT_n

SCL

SDASDA

Serial PD with

SA0 SA1 SA2

VSSZQCAL

SCL

SDA

SA0

SA1

SA2

Registered DIMM

datasheet DDR4 SDRAM

5. Pin Description

Pin Name Description Pin Name Description

A0–A17

BA0, BA1 Register bank select input SDA I

BG0, BG1 Register bank group select input SA0–SA2 I

RAS_n

CAS_n

WE_n

CS0_n, CS1_n,

CS2_n, CS3_n

CKE0, CKE1 Register clock enable lines input VSS Power supply return (ground)

ODT0, ODT1 Register on-die termination control lines input VDDSPD Serial SPD/TS positive power supply

ACT_n Register input for activate input ALERT_n Register ALERT_n output

DQ0–DQ63 DIMM memory data bus RESET_n Set Register and SDRAMs to a Known State

CB0–CB7 DIMM ECC check bits EVENT_n SPD signals a thermal event has occurred

DQS0_t– DQS17_t

DQS0_c– DQS17_c

CK0_t, CK1_t

CK0_c, CK1_c

2C serial bus data line for SPD/TS and register

2C slave address select for SPD/TS and register

DIMM Rank Select Lines input VREFCA SDRAM command/address reference supply

Data Buffer data strobes (positive line of differential pair)

Data Buffer data strobes (negative line of differential pair)

VTT

RFU Reserved for future use

SDRAM I/O termination supply

NOTE :

1. Address A17 is only valid for 16 Gb x4 based SDRAMs.

2. RAS_n is a multiplexed function with A16.

3. CAS_n is a multiplexed function with A15.

4. WE_n is a multiplexed function with A14.

6. ON DIMM Thermal Sensor

NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM

[ Table 1 ] Temperature Sensor Characteristics

Grade Range

75 < Ta < 95 - +/- 0.5 +/- 1.0

40 < Ta < 125 - +/- 1.0 +/- 2.0 -

-20 < Ta < 125 - +/- 2.0 +/- 3.0 -

Resolution 0.25 C /LSB -

Temperature Sensor Accuracy

Min. Typ . Max.

- 6 -

Units NOTE

C

Page 7

Rev. 1.41

Registered DIMM

datasheet DDR4 SDRAM

7. Input/Output Functional Description

Symbol Type Function

CK0_t, CK0_c,

CK1_t, CK1_c

CKE0, CKE1 Input

CS0_n, CS1_n,

CS2_n, CS3_n

C0, C1, C2 Input

ODT0, ODT1 Input

ACT_n Input

RAS_n/A16. CAS_n/A15.

WE_n/A14

BG0 - BG1 Input

BA0 - BA1 Input

A0 - A17 Input

A10 / AP Input

A12 / BC_n Input

RESET_n

DQS0_t-DQS17_t,

DQS0_c-DQS17_c

PAR Input

ALERT_n

RFU Reserved for Future Use: No on DIMM electrical connection is present

NC No Connect: No on DIMM electrical connection is present

Input

CMOS

Input

Input/

Output

Input/

Output

Output (Input)

Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and output drivers. Taking CKE LOW provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh.

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection. CS_n is considered part of the command code.

Chip ID : Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of stacked component. Chip ID is considered part of the command code.

On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c, TDQS_t and TDQS_c signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.

Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14

Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being entered. Those pins have multi function. For example, for activation with ACT_n Low, these are Addresses like A16, A15 and A14 but for non-activation command with ACT_n High, these are Command pins for Read, Write and other command defined in command truth table

Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write or Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle.

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle.

Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions. See other rows. The address inputs also provide the op-code during Mode Register Set commands. A17 is only defined for 16 Gb x4 SDRAM configurations.

Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.

Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst chop (on-thefly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation.

Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor specific data sheets to determine which DQ is used.

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS_t is paired with differential signals DQS_c, respectively, to provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended.

Command and Address Parity Input: DDR4 Supports Even Parity check in SDRAMs with MR setting. Once it’s enabled via Register in MR5, then SDRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A0. Input parity should be maintained at the rising edge of the clock and at the same time with command & address with CS_n LOW

Alert : It has multi functions such as CRC error flag, Command and Address Parity error flag as Output signal. If there is error in CRC, then ALERT_n goes LOW for the period time interval and goes back HIGH. If there is error in Command Address Parity Check, then ALERT_n goes LOW for relatively long period until on going SDRAM internal recovery transaction is complete. During Connectivity Test mode this pin functions as an input. Using this signal or not is dependent on the system. If the SDRAM ALERT_n pins are not connected to the ALERT_n pin on the edge connector is must still be connected to VDD on DIMM.

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Page 8

Rev. 1.41

Registered DIMM

Symbol Type Function

VDD

VSS Supply

VTT Supply

VPP Supply

VDDSPD Supply

VREFCA Supply

NOTE :

1. For PC4 VDD is 1.2V. For PC4L VDD is TBD.

Supply

Power Supply: 1.2 V ± 0.06 V

Ground

VDD/2

SDRAM Activating Power Supply: 2.5V ( 2.375V min, 2.75V max)

SPD and register supply voltage. Register requires the nominl volatge to be 2.5V ± 10%.

Reference voltage for CA

datasheet DDR4 SDRAM

- 8 -

Page 9

Rev. 1.41

Registered DIMM

datasheet DDR4 SDRAM

8. Registering Clock Driver Specification

8.1 Timing & Capacitance values

Symbol Parameter Conditions

fclock Input Clock Frequency application frequency 625 1080 625 1350 MHz

CH/tCL

ACT

PDM

DIS

Note:

1. This parameter does not include package capacitance

2. Data inputs are DCKE0/1, DODT0/1, DA0..DA17, DBA0..DBA1, DBG0..DBG1, DACT_n, DC0..DC2, DPAR, DCS0/1_n

Pulse duration, CK_t, CK_c HIGH or LOW

Inputs active time4 before DRST_n is taken HIGH

Propagation delay, single-bit switching, CK_t/ CK_c to output

output disable time

output enable time

Input capacitance, Data inputs

Input capacitance, CK_t, CK_c

Input capacitance, DRST_n

DCKE0/1 = LOW and DCS0/ 1_n = HIGH

1.2V Operation 1 1.3 1 1.3 ns

Rising edge of Yn_t to output float

Output valid to rising edge of Yn_t

1,2

NOTE

1,2

NOTE

or VSS ;

I=VDD

=1.2V

DDR4-1600/1866/2133 DDR4-2400/2666

Min Max Min Max

0.4 - 0.4 -

16 - 16 -

0.5*tCK +

tQSK1(min)

0.5*tCK -

tQSK1(max)

0.8 1.1 0.8 1.0

0.5 2.0 0.5 2.0

0.5*tCK +

tQSK1(min)

0.5*tCK -

tQSK1(max)

-ps

Units Notes

8.2 Clock driver Characteristics

Symbol Parameter Conditions

jit

(hper)

jit

dynoff

(cc)

STAB

CKsk

(per)

Qsk1

Cycle-to-cycle period jitter CK_t/CK_c stable 0

Stabilization time - 5 - 5 - 5 us

Clock Output skew - 10 - 10 - 10 ps

Yn Clock Period jitter

Half period jitter

Qn Output to clock tolerance

Maximum re-driven dynamic clock off-set

DDR4-1600/1866/

2133

Min Max Min Max Min Max

0.025 x tCK

-0.025 * tCK

-0.032 * tCK

-0.125 * tCK

0.025 * tCK

0.032 * tCK

0.125 * tCK

-50-45-45ps

DDR4-2400 DDR4-2666

-0.025 * tCK

-0.032 * tCK

-0.125 * tCK

0.025 x tCK

0.025 * tCK

0.032 * tCK

0.125 * tCK

-0.025 * tCK

-0.032 * tCK

-0.1 * tCK 0.1 * tCK ps

0.025 x tCK

0.025 * tCK

0.032 * tCK

Units Notes

- 9 -

Page 10

Rev. 1.41

DQS0_t

DQS0_c

DQ[3:0]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

CS_n

DQS1_t

DQS1_c

DQ[11:8]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

CS_n

DQS2_t

DQS2_c

DQ[19:16]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

CS_n

DQS3_t

DQS3_c

DQ[27:24]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

CS_n

DQS8_t

DQS8_c

CB[3:0]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

CS_n

DQS_t DQS_c

CKE

ODT

DQ[3:0]

CS_n

DQS_t DQS_c

CKE

ODT

DQ[3:0]

CS_n

DQS_t DQS_c

CKE

ODT

DQ[3:0]

CS_n

DQS_t DQS_c

CKE

ODT

DQ[3:0]

CS_n

DQS_t DQS_c

D10

CKE

ODT

DQ[3:0]

CS_n

DQS_t DQS_c

D15

CKE

ODT

DQ[3:0]

CS_n

DQS_t DQS_c

D16

CKE

ODT

DQ[3:0]

CS_n

DQS_t DQS_c

D17

CKE

ODT

DQ[3:0]

CS_n

DQS_t DQS_c

D18

CKE

ODT

DQ[3:0]

CS_n

DQS4_t

DQS4_c

DQ[35:32]

DQS_t DQS_c

D11

CKE

ODT

DQ[3:0]

CS_n

DQS5_t

DQS5_c

DQ[43:40]

DQS_t DQS_c

D12

CKE

ODT

DQ[3:0]

CS_n

DQS6_t

DQS6_c

DQ[51:48]

DQS_t DQS_c

D13

CKE

ODT

DQ[3:0]

CS_n

DQS7_t

DQS7_c

DQ[59:56]

DQS_t DQS_c

D14

CKE

ODT

DQ[3:0]

CS_n

QACS0_n

QAODT0 QACKE0

QBCS0_n

QBODT0 QBCKE0

VSS VSS VSSVSSVSS

VSS VSSVSSVSS

R E G

I S T E R

BA[1:0]

A[17:0]

ACT_n

PARITY

CKE0

RESET_n

QABA[1:0] -> BA[1:0] : SDRAMs D[10:1]

QAA[17:0] -> A[17:0] : SDRAMs D[10:1]

QAACT_n -> ACT_n : SDRAMs D[10:1]

QACKE0 -> CKE : SDRAMs D[10:1]

BG[1:0] QABG[1:0] -> BG[1:0] : SDRAMs D[10:1]

QBBA[1:0] -> BA[1:0] : SDRAMs D[18:11]

QBA[17:0] -> A[17:0] : SDRAMs D[18:11]

QBACT_n -> ACT_n : SDRAMs D[18:11]

QAPAR -> PAR : SDRAMs D[10:1] QBPAR -> PAR : SDRAMs D[18:11]

QBCKE0 -> CKE : SDRAMs D[18:11]

Y0_c -> CK_c : SDRAMs D[18:11] Y1_c -> CK_c : SDRAMs D[10:1]

QRST_n -> RESET_n : All SDRAMs

CK0_c

ODT0

CK0_t

Y0_t -> CK_t : SDRAMs D[18:11] Y1

-> CK_t : SDRAMs D[10:1]

QBBG[1:0] -> BG[1:0] : SDRAMs D[18:11]

CK1_c

CK1_t

CS0_n

ALERT_n

ERROR_IN_n -> ALERT_n : All SDRAMs

QAODT0 -> ODT : SDRAMs D[10:1] QBODT0 -> ODT : SDRAMs D[18:11]

QACS0_n -> CS_n : SDRAMs D[10:1] QBCS0_n -> CS_n : SDRAMs D[18:11]

D1 - D18

DDSPD

Serial PD

REFCA

NOTE :

1. Unless otherwise noted, resistor values are 15 5%.

2. See the Net Structure diagrams for all resistors associated with the command, address and control bus.

3. ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram.

Thermal sensor

SA0 SA1 SA2

SCL

EVENT_nEVENT_n

SCL

SDASDA

Serial PD with

SA0 SA1 SA2

VSSZQCAL

SCL

SDA

SA0

SA1

SA2

D1 - D18

DQS9_t

DQS9_c

DQ[7:4]

DQS10_t

DQS10_c

DQ[15:12]

DQS11_t

DQS11_c

DQ[23:20]

DQS12_t

DQS12_c

DQ[31:28]

DQS17_t

DQS17_c

CB[7:4]

DQS13_t

DQS13_c DQ[39:36]

DQS14_t

DQS14_c DQ[47:44]

DQS15_t

DQS15_c DQ[55:52]

DQS16_t

DQS16_c DQ[63:60]

Registered DIMM

datasheet DDR4 SDRAM

9. Function Block Diagram:

9.1 8GB, 1Gx72 Module (Populated as 1 rank of x4 DDR4 SDRAMs)

- 10 -

Page 11

Rev. 1.41

DQS0_t DQS0_c

DM0

DQS_t DQS_c

CKE

ODT

240

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS_t DQS_c

D10

CKE

ODT

IO IO IO IO IO IO IO IO

240

DQS1_t DQS1_c

DM1

DQS_t DQS_c

CKE

ODT

240

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS_t DQS_c

D11

CKE

ODT

IO IO IO IO IO IO IO IO

240

DQS2_t DQS2_c

DM2

DQS_t DQS_c

CKE

ODT

240

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS_t DQS_c

D12

CKE

ODT

IO IO IO IO IO IO IO IO

240

DQS3_t DQS3_c

DM3

DQS_t DQS_c

CKE

ODT

240

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS_t DQS_c

D13

CKE

ODT

IO IO IO IO IO IO IO IO

240

DQS8_t DQS8_c

DM8

DQS_t DQS_c

CKE

ODT

RCS0

240

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DQS_t DQS_c

D14

CKE

ODT

IO IO IO IO IO IO IO IO

RCS1

RCKE0 RCKE1 RODT0 RODT1

240

DQS7_t DQS7_c

DM7

DQS_t DQS_c

CKE

ODT

240

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS_t DQS_c

D18

CKE

ODT

IO IO IO IO IO IO IO IO

240

DQS6_t DQS6_c

DM6

DQS_t DQS_c

CKE

ODT

240

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS_t DQS_c

D17

CKE

ODT

IO IO IO IO IO IO IO IO

240

DQS5_t DQS5_c

DM5

DQS_t DQS_c

CKE

ODT

240

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS_t DQS_c

D16

CKE

ODT

IO IO IO IO IO IO IO IO

240

DQS4_t DQS4_c

DM4

DQS_t DQS_c

CKE

ODT

240

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS_t DQS_c

D15

CKE

ODT

IO IO IO IO IO IO IO IO

240

Registered DIMM

datasheet DDR4 SDRAM

9.2 8GB, 1Gx72 Module (Populated as 2 ranks of x8 DDR4 SDRAMs)

- 11 -

Page 12

Rev. 1.41

R E G

I S T E R

BA[1:0]

A[16:0]

ACT_n

PARITY

CKE0

CKE1

RESET_n

BA[1:0]A -> BA[1:0] : SDRAMs D[5:1], D[14:10]

A[16:0]A -> A[16:0] : SDRAMs D[5:1], D[14:10]

ACTA_n -> ACT_n : SDRAMs D[5:1], D[14 :10]

PARA -> PAR : SDRAMs D[5:1], D[14:10]

CKE1A -> CKE : SDRAMs D[14:10]

BG[1:0] BG[1:0]A -> BG[1:0] : SDRAMs D[5:1], D[14:10]

BA[1:0]B -> BA[1:0] : SDRAMs D[9:6], D[18:15]

A[16:0]B -> A[16:0] : SDRAMs D[9:6], D[18:15]

ACTB_n -> ACT_n : SDRAMs D[9:6], D[18 :15]

PARB -> PAR : SDRAMs D[9:6], D[18:15]

CKE0A -> CKE : SDRAMs D[5:1] CKE0B -> CKE : SDRAMs D[9:6]

CKE1B -> CKE : SDRAMs D[18:15]

Y0_c -> CK_c : SDRAMs D[9:6] Y1_c -> CK_c : SDRAMs D[5:1]

QRST_n -> RESET_n : All SDRAMs

CK0_c

ODT0

CK0_t

Y0_t -> CK_t : SDRAMs D[9:6] Y1

-> CK_t : SDRAMs D[5:1]

BG[1:0]B -> BG[1:0] : SDRAMs D[9:6], D[18:15]

CK1_c

CK1_t

CS0_n

ALERT_n

ERROR_IN_n <- ALERT_n : All SDRAMs

ODT0A -> ODT : SDRAMs D[5:1] ODT0B -> ODT : SDRAMs D[9:6]

CS0B_n -> CS_n : SDRAMs D[9:6]

D1 - D18

DDSPD

Serial PD

REFCA

Thermal sensor

SA0 SA1 SA2

SCL

EVENT_n

SCL

SDASDA

Serial PD with

SA0 SA1 SA2

VSSZQCAL

SCL

SDA

SA0

SA1

SA2

D1 - D18

ODT1

ODT1A -> ODT : SDRAMs D[14:10] ODT1B -> ODT : SDRAMs D[18:15]

CS0A_n -> CS_n : SDRAMs D[5:1]

CS1_n

CS1B_n -> CS_n : SDRAMs D[18:15]

CS1A_n -> CS_n : SDRAMs D[14:10]

-> CK_t : SDRAMs D[18:15]

-> CK_t : SDRAMs D[14:10]

Y2_c -> CK_c : SDRAMs D[18:15] Y3_c -> CK_c : SDRAMs D[14:10]

NOTE :

1. Unless otherwise noted, resistor values are 15 5%.

2. See the Net Structure diagrams for all resistors associated with the command, address and control bus.

3. ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram.

Registered DIMM

datasheet DDR4 SDRAM

- 12 -

Page 13

Rev. 1.41

DQS0_t

DQS0_c

DQ[3:0]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

DQS1_t

DQS1_c

DQ[11:8]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

DQS2_t

DQS2_c

DQ[19:16]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

DQS3_t

DQS3_c

DQ[27:24]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D16

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D17

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D18

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D19

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D11

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D12

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D13

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D14

CKE

ODT

DQ[3:0]

DQS9_t

DQS9_c

DQ[7:4]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

DQS10_t

DQS10_c

DQ[15:12]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

DQS11_t

DQS11_c

DQ[23:20]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

DQS12_t

DQS12_c

DQ[31:28]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

QACS0

QAODT0 QACKE0

VSS VSSVSSVSS

NOTE :

1. Unless otherwise noted, resistor values are 15 5%.

2. See the Net Structure diagrams for all resistors associated with the command, address and control bus.

3. ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram.

Thermal sensor

SA0 SA1 SA2

SCL

EVENT_nEVENT_n

SCL

SDASDA

Serial PD with

SA0 SA1 SA2

VSSZQCAL

SCL

SDA

SA0

SA1

SA2

QACS1

QAODT1 QACKE1

DQS8_t

DQS8_c

CB[3:0]

DQS_t DQS_c

D10

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D20

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D15

CKE

ODT

DQ[3:0]

DQS17_t

DQS17_c

CB[7:4]

DQS_t DQS_c

CKE

ODT

DQ[3:0]

VSS

D1 - D36

DDSPD

Serial PD

REFCA

D1 - D36

Registered DIMM

datasheet DDR4 SDRAM

9.3 16GB, 2Gx72 Module (Populated as 2 ranks of x4 DDR4 SDRAMs)

- 13 -

Page 14

Rev. 1.41

DQS4_t

DQS4_c

DQ[35:32]

DQS_t DQS_c

D25

CKE

ODT

DQ[3:0]

DQS5_t

DQS5_c

DQ[43:40]

DQS_t DQS_c

D26

CKE

ODT

DQ[3:0]

DQS6_t

DQS6_c

DQ[51:48]

DQS_t DQS_c

D27

CKE

ODT

DQ[3:0]

DQS7_t

DQS7_c

DQ[59:56]

DQS_t DQS_c

D28

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D33

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D34

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D35

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D36

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D29

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D30

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D31

CKE

ODT

DQ[3:0]

DQS_t DQS_c

D32

CKE

ODT

DQ[3:0]

DQS13_t

DQS13_c

DQ[39:36]

DQS_t DQS_c

D21

CKE

ODT

DQ[3:0]

DQS14_t

DQS14_c

DQ[47:44]

DQS_t DQS_c

D22

CKE

ODT

DQ[3:0]

DQS15_t

DQS15_c

DQ[55:52]

DQS_t DQS_c

D23

CKE

ODT

DQ[3:0]

DQS16_t

DQS16_c

DQ[63:60]

DQS_t DQS_c

D24

CKE

ODT

DQ[3:0]

QBCS0_n

QBODT0 QBCKE0

VSS VSSVSSVSS

QBCS1_n

QBODT1 QBCKE1

R E G

I S T E R

BA[1:0]

A[17:0]

ACT

C[2:0]

PARITY

CKE0

CKE1

RESET

QABA[1:0] -> BA[1:0] : SDRAMs D[20:1]

QAA[17:0] -> A[17:0] : SDRAMs D[20:1]

QAACT_n -> ACT_n : SDRAMs D[20:1]

QAC[2:0] -> C[2:0] : SDRAMs D[20:1]

QACKE0 -> CKE : SDRAMs D[10:1]

BG[1:0] QABG[1:0] -> BG[1:0] : SDRAMs D[20:1]

QBBA[1:0] -> BA[1:0] : SDRAMs D[36:21]

QBA[17:0] -> A[17:0] : SDRAMs D[36:21]

QBACT_n -> ACT_n : SDRAMs D[36:21]

QBC[2:0] -> C[2:0] : SDRAMs D[36:21]

QAPAR -> PAR : SDRAMs D[20:1] QBPAR -> PAR : SDRAMs D[36:21]

QBCKE0 -> CKE : SDRAMs D[28:21]

-> CK_c : SDRAMs D[24:21], D[32:29]

-> CK_c: SDRAMs D[5:1], D[15:11]

QRST

-> RESET_n : All SDRAMs

CK0

ODT0

QACKE1 -> CKE : SDRAMs D[20:11] QBCKE1 -> CKE : SDRAMs D[36:29]

CK0

Y0_t -> CK_t : SDRAMs D[24:21], D[32:29] Y1

-> CK_t : SDRAMs D[5:1], D[15:11]

QBBG[1:0] -> BG[1:0] : SDRAMs D[36:21]

CK1

ODT1

CS0

CS1

ALERT

ERROR_IN_n -> ALERT_n : All SDRAMs

QAODT0 -> ODT : SDRAMs D[10:1] QBODT0 -> ODT : SDRAMs D[28:21] QAODT1 -> ODT : SDRAMs D[20:11] QBODT1 -> ODT : SDRAMs D[36:29]

QACS0_n -> CS_n : SDRAMs D[10:1] QBCS0_n -> CS_n : SDRAMs D[28:21]

QACS1_n -> CS_n : SDRAMs D[20:11] QBCS1_n -> CS_n : SDRAMs D[36:29]

-> CK_t : SDRAMs D[28:25], D[36:33]

-> CK_t : SDRAMs D[10:6], D[20:16]

-> CK_c : SDRAMs D[28:25], D[36:33]

-> CK_c : SDRAMs D[10:6], D[20:16]

Registered DIMM

datasheet DDR4 SDRAM

- 14 -

Page 15

Rev. 1.41

Registered DIMM

datasheet DDR4 SDRAM

10. Absolute Maximum Ratings

10.1 Absolute Maximum DC Ratings

[ Table 2 ] Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

VDD Voltage on VDD pin relative to Vss -0.3 ~ 1.5 V 1,3

VDDQ Voltage on VDDQ pin relative to Vss -0.3 ~ 1.5 V 1,3

VPP Voltage on VPP pin relative to Vss -0.3 ~ 3.0 V 4

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV

4. VPP must be equal or greater than VDD/VDDQ at all times.

Voltage on any pin except VREFCA to Vss -0.3 ~ 1.5 V 1,3

IN, VOUT

Storage Temperature -55 to +100 °C 1,2

STG

11. AC & DC Operating Conditions

11.1 Recommended DC Operating Conditions

[ Table 3 ] Recommended DC Operating Conditions

Symbol Parameter

VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3

VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3

VPP Peak-to-Peak Voltage 2.375 2.5 2.75 V 3

NOTE:

1. Under all conditions V

2. V

tracks with VDD. AC parameters are measured with VDD and V

DDQ

3. DC bandwidth is limited to 20MHz.

must be less than or equal to VDD.

DDQ

Min. Typ. Max.

tied together.

DDQ

Rating

Unit NOTE

- 15 -

Page 16

Rev. 1.41

voltage

time

Registered DIMM

datasheet DDR4 SDRAM

12. AC & DC Input Measurement Levels

12.1 AC & DC Logic Input Levels for Single-Ended Signals

[ Table 4 ] Single-ended AC & DC Input Levels for Command and Address

Symbol Parameter

IH.CA(DC75) DC input logic high VREFCA+ 0.075 VDD TBD TBD V

IL.CA(DC75) DC input logic low VSS VREFCA-0.075 TBD TBD V

IH.CA(AC100) AC input logic high VREF + 0.1 Note 2 TBD TBD V 1

IL.CA(AC100) AC input logic low Note 2 VREF - 0.1 TBD TBD V 1

REFCA(DC) Reference Voltage for ADD, CMD inputs 0.49*VDD 0.51*VDD TBD TBD V 2,3

NOTE :

1. See “Overshoot and Undershoot Specifications” on section.

2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV)

3. For reference : approx. VDD/2 ± 12mV

12.2 AC and DC Input Measurement Levels : V

The DC-tolerance limits and ac-noise limits for the reference voltages V

function of time. (V

(DC) is the linear average of V

REF

Furthermore V

stands for V

REF

(t) may temporarily deviate from V

REF

REFCA

(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table X.

REF

(DC) by no more than ± 1% VDD.

REF

DDR4-1600/1866/2133/2400 DDR4-2666

Min. Max. Min. Max.

Tolerances.

REF

is illustrated in Figure 1. It shows a valid reference voltage V

REFCA

Unit NOTE

REF

(t) as a

Figure 1. Illustration of V

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on V

" shall be understood as V

REF

This clarifies, that DC-variations of V

which setup and hold is measured. System timing and voltage budgets need to account for V

data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

and voltage effects due to AC-noise on V

(DC), as defined in Figure 1.

REF

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

REF

up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

REF

(DC) tolerance and V

REF

- 16 -

AC-noise limits

REF

(DC) deviations from the optimum position within the

REF

AC-noise. Timing

REF

Page 17

Rev. 1.41

0.0

tDVAC

.DIFF.MIN

half cycle

Differential Input Voltage (CK-CK)

time

tDVAC

VIH.DIFF.AC.MIN

.DIFF.MAX

.DIFF.AC.MAX

(CK_t - CK_c)

Registered DIMM

datasheet DDR4 SDRAM

12.3 AC and DC Logic Input Levels for Differential Signals

12.3.1 Differential Signals Definition

Figure 2. Definition of differential ac-swing and “time above ac-level” t

NOTE :

1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.

2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.

DVAC

12.3.2 Differential Swing Requirements for Clock (CK_t - CK_c)

[ Table 5 ] Differential AC and DC Input Levels

Symbol Parameter

IHdiff

ILdiff

(AC)

IHdiff

(AC)

ILdiff

NOTE:

1. Used to define a differential signal slew-rate.

2. for CK_t - CK_c use V

3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (V

as well as the limitations for overshoot and undershoot.

differential input high +0.150 NOTE 3 TBD NOTE 3 V 1

differential input low NOTE 3 -0.150 NOTE 3 TBD V 1

differential input high ac

2 x (VIH(AC) - V

differential input low ac NOTE 3

IH.CA/VIL.CA

(AC) of ADD/CMD and V

[ Table 6 ] Allowed Time Before Ringback (tDVAC) for CK_t - CK_c

Slew Rate [V/ns]

> 4.0 120 -

4.0 115 -

3.0 110 -

2.0 105 -

1.8 100 -

1.6 95 -

1.4 90 -

1.2 85 -

1.0 80 -

< 1.0 80 -

DDR4 -1600/1866/2133 DDR4 -2400/2666

min max min max

REFCA

REF

)

NOTE 3

2 x (VIL(AC) - V

;

2 x (VIH(AC) - V

)

REF

tDVAC [ps] @ |V

min max

NOTE 3

IH.CA

(AC)| = 200mV

IH/Ldiff

)

REF

2 x (VIL(AC) - V

(DC) max, V

unit NOTE

NOTE 3 V 2

)

REF

(DC)min) for single-ended signals

IL.CA

- 17 -

Page 18

Rev. 1.41

VDD or V

DDQ

SEH

min

/2 or V

DDQ

SEL

max

SEH

VSS or V

SSQ

SEL

time

Registered DIMM

datasheet DDR4 SDRAM

12.3.3 Single-ended Requirements for Differential Signals

Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals.

CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle.

Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK_c

Figure 3. Single-ended requirement for differential signals.

Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.

[ Table 7 ] Single-ended Levels for CK_t, CK_c

Symbol Parameter

SEH

SEL

NOTE :

1. For CK_t - CK_c use V

(AC)/VIL(AC) for ADD/CMD is based on V

2. V

3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (V

signals as well as the limitations for overshoot and undershoot.

Single-ended high-level for CK_t , CK_c (VDD/2)+0.100 NOTE3 TBD NOTE3 V 1, 2

Single-ended low-level for CK_t , CK_c NOTE3 (VDD/2)-0.100 NOTE3 TBD V 1, 2

IH.CA/VIL.CA

(AC) of ADD/CMD;

;

REFCA

DDR4-1600/1866/2133 DDR4-2400/2666

Min Max Min Max

(DC) max, V

IH.CA

IL.CA

Unit NOTE

(DC)min) for single-ended

- 18 -

Page 19

Rev. 1.41

Delta TRdiff

Delta TFdiff

IHdiffmin

ILdiffmax

Differential Input Voltage(i,e, CK_t - CK_c)

Registered DIMM

datasheet DDR4 SDRAM

12.4 Slew Rate Definitions

12.4.1 Slew Rate Definitions for Differential Input Signals ( CK )

[ Table 8 ] Differential Input Slew Rate Definition

Description

Differential input slew rate for rising edge(CK_t - CK_c)

Differential input slew rate for falling edge(CK_t - CK_c)

NOTE: The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.

from to

ILdiffmax

IHdiffmin

ILdiffmax

Defined by



IHdiffmin - VILdiffmax



IHdiffmin - VILdiffmax



DeltaTRdiff



DeltaTFdiff

Figure 4. Differential Input Slew Rate Definition for CK_t, CK_c

- 19 -

Page 20

Rev. 1.41

Vix

CK_t

VDD/2

VSS

VDD

CK_c

Vix

VSEL

VSEH

Registered DIMM

datasheet DDR4 SDRAM

12.5 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in Table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS.

Figure 5. Vix Definition (CK)

[ Table 9 ] Cross Point Voltage for Differential Input Signals (CK)

Symbol Parameter

- Area of VSEH, VSEL

VlX(CK)

Symbol Parameter

- Area of VSEH, VSEL TBD TBD TBD TBD

VlX(CK)

Differential Input Cross Point Voltage relative to

VDD/2 for CK_t, CK_c

Differential Input Cross Point Voltage relative to

VDD/2 for CK_t, CK_c

VSEL =< VDD/2 -

145mV

-120mV

TBD TBD TBD TBD

min max

DDR4-1600/1866/2133

VDD/2 - 145mV =<

VSEL =< VDD/2 -

100mV

-(VDD/2 - VSEL) + 25mV

DDR4-2400/2666

VDD/2 + 100mV

=< VSEH =< VDD/

2 + 145mV

(VSEH - VDD/2) -

25mV

VDD/2 + 145mV

=< VSEH

120mV

- 20 -

Page 21

Rev. 1.41

OH(AC)

OL(AC)

delta TRsedelta TFse

VTT

Registered DIMM

datasheet DDR4 SDRAM

12.6 Single-ended AC & DC Output Levels

[ Table 10 ] Single-ended AC & DC Output Levels

Symbol Parameter DDR4-1600/1866/2133/2400/2666 Units NOTE

(DC) DC output high measurement level (for IV curve linearity) 1.1 x V

(DC) DC output mid measurement level (for IV curve linearity) 0.8 x V

(DC) DC output low measurement level (for IV curve linearity) 0.5 x V

(AC) AC output high measurement level (for output SR) (0.7 - 0.15) x V

(AC) AC output low measurement level (for output SR) (0.7 - 0.15) x V

NOTE :

1. The swing of ± 0.15 × V load of 50

Ω to V

is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test

DDQ

= V

DDQ

12.7 Differential AC & DC Output Levels

[ Table 11 ] Differential AC & DC Output Levels

Symbol Parameter DDR4-1600/1866/2133/2400/2666 Units NOTE

(AC) AC differential output high measurement level (for output SR) +0.3 x V

OHdiff

(AC) AC differential output low measurement level (for output SR) -0.3 x V

OLdiff

NOTE :

1. The swing of ± 0.3 × V

Ω to V

of 50

= V

DDQ

is based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load

DDQ

at each of the differential outputs.

12.8 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V single ended signals as shown in Table 12 and Figure 6.

[ Table 12 ] Single-ended Output Slew Rate Definition

Description

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

NOTE :

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

Figure 6. Single-ended Output Slew Rate Definition

Measured

From To

(AC) VOH(AC) [VOH(AC)-VOL(AC)] / Delta TRse

(AC) VOL(AC) [VOH(AC)-VOL(AC)] / Delta TFse

Defined by

OL(AC)

and V

OH(AC)

for

- 21 -

Page 22

Rev. 1.41

OHdiff

(AC)

OLdiff

(AC)

delta TRdiffdelta TFdiff

VTT

Registered DIMM

datasheet DDR4 SDRAM

[ Table 13 ] Single-ended Output Slew Rate

Parameter Symbol

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Min Max Min Max Min Max Min Max Min Max

Units

Single ended output slew rate SRQse 4 9 4 9 4 9 4 9 4 9 V/ns

Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting

NOTE :

1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.

-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the

same byte lane are static (i.e. they stay at either high or low).

-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the

same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 9 V/ns applies

12.9 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table 14 and Figure 7.

[ Table 14 ] Differential Output Slew Rate Definition

Description

Differential output slew rate for rising edge

Differential output slew rate for falling edge

NOTE :

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

OLdiff

OHdiff

Measured

From To

(AC) V

OHdiff

OLdiff

(AC) [V

OHdiff

(AC)-V

Defined by

(AC)] / Delta TRdiff

OLdiff

(AC)] / Delta TFdiff

OLdiff

Figure 7. Differential Output Slew Rate Definition

[ Table 15 ] Differential Output Slew Rate

Parameter Symbol

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666

Min Max Min Max Min Max Min Max Min Max

Units

Differential output slew rate SRQdiff 8 18 8 18 8 18 8 18 8 18 V/ns

Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals

For Ron = RZQ/7 setting

- 22 -

Page 23

Rev. 1.41

VOH(AC)

TR_output_CT

VTT

VOL(AC)

TR_output_CT

DDQ

CT_INPUTS

DUT

DQ, DM

DQSU_t , DQSU_c DQS_t , DQS_c

Rterm = 50 ohm

Timing Reference Points

SSQ

DQSL_t , DQSL_c

0.5*VDDQ

Registered DIMM

datasheet DDR4 SDRAM

12.10 Single-ended AC & DC Output Levels of Connectivity Test Mode

Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test Mode.

[ Table 16 ] Single-ended AC & DC Output Levels of Connectivity Test Mode

Symbol Parameter DDR4-1600/1866/2133/2400/2666 Unit Notes

OH(DC)

OM(DC)

OL(DC)

OB(DC)

OH(AC)

OL(AC)

NOTE :

1. The effective test load is 50Ω terminated by VTT = 0.5 * VDDQ.

DC output high measurement level (for IV curve linearity)

DC output mid measurement level (for IV curve linearity) 0.8 x VDDQ V

DC output low measurement level (for IV curve linearity) 0.5 x VDDQ V

DC output below measurement level (for IV curve linearity) 0.2 x VDDQ V

AC output high measurement level (for output SR) VTT + (0.1 x VDDQ) V 1

AC output below measurement level (for output SR)

1.1 x VDDQ V

VTT - (0.1 x VDDQ) V 1

Figure 8. Output Slew Rate Definition of Connectivity Test Mode

[ Table 17 ] Single-ended Output Slew Rate of Connectivity Test Mode

Parameter Symbol

Output signal Falling time TF_output_CT - 10 ns/V

Output signal Rising time TR_output_CT - 10 ns/V

DDR4-1600/1866/2133/2400/2666

Min Max

Unit Notes

12.11 Test Load for Connectivity Test Mode Timing

The reference load for ODT timings is defined in Figure 7.

Figure 9. Connectivity Test Mode Timing Reference Load

- 23 -

Page 24

Rev. 1.41

Registered DIMM

datasheet DDR4 SDRAM

13. DIMM IDD Specification Definition

[ Table 18 ] Basic IDD, IPP and IDDQ Measurement Conditions

Symbol Description

Operating One Bank Active-Precharge Current (AL=0)

IDD0

IDD0A

IPP0

IDD1

IDD1A

IPP1

IDD2N

IDD2NA

IPP2N

IDD2NT

IDDQ2NT (Optional)

IDD2NL

IDD2NG

IDD2ND

IDD2N_par

IDD2P

IPP2P

IDD2Q

CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern; BL: 8 between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: VDDQ; DM_n:

stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Operating One Bank Active-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD0

Operating One Bank Active-Precharge IPP Current Same condition with IDD0

Operating One Bank Active-Read-Precharge Current (AL=0)

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern; BL: 8

between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling; DM_n: sta-

ble at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Operating One Bank Active-Read-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD1

Operating One Bank Active-Read-Precharge IPP Current Same condition with IDD1

Precharge Standby Current (AL=0)

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 8 Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks

closed; Output Buffer and RTT: Enabled in Mode Registers for detail pattern

Precharge Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD2N

Precharge Standby IPP Current Same condition with IDD2N

Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 8 Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks

closed; Output Buffer and RTT: Enabled in Mode Registers Datasheet for detail pattern

Precharge Standby ODT IDDQ Current

Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current

Precharge Standby Current with CAL enabled

Same definition like for IDD2N, CAL enabled

Precharge Standby Current with Gear Down mode enabled

Same definition like for IDD2N, Gear Down mode enabled

Precharge Standby Current with DLL disabled

Same definition like for IDD2N, DLL disabled

Precharge Standby Current with CA parity enabled

Same definition like for IDD2N, CA parity enabled

Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 8 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;

Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

Precharge Power-Down IPP Current Same condition with IDD2P

Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 8 Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet

; ODT Signal: toggling according ; Pattern Details: Refer to Component

3,5

; ODT Signal: stable at 0

; AL: 0; CS_n: stable at 1; Command,

; ODT Signal: stable at 0

; AL: 0; CS_n: stable at 1; Command,

; AL: 0; CS_n: High

; ODT

; AL:

;

- 24 -

Page 25

Rev. 1.41

Registered DIMM

Symbol Description

Active Standby Current

IDD3N

IDD3NA

IPP3N

IDD3P

IPP3P

IDD4R

IDD4RA

IDD4RB

IPP4R

IDDQ4R

(Optional)

IDDQ4RB (Optional)

IDD4W

IDD4WA

IDD4WB

IDD4WC

IDD4W_par

IPP4W

IDD5B

IPP5B

IDD5F2

IPP5F2

open; Output Buffer and RTT: Enabled in Mode Registers for detail pattern

Active Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD3N

Active Standby IPP Current Same condition with IDD3N

Active Power-Down Current CKE: Low; External clock: On; tCK, CL: sRefer to Component Datasheet for detail pattern; BL: 8 Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers

Active Power-Down IPP Current Same condition with IDD3P

Operating Burst Read Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 8 Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different

data between one burst and the next one according ; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers Component Datasheet for detail pattern

Operating Burst Read Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4R

Operating Burst Read Current with Read DBI Read DBI enabled

Operating Burst Read IPP Current Same condition with IDD4R

Operating Burst Read IDDQ Current

Same definition like for IDD4R, however measuring IDDQ current instead of IDD current

Operating Burst Read IDDQ Current with Read DBI

Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current

Operating Burst Write Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 8 Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different

data between one burst and the next one ; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers Datasheet for detail pattern

Operating Burst Write Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4W

Operating Burst Write Current with Write DBI Write DBI enabled

Operating Burst Write Current with Write CRC Write CRC enabled

Operating Burst Write Current with CA Parity CA Parity enabled

Operating Burst Write IPP Current Same condition with IDD4W

Burst Refresh Current (1X REF) CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern; BL: 8 REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC ; Output Buffer and RTT: Enabled in Mode Registers

Refer to Component Datasheet for detail pattern

Burst Refresh Write IPP Current (1X REF) Same condition with IDD5B

Burst Refresh Current (2X REF) tRFC=tRFC_x2, Other conditions: see IDD5B

Burst Refresh Write IPP Current (2X REF) Same condition with IDD5F2

, Other conditions: see IDD4R

, Other conditions: see IDD4W

datasheet DDR4 SDRAM

; ODT Signal: stable at 0; Pattern Details:Refer to Component Datasheet

; ODT Signal: stable at 0

; AL: 0; CS_n: stable at 1; Command,

; AL: 0; CS_n: High between RD;

; ODT Signal: stable at 0; Pattern Details: Refer to

; AL: 0; CS_n: High between WR;

; ODT Signal: stable at HIGH; Pattern Details: Refer to Component

; AL: 0; CS_n: High between

; ODT Signal: stable at 0; Pattern Details:

- 25 -

Page 26

Rev. 1.41

Registered DIMM

datasheet DDR4 SDRAM

Symbol Description

IDD5F4

IPP5F4

Burst Refresh Current (4X REF) tRFC=tRFC_x4, Other conditions: see IDD5B

Burst Refresh Write IPP Current (4X REF) Same condition with IDD5F4

Self Refresh Current: Normal Temperature Range

IDD6N

CASE

to Component Datasheet for detail pattern; BL: 8

; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO:

: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal

High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers LEVEL

IPP6N

IDD6E

IPP6E

Self Refresh IPP Current: Normal Temperature Range Same condition with IDD6N

Self-Refresh Current: Extended Temperature Range

: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended

CASE

Refer to Component Datasheet for detail pattern; BL: 8 IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode

Registers

; ODT Signal: MID-LEVEL

)

; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address, Data

Self Refresh IPP Current: Extended Temperature Range Same condition with IDD6E

Self-Refresh Current: Reduced Temperature Range

IDD6R

IPP6R

CASE

to Component Datasheet for detail pattern; BL: 8 High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: MID-LEVEL

Self Refresh IPP Current: Reduced Temperature Range Same condition with IDD6R

; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO:

: 0 - 45°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer

Auto Self-Refresh Current

IDD6A

CASE

Component Datasheet for detail pattern; BL: 8

; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO:

: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer to

High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers MID-LEVEL

IPP6A

Auto Self-Refresh IPP Current Same condition with IDD6A

Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern; BL: 8

IDD7

CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM_n: stable at 1; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers Details: Refer to Component Datasheet for detail pattern

IPP7

Operating Bank Interleave Read IPP Current Same condition with IDD7

IDD8 Maximum Power Down Current TBD

IPP8 Maximum Power Down IPP Current Same condition with IDD8

NOTE :

1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].

2. Output Buffer Enable

- set MR1 [A12 = 0] : Qoff = Output buffer enabled

- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7

RTT_Nom enable

- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6

RTT_WR enable

- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2

RTT_PARK disable

- set MR5 [A8:6 = 000]

3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s

010] : 1866MT/s, 2133MT/s 011] : 2400MT/s, 2666MT/s Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate DLL disabled : set MR1 [A0 = 0] CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s 010] : 2400MT/s, 2666MT/s Read DBI enabled : set MR5 [A12 = 1] Write DBI enabled : set :MR5 [A11 = 1]

4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal

01] : Reduced Temperature range 10] : Extended Temperature range 11] : Auto Self Refresh

5. IDD2NG should be measured after sync pules(NOP) input.

; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer

; ODT Signal: MID-

; CKE: Low; External clock: Off; CK_t and CK_c: LOW; CL:

; ODT Signal:

; AL:

; ODT Signal: stable at 0; Pattern

- 26 -

Page 27

Rev. 1.41

Registered DIMM

datasheet DDR4 SDRAM

14. IDD SPEC Table

IDD and IPP values are for typical operating range of voltage and temperature unless otherwise noted.

[ Table 19 ] I

and I

Symbol

DD0

DD0A

DD1

DD1A

DD2N

DD2NA

DD2NT

DD2NL

DD2NG

DD2ND

DD2N_par

DD2P

DD2Q

DD3N

DD3NA

DD3P

DD4R

DD4RA

DD4RB

DD4W

DD4WA

DD4WB

DD4WC

DD4W_par

DD5B

DD5F2

DD5F4

DD6N

DD6E

DD6R

DD6A

DD7

DD8

Specification

DDQ

8GB(1Gx72) Module

M393A1G40EB1

M393A1G40EB2

DDR4-2133 DDR4-2400 DDR4-2666

15-15-15 17-17-17 19-19-19

VDD 1.2V VPP 2.5 VDD 1.2V VPP 2.5 VDD 1.2V VPP 2.5

IDD Max. IPP Max. IDD Max. IPP Max. IDD Max. IPP Max.

879 72 893 72 914 72 mA

900 72 926 72 950 72 mA

1135 54 1153 54 1195 54 mA

1177 54 1201 54 1249 54 mA

658 54 676 54 675 54 mA

660 54 678 54 687 54 mA

688 54 715 54 729 54 mA

586 54 603 54 624 54 mA

662 54 680 54 693 54 mA

631 54 645 54 662 54 mA

669 54 686 54 694 54 mA

442 54 450 54 463 54 mA

638 54 653 54 670 54 mA

828 54 849 54 862 54 mA

830 54 850 54 868 54 mA

532 54 541 54 562 54 mA

1673 54 1769 54 1877 54 mA

1735 54 1841 54 1967 54 mA

1695 54 1793 54 1912 54 mA

1610 54 1719 54 1860 54 mA

1676 54 1795 54 1947 54 mA

1610 54 1719 54 1865 54 mA

1526 54 1591 54 1650 54 mA

1720 54 1856 54 1992 54 mA

3660 324 3683 324 3726 342 mA

3111 270 3132 270 3205 288 mA

2430 198 2456 198 2534 252 mA

301 72 300 72 318 72 mA

427 72 427 72 431 90 mA

237 72 236 72 241 72 mA

291 72 290 72 298 72 mA

3379 162 3702 162 4184 252 mA

142 36 141 36 146 54 mA

Unit NOTE

NOTE :

1. DIMM IDD SPEC is based on the condition that de-actived rank(IDLE) is IDD2N. Please refer to Table20.

2. IDD current measure method and detail patterns are described on DDR4 component datasheet.

3. VDD and VDDQ are merged on module PCB ( IDDQ values are not considered by Qoff condition)

4. DIMM IDD Values are calculated based on the component IDD spec and Register power.

- 27 -

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Rev. 1.41

Registered DIMM

Symbol

DD0

DD0A

DD1

DD1A

DD2N

DD2NA

DD2NT

DD2NL

DD2NG

DD2ND

DD2N_par

DD2P

DD2Q

DD3N

DD3NA

DD3P

DD4R

DD4RA

DD4RB

DD4W

DD4WA

DD4WB

DD4WC

DD4W_par

DD5B

DD5F2

DD5F4

DD6N

DD6E

DD6R

DD6A

DD7

DD8

datasheet DDR4 SDRAM

M393A1G43EB1:

8GB(1Gx72) Module

DDR4-2133 DDR4-2400 DDR4-2666

15-15-15 17-17-17 19-19-19

VDD 1.2V VPP 2.5 VDD 1.2V VPP 2.5 VDD 1.2V VPP 2.5

IDD Max. IPP Max. IDD Max. IPP Max. IDD Max. IPP Max.

748 63 763 63 810 63 mA

759 63 780 63 828 63 mA

941 54 955 54 1008 54 mA

962 54 980 54 1036 54 mA

638 54 655 54 667 54 mA

640 54 657 54 699 54 mA

668 54 695 54 702 54 mA

568 54 584 54 616 54 mA

641 54 659 54 685 54 mA

611 54 625 54 633 54 mA

649 54 665 54 677 54 mA

426 54 435 54 449 54 mA

617 54 632 54 641 54 mA

786 54 806 54 853 54 mA

789 54 808 54 871 54 mA

505 54 514 54 531 54 mA

1293 54 1353 54 1435 54 mA

1322 54 1391 54 1480 54 mA

1306 54 1370 54 1453 54 mA

1182 54 1246 54 1334 54 mA

1215 54 1283 54 1388 54 mA

1181 54 1246 54 1343 54 mA

1139 54 1179 54 1281 54 mA

1237 54 1316 54 1419 54 mA

2183 189 2204 189 2347 189 mA

1909 162 1929 162 2036 162 mA

1570 126 1592 126 1693 126 mA

286 72 281 72 306 72 mA

410 72 405 72 427 72 mA

224 72 218 72 224 72 mA

277 72 272 72 287 72 mA

1763 108 1782 108 1956 108 mA

129 36 124 36 129 36 mA

Unit NOTE

NOTE :

1. DIMM IDD SPEC is based on the condition that de-actived rank(IDLE) is IDD2N. Please refer to Table20.

2. IDD current measure method and detail patterns are described on DDR4 component datasheet.

3. VDD and VDDQ are merged on module PCB ( IDDQ values are not considered by Qoff condition)

4. DIMM IDD Values are calculated based on the component IDD spec and Register power.

- 28 -

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Rev. 1.41

Registered DIMM

Symbol

DD0

DD0A

DD1

DD1A

DD2N

DD2NA

DD2NT

DD2NL

DD2NG

DD2ND

DD2N_par

DD2P

DD2Q

DD3N

DD3NA

DD3P

DD4R

DD4RA

DD4RB

DD4W

DD4WA

DD4WB

DD4WC

DD4W_par

DD5B

DD5F2

DD5F4

DD6N

DD6E

DD6R

DD6A

DD7

DD8

datasheet DDR4 SDRAM

16GB(2Gx72) Module

M393A2G40EB1 M393A2G40EB2

DDR4-2133 DDR4-2400 DDR4-2666

15-15-15 17-17-17 19-19-19

VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V

IDD Max. IPP Max. IDD Max. IPP Max. IDD Max. IPP Max.

1292 126 1308 126 1347 126 mA

1313 126 1341 126 1383 126 mA

1579 108 1609 108 1668 108 mA

1621 108 1657 108 1722 108 mA

1112 108 1132 108 1159 108 mA

1075 108 1095 108 1161 108 mA

1130 108 1170 108 1185 108 mA

927 108 945 108 975 108 mA

1079 108 1099 108 1114 108 mA

1017 108 1030 108 1051 108 mA

1093 108 1111 108 1175 108 mA

563 108 571 108 578 108 mA

1030 108 1045 108 1107 108 mA

1410 108 1435 108 1507 108 mA

1414 108 1439 108 1520 108 mA

743 108 752 108 756 108 mA

2116 108 2225 108 2351 108 mA

2178 108 2297 108 2440 108 mA

2138 108 2249 108 2386 108 mA

2054 108 2175 108 2334 108 mA

2120 108 2251 108 2420 108 mA

2054 108 2175 108 2338 108 mA

1970 108 2047 108 2224 108 mA

2164 108 2312 108 2465 108 mA

4104 378 4139 378 4199 396 mA

3554 324 3588 324 3679 342 mA

2873 252 2911 252 3007 306 mA

590 144 590 144 592 144 mA

843 144 843 144 856 180 mA

463 144 463 144 467 144 mA

571 144 569 144 571 144 mA

3823 216 4159 216 4659 306 mA

284 72 283 27 288 108 mA

Unit NOTE

NOTE :

1. DIMM IDD SPEC is based on the condition that de-actived rank(IDLE) is IDD2N. Please refer to Table20.

2. IDD current measure method and detail patterns are described on DDR4 component datasheet.

3. VDD and VDDQ are merged on module PCB ( IDDQ values are not considered by Qoff condition)

4. DIMM IDD Values are calculated based on the component IDD spec and Register power.

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Registered DIMM

[ Table 20 ] DIMM Rank Status

SEC DIMM Operating Rank The other Rank

DD0

DD1

DD2P

DD2N

DD2Q

DD3P

DD3N

DD4R

DD4W

DD5B

DD6

DD7

DD8

DD0

DD1

DD2P

DD2N

DD2Q

DD3P

DD3N

DD4R

DD4W

DD5B

DD6

DD7

DD8

datasheet DDR4 SDRAM

DD2N

DD2P

DD2N

DD2Q

DD3P

DD3N

DD2N

DD6

DD2N

DD8

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datasheet DDR4 SDRAM

15. Input/Output Capacitance

[ Table 21 ] Silicon Pad I/O Capacitance

Symbol Parameter

DIO

DDQS

DCK

DI_ CTRL

DI_ ADD_CMD

ALERT

TEN Input capacitance of TEN 0.2 2.3 0.2 2.3 pF 1,3,13

NOTE:

1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is validated by de-embedding the package L & C

parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all other signal pins floating. Measurement procedure tbd.

2. DQ, DM_n, DQS_T, DQS_c, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions, the loading matches DQ and DQS

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4. Absolute value CK_T-CK_C

5. Absolute value of CIO(DQS_T)-CIO(DQS_c)

6. CI applies to ODT, CS_n, CKE, A0-A17, BA0-BA1, BG0-BG1, RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.

7. CDI CTRL applies to ODT, CS_n and CKE

8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C))

9. CDI_ADD_ CMD applies to, A0-A17, BA0-BA1, BG0-BG1,RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.

10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C))

11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_c))

12. Maximum external load capacitance on ZQ pin: tbd pF.

13.TEN pin may be DRAM internally pulled low through a weak pull-down resistor to VSS. In this case C

specific information.

Input/output capacitance delta DQS_t and DQS_c - 0.05 - 0.05 pF

Input capacitance(CTRL, ADD, CMD pins only) 0.2 0.8 0.2 0.7 pF

Input capacitance delta(All CTRL pins only) -0.1 0.1 -0.1 0.1 pF

Input capacitance delta(All ADD/CMD pins only) -0.1 0.1 -0.1 0.1 pF

Input/output capacitance 0.55 1.4 0.55 1.15 pF 1,2,3

Input/output capacitance delta -0.1 0.1 -0.1 0.1 pF

Input capacitance, CK_t and CK_c 0.2 0.8 0.2 0.7 pF

Input capacitance delta CK_t and CK_c - 0.05 - 0.05 pF

Input/output capacitance of ALERT 0.5 1.5 0.5 1.5 pF

Input/output capacitance of ZQ 0.5 2.3 0.5 2.3 pF

DDR4-1600/1866/2133 DDR4-2400/2666

min max min max

TEN might not be valid and system shall verify TEN signal with Vendor

Unit NOTE

1,2,3,11

1,2,3,5

1,3

1,3,4

1,3,6

1,3,7,8

1,2,9,10

1,3

1,3,12

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datasheet DDR4 SDRAM

16. Electrical Characterisitics and AC Timing

16.1 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

[ Table 22 ] DDR4-1600 Speed Bins and Operations

Speed Bin DDR4-1600

Unit NOTECL-nRCD-nRP 11- 11-11

Parameter Symbol min max

Internal read command to first data tAA

Internal read command to first data with read DBI enabled tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 11

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to PRE command period tRAS 35 9 x tREFI ns 11

ACT to ACT or REF command period tRC

Normal Read DBI

CWL = 9

CWL = 9,11

CL = 9 CL = 11 tCK(AVG)

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4

CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3

Supported CL Settings 9,11,12 nCK 12,13

Supported CL Settings with read DBI 11,13,14 nCK 12

Supported CWL Settings 9,11 nCK

13.75

(13.50)

13.75

(13.50)

13.75

(13.50)

48.75

(48.50)

1.5

(Optional)

5,11

18.00 ns 11

- ns 11

1.6 ns 1,2,3,4,10,13

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[ Table 23 ] DDR4-1866 Speed Bins and Operations

Speed Bin DDR4-1866

Parameter Symbol min max

Internal read command to first data tAA

Internal read command to first data with read DBI enabled tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 11

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to PRE command period tRAS 34 9 x tREFI ns 11

ACT to ACT or REF command period tRC

Normal Read DBI

CWL = 9

CWL = 9,11

CWL = 10,12

CL = 9 CL = 11 tCK(AVG)

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) Reserved ns 4

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,6

CL = 12 CL = 14 tCK(AVG) Reserved ns 1,2,3,4

CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3

Supported CL Settings 9,11,12,13,14 nCK 12,13

Supported CL Settings with read DBI 11,13,14,15,16 nCK 12

Supported CWL Settings 9,10,11,12 nCK

datasheet DDR4 SDRAM

Unit NOTECL-nRCD-nRP 13-13-13

13.92

5,11

(13.50)

13.92

5,11

(13.50)

13.92

5,11

(13.50)

47.92

5,11

(47.50)

1.5

(Optional)

5,11

1.25 <1.5

(Optional)

18.00 ns 11

- ns 11

1.6 ns 1,2,3,4,10,13

5,11

ns 1,2,3,4,6

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[ Table 24 ] DDR4-2133 Speed Bins and Operations

Speed Bin DDR4-2133

Parameter Symbol min max

Internal read command to first data tAA

Internal read command to first data with read DBI

enabled

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to PRE command period tRAS 33 9 x tREFI ns 11

ACT to ACT or REF command period tRC

Normal Read DBI

CWL = 9

CWL = 9,11

CWL = 10,12

CWL = 11,14

CL = 9 CL = 11 tCK(AVG)

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,10

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,7

CL = 13 CL = 15 tCK(AVG)

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,7

CL = 14 CL = 17 tCK(AVG) Reserved ns 1,2,3,4

CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4

CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3

Supported CL Settings 9,11.12,13,14,15,16 nCK 12,13

Supported CL Settings with read DBI 11,13,14,15,16,18,19 nCK

Supported CWL Settings 9,10,11,12,14 nCK

datasheet DDR4 SDRAM

Unit NOTECL-nRCD-nRP 15-15-15

14.06

5,11

(13.75)

tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 11

14.06

5,11

(13.75)

14.06

5,11

(13.75)

47.06

5,11

(46.75)

1.5

(Optional)

5,11

1.25 <1.5

(Optional)

1.071 <1.25

(Optional)

5,11

18.00 ns 11

- ns 11

1.6 ns

1,2,3,4,10,1

ns 1,2,3,4,7

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[ Table 25 ] DDR4-2400 Speed Bins and Operations

Speed Bin DDR4-2400

Parameter Symbol min max

Internal read command to first data tAA

Internal read command to first data with read DBI

enabled

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to PRE command period tRAS 32 9 x tREFI ns 11

ACT to ACT or REF command period tRC

Normal Read DBI

CWL = 9

CWL = 9,11

CWL = 10,12

CWL = 11,14

CWL = 12,16

CL = 9 CL = 11 tCK(AVG) Reserved ns 1,2,3,4,9

CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,4,9

CL = 10 CL = 12 tCK(AVG) Reserved ns 4

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,8

CL = 12 CL = 14 tCK(AVG) Reserved ns 4

CL = 13 CL = 15 tCK(AVG)

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,8

CL = 14 CL = 17 tCK(AVG) Reserved ns 4

CL = 15 CL = 18 tCK(AVG)

CL = 16 CL = 19 tCK(AVG) 0.938 <1.071 ns 1,2,3,8

CL = 15 CL = 18 tCK(AVG) Reserved ns 1,2,3,4

CL = 16 CL = 19 tCK(AVG) Reserved ns 1,2,3,4

CL = 17 CL = 20 tCK(AVG) 0.833 <0.937

CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3

Supported CL Settings 10,11,12,13,14,15,16,17,18 nCK 12,13

Supported CL Settings with read DBI 12,13,14,15,16,18,19,20,21 nCK

Supported CWL Settings 9,10,11,12,14,16 nCK

datasheet DDR4 SDRAM

Unit NOTECL-nRCD-nRP 17-17-17

14.16

5,11

(13.75)

tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 11

14.16

5,11

(13.75)

14.16

5,11

(13.75)

46.16

5,11

(45.75)

1.25 <1.5

(Optional)

1.071 <1.25 ns 1,2,3,4,8

(Optional)

0.938 <1.071 ns 1,2,3,4,8

(Optional)

5,11

18.00 ns 11

- ns 11

ns 1,2,3,4,8

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[ Table 26 ] DDR4-2666 Speed Bins and Operations

Speed Bin DDR4-2666

Parameter Symbol min max

Internal read command to first data tAA

Internal read command to first data with read DBI

ACT to internal read or write delay time tRCD

ACT to PRE command period tRAS 32 9 x tREFI ns 11

ACT to ACT or REF command period tRC

CWL = 9

CWL = 9,11

CWL = 10,12

CWL = 11,14

CWL = 12,16

CWL = 14.18

enabled

PRE command period tRP

Normal Read DBI

CL = 9 CL = 11 tCK(AVG) Reserved ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,10

CL = 10 CL = 12 tCK(AVG) Reserved ns 4

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,9

CL = 12 CL = 14 tCK(AVG) Reserved ns 4

CL = 13 CL = 15 tCK(AVG)

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,9

CL = 14 CL = 17 tCK(AVG) Reserved ns 4

CL = 15 CL = 18 tCK(AVG)

CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,9

CL = 15 CL = 18 tCK(AVG) Reserved ns 4

CL = 16 CL = 19 tCK(AVG) Reserved ns

CL = 17 CL = 20 tCK(AVG)

CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3

CL = 17 CL = 20 tCK(AVG) Reserved ns

CL = 18 CL = 21 tCK(AVG) Reserved ns

CL = 19 CL = 22 tCK(AVG) 0.75 <0.833 ns

CL = 20 CL = 23 tCK(AVG) 0.75 <0.833 ns 1,2,3

Supported CL Settings 10,11,12,13,14,15,16,17,18,19,20 nCK 12

Supported CL Settings with read DBI 12,13,14,15,17,18,19,20,21,22,23 nCK

Supported CWL Settings 9,10,11,12,14,16,18 nCK

datasheet DDR4 SDRAM

Unit NOTECL-nRCD-nRP 19-19-19

14.25

5,12

(13.75)

tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 11

14.25

5,12

(13.75)

14.25

5,12

(13.75)

46.25

5,12

(45.75)

1.25 <1.5

(Optional)

1.071 <1.25

(Optional)

0.937 <1.071

(Optional)

0.833 <0.937

(Optional)

5,12

18.00 ns 11

- ns 11

ns 1,2,3,4,9

1,2,3,4,9

1,2,3,4

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datasheet DDR4 SDRAM

16.2 Speed Bin Table Note

Absolute Specification

- VDDQ = VDD = 1.20V +/- 0.06 V

- VPP = 2.5V +0.25/-0.125 V

- The values defined with above-mentioned table are DLL ON case.

- DDR4-1600, 1866, 2133,2400 and 2666 Speed Bin Tables are valid only when Geardown Mode is disabled.

1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from

CL setting as well as requirements from CWL setting.

2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be

guaranteed. An application should use the next smaller JEDEC standard tCK(avg) value (1.5, 1.25, 1.071, 0.938 or 0.833 ns) when calculating CL [nCK] = tAA [ns] / tCK(avg) [ns], rounding up to the next ‘Supported CL’, where tAA = 12.5ns and tCK(avg) = 1.3 ns should only be used for CL = 10 calculation.

3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or

0.938 ns or 0.833 ns). This result is tCK(avg).MAX corresponding to CL SELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD

information if and how this setting is supported.

6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

7. Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

8. Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

9. Any DDR4-2666 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

10. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.

11. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables.

12. CL number in parentheses, it means that these numbers are optional.

13. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).

15. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to be JEDEC compliant. JEDEC compliance does not require support for

all speed bins within a given speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins.

- 37 -

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datasheet DDR4 SDRAM

17. Timing Parameters by Speed Grade

[ Table 27 ] Timing Parameters by Speed Bin for DDR4-1600 to DDR4-2666

Speed DDR4-1600 DDR4-1866 DDR4-213 3 DDR4-2400 DDR4-2666

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode)

Average Clock Period tCK(avg) 1.25 <1.5 1.071 <1.25 0.938 <1.071 0.833 <0.938 0.750 <0.833 ns 35,36

Average high pulse width tCH(avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK(avg)

Average low pulse width tCL(avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK(avg)

Absolute Clock Period tCK(abs)

Absolute clock HIGH pulse width tCH(abs) 0.45 - 0.45 - 0.45 - 0.45 - 0.45 - tCK(avg) 23

Absolute clock LOW pulse width tCL(abs) 0.45 - 0.45 - 0.45 - 0.45 - 0.45 - tCK(avg) 24

Clock Period Jitter- total JIT(per)_tot -63 63 -54 54 -47 47 -42 42 -38 38 ps 23

Clock Period Jitter- deterministic JIT(per)_dj -31 31 -27 27 -23 23 -21 21 -19 19 ps 26

Clock Period Jitter during DLL l ocking period

Cycle to Cycle Period Jitter tJIT(cc)_tota l - 125 - 107 - 94 - 83 - 75 ps 25

Cycle to Cycle Period Jitter deterministic tJIT(cc)_dj - 63 - 54 - 47 - 42 - 38 ps 26

Cycle to Cycle Period Jitter during DLL locking period

Duty Cycle Jitter tJIT(duty) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ps

Cumulative error across 2 cycles tERR(2per) -92 92 -79 79 -69 69 -61 61 -55 55 ps

Cumulative error across 3 cycles tERR(3per) -109 109 -94 94 -82 82 -73 73 -66 66 ps

Cumulative error across 4 cycles tERR(4per) -121 121 -104 104 -91 91 -81 81 -73 73 ps

Cumulative error across 5 cycles tERR(5per) -131 131 -112 112 -98 98 -87 87 -78 78 ps

Cumulative error across 6 cycles tERR(6per) -139 139 -119 119 -104 104 -92 92 -83 83 ps

Cumulative error across 7 cycles tERR(7per) -145 145 -124 124 -109 109 -97 97 -87 87 ps

Cumulative error across 8 cycles tERR(8per) -151 151 -129 129 -113 113 -101 101 -91 91 ps

Cumulative error across 9 cycles tERR(9per) -156 156 -134 134 -117 117 -104 104 -94 94 ps

Cumulative error across 10 cycles tERR(10per) -160 160 -137 137 -120 120 -107 107 -96 96 ps

Cumulative error across 11 cycles tERR(11per) -164 164 -141 141 -123 123 -110 110 -99 99 ps

Cumulative error across 12 cycles tERR(12per) -168 168 -144 144 -126 126 -112 112 -101 101 ps

Cumulative error across 13 cycles tERR(13per) -172 172 -147 147 -129 129 -114 114 -103 103 ps

Cumulative error across 14 cycles tERR(14per) -175 175 -150 150 -131 131 -116 116 -104 104 ps

Cumulative error across 15 cycles tERR(15per) -178 178 -152 152 -133 133 -118 118 -106 106 ps

Cumulative error across 16 cycles tERR(16per) -180 189 -155 155 -135 135 -120 120 -108 108 ps

Cumulative error across 17 cycles tERR(17per) -183 183 -157 157 -137 137 -122 122 -110 110 ps

Cumulative error across 18 cycles tERR(18per) -185 185 -159 159 -139 139 -124 124 -112 112 ps

Cumulative error across n = 13, 14 . . . 49, 50 cycles

Command and Address setup time to CK_t,

CK_c referenced to Vih(ac) / Vil(ac) levels

Command and Address setup time to CK_t, CK_c referenced to Vref levels

Command and Address hold time to CK_t, CK_c referenced to Vih(dc) / Vil(dc) levels

Command and Address hold time to CK_t, CK_c referenced to Vref levels

Control and Address Input pulse width for each input

Command and Address Timing

CAS_n to CAS_n command delay for same bank group

CAS_n to CAS_n command delay for different bank group

ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size

tCK

(DLL_OFF)

tJIT(per, lck) -50 50 -43 43 -38 38 -33 33 -30 30 ps

tJIT(cc, lck) - 100 - 86 - 75 - 67 - 60 ps

tERR(nper)

tIS(base) 115 - 100 - 80 - 62 - TBD - ps

tIS(Vref) 215 - 200 - 180 - 162 - TBD - ps

tIH(base)140-125-105- 87-TBD-ps

tIH(Vref) 215 - 200 - 180 - 162 - TBD - ps

tIPW 600-525-460-410-385- ps

tCCD_L

tCCD_S 4 - 4 - 4 - 4 - 4 - nCK 34

tRRD_S(2K)

8 20 8 20 8 20 8 20 8 20 ns -

tCK(avg)min + tJIT(per)min_tot

tCK(avg)m ax + tJIT(per)max_tot

ERR(nper)min = ((1 + 0.68ln(n)) * tJIT(per)_total min)

tERR(nper)max = ((1 + 0.68ln(n)) * tJIT(per)_total max)

max(5

nCK,

6.250 ns)

Max(4nC

K,6ns)

max(5

nCK,

5.355 ns)

Max(4nC

K,5.3ns)

max(5

nCK,

5.625 ns)

Max(4nC

K,5.3ns)

max(5

nCK, 5 ns)

Max(4nC

K,5.3ns)

max(5

nCK, 5 ns)

Max(4nC

K,5.3ns)

Units NOTE

tCK(avg)

-nCK34

- 38 -

Page 39

Rev. 1.41

Registered DIMM

Speed DDR4-1600 DDR4-1866 DDR4-213 3 DDR4-2400 DDR4-2666

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size

ACTIVATE to ACTIVATE Command delay to different bank group for 1/2KB page size

ACTIVATE to ACTIVATE Command delay to same bank group for 2KB page size

ACTIVATE to ACTIVATE Command delay to same bank group for 1KB page size

ACTIVATE to ACTIVATE Command delay to same bank group for 1/2KB page size

Four activate window for 2KB page size tFAW_2K

Four activate window for 1KB page size tFAW_1K

Four activate window for 1/2KB page size tFAW_1/2K

Delay from start of internal write transaction to internal read command for different bank group

Delay from start of internal write transaction to internal read command for same bank group

Internal READ Command to PRECHARGE Command delay

WRITE recovery time tWR 15 - 15 - 15 - 15 - 15 - ns 1

Write recovery time when CRC and DM are enabled

delay from start of internal writ e transaction to internal read command for different bank group with both CRC and DM enabled

delay from start of internal writ e transaction to internal read command for same bank group with both CRC and DM enabled

DLL locking time tDLLK 597 - 597 - 768 - 768 - 854 - nCK

Mode Register Set command cycle time tMRD 8 - 8 - 8 - 8 - 8 - nCK

Mode Register Set command update delay tMOD

Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - 1 - 1 - nCK 33

Multi Purpose Register Write Recovery Time

Auto precharge write recovery + precharge time

DQ0 or DQL0 driven to 0 set-up time to first DQS rising edge

DQ0 or DQL0 driven to 0 hold time from last DQS fall-ing edge

CS_n to Command Address Latency

CS_n to Command Address Latency tCAL 3 - 4 - 4 - 5 - 5 - nCK

Mode Register Set cyce time in CAL mode tMRD_tCAL

Mode Register Set update delay in CAL mode

DRAM Data Timing

DQS_t,DQS_c to DQ skew, per group, per access

DQ output hold per group, per access from DQS_t,DQS_c

Data Valid Window per device: (tQH - tDQSQ) of each UI on a given DRAM

Data Valid Window , per pin per UI : (tQH tDQSQ) each UI on a pin of a given DRAM

DQ low impedance time from CK_t, CK_c tLZ(DQ) -450 225 -390 195 -390 180 -330 175 -310 170 ps 39

DQ high impedance time from CK_t, CK_c tHZ(DQ) -225-195-180

Data Strobe Timing

tRRD_S(1K)

tRRD_S(1/2K)

tRRD_L(2K)

tRRD_L(1K)

tRRD_L(1/2K)

tWTR_S

tWTR_L

tRTP

tWR_CRC

_DM

tWTR_S_C

RC_DM

tWTR_L_C

RC_DM

tWR_MPR

tDAL(min) Programmed WR + roundup ( tRP / tCK(avg)) nCK

tPDA_S 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - UI 45,47

tPDA_H 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - UI 46,47

tMOD_tCAL

tDQSQ - 0.16 - 0.16 - 0.16 - 0.16 - 0.18

tQH 0.76 - 0.76 - 0.76 - 0.74 - 0.74 -

tDVWd 0.63 - 0.63 - 0.64 - 0.64 - TBD - UI

tDVWp 0.66 - 0.66 - 0.69 - 0.72 - 0.72 - UI

Max(4nC

K,5ns)

Max(4nC

K,5ns)

Max(4nC

K,7.5ns)

Max(4nC

K,6ns)

Max(4nC

K,6ns)

Max(28nC

K,35ns)

Max(20nC

K,25ns)

Max(16nC

K,20ns)

max(2nC

K,2.5ns)

max(4nC

K,7.5ns)

max(4nC

K,7.5ns)

tWR+max (4nCK,3.7

5ns)

tWTR_S+

max

(4nCK,3.7

5ns)

tWTR_L+

max

(4nCK,3.7

5ns)

max(24nC

K,15ns)

tMOD

(min)

+ AL + PL

datasheet DDR4 SDRAM

Units NOTE

Max(4nC

K,4.2ns)

Max(4nC

K,4.2ns)

Max(4nC

K,6.4ns)

Max(4nC

K,5.3ns)

Max(4nC

K,5.3ns)

Max(28nC

K,30ns)

Max(20nC

K,23ns)

Max(16nC

K,17ns)

max(2nC

K,2.5ns)

max(4nC

K,7.5ns)

max(4nC

K,7.5ns)

tWR+max

(5nCK,3.7

5ns)

tWTR_S+

max

(5nCK,3.7

5ns)

tWTR_L+

max

(5nCK,3.7

5ns)

max(24nC

K,15ns)

tMOD

(min)

+ AL + PL

Max(4nC

K,3.7ns)

Max(4nC

K,3.7ns)

Max(4nC

K,6.4ns)

Max(4nC

K,5.3ns)

Max(4nC

K,5.3ns)

Max(28nC

K,30ns)

Max(20nC

K,21ns)

Max(16nC

K,15ns)

max(2nC

K,2.5ns)

max(4nC

K,7.5ns)

max(4nC

K,7.5ns)

tWR+max

(5nCK,3.7

5ns)

tWTR_S+

max

(5nCK,3.7

5ns)

tWTR_L+

max

(5nCK,3.7

5ns)

max(24nC

K,15ns)

tMOD

(min)

+ AL + PL

Max(4nC

K,3.3ns)

Max(4nC

K,3.3ns)

Max(4nC

K,6.4ns)

Max(4nC

K,4.9ns)

Max(4nC

K,4.9ns)

Max(28nC

K,30ns)

Max(20nC

K,21ns)

Max(16nC

K,13ns)

max

(2nCK,

2.5ns)

max

(4nCK,7.5

ns)

max

(4nCK,7.5

ns)

tWR+max (5nCK,3.7

5ns)

tWTR_S+

max

(5nCK,3.7

5ns)

tWTR_L+

max

(5nCK,3.7

5ns)

max(24nC

K,15ns)

tMOD

(min)

+ AL + PL

tMOD+

tCAL

tMOD+

tCAL

Max(4nC

K,3ns)

Max(4nC

K,3ns)

Max(4nC

K,6.4ns)

Max(4nC

K,4.9ns)

Max(4nC

K,4.9ns)

Max(28nC

K,30ns)

Max(20nC

K,21ns)

Max(16nC

K,12ns)

max

(2nCK,

2.5ns)

max

(4nCK,7.5

ns)

max

(4nCK,7.5

ns)

tWR+max

(5nCK,3.7

5ns)

tWTR_S+

max

(5nCK,3.7

5ns)

tWTR_L+

max

(5nCK,3.7

5ns)

max(24nC

K,15ns)

tMOD

(min)

+ AL + PL

tMOD+

tCAL

tMOD+

tCAL

175 - 170 ps 39

-nCK34

-ns34

-ns

-ns1,34

-ns34

-ns1, 28

-ns

-nCK

tCK(avg)/213,18,3

tCK(avg)/213,17,1

1,2,e,3

2, 29,

3,30,

9,49

8,39,49

17,18,3

9,49

17,18,3

9,49

- 39 -

Page 40

Rev. 1.41

Registered DIMM

Speed DDR4-1600 DDR4-1866 DDR4-213 3 DDR4-2400 DDR4-2666

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

DQS_t, DQS_c different ial READ Preamble

DQS_t, DQS_c different ial READ Postamble

DQS_t,DQS_c differential output high time tQSH 0.4 - 0.4 - 0.4 - 0.4 - 0.4 - tCK 21,39

DQS_t,DQS_c differential output low time tQSL 0.4 - 0.4 - 0.4 - 0.4 - 0.4 - tCK 20,39

DQS_t, DQS_c differential WRITE Preamble

DQS_t, DQS_c differential WRITE Postamble

DQS_t and DQS_c low-impedance time (Referenced from RL-1)

DQS_t and DQS_c high-impedance time (Referenced from RL+BL/2)

DQS_t, DQS_c differential input low pulse width

DQS_t, DQS_c differential input high pulse width

DQS_t, DQS_c rising edge to CK_t, CK_c rising edge (1 clock preamble)

DQS_t, DQS_c falling edge setup time to CK_t, CK_c rising edge

DQS_t, DQS_c falling edge hold time from CK_t, CK_c rising edge

DQS_t, DQS_c rising edge output timing locatino from rising CK_t, CK_c with DLL On mode

DQS_t, DQS_c rising edge output variance window per DRAM

MPSM Timing

Command path disable delay upon MPSM entry

Valid clock requirement after MPSM entry tCKMPE

Valid clock requirement before MPSM exit tCKMPX

Exit MPSM to commands not requiring a locked DLL

Exit MPSM to commands requiring a locked DLL

CS setup time to CKE tMPX_S

Calibration Timing

Power-up and RESET calibration time tZQinit 1024 - 1024 - 1024 - 1024 - 1024 - nCK

Normal operation Full calibration time tZQoper 512 - 512 - 512 - 512 - 512 - nCK

Normal operation Short calibration time tZQCS 128 - 128 - 128 - 128 - 128 - nCK

Reset/Self Refresh Timing

Exit Reset from CKE HIGH to a valid command

Exit Self Refresh to commands not requiring a locked DLL

SRX to commands not requiring a locked DLL in Self Refresh ABORT

Exit Self Refresh to ZQCL,ZQCS and MRS (CL,CWL,WR,RTP and Gear Down)

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

tRPRE

tRPST 0.33 NOTE 45 0.33 NOTE 45 0.33

tWPRE

tWPST 0.33 - 0.33 - 0.33 - 0.33 - 0.33 - tCK

tLZ(DQS) -450 225 -390 195 -360 180 -330 175 -310 170 ps 39

tHZ(DQS) - 225 - 195 - 180 - 175 - 170 ps 39

tDQSL 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 tCK

tDQSH 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 tCK

tDQSS -0.27 0.27 -0.27 0.27 -0.27 0.27 -0.27 0.27 -0.27 0.27 tCK

tDSS 0.18 - 0.18 - 0.18 - 0.18 - 0.18 - tCK

tDSH 0.18 - 0.18 - 0.18 - 0.18 - 0.18 - tCK

tDQSCK (DLL On)

tDQSCKI (DLL On)

tMPED

tXMP tXS(min) - tXS(min) - tXS(min) - tXS(min) - TBD -

tXMPDLL

tXPR

tXS

tX-

S_ABORT(mi

tXS_FAST

(min)

tXSDLL

tCKESR

0.9 NOTE44 0.9 NOTE44 0.9 NOTE44 0.9

NA NA NA NA NA NA 1.8

0.9 - 0.9 - 0.9 - 0.9 - 0.9 - tCK 42

NA NA NA 1.8 - 1.8 - tCK 43

-225 225 -195 195 -180 180 -175 175 -170 170 ps

tMOD(min

tCP-

DED(min)

tMOD(min

tCP-

DED(min)

tCKSRX(

min)

tXMP(min

tXS-

DLL(min)

tIS(min) +

tIHL(min)

max (5nCK,tR FC(min)+

10ns)

tRFC(min)

+10ns

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

tDLLK(mi

tCKE(min)

+1nCK

datasheet DDR4 SDRAM

) +

NOTE

370 330 310 290 270 ps

tMOD(min

) +

tCP-

DED(min)

tMOD(min

) + tCP-

DED(min)

tCKSRX(

min)

tXMP(min

) +

tXS-

DLL(min)

tIS(min) +

tIHL(min)

max (5nCK,tR FC(min)+

10ns)

tRFC(min)

+10ns

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

tDLLK(mi

tCKE(min)

+1nCK

tMOD(min

) +

tCP-

DED(min)

tMOD(min

) +

tCP-

DED(min)

tCKSRX(

min)

tXMP(min

) +

tXS-

DLL(min)

tIS(min) +

tIHL(min)

max

(5nCK,tR

FC(min)+

10ns)

tRFC(min)

+10ns

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

tDLLK(mi

tCKE(min)

+1nCK

tMOD(min

DED(min)

tMOD(min

DED(min)

tCKSRX(

tXMP(min

DLL(min)

tIS(min) +

tIHL(min)

(5nCK,tR FC(min)+

10ns)

tRFC(min)

+10ns

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

tDLLK(mi

tCKE(min)

+1nCK

0.33

) +

tCP-

) +

tCP-

min)

) +

tXS-

max

NOTE

-TBD-

(5nCK,tR

FC(min)+

tRFC(min)

+10ns

tRFC4(mi

n)+10ns

tRFC4(mi

n)+10ns

tDLLK(mi

tCKE(min)

+1nCK

0.9

1.8

0.33

max

10ns)

NOTE

-nCK

Units NOTE

tCK 39,40

tCK 39,41

tCK 39

37,38,3

- 40 -

Page 41

Rev. 1.41

Registered DIMM

Speed DDR4-1600 DDR4-1866 DDR4-213 3 DDR4-2400 DDR4-2666

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Minimum CKE low width for Self refresh entry to exit timing with CA Parity enabled

Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE)

Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down when CA Parity is enabled

Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit Precharge Power Down with DLL frozen to commands n ot requiring a locked DLL

CKE minimum pulse width tCKE

Command pass disable delay tCPDED 4 - 4 - 4 - 4 - 4 - nCK

Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI nCK 6

Timing of ACT command to Power Down entry

Timing of PRE or PREA command to Power Down entry

Timing of RD/RDA command to Power Down entry

Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF)

Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF)

Timing of WR command to Power Down entry (BC4MRS)

Timing of WRA command to Power Down entry (BC4MRS)

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry

PDA Timing

Mode Register Set command cycle time in PDA mode

Mode Register Set command update del ay in PDA mode

ODT Timing

Asynchronous RTT turn-on delay (PowerDown with DLL frozen)

Asynchronous RTT turn-off delay (PowerDown with DLL frozen)

RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg)

Write Leveling Timing

First DQS_t/DQS_n rising edge after write leveling mode is programmed

DQS_t/DQS_n delay after write leveling mode is programmed

Write leveling setup time from rising CK_t, CK_c crossing to rising DQS_t/DQS_n crossing

Write leveling hold time from rising DQS_t/ DQS_n crossing to rising CK_t, CK_ crossing

Write leveling output delay

Write leveling output error tWLOE 0 2 0 2 0 2 0 2 0 2 ns

CA Parity Timing

Commands not guaranteed to be exe cuted during this time

Delay from errant command to ALERT_n assertion

tCKESR_ PAR

tCKSRE

tCKSRE_PAR

tCKSRX

tXP

tACTPDEN 1 - 1 - 2 - 2 - 2 - nCK 7

tPRPDEN1-1-2-2-2-nCK7

tRDPDEN RL+4+1 - RL+4+1 - RL+4+1 - RL+4+1 - RL+4+1 - nCK

tWRPDEN

tWRAPDEN

tWRP-

BC4DEN

tWRAP-

BC4DEN

tREFPDEN 1 - 1 - 2 - 2 - 2 - nCK 7

tMRSPDEN

tMRD_PDA

tMOD_PDA tMOD tMOD tMOD tMOD tMOD nCK

tAONAS 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 ns

tAOFAS 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 ns

tWLMRD 40 - 40 - 40 - 40 - 40 - nCK 12

tWLDQSEN 25 - 25 - 25 - 25 - 25 - nCK 12

tWLS 0.13 - 0.13 - 0.13 - 0.13 - 0.13 - tCK(avg)

tWLH 0.13 - 0.13 - 0.13 - 0.13 -0.13-tCK(avg)

tWLO 0 9.5 0 9.5 0 9.5 0 9.5 0 9.5 ns

tPAR_UN-

KNOWN

tPAR_ALERT

_ON

tCKE(min)

1nCK+PL

max(5nC

K,10ns)

max

(5nCK,10

ns)+PL

max(5nC

K,10ns)

max

(4nCK,6ns)-

max

(3nCK,

5ns)

WL+4+(t

WR/

tCK(avg))

WL+4+W

R+1

WL+2+(t

WR/

tCK(avg))

WL+2+W

R+1

tMOD(min

max(16nC

K,10ns)

datasheet DDR4 SDRAM

Units NOTE

)

- PL - PL - PL - PL -PLnCK

- PL+6ns - PL+6ns - PL+6ns - PL+6ns - PL+6ns nCK

tCKE(min)

1nCK+PL

max(5nC

K,10ns)

max

(5nCK,10

ns)+PL

max(5nC

K,10ns)

max

(4nCK,6ns)-

max

(3nCK,

5ns)

WL+4+(t

WR/

tCK(avg))

WL+4+W

R+1

WL+2+(t

WR/

tCK(avg))

WL+2+W

R+1

tMOD(min

)

max(16nC

K,10ns)

tCKE(min)

1nCK+PL

max(5nC

K,10ns)

max

(5nCK,10

ns)+PL

max(5nC

K,10ns)

max

(4nCK,6ns)-

max

(3nCK,

5ns)

WL+4+(t

WR/

tCK(avg))

WL+4+W

R+1

WL+2+(t

WR/

tCK(avg))

WL+2+W

R+1

tMOD(min

)

max(16nC

K,10ns)

tCKE(min)

1nCK+PL

max

(5nCK,10

ns)

max

(5nCK,10

ns)+PL

max

(5nCK,10

ns)

max

(4nCK,6ns)-

max

(3nCK,

5ns)

WL+4+(t

WR/

tCK(avg))

WL+4+W

R+1

WL+2+(t

WR/

tCK(avg))

WL+2+W

R+1

tMOD(min

)

max(16nC

K,10ns)

tCKE(min)

1nCK+PL

max

(5nCK,10

ns)

max

(5nCK,10

ns)+PL

max

(5nCK,10

ns)

max

(4nCK,6ns)-nCK

max

(3nCK,

5ns)

WL+4+(t

WR/

tCK(avg))

WL+4+W

R+1

WL+2+(t

WR/

tCK(avg))

WL+2+W

R+1

tMOD(min

)

max(16nC

K,10ns)

-nCK

- nCK 31,32

-nCK4

-nCK5

-nCK4

-nCK5

-nCK

- 41 -

Page 42

Rev. 1.41

Registered DIMM

Speed DDR4-1600 DDR4-1866 DDR4-213 3 DDR4-2400 DDR4-2666

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Pulse width of ALERT_n signal when asserted

Time from when Alert is asserted till controller must start providing DES comma nds in Persistent CA parity mode

Parity Latency PL 4 4 4 5 5 nCK

CRC Error Reporting

CRC error to ALERT_n latency tCRC_ALERT 3 13 3 13 3 13 3 13 3 13 ns

CRC ALERT_n pulse width

Geardown timing

Exit RESET from CKE HIGH to a valid MRS geardown (T2/Reset)

CKE High Assert to Gear Down Enable time(T2/CKE)

MRS command to Sync pulse time(T3)

Sync pulse to First valid command(T4)

Geardown setup time tGEAR_setup

Geardown hold time tGEAR_hold

tREFI

tRFC1 (min)

tRFC2 (min)

tRFC4 (min)

tPAR_ALERT

_PW

tPAR_ALERT

_RSP

CRC_ALERT_

tXPR_GEAR

tXS_GEAR

tSYNC_GEA

tCMD_GEAR

2Gb 160-160-160-160-160-ns34

4Gb 260-260-260-260-260-ns34

8Gb 350-350-350-350-350-ns34

16Gb 550 - 550 - 550 - 550 - 550 -ns34

2Gb 110 - 110 - 110 - 110 - 110 -ns34

4Gb 160-160-160-160-160-ns34

8Gb 260-260-260-260-260-ns34

16Gb 350 - 350 - 350 - 350 - 350 -ns34

2Gb 90 - 90 - 90 - 90 - 90 -ns34

4Gb 110 - 110 - 110 - 110 - 110 -ns34

8Gb 160-160-160-160-160-ns34

16Gb 260 - 260 - 260 - 260 - 260 - ns 34

datasheet DDR4 SDRAM

Units NOTE

48 96 56 112 64 128 72 144 80 160 nCK

- 43 - 50 - 57 - 64 71 nCK

6 10 6 10 6 10 6 10 6 10 nCK

- - - - - - - -

TBD

TBD - 27

TBD 27

2 - nCK

- 42 -

Page 43

Rev. 1.41

Registered DIMM

NOTE :

1. Start of internal write transaction is defined as follows : For BL8 (Fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL.

2. A separate timing parameter will cover the delay from write to read when CRC and DM are simultaneously enabled

3. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

4. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer.

5. WR in clock cycles as programmed in MR0.

6. tREFI depends on TOPER.

7. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be

applied until finishing those operations.

8. For these parameters, the DDR4 SDRAM device supports tnPARAM[nCK]=RU{tPARAM[ns]/tCK(avg)[ns]}, which is in clock cycles assuming all input clock jitter

specifications are satisfied

9. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.

10. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.

11. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L.

12. The max values are system dependent.

13. DQ to DQS total timing per group where the total includes the sum of deterministic and random timing terms for a specified BER. BER spec and measurement method are

tbd.

14. The deterministic component of the total timing. Measurement method tbd.

15. DQ to DQ static offset relative to strobe per group. Measurement method tbd.

16. This parameter will be characterized and guaranteed by design.

17. When the device is operated with the input clock jitter, this parameter needs to be derated by the actual tjit(per)_total of the input clock. (output deratings are relative to the

SDRAM input clock). Example tbd.

18. DRAM DBI mode is off.

19. DRAM DBI mode is enabled. Applicable to x8 and x16 DRAM only.

20. tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge

21. tQSH describes the instantaneous differential output high pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge

22. There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI

23. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge

24. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge

25. Total jitter includes the sum of deterministic and random jitter terms for a specified BER. BER target and measurement method are tbd.

26. The deterministic jitter component out of the total jitter. This parameter is characterized and gauranteed by design.

27. This parameter has to be even number of clocks

28. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.

29. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.

30. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L.

31. After CKE is registered LOW, CKE signal level shall be maintained below VILDC for tCKE specification ( Low pulse width ).

32. After CKE is registered HIGH, CKE signal level shall be maintained above VIHDC for tCKE specification ( HIGH pulse width ).

33. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

34. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables.

35. This parameter must keep consistency with Speed-Bin Tables .

36. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.

UI=tCK(avg).min/2

37. applied when DRAM is in DLL ON mode.

38. Assume no jitter on input clock signals to the DRAM

39. Value is only valid for RZQ/7 RONNOM = 34 ohms

40. 1tCK toggle mode with setting MR4:A11 to 0

41. 2tCK toggle mode with setting MR4:A11 to 1, which is valid for DDR4-2400/2666 speed grade.

42. 1tCK mode with setting MR4:A12 to 0

43. 2tCK mode with setting MR4:A12 to 1, which is valid for DDR4-2400/2666 speed grade.

44. The maximum read preamble is bounded by tLZ(DQS)min on the left side and tDQSCK(max) on the right side.

45. DQ falling signal middle-point of transferring from High to Low to first rising edge of DQS diff-signal cross-point

46. last falling edge of DQS diff-signal cross-point to DQ rising signal middle-point of transferring from Low to High

47. VrefDQ value must be set to either its midpoint or Vcent_DQ(midpoint) in order to capture DQ0 or DQL0 low level for entering PDA mode.

48. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side.

49. Reference level of DQ output signal is specified with a midpoint as a widest part of Output signal eye which should be approximately 0.7 * VDDQ as a center level of the

static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and an effective test load of 50 ohms to VTT = VDDQ.

datasheet DDR4 SDRAM

- 43 -

Page 44

Rev. 1.41

133.35

Units : Millimeters

0.85

0.25

E : 2.6

Detail B,E

Detail A

1.50 ± 0.05

0.6 ± 0.03

Detail C

31.25

30.75

17.60

126.65

4.30

B : 2.1

2.1

9.35

10.20

2.6

2.1

9.35

10.20

2.6

Detail D

56.1064.60 3.35

AC EDB

3.85 ± 0.10

1.4 ± 0.10

Max 1.4

The used device is 1G x4 DDR4 SDRAM, Flip-Chip. DDR4 SDRAM Part NO : K4A4G045WE-BC**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

Address, Command and Control lines

D18 D17 D16 D15 D10 D9 D8 D7 D6

D1 D2 D3 D4 D5 D11 D12 D13 D14

Registered DIMM

datasheet DDR4 SDRAM

18. Physical Dimensions

18.1 1Gx4 based 1Gx72 Module (1 Rank) -

M393A1G40EB1/M393A1G40EB2

18.1.1 x72 DIMM, populated as one physical rank of x4 DDR4 SDRAMs

- 44 -

Page 45

Rev. 1.41

133.35

Units : Millimeters

0.85

0.25

E : 2.6

Detail B,E

Detail A

1.50 ± 0.05

0.6 ± 0.03

Detail C

31.25

30.75

17.60

126.65

4.30

B : 2.1

2.1

9.35

10.20

2.6

2.1

9.35

10.20

2.6

Detail D

56.1064.60 3.35

AC EDB

3.85 ± 0.10

1.4 ± 0.10

Max 1.4

The used device is 512M x8 DDR4 SDRAM, Flip-Chip. DDR4 SDRAM Part NO : K4A4G085WE-BC**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

Address, Command and Control lines

D18 D17 D16 D15 D14 D13 D12 D11 D10

D1 D2 D3 D4 D5 D6 D7 D8 D9

Registered DIMM

datasheet DDR4 SDRAM

18.2 512Mx8 based 1Gx72 Module (2 Ranks) -

M393A1G43EB1

18.2.1 x72 DIMM, populated as two physical ranks of x8 DDR4 SDRAMs

- 45 -

Page 46

Rev. 1.41

133.35

Units : Millimeters

0.85

0.25

E : 2.6

Detail B,E

0.6 ± 0.03

Detail C

31.25

30.75

17.60

126.65

B : 2.1

2.1

9.35

10.20

2.6

2.1

9.35

10.20

2.6

Detail D

56.1064.60 3.35

E B

Detail A

1.50 ± 0.05

4.30

3.85 ± 0.10

1.4 ± 0.10

Max 1.4

The used device is 1G x4 DDR4 SDRAM, Flip-Chip. DDR4 SDRAM Part NO : K4A4G045WE-BC**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

Address, Command and Control lines

D1 D2 D4 D5 D21 D22 D23 D24

D6 D7 D8 D9 D10 D25 D26 D27 D28

D32 D31 D30 D29 D15

D14

D13 D12 D11

D36 D35 D34 D33 D20 D19 D18 D17 D16

Registered DIMM

datasheet DDR4 SDRAM

18.3 1Gbx4 based 2Gx72 Module (2 Ranks) -

M393A2G40EB1/M393A2G40EB2

18.3.1 x72 DIMM, populated as two physical ranks of x4 DDR4 SDRAMs

- 46 -

Samsung M393A2G40EB2-CTD User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. DDR4 Registered DIMM Ordering Information

2. Key Features

3. Address Configuration

4. Registered DIMM Pin Configurations (Front side/Back side)

5. Pin Description

6. ON DIMM Thermal Sensor

7. Input/Output Functional Description

8. Registering Clock Driver Specification

8.1 Timing & Capacitance values

8.2 Clock driver Characteristics

9. Function Block Diagram:

9.1 8GB, 1Gx72 Module (Populated as 1 rank of x4 DDR4 SDRAMs)

9.2 8GB, 1Gx72 Module (Populated as 2 ranks of x8 DDR4 SDRAMs)

9.3 16GB, 2Gx72 Module (Populated as 2 ranks of x4 DDR4 SDRAMs)

10. Absolute Maximum Ratings

10.1 Absolute Maximum DC Ratings

11. AC & DC Operating Conditions

11.1 Recommended DC Operating Conditions

12. AC & DC Input Measurement Levels

12.1 AC & DC Logic Input Levels for Single-Ended Signals

12.3 AC and DC Logic Input Levels for Differential Signals

12.3.1 Differential Signals Definition

12.3.2 Differential Swing Requirements for Clock (CK_t - CK_c)

12.3.3 Single-ended Requirements for Differential Signals

12.4 Slew Rate Definitions

12.4.1 Slew Rate Definitions for Differential Input Signals ( CK )

12.5 Differential Input Cross Point Voltage

12.6 Single-ended AC & DC Output Levels

12.7 Differential AC & DC Output Levels

12.8 Single-ended Output Slew Rate

12.9 Differential Output Slew Rate

12.10 Single-ended AC & DC Output Levels of Connectivity Test Mode

12.11 Test Load for Connectivity Test Mode Timing

13. DIMM IDD Specification Definition

14. IDD SPEC Table

15. Input/Output Capacitance

16. Electrical Characterisitics and AC Timing

16.1 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

16.2 Speed Bin Table Note

17. Timing Parameters by Speed Grade

18. Physical Dimensions

18.1.1 x72 DIMM, populated as one physical rank of x4 DDR4 SDRAMs

18.2.1 x72 DIMM, populated as two physical ranks of x8 DDR4 SDRAMs

18.3.1 x72 DIMM, populated as two physical ranks of x4 DDR4 SDRAMs