Samsung M393A2G40EB2-CTD User Manual

Rev. 1.41, Nov. 2016

M393A1G40EB1

M393A1G40EB2

M393A1G43EB1

M393A2G40EB1

M393A2G40EB2

288pin Registered DIMM based on 4Gb E-die

78FBGA with Lead-Free & Halogen-Free (RoHS compliant)

datasheet

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- 1 -

Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

Revision History

Revision No.	History	Draft Date	Remark	Editor
1.0	- First SPEC Release	19th Oct.2015	-	J.Y.Lee
1.1	- Change of IDD value on page 27~28	2nd Feb.2016	-	J.Y.Lee
	- Change of 8.1 Timing & Capacitance values (tACT) on page 9
	- Change of Physical Dimensions (Module Thickness) on page 41~43
1.2	- Addition of DDR4-2666	7th Apr.2016	-	J.Y.Lee
1.21	- Correction of Physical Dimensions on page 44~45	18th May.2016	-	J.Y.Lee
1.3	- Correction of Typo	10th Sep.2016	-	J.Y.Lee
	- Addition of IDD value on page 28~31
1.4	( M393A5143EB0-CRC, M393A5143EB1-CTD, M393A1G40EB2-CTD,	20th Sep.2016	-	J.Y.Lee
	M393A1G43EB1-CTD, M393A2G40EB2-CTD)
1.41	- Correction of Typo	2nd Nov.2016	-	J.Y.Lee

- 2 -

Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

Table Of Contents
288pin Registered DIMM based on 4Gb E-die
1. DDR4 Registered DIMM Ordering Information .............................................................................................................		4
2. Key Features.................................................................................................................................................................		4
3. Address Configuration ..................................................................................................................................................		4
4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................		5
5. Pin Description .............................................................................................................................................................		6
6. ON DIMM Thermal Sensor ...........................................................................................................................................		6
7. Input/Output Functional Description..............................................................................................................................		7
8. Registering Clock Driver Specification..........................................................................................................................		9
8.1 Timing & Capacitance values ..................................................................................................................................		9
8.2 Clock driver Characteristics.....................................................................................................................................		9
9. Function Block Diagram:...............................................................................................................................................		10
9.1 8GB, 1Gx72 Module (Populated as 1 rank of x4 DDR4 SDRAMs) .........................................................................		10
9.2 8GB, 1Gx72 Module (Populated as 2 ranks of x8 DDR4 SDRAMs) .......................................................................		11
9.3 16GB, 2Gx72 Module (Populated as 2 ranks of x4 DDR4 SDRAMs) .....................................................................		13
10. Absolute Maximum Ratings ........................................................................................................................................		15
10.1	Absolute Maximum DC Ratings.............................................................................................................................	15
11. AC & DC Operating Conditions...................................................................................................................................		15
11.1	Recommended DC Operating Conditions .............................................................................................................	15
12. AC & DC Input Measurement Levels ..........................................................................................................................		16
12.1	AC & DC Logic Input Levels for Single-Ended Signals .........................................................................................	16
12.2	AC and DC Input Measurement Levels : VREF Tolerances..................................................................................	16
12.3	AC and DC Logic Input Levels for Differential Signals ..........................................................................................	17
12.3.1. Differential Signals Definition .........................................................................................................................		17
12.3.2. Differential Swing Requirements for Clock (CK_t - CK_c) .............................................................................		17
12.3.3. Single-ended Requirements for Differential Signals ......................................................................................		18
12.4	Slew Rate Definitions ............................................................................................................................................	19
12.4.1. Slew Rate Definitions for Differential Input Signals ( CK ) .............................................................................		19
12.5	Differential Input Cross Point Voltage....................................................................................................................	20
12.6	Single-ended AC & DC Output Levels...................................................................................................................	21
12.7	Differential AC & DC Output Levels.......................................................................................................................	21
12.8	Single-ended Output Slew Rate ............................................................................................................................	21
12.9	Differential Output Slew Rate ................................................................................................................................	22
12.10 Single-ended AC & DC Output Levels of Connectivity Test Mode ......................................................................		23
12.11 Test Load for Connectivity Test Mode Timing .....................................................................................................		23
13. DIMM IDD Specification Definition..............................................................................................................................		24
14. IDD SPEC Table .........................................................................................................................................................		27
15. Input/Output Capacitance ...........................................................................................................................................		31
16. Electrical Characterisitics and AC Timing ...................................................................................................................		32
16.1	Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................	32
16.2	Speed Bin Table Note ...........................................................................................................................................	37
17. Timing Parameters by Speed Grade ..........................................................................................................................		38
18. Physical Dimensions...................................................................................................................................................		44
18.1	1Gx4 based 1Gx72 Module (1 Rank) - M393A1G40EB1/M393A1G40EB2..........................................................	44
18.1.1. x72 DIMM, populated as one physical rank of x4 DDR4 SDRAMs................................................................		44
18.2	512Mx8 based 1Gx72 Module (2 Ranks) - M393A1G43EB1................................................................................	45
18.2.1. x72 DIMM, populated as two physical ranks of x8 DDR4 SDRAMs ..............................................................		45
18.3	1Gbx4 based 2Gx72 Module (2 Ranks) - M393A2G40EB1/M393A2G40EB2 ......................................................	46
18.3.1. x72 DIMM, populated as two physical ranks of x4 DDR4 SDRAMs ..............................................................		46

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Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

1. DDR4 Registered DIMM Ordering Information

	Part Number2	Density	Organization	Component Composition1	Number of	Height
					Rank
	M393A1G40EB1-CPB/RC	8GB	1Gx72	1Gx4(K4A4G045WE-BC##)*18	1	31.25mm
	M393A1G40EB2-CTD
	M393A1G43EB1-CPB/RC/TD	8GB	1Gx72	512Mx8(K4A4G085WE-BC##)*18	2	31.25mm
	M393A2G40EB1-CPB/RC	16GB	2Gx72	1Gx4(K4A4G045WE-BC##)*36	2	31.25mm
	M393A2G40EB2-CTD

NOTE:

1."##" - PB/RC/TD

2.PB(2133Mbps 15-15-15)/RC(2400Mbps 17-17-17)/TD(2666Mbps 19-19-19)

-DDR4-2666(19-19-19) is backward compatible to DDR4-2400(17-17-17)

2. Key Features

	Speed	DDR4-1600	DDR4-1866	DDR4-2133	DDR4-2400	DDR4-2666	Unit
		11-11-11	13-13-13	15-15-15	17-17-17	19-19-19
	tCK(min)	1.25	1.071	0.938	0.833	0.75	ns
	CAS Latency	11	13	15	17	19	nCK
	tRCD(min)	13.75	13.92	14.06	14.16	14.25	ns
	tRP(min)	13.75	13.92	14.06	14.16	14.25	ns
	tRAS(min)	35	34	33	32	32	ns
	tRC(min)	48.75	47.92	47.06	46.16	46.25	ns

•JEDEC standard 1.2V ± 0.06V Power Supply

•VDDQ = 1.2V ± 0.06V

•800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin, 1067MHz fCK for 2133Mb/sec/pin,1200MHz fCK for 2400Mb/sec/pin,1333MHz fCK for 2666Mb/sec/pin

•16 Banks (4 Bank Groups)

•Programmable CAS Latency: 10,11,12,13,14,15,16,17,18,19,20

•Programmable Additive Latency (Posted CAS): 0, CL - 2, or CL - 1 clock

•Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600) , 10,12 (DDR4-1866), 11,14 (DDR4-2133),12,16 (DDR4-2400) and 14,18 (DDR42666)

•Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]

•Bi-directional Differential Data Strobe

•On Die Termination using ODT pin

•Average Refresh Period 7.8us at lower then TCASE 85 C, 3.9us at 85 C < TCASE 95 C

•Asynchronous Reset

3. Address Configuration

Organization	Row Address	Column Address	Bank Group Address	Bank Address	Auto Precharge
1Gx4(4Gb) based Module	A0-A15	A0-A9	BG0-BG1	BA0-BA1	A10/AP
512Mx8(4Gb) based Module	A0-A14	A0-A9	BG0-BG1	BA0-BA1	A10/AP

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Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

4. Registered DIMM Pin Configurations (Front side/Back side)

Pin	Front	Pin	Back	Pin	Front		Pin	Back	Pin	Front	Pin	Back	Pin	Front	Pin	Back
1	12V3,NC	145	12V3,NC	40	TDQS12_t,		184	VSS	78	EVENT_n	222	PARITY	117	DQ52	261	VSS
					DQS12_t
2	VSS	146	VREFCA	41	TDQS12_c,		185	DQS3_c	79	A0	223	VDD	118	VSS	262	DQ53
					DQS12_c
3	DQ4	147	VSS	42	VSS		186	DQS3_t	80	VDD	224	BA1	119	DQ48	263	VSS
4	VSS	148	DQ5	43	DQ30		187	VSS	81	BA0	225	A10/AP	120	VSS	264	DQ49
5	DQ0	149	VSS	44	VSS		188	DQ31	82	RAS_n/A16	226	VDD	121	TDQS15_t,	265	VSS
														DQS15_t
6	VSS	150	DQ1	45	DQ26		189	VSS	83	VDD	227	RFU	122	TDQS15_c,	266	DQS6_c
														DQS15_c
7	TDQS9_t,	151	VSS	46	VSS		190	DQ27	84	S0_n	228	WE_n/A14	123	VSS	267	DQS6_t
	DQS9_t
8	TDQS9_c,	152	DQS0_c	47	CB4		191	VSS	85	VDD	229	VDD	124	DQ54	268	VSS
	DQS9_c
9	VSS	153	DQS0_t	48	VSS		192	CB5	86	CAS_n/A15	230	NC	125	VSS	269	DQ55
10	DQ6	154	VSS	49	CB0		193	VSS	87	ODT0	231	VDD	126	DQ50	270	VSS
11	VSS	155	DQ7	50	VSS		194	CB1	88	VDD	232	A13	127	VSS	271	DQ51
12	DQ2	156	VSS	51	TDQS17_t,		195	VSS	89	S1_n	233	VDD	128	DQ60	272	VSS
					DQS17_t
13	VSS	157	DQ3	52	TDQS17_c,		196	DQS8_c	90	VDD	234	A17	129	VSS	273	DQ61
					DQS17_c
14	DQ12	158	VSS	53	VSS		197	DQS8_t	91	ODT1	235	NC,C2	130	DQ56	274	VSS
15	VSS	159	DQ13	54	CB6		198	VSS	92	VDD	236	VDD	131	VSS	275	DQ57
16	DQ8	160	VSS	55	VSS		199	CB7	93	C0,CS2_n,NC	237	NC,CS3_c,C1	132	TDQS16_t,	276	VSS
														DQS16_t
17	VSS	161	DQ9	56	CB2		200	VSS	94	VSS	238	SA2	133	TDQS16_c,	277	DQS7_c
														DQS16_c
18	TDQS10_t,	162	VSS	57	VSS		201	CB3	95	DQ36	239	VSS	134	VSS	278	DQS7_t
	DQS10_t
19	TDQS10_c,	163	DQS1_c	58	RESET_n		202	VSS	96	VSS	240	DQ37	135	DQ62	279	VSS
	DQS10_c
20	VSS	164	DQS1_t	59	VDD		203	CKE1	97	DQ32	241	VSS	136	VSS	280	DQ63
21	DQ14	165	VSS	60	CKE0		204	VDD	98	VSS	242	DQ33	137	DQ58	281	VSS
22	VSS	166	DQ15	61	VDD		205	RFU	99	TDQS13_t,	243	VSS	138	VSS	282	DQ59
										DQS13_t
23	DQ10	167	VSS	62	ACT_n		206	VDD	100	TDQS13_c,	244	DQS4_c	139	SA0	283	VSS
										DQS13_c
24	VSS	168	DQ11	63	BG0		207	BG1	101	VSS	245	DQS4_t	140	SA1	284	VDDSPD
25	DQ20	169	VSS	64	VDD		208	ALERT_n	102	DQ38	246	VSS	141	SCL	285	SDA
26	VSS	170	DQ21	65	A12/BC_n		209	VDD	103	VSS	247	DQ39	142	VPP	286	VPP
27	DQ16	171	VSS	66	A9		210	A11	104	DQ34	248	VSS	143	VPP	287	VPP
28	VSS	172	DQ17	67	VDD		211	A7	105	VSS	249	DQ35	144	RFU	288	VPP4
29	TDQS11_t,	173	VSS	68	A8		212	VDD	106	DQ44	250	VSS
	DQS11_t
30	TDQS11_c,	174	DQS2_c	69	A6		213	A5	107	VSS	251	DQ45
	DQS11_c
31	VSS	175	DQS2_t	70	VDD		214	A4	108	DQ40	252	VSS
32	DQ22	176	VSS	71	A3		215	VDD	109	VSS	253	DQ41
33	VSS	177	DQ23	72	A1		216	A2	110	TDQS14_t,	254	VSS
										DQS14_t
34	DQ18	178	VSS	73	VDD		217	VDD	111	TDQS14_c,	255	DQS5_c
										DQS14_c
35	VSS	179	DQ19	74	CK0_t		218	CK1_t	112	VSS	256	DQS5_t
36	DQ28	180	VSS	75	CK0_c		219	CK1_c	113	DQ46	257	VSS
37	VSS	181	DQ29	76	VDD		220	VDD	114	VSS	258	DQ47
38	DQ24	182	VSS	77	VTT		221	VTT	115	DQ42	259	VSS
39	VSS	183	DQ25		KEY				116	VSS	260	DQ43

NOTE:

1.VPP is 2.5V DC

2.Pin 230 is defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pin 230 is defined as SAVE_n for NVDIMMs.

3.Pins 1 and 145 are defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pins 1 and 145 are defined as 12V for Hybrid /NVDIMM

4.The 5th VPP is required on all modules. DIMMs.

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Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

5. Pin Description

	Pin Name	Description	Pin Name	Description
	A0–A171	Register address input	SCL	I2C serial bus clock for SPD/TS and register
	BA0, BA1	Register bank select input	SDA	I2C serial bus data line for SPD/TS and register
	BG0, BG1	Register bank group select input	SA0–SA2	I2C slave address select for SPD/TS and register
	RAS_n2	Register row address strobe input	PAR	Register parity input
	CAS_n3	Register column address strobe input	VDD	SDRAM core power supply
	WE_n4	Register write enable input	VPP	SDRAM activating power supply
	CS0_n, CS1_n,	DIMM Rank Select Lines input	VREFCA	SDRAM command/address reference supply
	CS2_n, CS3_n
	CKE0, CKE1	Register clock enable lines input	VSS	Power supply return (ground)
	ODT0, ODT1	Register on-die termination control lines input	VDDSPD	Serial SPD/TS positive power supply
	ACT_n	Register input for activate input	ALERT_n	Register ALERT_n output
	DQ0–DQ63	DIMM memory data bus	RESET_n	Set Register and SDRAMs to a Known State
	CB0–CB7	DIMM ECC check bits	EVENT_n	SPD signals a thermal event has occurred
	DQS0_t–	Data Buffer data strobes	VTT	SDRAM I/O termination supply
	DQS17_t	(positive line of differential pair)
	DQS0_c–	Data Buffer data strobes	RFU	Reserved for future use
	DQS17_c	(negative line of differential pair)
	CK0_t, CK1_t	Register clock input (positive line of differential
		pair)
	CK0_c, CK1_c	Register clocks input (negative line of differential
		pair)

NOTE :

1.Address A17 is only valid for 16 Gb x4 based SDRAMs.

2.RAS_n is a multiplexed function with A16.

3.CAS_n is a multiplexed function with A15.

4.WE_n is a multiplexed function with A14.

6. ON DIMM Thermal Sensor

SA2

SA1
SA0			1K
SA0	SA1	SA2	SA0	SA1	SA2

SCL			SCL					SCL
SDA			SDA					SDA
			EVENT_n			EVENT_n		ZQCAL			VSS
			Serial PD with					Register
			Thermal sensor
NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM

[ Table 1 ] Temperature Sensor Characteristics

Grade	Range		Temperature Sensor Accuracy			Units	NOTE
		Min.		Typ.	Max.
	75 < Ta < 95	-		+/- 0.5	+/- 1.0		-
						C
B	40 < Ta < 125	-		+/- 1.0	+/- 2.0		-
	-20 < Ta < 125	-		+/- 2.0	+/- 3.0		-
	Resolution		0.25			C /LSB	-

- 6 -

Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

7. Input/Output Functional Description

	Symbol	Type	Function
	CK0_t, CK0_c,	Input	Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of
	CK1_t, CK1_c		the positive edge of CK_t and negative edge of CK_c.
			Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and
			output drivers. Taking CKE LOW provides Precharge Power-Down and Self-Refresh operation (all banks idle), or
	CKE0, CKE1	Input	Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal
			DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all
			operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers,
			excluding CK_t, CK_c, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE, are disabled
			during Self-Refresh.
	CS0_n, CS1_n,	Input	Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection.
	CS2_n, CS3_n		CS_n is considered part of the command code.
	C0, C1, C2	Input	Chip ID : Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of stacked component. Chip ID
			is considered part of the command code.
	ODT0, ODT1	Input	On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM.
			When enabled, ODT is only applied to each DQ, DQS_t, DQS_c, TDQS_t and TDQS_c signal. The ODT pin will be
			ignored if MR1 is programmed to disable RTT_NOM.
	ACT_n	Input	Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The input into
			RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14
	RAS_n/A16.		Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being entered.
		Input	Those pins have multi function. For example, for activation with ACT_n Low, these are Addresses like A16, A15 and
	CAS_n/A15.
			A14 but for non-activation command with ACT_n High, these are Command pins for Read, Write and other command
	WE_n/A14
			defined in command truth table
	BG0 - BG1	Input	Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write or Precharge command is being
			applied. BG0 also determines which mode register is to be accessed during a MRS cycle.
	BA0 - BA1	Input	Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied.
			Bank address also determines which mode register is to be accessed during a MRS cycle.
			Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write
	A0 - A17	Input	commands to select one location out of the memory array in the respective bank. A10/AP, A12/BC_n, RAS_n/A16,
			CAS_n/A15 and WE_n/A14 have additional functions. See other rows. The address inputs also provide the op-code
			during Mode Register Set commands. A17 is only defined for 16 Gb x4 SDRAM configurations.
			Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be
	A10 / AP	Input	performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10
			is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all
			banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.
	A12 / BC_n	Input	Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst chop (on-thefly) will be
			performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.
	RESET_n	CMOS	Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH.
		Input	RESET_n must be HIGH during normal operation.
	DQ	Input/	Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of
			Data Burst. Any DQ from DQ0-DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4
		Output
			A4=High. Refer to vendor specific data sheets to determine which DQ is used.
	DQS0_t-DQS17_t,	Input/	Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data
			strobe DQS_t is paired with differential signals DQS_c, respectively, to provide differential pair signaling to the system
	DQS0_c-DQS17_c	Output
			during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended.
			Command and Address Parity Input: DDR4 Supports Even Parity check in SDRAMs with MR setting. Once it’s enabled
	PAR	Input	via Register in MR5, then SDRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1,
			BA0-BA1, A17-A0. Input parity should be maintained at the rising edge of the clock and at the same time with
			command & address with CS_n LOW
			Alert : It has multi functions such as CRC error flag, Command and Address Parity error flag as Output signal. If there
			is error in CRC, then ALERT_n goes LOW for the period time interval and goes back HIGH. If there is error in
	ALERT_n	Output	Command Address Parity Check, then ALERT_n goes LOW for relatively long period until on going SDRAM internal
		(Input)	recovery transaction is complete. During Connectivity Test mode this pin functions as an input.
			Using this signal or not is dependent on the system. If the SDRAM ALERT_n pins are not connected to the ALERT_n
			pin on the edge connector is must still be connected to VDD on DIMM.
	RFU		Reserved for Future Use: No on DIMM electrical connection is present
	NC		No Connect: No on DIMM electrical connection is present
			- 7 -

Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

Symbol	Type	Function
VDD1	Supply	Power Supply: 1.2 V ± 0.06 V
VSS	Supply	Ground
VTT	Supply	VDD/2
VPP	Supply	SDRAM Activating Power Supply: 2.5V ( 2.375V min, 2.75V max)
VDDSPD	Supply	SPD and register supply voltage. Register requires the nominl volatge to be 2.5V ± 10%.
VREFCA	Supply	Reference voltage for CA

NOTE :

1. For PC4 VDD is 1.2V. For PC4L VDD is TBD.

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Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

8. Registering Clock Driver Specification

8.1 Timing & Capacitance values

	Symbol	Parameter	Conditions	DDR4-1600/1866/2133		DDR4-2400/2666		Units	Notes
				Min	Max	Min	Max
	fclock	Input Clock Frequency	application frequency	625	1080	625	1350	MHz
	tCH/tCL	Pulse duration, CK_t, CK_c HIGH or		0.4	-	0.4	-	tCK
		LOW
	tACT	Inputs active time4 before DRST_n is	DCKE0/1 = LOW and DCS0/	16	-	16	-	tCK
		taken HIGH	1_n = HIGH
	tPDM	Propagation delay, single-bit switch-	1.2V Operation	1	1.3	1	1.3	ns
		ing, CK_t/ CK_c to output
	tDIS	output disable time	Rising edge of Yn_t to out-	0.5*tCK +	-	0.5*tCK +	-	ps
			put float	tQSK1(min)		tQSK1(min)
	tEN	output enable time	Output valid to rising edge of	0.5*tCK -	-	0.5*tCK -	-	ps
			Yn_t	tQSK1(max)		tQSK1(max)
	CI	Input capacitance, Data inputs	NOTE1,2	0.8	1.1	0.8	1.0
	CCK	Input capacitance, CK_t, CK_c	NOTE1,2	0.8	1.1	0.8	1.0	pF
	CIR	Input capacitance, DRST_n	VI=VDD or VSS ;	0.5	2.0	0.5	2.0
			VDD=1.2V

Note:

1.This parameter does not include package capacitance

2.Data inputs are DCKE0/1, DODT0/1, DA0..DA17, DBA0..DBA1, DBG0..DBG1, DACT_n, DC0..DC2, DPAR, DCS0/1_n

8.2 Clock driver Characteristics

				DDR4-1600/1866/		DDR4-2400		DDR4-2666
	Symbol	Parameter	Conditions	2133						Units	Notes
				Min	Max	Min	Max	Min	Max
	tjit (cc)	Cycle-to-cycle period jitter	CK_t/CK_c stable	0	0.025 x	0	0.025 x	0	0.025 x	ps
					tCK		tCK		tCK
	tSTAB	Stabilization time		-	5	-	5	-	5	us
	tCKsk	Clock Output skew		-	10	-	10	-	10	ps
	tjit(per)	Yn Clock Period jitter		-0.025 *	0.025 *	-0.025 *	0.025 *	-0.025 *	0.025 *	ps
				tCK	tCK	tCK	tCK	tCK	tCK
	tjit(hper)	Half period jitter		-0.032 *	0.032 *	-0.032 *	0.032 *	-0.032 *	0.032 *	ps
				tCK	tCK	tCK	tCK	tCK	tCK
	tQsk1	Qn Output to clock toler-		-0.125 *	0.125 *	-0.125 *	0.125 *	-0.1 * tCK	0.1 * tCK	ps
		ance		tCK	tCK	tCK	tCK
	tdynoff	Maximum re-driven dynamic		-	50	-	45	-	45	ps
		clock off-set

- 9 -

Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

9. Function Block Diagram:

9.1 8GB, 1Gx72 Module (Populated as 1 rank of x4 DDR4 SDRAMs)

QACS0_n
QAODT0
QACKE0
				CKE
					ODT CS_n
						D1
DQS0_t				DQS_t
DQS0_c				DQS_c
DQ[3:0]				DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D6

DQS9_t DQS_t

DQS9_c DQS_c DQ[7:4] DQ[3:0]

ZQ

QBCS0_n

QBODT0

QBCKE0

VSS

DQS4_t

DQS4_c

DQ[35:32]

CS_n

ODT

CKE

D11

DQS_t

DQS_c DQ[3:0]

ZQ

VSS DQS13_t

DQS13_c DQ[39:36]

CS_n

ODT

CKE

D15

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

				CKE
				ODT nCS
				D2
DQS1_t				DQS_t
DQS1_c				DQS_c
DQ[11:8]				DQ[3:0]

ZQ

VSSDQS10_t DQS10_c DQ[15:12]

CS_n

ODT

CKE

D7

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

DQS5_t

DQS5_c

DQ[43:40]

CS_n

ODT

CKE

D12

DQS_t

DQS_c DQ[3:0]

ZQ

VSS DQS14_t

DQS14_c DQ[47:44]

CS_n

ODT

CKE

D16

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

				CKE
				ODT nCS
				D3
DQS2_t				DQS_t
DQS2_c				DQS_c
DQ[19:16]				DQ[3:0]

ZQ

VSS

DQS11_t

DQS11_c

DQ[23:20]

CS_n

ODT

CKE

D8

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

DQS6_t

DQS6_c

DQ[51:48]

CS_n

ODT

CKE

D13

DQS_t

DQS_c DQ[3:0]

ZQ

VSS DQS15_t

DQS15_c DQ[55:52]

CS_n

ODT

CKE

D17

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

				CKE
				ODT nCS
				D4
DQS3_t				DQS_t
DQS3_c				DQS_c
DQ[27:24]				DQ[3:0]

ZQ

VSS DQS12_t

DQS12_c DQ[31:28]

CS_n

ODT

CKE

D9

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

DQS7_t

DQS7_c

DQ[59:56]

CS_n

ODT

CKE

D14

DQS_t

DQS_c DQ[3:0]

ZQ

VSS DQS16_t

DQS16_c DQ[63:60]

CS_n

ODT

CKE

D18

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

BG[1:0]

ODT CSn

ODT CSn

CKE

ZQ

CKE

ZQ

BA[1:0]

D5

VSS

D10

VSS

A[17:0]

DQS8_t

DQS_t

DQS17_t

DQS_t

DQS8_c

DQS_c

DQS17_c

DQS_c

ACT_n

CB[3:0]

DQ[3:0]

CB[7:4]

DQ[3:0]

PARITY

VDDSPD

Serial PD

CKE0

VPP

D1 - D18

VDD

D1 - D18

ODT0

VTT

D1 - D18

VREFCA

CS0_n

VSS

D1 - D18

SA2
SA1								CK0_t
SA0				1K
	SA0	SA1	SA2	SA0	SA1	SA2		CK0_c
SCL	SCL			SCL				CK1_t
SDA	SDA			SDA				CK1_c
		EVENT_n		EVENT_n		ZQCAL	VSS	RESET_n
	Serial PD with				Register
	Thermal sensor							ALERT_n

NOTE :

1.Unless otherwise noted, resistor values are 15 5%.

2.See the Net Structure diagrams for all resistors associated with the command, address and control bus.

3.ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram.

			QABG[1:0] -> BG[1:0] : SDRAMs D[10:1]
			QBBG[1:0] -> BG[1:0] : SDRAMs D[18:11]
			QABA[1:0] -> BA[1:0] : SDRAMs D[10:1]
			QBBA[1:0] -> BA[1:0] : SDRAMs D[18:11]
			QAA[17:0] -> A[17:0] : SDRAMs D[10:1]
			QBA[17:0] -> A[17:0] : SDRAMs D[18:11]
			QAACT_n -> ACT_n : SDRAMs D[10:1]
			QBACT_n -> ACT_n : SDRAMs D[18:11]
			QAPAR -> PAR : SDRAMs D[10:1]
			QBPAR -> PAR : SDRAMs D[18:11]
R			QACKE0 -> CKE : SDRAMs D[10:1]
			QBCKE0 -> CKE : SDRAMs D[18:11]
E
G
I
S			QAODT0 -> ODT : SDRAMs D[10:1]
T			QBODT0 -> ODT : SDRAMs D[18:11]
E
R
			QACS0_n -> CS_n : SDRAMs D[10:1]
			QBCS0_n -> CS_n : SDRAMs D[18:11]
			Y0_t -> CK_t : SDRAMs D[18:11]
			Y1_t -> CK_t : SDRAMs D[10:1]
			Y0_c -> CK_c : SDRAMs D[18:11]
			Y1_c -> CK_c : SDRAMs D[10:1]
			QRST_n -> RESET_n : All SDRAMs
			ERROR_IN_n -> ALERT_n : All SDRAMs

- 10 -

Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

9.2 8GB, 1Gx72 Module (Populated as 2 ranks of x8 DDR4 SDRAMs)

RCS0_n RCS1_n RCKE0 RCKE1 RODT0 RODT1

DQS8_t DQS8_c DM8

CB0

CB1

CB2 CB3 CB4 CB5 CB6 CB7

240

DQS3_t DQS3_c DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

240

DQS2_t DQS2_c DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

240

DQS1_t DQS1_c DM1

DQ8

DQ9

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

240

DQS0_t DQS0_c DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

240

DQS_t	CS n CKE ODT
DQS_c
DM
IO
IO
IO	D5
IO
IO
IO
IO
IO
DQS_t	CS n CKE ODT
DQS_c
DM
IO
IO
IO	D4
IO
IO
IO
IO
IO
DQS_t	CS n CKE ODT
DQS_c
DM
IO
IO
IO	D3
IO
IO
IO
IO
IO
DQS_t	CS n CKE ODT
DQS_c
DM
IO
IO
IO	D2
IO
IO
IO
IO
IO
DQS_t	CS n CKE ODT
DQS_c
DM
IO
IO
IO	D1
IO
IO
IO
IO
IO

	DQS_t		CS n CKE ODT
	DQS_c
	DM
	IO
	IO
	IO	D14
	IO
	IO
	IO
	IO
	IO
	DQS_t		CS n CKE ODT
	DQS_c
	DM
	IO
	IO
	IO	D13
	IO
	IO
	IO
	IO
	IO
	DQS_t		CS n CKE ODT
	DQS_c
	DM
	IO
	IO
	IO	D12
	IO
	IO
	IO
	IO
	IO
	DQS_t		CS n CKE ODT
	DQS_c
	DM
	IO
	IO
	IO	D11
	IO
	IO
	IO
	IO
	IO
	DQS_t		CS n CKE ODT
	DQS_c
	DM
	IO
	IO
	IO	D10

IO

IO

IO

IO

IO

240

240

240

240

240

DQS4_t DQS4_c DM4

DQ32

DQ33

DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

240

DQS5_t DQS5_c DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

240

DQS6_t DQS6_c DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

240

DQS7_t DQS7_c DM7

DQ56

DQ57

DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

240

DQS_t	CS n CKE ODT
DQS_c
DM
IO
IO
IO	D6
IO
IO
IO
IO
IO
DQS_t	CS n CKE ODT
DQS_c
DM
IO
IO
IO	D7
IO
IO
IO
IO
IO
DQS_t	CS n CKE ODT
DQS_c
DM
IO
IO
IO	D8
IO
IO
IO
IO
IO
DQS_t	CS n CKE ODT
DQS_c
DM
IO
IO
IO	D9
IO
IO
IO
IO
IO

	DQS_t		CS n CKE ODT
	DQS_c
	DM
	IO
	IO
	IO	D15
	IO
	IO
	IO
	IO
	IO
	DQS_t		CS n CKE ODT
	DQS_c
	DM
	IO
	IO
	IO	D16
	IO
	IO
	IO
	IO
	IO
	DQS_t		CS n CKE ODT
	DQS_c
	DM
	IO
	IO
	IO	D17
	IO
	IO
	IO
	IO
	IO
	DQS_t		CS n CKE ODT
	DQS_c
	DM
	IO
	IO
	IO	D18
	IO

IO

IO

IO

IO

240

240

240

240

- 11 -

Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

BG[1:0]

VDDSPD

Serial PD

BA[1:0]

A[16:0]

VPP

D1 - D18

ACT_n

VDD

D1 - D18

PARITY

VTT

D1 - D18

VREFCA

CKE0

VSS

D1 - D18

CKE1

ODT0

SA2		ODT1
SA1		CS0_n
SA0	1K	CS1_n

			SA0 SA1 SA2					SA0 SA1 SA2
SCL			SCL					SCL			CK0_t
SDA			SDA					SDA
			EVENT_n			EVENT_n		ZQCAL			VSS
			Serial PD with					Register			CK0_c
			Thermal sensor

CK1_t

CK1_c

RESET_n

ALERT_n

NOTE :

1.Unless otherwise noted, resistor values are 15 5%.

2.See the Net Structure diagrams for all resistors associated with the command, address and control bus.

3.ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram.

			BG[1:0]A -> BG[1:0] : SDRAMs D[5:1], D[14:10]
			BG[1:0]B -> BG[1:0] : SDRAMs D[9:6], D[18:15]
			BA[1:0]A -> BA[1:0] : SDRAMs D[5:1], D[14:10]
			BA[1:0]B -> BA[1:0] : SDRAMs D[9:6], D[18:15]
			A[16:0]A -> A[16:0] : SDRAMs D[5:1], D[14:10]
			A[16:0]B -> A[16:0] : SDRAMs D[9:6], D[18:15]
			ACTA_n -> ACT_n : SDRAMs D[5:1], D[14:10]
			ACTB_n -> ACT_n : SDRAMs D[9:6], D[18:15]
			PARA -> PAR : SDRAMs D[5:1], D[14:10]
			PARB -> PAR : SDRAMs D[9:6], D[18:15]
			CKE0A -> CKE : SDRAMs D[5:1]
			CKE0B -> CKE : SDRAMs D[9:6]
R			CKE1A -> CKE : SDRAMs D[14:10]
			CKE1B -> CKE : SDRAMs D[18:15]
E
G			ODT0A -> ODT : SDRAMs D[5:1]
I			ODT0B -> ODT : SDRAMs D[9:6]
S			ODT1A -> ODT : SDRAMs D[14:10]
T			ODT1B -> ODT : SDRAMs D[18:15]
E
			CS0A_n -> CS_n : SDRAMs D[5:1]
R
			CS0B_n -> CS_n : SDRAMs D[9:6]
			CS1A_n -> CS_n : SDRAMs D[14:10]
			CS1B_n -> CS_n : SDRAMs D[18:15]
			Y0_t -> CK_t : SDRAMs D[9:6]
			Y1_t -> CK_t : SDRAMs D[5:1]
			Y2_t -> CK_t : SDRAMs D[18:15]
			Y3_t -> CK_t : SDRAMs D[14:10]
			Y0_c -> CK_c : SDRAMs D[9:6]
			Y1_c -> CK_c : SDRAMs D[5:1]
			Y2_c -> CK_c : SDRAMs D[18:15]
			Y3_c -> CK_c : SDRAMs D[14:10]
			QRST_n -> RESET_n : All SDRAMs
			ERROR_IN_n <- ALERT_n : All SDRAMs

- 12 -

Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

9.3 16GB, 2Gx72 Module (Populated as 2 ranks of x4 DDR4 SDRAMs)

QACS0_n
QAODT0
QACKE0
QACS1_n
QAODT1
QACKE1
				CKE
					ODT CSn_
						D6
DQS0_t				DQS_t
DQS0_c				DQS_c
DQ[3:0]				DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D16

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

				CKE
				ODT nCS
				D1
DQS9_t				DQS_t
DQS9_c				DQS_c
DQ[7:4]				DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D11

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

				CKE
				ODT nCS
				D7
DQS1_t				DQS_t
DQS1_c				DQS_c
DQ[11:8]				DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D17

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

DQS10_t DQS10_c DQ[15:12]

CS_n

ODT

CKE

D2

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D12

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

				CKE
				ODT nCS
				D8
DQS2_t				DQS_t
DQS2_c				DQS_c
DQ[19:16]				DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D18

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

DQS11_t DQS11_c DQ[23:20]

CS_n

ODT

CKE

D3

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D13

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

				CKE
				ODT nCS
				D9
DQS3_t				DQS_t
DQS3_c				DQS_c
DQ[27:24]				DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D19

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

DQS12_t DQS12_c DQ[31:28]

CS_n

ODT

CKE

D4

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D14

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

				CKE
				ODT CSn
				D10
DQS8_t				DQS_t
DQS8_c				DQS_c
CB[3:0]				DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D20

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D5

DQS17_t DQS_t

DQS17_c DQS_c CB[7:4] DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D15

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

	SA2					VDDSPD
	SA1					VPP
	SA0
				1K		VDD
	SA0	SA1	SA2	SA0	SA1
						SA2

SCL			SCL					SCL			VTT
SDA			SDA					SDA			VREFCA
			EVENT_n			EVENT_n		ZQCAL			VSS
											VSS
			Serial PD with					Register
			Thermal sensor

NOTE :

1.Unless otherwise noted, resistor values are 15 5%.

2.See the Net Structure diagrams for all resistors associated with the command, address and control bus.

3.ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram.

Serial PD

D1 - D36

D1 - D36

D1 - D36

D1 - D36

- 13 -

Registered DIMM

datasheet

Rev. 1.41

DDR4 SDRAM

QBCS0_n
QBODT0
QBCKE0
QBCS1_n
QBODT1
QBCKE1
				CKE
					ODT CSn_
						D25
DQS4_t				DQS_t
DQS4_c				DQS_c
DQ[35:32]				DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D33

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

DQS13_t DQS13_c DQ[39:36]

CS_n

ODT

CKE

D21

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D29

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

				CKE
				ODT CSn
				D26
DQS5_t				DQS_t
DQS5_c				DQS_c
DQ[43:40]				DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D34

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

DQS14_t DQS14_c DQ[47:44]

CS_n

ODT

CKE

D22

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D30

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

				CKE
				ODT CSn
				D27
DQS6_t				DQS_t
DQS6_c				DQS_c
DQ[51:48]				DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D35

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

DQS15_t DQS15_c DQ[55:52]

CS_n

ODT

CKE

D23

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D31

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

				CKE
				ODT CSn
				D28
DQS7_t				DQS_t
DQS7_c				DQS_c
DQ[59:56]				DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D36

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

DQS16_t DQS16_c DQ[63:60]

CS_n

ODT

CKE

D24

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

CS_n

ODT

CKE

D32

DQS_t

DQS_c DQ[3:0]

ZQ

VSS

BG[1:0]

BA[1:0]

A[17:0]

ACT_n

C[2:0]

PARITY

CKE0

CKE1

ODT0

ODT1

CS0_n

CS1_n

CK0_t

CK0_c

CK1_t

CK1_c

RESET_n

ALERT_n

			QABG[1:0] -> BG[1:0] : SDRAMs D[20:1]
			QBBG[1:0] -> BG[1:0] : SDRAMs D[36:21]
			QABA[1:0] -> BA[1:0] : SDRAMs D[20:1]
			QBBA[1:0] -> BA[1:0] : SDRAMs D[36:21]
			QAA[17:0] -> A[17:0] : SDRAMs D[20:1]
			QBA[17:0] -> A[17:0] : SDRAMs D[36:21]
			QAACT_n -> ACT_n : SDRAMs D[20:1]
			QBACT_n -> ACT_n : SDRAMs D[36:21]
			QAC[2:0] -> C[2:0] : SDRAMs D[20:1]
			QBC[2:0] -> C[2:0] : SDRAMs D[36:21]
			QAPAR -> PAR : SDRAMs D[20:1]
			QBPAR -> PAR : SDRAMs D[36:21]
R			QACKE0 -> CKE : SDRAMs D[10:1]
			QBCKE0 -> CKE : SDRAMs D[28:21]
E
G			QACKE1 -> CKE : SDRAMs D[20:11]
I			QBCKE1 -> CKE : SDRAMs D[36:29]
S			QAODT0 -> ODT : SDRAMs D[10:1]
T			QBODT0 -> ODT : SDRAMs D[28:21]
E
			QAODT1 -> ODT : SDRAMs D[20:11]
R
			QBODT1 -> ODT : SDRAMs D[36:29]
			QACS0_n -> CS_n : SDRAMs D[10:1]
			QBCS0_n -> CS_n : SDRAMs D[28:21]
			QACS1_n -> CS_n : SDRAMs D[20:11]
			QBCS1_n -> CS_n : SDRAMs D[36:29]
			Y0_t -> CK_t : SDRAMs D[24:21], D[32:29]
			Y1_t -> CK_t : SDRAMs D[5:1], D[15:11]
			Y2_t -> CK_t : SDRAMs D[28:25], D[36:33]
			Y3_t -> CK_t : SDRAMs D[10:6], D[20:16]
			Y0_c -> CK_c : SDRAMs D[24:21], D[32:29]
			Y1_c -> CK_c: SDRAMs D[5:1], D[15:11]
			Y2_c -> CK_c : SDRAMs D[28:25], D[36:33]
			Y3_c -> CK_c : SDRAMs D[10:6], D[20:16]
			QRST_n -> RESET_n : All SDRAMs
			ERROR_IN_n -> ALERT_n : All SDRAMs

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