Richtek RT8237EZQW Schematic [ru]

RT8237E

High Efficiency Single Synchronous Buck PWM Controller

General Description

The RT8237E PWM controller provides high efficiency, excellent transient response, a nd high DC output a ccuracy needed for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM supplies in notebook computers.

The constant on-time PWM control scheme ha ndles wide input/output voltage ratios with ea se and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency .

The RT8237E achieves high ef ficiency at a reduced cost by eliminating the current sense resistor found in traditional current mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronous rectifier MOSFETs and enter diode emulation mode at light load condition. The Buck conversion allows this device to directly step down high voltage batteries at the highest possible

minimize design effort required for new designs. The RT8237E is intended for CPU core, chipset, DRAM, or other low voltage supplies as low as 0.7V. The R T8237E is available in the WDFN-10L 3x3 pa ckage.

efficiency. The pre-set frequency selections

Features

z Wide Input Voltage Range : 4.5V to 26V z Output Voltage Range : 0.7V to 3.3V z Built-in 0.5% 0.7V Reference Voltage z Quick Load-Step Response within 100ns z 4700ppm/

DS(ON)

z Adjustable Current Limit with Low Side MOSFET z 4 Selectable Frequency Setting z Soft-Start Control z Drives Large Synchronous-Rectifier FET s z Integrated Boot Switch z Built-in OVP/OCP/UVP z Thermal Shutdown z Power Good Indicator z RoHS Compliant and Halogen Free

°°

°C Current Source for Current Limit

°°

Applications

z Notebook Computers z CPU Core Supply z Chipset/RAM Supply a s Low as 0.7V z Generic DC/DC Power Regulator

Simplified Application Circuit

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EN RF

OUT

RT8237E

Ordering Information

RT8237E

(2)

Pin Configurations

Pin 1 Orientation (2) : Quadrant 2, Follow EIA-481-D

Package Type QW : WDFN-10L 3x3 (W-Type)

Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free)

Note : Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Marking Information

88 DF

A26

Functional Pin Description

Pin No. Pin Name Pi n Fun cti o n

1 PGOOD Open Drain Power Good Indicator. High impedance indicates power is good. 2 CS 3 EN Enable Control Input. Pull low to GND to disable the PWM. 4 FB

5 RF

6 LGATE Gate Drive Output for Low Side External MOSFET.

7 VCC

8 PHASE

9 UGATE Gate Drive Output for High Side External MOSFET.

10 BOOT

(Exposed Pad)

GND

Current Limit Threshold Setting Input. Connect a setting resistor to GND and the current limit threshold is equal to 1/8 of the voltage at this pin.

Feedback Input. Connect FB to a resistor voltage divider from V

OUT

to adjust the output from 0.7V to 3.3V Switching Frequency Selection. Connect a resistance to select switching

frequency as shown in Electrical Characteristics. The switching frequency is detected and latched after startup. This pin also controls diode emulation mode or forced CCM selection. Pull down to GND with resistor : Diode Emulation Mode. Connect to PGOOD with resistor : forced CCM after PGOOD becomes high.

Supply Voltage Input. This pin provides the power for the Buck controller, the low side driver and the bootstrap circuit for high side driver. Bypass to GND with a 1μF ceramic capacitor.

External Inductor Connection Pin for PWM Converter. It behaves as the current sense comparator input for low side MOSFET R voltage for on time generation.

Bootstrap Supply for High Side Gate Driver. Connect through a capacitor to the floating node (PHA SE).

Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

(TOP VIEW)

PGOOD

1 2

WDFN-10L 3x3

88 : Product Code DFA26 : Date Code

DS(ON)

BOOT

UGATE

PHASE

GND

VCC

LGATE

to GND

OUT

sensing and reference

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Function Block Diagram

TRIG

PHASE

On-time

Compute

COMP

RT8237E

BOOT

PWM

DRV

UGATE

VCC

POR

10µA

125%

REF

70%

REF

Timer

REF

125% V

90% V

Latch

S1 Q

Latch

S1 Q

REF

Thermal

Shutdown

Min. t

OFF

QTRIG

DEM/FCCM

X(1/8)

X(-1/8)

VCC

DRV

PHASE

LGATE GND

PGOOD

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RT8237E

Operation

The RT8237E integrates a Constant-On-T ime (COT) PWM controller, and the controller provides the PWM signal which relies on the output ripple voltage comparing with internal reference voltage.

The UGA TE driver is turned on at the beginning of each cycle. After the internal one-shot ti mer expires, the UGA TE driver will be turned off. The pulse width of this one-shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the input voltage and output voltage ra nge.

Power On Reset, UVLO

Power On Reset (POR) occurs when VCC rises above to approximately 4.1V (typical), the RT8237E will reset the fault latch and prepare the PWM for operation. When the input voltage below 3.7V(min), the Under Voltage Lockout (UVLO) circuitry inhibits switching by keeping UGA TE and LGA TE low.

Soft-Start

Mode Selection

The RT8237E supports mode selection through the RF by connecting a resistor from the RF pin to either G ND or PGOOD. When the resistor is connected to GND, the controller operates in diode emulation mode. When the resistor is connected to PGOOD, the controller operates in CCM mode.

Current Limit Setting

The RT8237E has a cycle-by-cycle current limit control. The current limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the sensing signal at PHASE is above the current limit threshold, the PWM is not allowed to initiate a new cycle.

Over Voltage Protection

The output voltage can be continuously monitored for over voltage condition. When the output voltage exceeds 25% of its set voltage threshold, the UGA TE goes low and the LGA TE is forced high.

The output voltage will track the internal ra mp voltage during soft-start interval to prevent large inrush current and output voltage overshoot while the converter is being powered up.

Under Voltage Protection

The output voltage can be continuously monitored for under voltage condition. When the output voltage is less than 70% of its set voltage, under voltage protection is triggered and then both UGA TE a nd LGATE gate drivers are f orced low.

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RT8237E

Absolute Maximum Ratings (Note 1)

z VCC, FB, PGOOD, EN, CS, RF to GN D ----------------------------------------------------------------------------- −0.3V to 6V z BOOT to PHASE ----------------------------------------------------------------------------------------------------------- −0.3V to 6V z PHASE to GND

DC------------------------------------------------------------------------------------------------------------------------------ −0.3V to 32V <20ns ------------------------------------------------------------------------------------------------------------------------- −8V to 38V

z UGA TE to PHASE --------------------------------------------------------------------------------------------------------- −0.3V to 6V

DC------------------------------------------------------------------------------------------------------------------------------ −0.3V to 6V <20ns ------------------------------------------------------------------------------------------------------------------------- −5V to 7.5V

z LGA TE t o G ND -------------------------------------------------------------------------------------------------------------- −0.3V to 6V

z Power Dissipation, P

W D FN-10L 3x3-------------------------------------------------------------------------------------------------------------- 3.28W

z Package Thermal Resistance (Note 2)

W DFN-10L 3x3, θJA-------------------------------------------------------------------------------------------------------- 30.5°C/W WDFN-10L 3x3, θJC-------------------------------------------------------------------------------------------------------- 7.5°C/W

z Lead T e mperature (Soldering, 10 sec.)-------------------------------------------------------------------------------- 260 °C z Junction T emperature------------------------------------------------------------------------------------------------------ 150°C z Storage T emperature Range --------------------------------------------------------------------------------------------- −65°C to 150°C z ESD Susceptibility (Note 3)

HBM (Human Body Model)----------------------------------------------------------------------------------------------- 2kV

@ TA = 25°C

Recommended Operating Conditions (Note 4)

z Input V oltage, VIN ---------------------------------------------------------------------------------------------------------- 4.5V to 26V z Control Voltage, VCC----------------------------------------------------------------------------------------------------- 4.5V to 5.5V z Junction T emperature Range--------------------------------------------------------------------------------------------- −40°C to 125°C z Ambient T emperature Range--------------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

(VCC = 5V, T

Input Power Supply

VCC Quiescent Supply Current

VCC Shutdown Current I CS Shutdo wn Current CS pull to GND -- -- 1 μA

FB Error Comparator Threshold

FB In put Bias Current V

= 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

SHDN

FB forced above the regulation point, V

= 5V,

VCC current, VEN = 0V -- -- 1 μA

-- 0.5 1.25 mA

DEM 0.7005 0.704 0.7075

REF

DEM, T

= −40 to 85°C (Note 5) 0.697 0.704 0.711

= 0.735V −1 0.01 1 μA

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RT8237E

Parameter Symbol Test Conditions Min Typ Max Unit

Voltage Range 0.7 -- 3.3 V

OUT

RRF = 470kΩ (Note 6) -- 290 --

Switching Frequency f

kHz

RRF = 100kΩ (Note 6) -- 380 -RRF = 39kΩ (Note 6) -- 430 --

Minimum Off-Time 250 400 550 ns

Current Sensing

CS Source Current ICS 9 10 11 μA CS Source Current T C -- 4700 -- ppm/°C Zero Crossing Threshold DEM −10 -- 5 mV

RRF = 200kΩ (Note 6) -- 340 --

Current Limit Threshold V

LIM

GND − PHASE, V GND − PHASE, VCS = 1.6V 185 200 215

= 2.4V 280 300 320

GND − PHASE, VCS = 0.4V 40 50 60

PHASE − GND, VCS = 2.4V -- 300 --

Negative Current Limit Threshold

PHASE − GND, VCS = 1.6V -- 200 - PHASE − GND, V

= 0.4V -- 50 --

Protection Function

Output UV Threshold

OVP Threshold

With respect to error comparator threshold With respect to error comparator threshold

65 70 75 %

120 125 130 % OV Fault Delay FB forced above OV threshold -- 5 -- μs VCC Under Voltage Lockout

Threshold V

Soft-Start From EN = high to V

OUT

UVLO

Falling edge, hysteresis = 100mV, PWM disabled below this level

= 95% -- 1300 -- μs

OUT

3.7 3.9 4.1 V

UV Blank Time From EN signal going high -- 3 -- ms Thermal Shutdown TSD -- 150 -- °C

Driver On Resistance

UGATE Dri ve Source R UGATE Dri ve Sink R LGATE Drive Source R LGATE Drive Sink R

Dead Time

UGATEsr UGATEsk LGATEsr LGATEsk

LGATE Rising (V

BOOT − PHASE forced to 5V -- 1.8 3.6 Ω

BOOT − PHASE forced to 5V -- 1.2 2.4 Ω

LGATE, High State -- 1.8 3.6 Ω

LGATE, Low State -- 0.8 1.6 Ω

= 1.5V) -- 30 --

PHASE

UGATE Rising -- 30 --

Internal Boost Charging Swi tch On Resistance

VCC to BOOT, 10mA -- -- 80 Ω

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Parameter Symbol Test Conditions Min Typ Max Unit

EN Threshold

RT8237E

EN Input Voltage

Logic-High VIH 1.8 -- -Logic-Low V

-- -- 0.5

Mode Decision

VRF Threshold for DEM -- -- 0.5 V VRF Threshold for FCCM 1.8 -- -- V PGOOD

Tr ip Thre sho ld (fa lli ng, leaving PGOOD)

Trip Threshold (rising, leaving PGOOD)

Fault Propagation Delay Output Low Voltage I

Measured at FB, with respect to reference, Hysteresis = 3%

Measured at FB, with respect to reference,

H y stere sis = 3%

Falling Edge, FB forced below PGOOD trip threshold

= 1mA -- -- 0.4 V

SINK

87 90 93 %

120 125 130 %

-- 2.5 -- μs

Leakage Current High State, forced to 5V -- -- 1 μA

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. Not production tested. Note 6. Not production tested. Test condition is V

is measured at T

measured at the exposed pad of the package.

= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

= 8V, V

= 1.1V, I

OUT

= 10A using ap plication circuit.

OUT

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RT8237E

Typical Application Circuit

Enable

470k

C1 1µF

16V

OC_SET

30k

11 (Exposed Pad)

R5 100k

BOOT

LGATE

0.1µF 50V

UGATE

BOOT

C2 10µF x 3

50V

OUT

0.45µH

R2*

C3*

FB1

5.1k

FB2

10k

R3*

C4*

C5*

C6 10µF x 2

16V

OUT

1.05V

OUT

330µF x 2 16V

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Typical Operating Characteristics

RT8237E

Efficiency vs. Load Current

100

90 80 70 60 50 40

Efficiency (% )

30 20 10

0.001 0.01 0.1 1 10 100

DEM

CCM

= 8V, V

= 1.05V, R

OUT

= 470kΩ

Load Curren t (A)

Efficiency vs. Load Current

100

90 80 70 60 50 40

Efficiency (% )

30 20 10

0.001 0.01 0.1 1 10 100

DEM

= 20V , V

Load Current (A)

CCM

= 1.05V, R

OUT

= 470kΩ

Efficiency vs. Load Current

100

90 80 70 60 50 40

Efficiency (% )

30 20 10

0.001 0.01 0.1 1 10 100

DEM

CCM

= 12V , V

= 1.05V, R

OUT

Load Current (A)

Switchin g Frequency vs. Load Current

1000

100

Switching Fr equency (kHz) 1

0.1

0.001 0.01 0.1 1 10 100

CCM

Load Curren t (A)

DEM

= 12V , V

= 1.05V, R

OUT

= 470kΩ

Switching Frequenc y vs. Load Current

1000

CCM

100

DEM

Switching Fr equency (kHz) 1

= 12V , V

0.1

0.001 0.01 0.1 1 10 100

Load Curren t (A)

= 1.05V, R

OUT

= 200kΩ

Switching Frequency vs. Load Current

1000

CCM

100

DEM

Swit ching Frequency (kHz) 1

= 12V , V

0.1

0.001 0.01 0.1 1 10 100

Load Current (A)

= 1.05V, R

OUT

= 100kΩ

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RT8237E

)

Switching Frequency vs . Loa d Current

1000

CCM

100

DEM

Swit ching Frequency (kHz) 1

= 12V, V

0.1

0.001 0.01 0.1 1 10 100

= 1.05V, R

OUT

Load Current (A)

Line Regula tion vs . Tem pe rature

1.0

DEM

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

Line Regulation (%

-0.6

-0.8

-1.0

= 12V, V

-50 -25 0 25 50 75 100 125

= 1.05V, R

OUT

= 470kΩ, No Load

Temperature (°C)

= 39kΩ

Load Regulation vs. Temperature

1.0

CCM

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

Load Regulat ion (%

-0.6

-0.8

-1.0

= 12V, V

-50 -25 0 25 50 75 100 125

OUT

= 1.05V, I

OUT

= 10A, R

Temperature (°C)

Switching Frequenc y vs. Input Voltage

500 475 450 425 400 375 350 325 300 275 250

Switching Fr equency (kHz) 1

225 200

4 6 8 10 12 14 16 18 20 22 24 26

RRF = 39k

RRF = 100k

RRF = 200k

RRF = 470k

Input Voltage (V)

= 470kΩ

OUT

= 10A

CS Source Current vs. Temperature

20 18 16 14 12 10

8 6 4

CS Source Current (µA)

2 0

-50 -25 0 25 50 75 100 125

= 5V

OUT

(50mV/Div)

OUT

(10A/Div)

UGATE

(20V/Div)

LGATE

(5V/Div)

Load Transient Response

VIN = 12V, I

= 0A to 20A, V

OUT

Time (40μs/Div)

OUT

= 1.05V

Temperature (°C)

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RT8237E

OUT

(500mV/Div)

LGATE

(5V/Div)

PGOOD (5V/Div)

(5V/Div)

OUT

(500mV/Div)

PGOOD

(5V/Div)

OVP

DEM, VIN = 12V, No Load

Time (40μs/Div)

Power On from EN

OUT

(1V/Div)

PGOOD (5V/Div)

UGATE

(20V/Div)

LGATE

(5V/Div)

OUT

(500mV/Div)

PGOOD

(5V/Div)

UVP

VIN = 12V, V

Time (40μs/Div)

Power On from EN

OUT

= 1.05V

UGATE

(10V/Div)

DEM, VIN = 12V, No Load

Time (1ms/Div)

UGATE

(10V/Div)

CCM, VIN = 12V, No Load

Time (1ms/Div)

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RT8237E

Application Information

ResponseTM technology is specifically designed for providing 100ns“instant-on” response to load steps while maintaining a relatively constant operating frequency a nd inductor operating point over a wide range of input voltages. The topology solves the poor load tran sient response timing problems of fixed frequency current mode PWMs and avoids the problems caused by widely varying switching frequencies in conventional constant on-ti me and consta nt off-time PWM schemes.

On-Time Control (TON/MODE)

The on-time one-shot comparator has two inputs. One input monitors the output voltage from the PHASE pin,

while the other input sa mples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time ca pa citor . The on-time is the time required for the voltage on this capacitor to charge from zero volts to V

, thereby making the on-

OUT

time of the high side switch directly proportional to output voltage and inversely proportional to input voltage.

Enable and Disable

The EN pin allows for power sequencing between the controller bias voltage and another voltage rail. The RT8237E remains in shutdown if the EN pin is lower than 500mV. When the EN pin rises above the VEN trip point, the RT8237E will begin a new initialization a nd soft-start cycle.

POR, UVLO and Soft-Start

Power-on reset (POR) occurs when VCC rises above

approxi mately 4.1V , in which the RT8237E resets the fault latch and prepares the PWM for operation. When the input voltage below 3.7V (min), the VCC Under V oltage Lockout (UVLO) circuitry inhibits switching by keeping UGA TE and LGA TE low. A built-in soft-start is used to prevent the power supply input from surge currents after PWM is enabled. A

ramping up current limit threshold eliminates the V

OUT

folded-back current during the soft-start duration.

Mode Selection (RF) Operation

T o select the operation mode, connect a resistor from the RF pin to either GND or PGOOD. When the resistor is connected to GND, the controller operates in diode emulation mode. When the resistor is connected to

PGOOD, the controller operates in CCM mode. The on-time is given by : tON = (V

OUT

/ VIN) / f

Diode-Emulation Mode (RRF connected to GND)

In diode-emulation mode, the RT8237E automatically

reduces switching frequency at light load conditions to

Table 1. RF Connection and Switching Frequency

RRF (kΩ) Switching Frequency (kHz)

470kΩ 290 200kΩ 340 100kΩ 380

39kΩ 430

Note : For DEM, connect RRF to GND; for CCM, connect

to PGOOD.

maintain high efficiency. This reduction of frequency is

achieved smoothly without increa sing V

ripple or load

OUT

regulation. As the output current decreases from heavy

load condition, the inductor current is reduced and

eventually comes to the point where its valley touches

zero current, which is the boundary between continuous

conduction and discontinuous conduction modes. To

emulate the behavior of diodes, the low side MOSFET

allows only partial negative current to flow when the

inductor freewheeling current reaches negative. As the load

current is further decrea sed, it takes longer a nd longer to

discharge the output capacitor to the level that requires

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RT8237E

)

the next “ON” cycle. The on-time is kept the same as that in heavy load condition. On the contrary, when the output current increa ses from light load to heavy load, the switching frequency increa ses to the preset value as the inductor current reaches the continuous condition. This is shown in Figure 1. The tran sition load point to the light load operation is calculated a s follows :

−

(

IN OUT

≈×

LOAD ON

where t

is the on-time.

Slope = (VIN -V

OUT

) / L

L, PEAK

LOAD

= I

L, PEAK

/ 2

Figure 1. Boundary Condition of CCM/DCM

the benefit of forced-CCM mode, but this comes at a cost.

The no load battery current can be up to 10mA to 40mA,

depending on the external MOSFETs.

Current Limit Setting (CS)

The RT8237E has a cycle-by-cycle current limit control.

The current limit circuit employs a unique “valley” current

sensing algorithm. If the magnitude of the current sense

signal at PHASE is above the current limit threshold, the

PWM is not allowed to initiate a new cycle (see Figure

2). In order to provide both good accuracy and a cost

effective solution, the RT8237E supports temperature

compensated MOSFET R

DS(ON)

sensing.

The CS pin of the RT8237E is a multiplexed pin for PWM

enable/disable control a nd current limit threshold setting.

Connect a setting resistor from this pin to GND via an N-

MOSFET. When the N-MOSFET is turned off, the PWM

is disabled. When the N-MOSFET is turned on, the PWM

is enabled a nd the current limit threshold is equal to 1/8

of the voltage at this pin.

The switching waveforms may appear noisy and asynchronous when light loa ding causes diode-emulation operation, but this is a normal operating condition that results in high light load efficiency . T rade-offs in DEM noise vs. light load efficiency is made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. The disadvantages for using higher inductor values include larger physical size and degraded load tra nsient response (especially at low input voltage levels).

Forced-CCM Mode (FCCM)

The low noise, forced-CCM mode disables the zerocrossing comparator, which controls the low side switch on-time. This causes the low side gate drive waveform to become the complement of the high side gate drive waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop to maintain duty ratio V

OUT/VIN

. A fairly constant switching frequency is

Choose a current limit resistor by following below equation:

RIPPLE

−××

OC_SET

⎛⎞

I8R

LOAD_OC DS(ON)

CS_OC

CS CS

⎜⎟ ⎝⎠

Inductor current is monitored by the voltage between the

GND and PHASE pins, so the PHASE pin should be

connected to the Drain termin al of the low side MOSFET .

ICS has a temperature coefficient to compensate the

temperature dependency of the R

. GND is used as

DS(ON)

the positive current sensing node, so GND should be

connected to the Source terminal of the low side MOSFET .

As the comparison is being done during the OFF state,

(current limit threshold) sets the valley level of the

LIMIT

inductor current. Thus, the load current at over current

threshold, I

I = +

LOAD_OC

= +

×××

8R 2Lf V

, can be calculated as follows :

CS_OC

8R 2

DS(ON)

CS_OC

DS(ON) IN

RIPPLE

−×

(V V ) V

IN OUT OUT

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RT8237E

In an over current condition, the current to the load exceeds the current to the output capa citor . Thus, the output voltage falls and eventually crosses the under voltage protection threshold, inducing IC shutdown.

L, PEAK

LOAD_OC

LIMIT

Figure 2. “Valley” Current Limit

When the device is operating in the FCCM, the negative current limit protects the external component. The negative current limit detect threshold is set a s the same value as positive current limit but negative polarity . The threshold still is the valley value of the inductor current.

BOOT

UGATE

PHASE

Figure 3. Reducing the UGA TE Rise T ime

Power Good Output (PGOOD)

The power good output is an open-drain output and requires

a pull-up resistor. When the output voltage is 20% a bove

or 10% below its set voltage, PGOOD will be pulled low . It

is held low until the output voltage returns to within these

tolerances once more. During soft-start, PGOOD is a ctively

held low and is allowed to tra nsition high only after soft-

start is over and the output rea ches 90% of its set voltage.

There is a 2.5μs delay built into the PGOOD circuitry to

prevent false transitions.

MOSFET Gate Driver

The high side driver is designed to drive high current, low R

N-MOSFET(s). When configured as a floating

DS(ON)

driver, 5V bi a s voltage is delivered from the VCC supply . The average drive current is proportional to the gate charge at VGS = 5V times switching frequency . The insta ntaneous drive current is supplied by the flying capacitor between the BOOT and PHASE pins. To prevent shoot through, a dead-time is internally generated between high side MOSFET off to low side MOSFET on, and low side

Output Over Voltage Protection (OVP)

The output voltage is continuously monitored for over

voltage condition. When the output voltage exceeds 25%

of its set voltage threshold, over voltage protection will be

triggered and the low side MOSFET is latched on. This

activates the low side MOSFET to discharge the output

ca pacitor . The RT8237E is latched once OVP is triggered

and ca n only be released by VCC or EN power on reset.

There is a 5μs delay built into the over voltage protection

circuit to prevent false transitions.

MOSFET off to high side MOSFET on. The low side driver is designed to drive high current low R

DS(ON)

N-MOSFET(s). The internal pull-down tran sistor that drives LGATE low is robust, with a 0.5Ω typical on-resistance. A 5V bias voltage is delivered from the VCC supply. The instantaneous drive current is supplied by the flying cap acitor between VCC a nd GND.

For high current applications, certain combin ations of high and low side MOSFETs may cause excessive gate-drain coupling, which can lead to efficiency-killing, EMIproducing shoot-through currents. This is often remedied by adding a resistor in series with BOOT , which increa ses the turn-on time of the high side MOSFET without degrading the turn-off time (see Figure 3).

Output Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under

voltage condition. When the output voltage is less than

70% of its set voltage threshold, under voltage protection

will be triggered and then both UGATE and LGATE gate

drivers are forced low . There is a 2.5μs delay built into the

under voltage protection circuit to prevent false transition s.

During soft-start, the UVP blanking time is 3ms.

Thermal Shutdown (OTP)

The device implements an intern al thermal shutdown to

protect itself if junction temperature exceeds 150°C. When

the junction temperature exceeds the thermal shutdown

threshold that the OTP function will be triggered and the

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RT8237E

RT8237E will shut down and enter Latch-Off Mode. In Latch-Off Mode, the RT8237E can be re set by EN or power input VCC.

Input Capacitor Selection

V oltage rating a nd current rating are the key parameters

in selecting an input capacitor. For a conservatively safe

design, an input ca pa citor should generally have a voltage

Output V oltage Setting (FB)

rating 1.5 times greater tha n the maximum input voltage.

The output voltage can be adjusted from 0.7V to 3.3V by setting the feedback resistors, R1 a nd R2 (see Figure 4). Choose R2 to be approximately 10kΩ and solve for R1 using the equation below :

V = V 1+

OUT REF

where V

REF

⎛⎞

⎜⎟

⎝⎠

is 0.704V (typ.).

OUT

The input capacitor is used to supply the input RMS

current, which is approximately calculated using the

following equation :

II 1

=× ×−

RMS OUT

⎛⎞

OUT OUT

⎜⎟

⎝⎠

IN IN

The next step is to select a proper capacitor for RMS

current rating. Placing more than one cap acitor with low

Equivalent Series Resistance (ESR) in parallel to form a

capacitor bank is a good design. Also, placing ceramic

capacitor close to the Drain of the high side MOSFET is

helpful in reducing the input voltage ripple at heavy load.

Figure 4. Setting V

Inductor Selection

with a Resistive V oltage Divider

OUT

Output Capacitor Selection

The output cap acitor and the inductor f orm a low-pass filter

in the buck topology . In steady-state condition, the ripple The inductor plays an important role in step-down

converters because it stores the energy from the input power rail and then relea ses the energy to the load. From the viewpoint of efficiency , the dc resistance (DCR) of the inductor should be as small as possible to minimize the conduction loss. In addition, because the inductor takes up a significant portion of the board spa ce, its size is also important. Low profile inductors can save board space especially when there is a height limitation. However , low DCR and low profile inductors are usually cost ineff ective.

Additionally, larger inductance results in lower ripple

current, which means lower power loss. The inductor current rising time increa se s with inducta nce value. This means the transient response will be slower. Therefore, the inductor design is a compromise between performance, size a nd cost.

In general, the inductance is designed such that the ripple

current ranges between 20% to 40% of the full load current. The inductance can be calculated using the following equation :

=×

MIN

fkI V

SW OUT_rated IN

−

VV V

IN OUT OUT

××

where k is the ratio between inductor ripple current and

current that flows into or out of the capacitor results in

ripple voltage. The output voltage ripples contains two

components, ΔV

V I ESRΔ=Δ×

OUT_ESR L

Δ=Δ×

OUT_C L

OUT_ESR

and ΔV

8C f

××

OUT SW

OUT_C

When load tran sient occurs, the output capa citor supplies

the load current before the controller can respond.

Therefore, the ESR will dominate the output voltage sag

during load transient. The output voltage sag can be

calculated using the following equation :

VESRI=×Δ

OUT_sag OUT

For a given output voltage sag specification, the ESR value

can be determined.

Another parameter that ha s influence on the output voltage

sag is the equivalent series inductance (ESL). A rapid

change in load current results in di/dt during transient.

Therefore, ESL contributes to part of the voltage sag. Use

a capacitor that has low ESL to obtain better transient

performance. Generally , using several capa citors in parallel

will have better transient performance than using single

cap acitor for the same total ESR. rated output current.

DS8237E-00 December 2012 www.richtek.com

RT8237E

Unlike the electrolytic ca pa citor, the cera mic ca pacitor ha s relative low ESR and ca n reduce the voltage deviation during load transient. However, the ceramic capacitor can only provide low capacitance value. Therefore, use a mixed combination of electrolytic ca pacitor a nd ceramic ca pa citor for better tran sient performance.

MOSFET Selection

The majority of power loss in the step-down power conversion is due to the loss in the power MOSFET s. For low voltage high current applications, the duty cycle of the high side MOSFET is small. Therefore, the switching loss of the high side MOSFET is of concern. Power MOSFETs with lower total gate charge are preferred in such applications.

However, the small duty cycle mea ns the low side MOSFET is on for most of the switching cycle. Therefore, the conduction loss tends to dominate the total power loss of the converter. To improve the overall efficiency , MOSFETs with low R

are preferred in circuit design. In some

DS(ON)

cas es, more than one MOSFET are connected in parallel to further decrea se the on-state resistance. However , this depends on the low side MOSFET driver capability and the budget.

test board. The maximum power dissipation at TA = 25°C

can be calculated by the following f ormula :

= (125°C − 25°C) / (30.5°C/W) = 3.28W for

D(MAX)

W DF N-10L 3x3 pa ckage

The maximum power dissipation depends on the operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. The derating curve in Figure 5 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

3.6

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

Maximum Power Dissipation (W) 1

0.0 0255075100125

Ambient Tem peratu re (°C)

Four-Layer PCB

Figure 5. Derating Curve of Maxi mum Power Dissi pation

Thermal Considerations

For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and a mbient temperature. The maximum power dissipation can be calculated by the following formula :

P where T

the ambient temperature, a nd θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

is the maximum junction temperature, T

is the junction to ambient

thermal resistance.

For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resista nce, θJA, is layout dependent. For W DFN-10L 3x3 packages, the thermal resistance, θJA, is

30.5°C/W on a standard JEDEC 51-7 four-layer thermal

Layout Considerations

Layout is very important in high frequency switching converter design. If designed improperly, the PCB may radiate excessive noise and contribute to converter instability. Certain points must be considered before starting a layout for the RT8237E.

` Connect an RC low pass filter for VCC; 1μF and 10Ω

are recommended. Place the filter capacitor close to

the IC.

` Keep current limit setting network a s close to the IC a s

possible. Routing of the network should avoid coupling to high voltage switching node.

` Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be a s short as possible to reduce stray inductance.

DS8237E-00 December 2012www.richtek.com

` All sensitive analog traces and components such as

FB, GND, EN, CS, PGOOD, VCC, and RF should be placed away from high voltage switching nodes such a s PHASE, LGATE, UGATE, or BOOT nodes to avoid coupling. Use internal layer(s) a s ground pla ne(s) a n d shield the feedback trace from power traces and components.

` Current sense connections must always be made using

Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device.

` Power sections should connect directly to ground

plane(s) using multiple vias as required for current handling (including the chip power ground connection s). Power components should be placed close to the IC to minimize loops and reduce losses.

RT8237E

DS8237E-00 December 2012 www.richtek.com

RT8237E

Outline Dimension

SEE DETAIL A

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104

E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069

e 0.500 0.020 L 0.350 0.450

W-Type 10L DFN 3x3 Package

0.014 0.018

Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS8237E-00 December 2012www.richtek.com

Richtek RT8237EZQW Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual