Philips 74HCT280N, 74HCT280DB, 74HCT280D, 74HCT280U, 74HC280U Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT280

9-bit odd/even parity generator/checker

Product specification			December 1990
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
9-bit odd/even parity generator/checker	74HC/HCT280

FEATURES

·Word-length easily expanded by cascading

·Similar pin configuration to the “180” for easy system up-grading

·Generates either odd or even parity for nine data bits

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT280 are 9-bit parity generators or checkers commonly used to detect errors in high-speed data

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

transmission or data retrieval systems. Both even and odd parity outputs are available for generating or checking even or odd parity up to 9 bits.

The even parity output (åE) is HIGH when an even number of data inputs (I0 to I8) are HIGH. The odd parity output (å0) is HIGH when an odd number of data inputs are HIGH.

Expansion to larger word sizes is accomplished by tying the even outputs (åE) of up to nine parallel devices to the data inputs of the final stage. For a single-chip 16-bit even/odd parity generator/checker, see PC74HC/HCT7080.

APPLICATIONS

·25-line parity generator/checker

·81-line parity generator/checker

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL		UNIT
				HC	HCT
	tPHL/ tPLH	propagation delay	CL = 15 pF; VCC = 5 V
		In to åE		17	18	ns
		In to åO		20	22	ns
	CI	input capacitance		3.5	3.5	pF
	CPD	power dissipationcapacitance per package	notes 1 and 2	65	65	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

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Philips Semiconductors			Product specification
9-bit odd/even parity generator/checker			74HC/HCT280
PIN DESCRIPTION
PIN NO.	SYMBOL	NAME AND FUNCTION
8, 9, 10, 11, 12, 13, 1, 2, 4	I0 to I8	data inputs
5, 6	åE, åO	parity outputs
7	GND	ground (0 V)
14	VCC	positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

December 1990

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