This symbol located near the fuse indicates that the
fuse used is slow operating type. For continued protection against
fire hazard, replace with same type fuse. For fuse rating, refer to
the marking adjacent to the symbol.
Ce symbole indique que le fusible utilise est e lent.
Pour une protection permanente, n'utiliser que des fusibles de meme
type. Ce demier est indique la qu le present symbol est appose.
HT-R940
REF NO.
F901
F901 or
F901
F901 or
F903
F903 or
F903
F903 or
F6901
F6901 or
F6902
F6902 or
1. Press and hold down VIDEO 1/VCR button, then press STANDBY/ON button when the unit is powered on.
2. After " Clear " is displayed, the preset memory and each mode stored in the memory, are initialized and
will return to the factory settings.
3. To check version of microprocessor
<Note>
Main microprocessor Q701 only.
1. Press and hold down DISPLAY button, then press STANDBY/ON button when the unit is powered on.
The version will be displayed on FL display only for 3 seconds.
Ex.
Ver.1.01/05305a
2. Press STANDBY/ON button to power off.
4. Memory Backup
The AV receiver uses a battery-less memory backup system in order to retain radio presets and other settings
when it is unplugged or in the case of a power failure.
Although no batteries are required, the AV receiver must be plugged into a wall outlet in order to charge the
backup system. Once it has been charged, the AV receiver will retain the settings for several weeks,
although this depends on the environment and will be shorter in humid climates.
Page 3
OPERATION CHECK-1
SPEAKER PROTECT-1 (DC VOLTAGE DETECTIION)
[When]
1. Exchange power transistors (Q6050 - Q6056, Q6060 - Q6066).
2. Exchange amplifier PC board ass'y (NAAF-8779).
[Procedure]
<Note> No load. No input.
1. Press and hold down CD button, then press STANDBY/ON button while the unit is powered on.
" Test - _ " is displayed only for 5 seconds.
HT-R940
Test - _
2. Press VIDEO 3 button while the characters of " Test - _ " are displayed.
The unit will be in the state of " Test-4-00 ".
Blinks
Test - 4-00
3. Repeatedly press +(TONE) button until the characters of " Test-4-21 " are displayed.
Test - 4-21
Check whether the operation starts and continues automatically as follows.
Test - 4-21
Front L ch
Protect OK
Test - 4-22
Protect OK
Test - 4-23
Protect OK
Test - 4-24
Protect OK
Check
Front R ch
Check
Center ch
Check
Surround L ch
Check
Test - 4-25
Protect OK
Test - 4-26
Protect OK
Test - 4-27
Protect OK
Protect
Surround R ch
Check
Surround Back L ch
Check
Surround Back R ch
Check
If all channels are OK, the characters of " Test-4-35 " are displayed.
Test - 4-35
4. Press STANDBY/ON button.
Clear
Turn off
Page 4
OPERATION CHECK-2
SPEAKER PROTECT-2 (CURRENT DETECTION)
[When]
1. Exchange power transistors (Q6050 - Q6056, Q6060 - Q6066).
2. Exchange amplifier PC board ass'y (NAAF-8779).
[Procedure]
<Note> No input.
Do not check two or more channels at the same time.
Do not connect a dummy load to speaker terminal longer than 2 seconds.
1. Press and hold down CD button, then press STANDBY/ON button while the unit is powered on.
" Test - _ " is displayed only for 5 seconds.
HT-R940
Test - _
2. Press VIDEO 3 button, while " Test - _ " is displayed.
The unit will be in the state of " Test-4-00 ".
Blinks
Test - 4-00
3. Repeatedly press +(TONE) button until " Test-4-35 " is displayed.
Test - 4-35
4. Connect the dummy load of 3 ohms to the Front L ch speaker terminals.
At this time, confirm that the speaker relay is not turned off.
Test - 4-35
5. Connect the dummy load of 1 ohm to the Front L ch speaker terminals.
At this time, confirm that the speaker relay is turned off and " Protect " is displayed.
Protect
Disconnect the dummy load immediately after checking the display of " Protect ".
Test - 4-35
6. Check other channels according to the same procedure as 4 and 5.
7. Press the STANDBY/ON button.
Clear
Turn off
Page 5
OPERATION CHECK-3
CONTROL OF POWER SUPPLY (OUTPUT SENSOR AND THERMAL SENSOR)
[When]
1. Exchange power transistors (Q6050 - Q6056, Q6060 - Q6066).
2. Exchange power amplifier PC board ass'y (NAAF-8779).
3. Exchange thermal sensor PC board ass'y (NAETC-8781).
[Procedure]
<Note> No output. No input.
Output sensor
1. Press and hold down CD button, then press STANDBY/ON button while the unit is powered on.
" Test - _ " is displayed only for 5 seconds.
HT-R940
Test - _
2. Press VIDEO 3 button while " Test - _ " is displayed.
The unit will be in the state of " Test-4-00 ".
Blinks
Test - 4-00
3. Repeatedly press +(TONE) button until " Test-4-36 " is displayed.
Test - 4-36
4. At this time, confirm that the red characters of " FM STEREO " is displayed.
And, confirm that the relays RL6901 and RL6902 are turned off in 2 or 3 seconds.
FM STEREO
Test - 4-36
5. Press +(TONE) button and confirm that the red characters of " FM STEREO " is displayed.
And, confirm that the relays RL6901 and RL6902 are turned off in 2 or 3 seconds.
FM STEREO
Test - 4-37
6. Press STANDBY/ON button.
Turn off
Clear
Thermal sensor
1. Press and hold down DISPLAY button, then press STANDBY/ON button when the unit is powered on.The microprocessor version will be displayed for 3 seconds.
<Ex.>
Ver. 1.01/06222A
2. Press TONE button while the version is displayed.
<Ex.>
T: 25 C/ 77 F
3. Confirm that the displayed temperature is within +/-20 C from the ambient temperature.
4. Press STANDBY/ON button.
Turn off
Clear
Page 6
OPERATION CHECK-4
DEBUG MODE-1
The operations of DSP and DIR etc are able to checked by the information displayed on FL in this debug mode.
This information will help to analysing digital audio no sound trouble.
To set in Debug mode
1. Press and hold down DISPLAY button, then press STANDBY/ON button while the unit is powered on.
The version number of microprocessor is displayed only for 3 seconds.
<Ex.>
1. Press TONE+ button within 3 seconds above, the version number of DSP will be displayed for 5 seconds.
<Ex.>
2. Press DISPLAY button while the DSP version is displayed. The status of DSP and DIR etc will be displayed.
<Ex.>
To exit
Press STANDBY/ON button.
Ver. 101/06222A
DSP :06206A
E1A48K0N/OFFPoO
HT-R940
Content of Display
2
1
-------------------------------- DIR ------------------------------------
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
!
R5667
22
C5667
220/25
C5666
220/25
R5666
22
<Note>
NC = No mount of parts.
SD-Z : XY
Location of connected terminal in schematic diagrams.
SD-Z = Schematic diagrams-Z. X = A to H, Y = 1 to 5.
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
BLANK17ALSB18GND19VAA20SCLOCK21SDATA22RSET223COMP224DAC F
16
R4076 100
R4074 4.7K
R4075 4.7K
LC74761M-9836
1
VSS
2
XTALIN1
3
XTALOUT1
4
HSYNCOUT
5
XTALIN2
6
XTALOUT2
7
VSYNCOUT
8
CS
9
SIN
10
SCLK
11
SW1
12
SW2
13
SW3
14
SW4
15
RST16CVOUT
220
220
R4124
Q4014
2SA1162-GR
R4064
R4063 1.2K
38
39
40
TTX
RSET1
TTXREQ
SCRESET/RTC
R4077 100
R4078 1.2K
R4079 1.2K
Page 26
HT-R940
A
SCHEMATIC DIAGRAMS-5
SPEAKER TERMINAL SECTION
MPP Type only
1
(SD-7 : B5)
To NAETC-8790
2
(SD-2 : E5)
To NAAF-8779(2/2)
3
(SD-8 : D1)
To NAPS-8781
4
(SD-8 : E1)
To NAPS-8781
JL6605B
JL6600B
5
4
3
2
1
JL901B
1
2
3
4
JL9101B
5
6
1
HPL
2
LSPE
3
HPR
4
5
MPUGND
1
2
3
4
5
6
7
FLAC1
FLAC2
SEC3-1
SEC3-2
SEC2-1
SEC2-2
R6691
HPDET
CSP
LSP
RSP
SLSP
SRSP
SBLSP
SBRSP
POFF
+12VD
MPUGND
+10S
POWERD
390(1/2W)
R6992
390(1/2W)
L6602 S1.3C
R6602 22
R6612 22
MDC Type only
MPP Type only
L6600 S1.3C
R6600 22
R6610 22
MDC Type only
MPP Type only
L6601
R6601 22
R6611 22
MDC Type only
MPP Type only
L6603
R6603 22
R6613 22
MDC Type only
MPP Type only
L6604 S1.3C
R6604 22
R6614 22
MDC Type only
MPP Type only
L6605
R6605 22
R6615 22
MDC Type only
MPP Type only
L6606 S1.3C
R6606 22
R6616
MDC Type only
D9001
RL1N4003
J6851
J6600
S1.3C
J6604
S1.3C
J6619
J6620
S1.3C
J6626
22
J6625
D9002
RL1N4003
+
C9001
D9013
R9005
220(1/2W)
470/63
8.2K
R9003
D9005
MTZJ36D
1SS133
Q9001
2SC2235-Y
8.2K
R9006
47/50
C9005
C6602
104Z
RL6602
6
2
D6600
1SS133
C6600
104Z
6
RL6600
D6603
1SS133
C6603
104Z
6
2
5
RL6603
D6605
1SS133
C6605
104Z
6
RL6605
D6607
1SS133
C6607
104Z
6
2
54
RL6607
+5V
+5VDIS
33K
223Z
C9006
R9004
-VP
BCDE
<Note>
NC = No mount of parts.
SD-Z : XY
Location of connected terminal in schematic diagrams.
SD-Z = Schematic diagrams-Z. X = A to H, Y = 1 to 5.
U20
VIDEO & SPEAKER TERMINAL PC BOARD
+
470/16
SPRLB
Q9021
SI-8008
1
VIN
5
SS
RL1N4003
D9022
GND
SW
VADJ
3
SPRLF
SPRLCS
MDC Type only
L9001
NCH-2541_470K
2
4
D9021
CRS09
R9001
3.3(2W)
R9002
3.3(2W)
10k
R9020
1.5k
R9021
R9018
0
10k
+
R9027
1.5k
C9023 470/6.3
R9008
Q9031
MPC2905HF
1
I
2
+
C9031
470/16
O
G
223Z
C9024
3
C9032
1
2
D9020
+
R6690
10(1/2W)
MPP Type only
Q9022
BA00JC5WT
Vc
Adj
Vin
GND
3
1SS133
J403
470/6.3
GND_VD
432
1
Q9031A
Vo
10000/16
POFF2
Q6601
DTC123JKA
Q6602
DTC123JKA
Q6604
DTC123JKA
R9028
0.47(1/2W)
+10.6V
C9021
1
3
45
1
3452
1
3
4
1
3452
1
3
Q9002
RN1205
CENTER
SPEAKER
P6601
C6642
R
L
103J
C6640
FRONT SPEAKERS A
C6650
102J
C6653
102J
SURROUND
SPEAKERS
L
103J
C6643
L
103J
C6645
SURROUND BACK
SPEAKERS
C6655
102J
R9011
APOWER
SEC2-1
SEC2-2
R9013
D9015
1SS133
P6602
4.7(1/2W)
4.7(1/2W)
C6641
R
C6644
R
C6646
D9012 1SS133
R9012
4.7(1/2W)
D9014
3.3/50
C9013
1SS133
103J
103J
103J
103J
C9012
334J
R9014
C6652
C6651
C6654
C6656
100k
102J
102J
102J
102J
4
3
D9011
2
D3SBA20
D9024
MTZJ5.6B
DTC123JKA
+10.9V
1
Q6603
D9017
1SS133
C9011
NAVD-8811(2/2)
R9017
VPOWER
0
5
+5.3V
4
6.8k
R9023
R9024
R9022
33k
100k
+5V_VD
+
C9025
C9022
470/6.3
105M
+24V
RLGND
CSPE
LSPE
RSPE
SLSPE
SRSPE
SBLSPE
SBRSPE
RLGND
+24V
SBRSPE
SBLSPE
SPBROUT
SPBLOUT
To NAVD-8811(1/2)
SPRLB
SPRLSB
SPRLCS
SPRLF
GND_HD
R9029
0.47(1/2W)
HPDET
VPOWER
+5V_XM
GND_XM
+5VDIS
+5VDSP
GND_VD
GND_VD
+10VDSP
POFF
POFF2
APOWER
10S+12VD
-VP
FLAC1
FLAC2
JL6603B
(SD-2 : E4)
To NAAF-8779(2/2)
JL6604B
4
3
2
1
(SD-2 : G5)
To NAAF-8779(1/2)
(SD-4 : G1)
4
3
2
NC
1
NC
JL8001A
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(SD-3 : D1)
To NADG-8808
P2005B
HT-R940
Page 27
HT-R940
A
BCDE
SCHEMATIC DIAGRAMS-6
XM DIGITAL TRANSCEIVER SECTION (MDC Type only)
1
2
3
NADG-8809
U19
XM DIGITAL TRANSCEIVER PC BOARD
L2002
BK1608LM182
104Z
XM_SDI_L
XM_SDO_L
XM_COM_SEL
XM_ERR_IRQ
XM_RESET
100K
R2001
R2003
100K
R2002
100K
C2002
102K
C2001
104Z
R2004
100K
+3.3V
1
LSDP
2
VSS
3
SC_TX_OUT
4
VDD
5
SC_RX_IN
6
VSS
7
CMD_SEL
8
VDD
9
ERR_IRQ
10
VSS
11
RST
12
C2013
+3.3V
46
47
48
SAII_DA
SAII_EN
12 : SLAVE_SEL
COMM_RX_DIG
COMM_TX_DIG
13
14
15
100K
R2005
42
43
44
45
VSS
VSS
VDD
SAII_CLK
I2S_OCLK
Q2001
F2602E-01
XMDTIC
COMM_TX_EN
VSS17VDD18COMM_RX_P
COMM_RX_M20VDD21VSS22COMM_TX_M
16
19
104Z
C2003
1K
104Z
C2004
R2008
R2006
R2009
1K
R2007
C2012
40
41
VDD
I2S_LRCLK
100
100
104Z
39
I2S_CLK
I2S_OCLK
I2S_SCLK
I2S_SDO
I2S_LRCLK
37
38
VSS
I2S_DA
HSDP_EN
HSDP_CLK
HSDP_DA
OSC_IN
OSC_OUT
COMM_TX_P24VSS
23
C2005
104Z
C2006
104Z
VSS
VDD
VSS
TEST
VSS
VDD
VSS
+3.3V
+3.3V
36
35
34
C2011
33
104Z
32
31
30
29
28
27
26
25
C2007
C2010
104Z
100/16
C2008
040C
C2009
080D
R2011
R2010
1M
680
DAC_RESET
X2001
45.1584MHz
R2012
R2013
R2014
R2015
R2016
<Note>
NC = No mount of parts.
SD-Z : XY
Location of connected terminal in schematic diagrams.
SD-Z = Schematic diagrams-Z. X = A to H, Y = 1 to 5.
C2027
10/50
C2028
10/50
C2029
C2030
R2044
R2031
22(1/2W)
220/16
220/16
R2032
22(1/2W)
220
C2044
C2034
+5.3V
102K
L2006
L2004
BLM21PG221SN1
104Z
C2042
100/16
R2033
R2034
L2005
BLM21PG221SN1
XM_L_OUT
1
XM_R_OUT
2
3
GND_A
C2041
NC
NC
C2040
NC
22
22
+12V
-12V
4
3
2
1
P2001
JL5502B
4
5
6
7
To NAAF-8779
E2002
E2001
GND
D+
XM
D+V
(SD-1 : B1)
+12V
C2025
821J
821J
C2023
821J
C2024
14
13
12
11
10
9
8
C2026
821J
UDZS5.1B
NJM4580M-D
8
Q2003
3
2
R2027
2.2K
3.3K
R2029
R2028
3.3K
R2030
2.2K
6
5
4
Q2003
NJM4580M-D
D2001
C2035
104Z
1
7
-12V
+5V
Q2002
AK4384ET
100
330
330
330
0
C2014
102K
DAC
1
MCLK
2
BICK
3
SDTI
4
LRCK
5
PDN
6
SMUTE/CSN
7
ACKS/CCLK
8
DIF0/CDTI9P/S
DZFL
DZFR
VDD
VCOM
AOUTL
AOUTR
VSS
16
15
14
13
12
11
10
+5V
Q2004
TA48033AF
L2001
022K
+3.3V
C2033
3
470/6.3
O
XM_ERR_IRQ
XM_SDI_L
22(1/2W)
1
I
G
2
104Z
C2032
C2018
470/6.3
C2017
104Z
C2016
10/50
C2015
104Z
2
1O3
G
Q2005
78L05
R2047
C2043
100/6.3
I
C2021
R2021
2.2K
10/50
100K
R2023
100K
R2024
C2022
R2022
10/50
2.2K
104Z
L2003
C2031
022K
+11.8V
R2036
0
Q2006
TC74HCT7007AF
1
2
3
4
5
6
7
GND
VCC
OUT6
OUT5
OUT4
R2025
2.2K
R2026
2.2K
IN6
IN5
IN4
DAC_RESET
XM_COM_SEL
XM_SDO_L
XM_RESET
4
+3.3V
C2036
104Z
11
Y8
12
Y7
13
Y6
14
Y5
15
Y4
16
Y3
17
Y2
18
Y1
19
_G2
20
VCC1_G1
10
GND
9
A8
8
A7
7
A6
6
A5
5
A4
4
Q2007
A3
3
A2
2
TC74VHC541FT
A1
R2035
R2046
XMDACRST
1
XMCOMSEL
2
XMERRIRQ
3
JL101B
0
0
+5.3V
XMSRTXD
XMSRRXD
XMRST
GND
+5V_XM
4
5
6
7
8
9
To NADG-8808
(SD-3 : D3)
HT-R940
Page 28
A
SCHEMATIC DIAGRAMS-7
DISPLAY SECTION
1
NOTE
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
<Note>
2
3
4
NC = No mount of parts.
SD-Z : XY
Location of connected terminal in schematic diagrams.
SD-Z = Schematic diagrams-Z. X = A to H, Y = 1 to 5.
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
<Note>
2
3
4
NC = No mount of parts.
SD-Z : XY
Location of connected terminal in schematic diagrams.
SD-Z = Schematic diagrams-Z. X = A to H, Y = 1 to 5.
THE COMPONENTS IDENTIFIED BY MARK ARE CRITICAL FOR SAFETY
REPLACE ONLY WITH PART NUMBER SPECIFIED.
VOLTAGE (MEASURED WITH VOLTMETER) IS DC VOLTAGE.(NO INPUT SIGNAL).
ALL PNP TRANSISTORS ARE EQUIVALENT TO 2SA1015-GR UNLESS OTHERWISE NOTED.
ALL NPN TRANSISTORS ARE EQUIVALENT TO 2SC1815-GR UNLESS OTHERWISE NOTED.
ALL DIODES ARE EQUIVALENT TO 1SS133 UNLESS OTHERWISE NOTED.
ELECTROLYTIC CAPACITORS ( ) ARE IN uF/WV.
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030- 3pF 330- 33pF 331- 330pF 333- 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS.
EX) PRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
<Note>
NC = No mount of parts.
SD-Z : XY
Location of connected terminal in schematic diagrams.
SD-Z = Schematic diagrams-Z. X = A to H, Y = 1 to 5.
TYPE
MDC
MPA
AC IN
120V, 60Hz
230 - 240V, 50Hz
BCDE
!
D933
1SS133
D935
1SS133
C933
4.7/50
D930 1SS133
D931 1SS133
D923 1SS133
9
8
D921 1SS133
7
D924 1SS133
C921 223Z
D922 1SS133
D925
1SS133
C902
104J
!
RL901
C901
!
103M/275VAC
F903
AC IN
!
T902
1
2
3
456
P921A
NC
P922A
NC
!
P901A
!
!
P941A
NC
!
P902
AC OUTLET
U07
POWER SUPPLY PC BOARD
+10.4V
D934
MTZJ5.1B
100K
R934
+10.9V
+
C930
100/35
C922
2200/25
+
+10.4V
R921
56(1/2W)
!
F901
P923AP924AP925A
NCNCNC
J931
Q930
SI-3010KF
1Vc2
100K
R930
R931
C931
100K
Vin3GND4Vout5ADJ
10/50
!
NAPS-8787
NC
82K
R932
C932
10K
R933
P911
J932
100/16
POFF
+12VD
MPUGND
+10VS
POWERD
C911 102J
E901
1SS133
!
T901
PRI.
D911
JL901A
5
4
3
2
1
D912
To NAVD-8811
(SD-5 : A4)
1SS133
S4
S3
S2
S1
To NAVD-8811
(SD-5 : A4)
JL9101A
12345
10
11
12
13
14
8
9
R9102
8.2(1/2W)
U08
104J
C9101
R9101
F910
NC
FLAC1
!
TRANS SEC. TERMINAL
PC BOARD
To NAAF-8779
(SD-2 : A5)
NAETC-8788
FLAC2
SEC3_2
SEC3_1
6
SEC2_1
SEC2_2
P942A
NC
Refer to following table about the parts displayed by mark " ".
THIS SYMBOL LOCATED NEAR THE FUSE INDICATES
THAT THE FUSE USED IS SLOW OPERATING TYPE
FOR CONTINUED PROTECTION AGAINST FIRE
HAZARD,REPLACE WITH SAME TYPE FUSE. FOR FUSE
RATING REFER TO THE MARKING ADJACENT TO THE SYMBOL.
CE SYMBOLE INDIQUE QUE LE FUSIBLE UTLISE EST
E LENT.POUR UNE PROTECTION PERMANENTE,N'UTILISER
QUE DES FUSIBLES DE MEME TYPE. CE DARNIER EST
4
INDIQUE LA QU LE PRESENT SYMBOL EST APPOSE.
CAUTION
FOR CONTINUED PROTECTION
AGAINST FIRE HAZARD, REPLACE
ONLY WITH FUSE OF SAME TYPE
VA
AND RATING INDICATED.
ATTENTION
AFIN D'ASSURER UNE PROTECTION
PERMANENTE CONTRE LES RISQUES
D'INCENDIE, REMPLACER UNIQUEMENT
VA
PAR UN FUSIBLE DE MEME TYPE
ET CALIBRATION COMME INDIQUE.
TYPE
MDC
MPP
F901
8A/125V
T4AL250V
F903
5A/125V
T2.5AL250V
T901T902R9101
NPT-1517D
NPT-1517P
NPT-1520JQ
NPT-1519GQ
0.1(1/2W)
0.22(1/2W)
HT-R940
Page 32
HT-R940
A
SCHEMATIC DIAGRAMS-9
DIGITAL AUDIO WAVE FORM SECTION
NOTE:
1. WF01 is short for Wave form 01 .
2. See SD-3 (SCHEMATIC DIAGRAM-3) for details.
1
74HCU04AF
Q131
COAXIAL
IN 1
2
IN 2
IN 3
13
IN
R141
WF01
IN
R145
IN
R143
WF01
WF02
COAX1
R331
OPT1
OPT2
OPT3
48
DIR
46
45
43
10
WF03
54
R312
61
R320
60
R315
WF04
LR CLOCK (SAI_LRCK, CX_LRCK)BIT CLOCK (SAI_SLCK, CX_SLCK)
19A11A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high, bank 1 is
16CASCAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth
34CKEThe CKE input determines whether the CLK input is enabled within the device.
A0-A10A0 to A10 are address inputs. A0-A10 are used as row address inputs during active command input
and A0-A7 as column address inputs during read or write command input. A10 is also used to
determine the precharge mode during other commands. If A10 is LOW during precharge command,
the bank selected by A11 is precharged, but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automatically after
the burst access.
These signals become part of the OP CODE during mode register set command input.
selected. This signal becomes part of the OP CODE during mode register set command input.
Table" item for details on device commands.
When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid.
When CKE is LOW, the device will be in either the power-down mode, the clock suspend mode,
or the self refresh mode. The CKE is an asynchronous input.
TX-SR574
35CLKCLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired
in synchronization with the rising edge of this pin.
18CSThe CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in
the previous state when CS is HIGH.
2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
42, 43, 45, 46,
48, 49
14, 36LDQM,
17RASRAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth
15WEWE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth
7, 13, 38, 44V
1, 25V
4, 10, 41, 47GNDQGNDQ is the output buffer ground.
26, 50GNDGND is the device internal ground.
I/O0
to
I/O15
UDQM
CCQVCCQ is the output buffer power supply.
CCVCC is the device internal power supply.
I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units using the LDQM and
UDQM pins.
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and
UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to theHIGH
impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional
DRAMs. In write mode, LDQM and UDQM control the input buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to
the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device.
Table" item for details on device commands.
Table" item for details on device commands.
Page 70
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-10
Q282 : ES29LV400 (4 Mbit Flash Memory)
BLOCK DIAGRAM
RY/BY#
Vcc
Vss
WE#
RESET#
Vcc Detector
Command
Register
Timer/
Counter
Analog Bias
Generator
Write
State
Machine
Sector Switches
TX-SR574
DQ0-DQ15(A-1)
Input/Output
Buffers
Data Latch/
Sense Amps
A<0:17>
CE#
OE#
BYTE#
Chip Enable
Output Enable
Logic
Y-Decoder
X-Decoder
Address Latch
Y-Decoder
Cell Array
Page 71
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-11
Q282 : ES29LV400 (4 Mbit Flash Memory)
PIN CONFIGURATION
TX-SR574
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TERMINAL DESCRIPTION
ES29LV400
48-Pin Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CE#
A0
Terminal
A0-A17
DQ0-DQ14
DQ15/A-1
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
Vcc
Vss
NC
Description
18 Addresses
15 Data Inputs/Outputs
DQ15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Chip Enable
Output Enable
Write Enable
Hardware Reset Pin, Active Low
Selects 8-bit or 16-bit mode
Ready/Busy Output
3.0 volt-only single power supply
(see Product Selector Guide for speed options and voltage supply tolerances)
Device Ground
Pin Not Connected Internally
Page 72
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-12
Q301 : CS42518 (8-ch Codec with S/PDIF Receiver)-1/4
Q301 : CS42518 (8-ch Codec with S/PDIF Receiver)-2/4
PIN CONFIGURATION
CX_SDIN2
CX_SDIN3
CX_SDIN4
SAI_SCLK
SAI_LRCK
OMCK
ADCIN1
ADCIN2
CX_SDOUT
RMCK
SAI_SDOUT
VLS
CX_SDIN1
CX_SCLK
CX_LRCK
VD
DGND
VLC
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
INT
RST
AINR-
AINR+
AINL+
AINL-
646362616059585756555453525150
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS42518
DGNDVDTXP
RXPO
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TX-SR574
RXP1/GP01
RXP1/GP01
RXP1/GP01
RXP1/GP01
RXP1/GP01
RXP1/GP01
RXP1/GP01
VARX
AGND
LPFLT
MUTEC
AOUTA1-
AOUTA1+
AOUTB1+
AOUTB1-
AOUTA2-
171819202122232425262728293031
VQ
FILT+
REFGND
AOUTB4-
AOUTB4+
VA
AOUTA4-
AOUTA4+
AGND
AOUTB3-
AOUTA3-
AOUTB3+
AOUTA3+
32
AOUTB2-
AOUTB2+
AOUTA2+
TERMINAL DESCRIPTION(1/3)
Pin Name#Pin Description
Codec Serial Audio Data Input (Input) - Input for two's complement serial audio data.
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
CX_SCLKCODEC Serial Clock (Input/Output) - Serial clock for the CODEC serial audio interface
CX_LRCK
VD
DGND
VLC
SCL/CCLK
SDA/CDOUT
AD1/CDIN
1
64
63
62
2
3
CODEC Left Right Clock (Input/ Output) - Determines which channel, Left or Right, is currently active on
the CODEC serial audio data line.
4
Digital Power (Input) - Positive power supply for the digital section.
51
5
Digital Ground (Input) - Ground reference. Should be connected to digital ground.
52
6
Control Port Power (Input) - Determines the required signal level for the control port.
7
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage in I2C mode as shown in the Typical Connection Diagram.
8
Serial Control Data (Input/Output) - SDA is a data I/O line in IC mode and requires an external pull-up
resistor to the logic interface voltage, as shown in the Typical connection Diagram. CDOUT is the output
data line for the control port interface in SPI mode.
Address Bit 1 (I2C)/Serial Control Data (SPI) (Input) - AD1 a chip address pin in I2C mode; CDIN is
9
the input data line for control port interface in SPI mode.
Page 74
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-14
Q301 : CS42518 (8-ch Codec with S/PDIF Receiver)-3/4
TERMINAL DESCRIPTION(2/3)
Pin Name#Pin Description
AD0/CS10Address Bit 0 (I2C)/Control Port Chip Select (SPI) (INput) - AD0 is a chip address pin in I2C mode; CS
is the chip select signal in SPI mode.
INT11Interrupt (Ountput) - The CS42518 will generate an interrupt condition as per the Interrupt Mask register.
RST12Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
AINRAINR+
AINLAINL+
VQ17Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
FILT+18Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
REFGND19Reference Ground (Input) - Ground reference for the internal sampling circuits.
Differential right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
modulators via the AINR+/- pins.
Differential right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
modulators via the AINR+/- pins.
Differential Analog Output (Output) - The full-scale differential analog output level is specified in the
Analog Characteristics specification table.
Analog Power (Input) - Positive power supply for the analog section.
Analog Ground (Input) - Ground reference. Should be connected to analog ground.
dition or whenever the PDN bit is set to a "1", forcing the codec into power -down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected "active" state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not mandatoy but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
S/PDIF Receiver Input/ General Purpose Output (Input/ Output) - Receiver inputs for S/PDIF encoded
data. The CS42518 has an internal 8:2 multiplexer to select the active receiver port, according to the
Receiver Mode Control 2 resister. These pins can also be configured as general purpose output pins,
ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control
resisters.
receiver inputs as indicated by the Receiver Mode Control 2 resister.
Serial Audio Interface Serial Data Output (Output) - Output for two's complement serial audio PCM
data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the internal and external ADCs.
TX-SR574
Page 75
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-15
Q301 : CS42518 (8-ch Codec with S/PDIF Receiver)-4/4
TERMINAL DESCRIPTION(3/3)
Pin Name#Pin Description
CL_SDOUT56CODEC Serial Data Output (Output) - Output for two's complement serial audio data the internal
and external ADCs.
ADCIN1
ADCIN2
OMCK59External Reference Clock (Input) - External clock reference that must be within the ranges specified in
SAI_LRCK60Serial Audio Interface Left/Right Clock (Input/Output) - Determines which channel, Left of Right, is
SAI_LRCK61Serial Audio Interface Serial Clock (Input/Output) - Serial clock for the Serial Audio Interface
58
57
External ADC Serial Input (Input) - The CS42518 provides for up two external stereo analog to digital
converter inputs to provide a maximum of six channels on serial data output line when the CS42518
is placed in One Line mode.
currently active on the serial audio data line.
currently active on the serial audio data line.
TX-SR574
Page 76
TX-SR574
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-16
Q4001 : ADV7183
(Advanced Video Decoder with 10-Bit ADC and Component Input Support)-1/3
(Advanced Video Decoder with 10-Bit ADC and Component Input Support)-2/3
TERMINAL DESCRIPTION (1/2)
PinMnemonicInput/OutputFunction
1VS/VACTIVEOVS or Vertical Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is an
output signal that indicates a vertical sync with respect to the YUV pixel
data. The active period of this signal is six lines of video long. The polarity
of the VS signal is controlled by the PVS bit. VACTIVE (OM_SEL[1:0] =
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video field. The polarity of VACTIVE is controlled by PVS bit.
11AFFOAlmost Full Flag. A FIFO control signal indicating when the FIFO has
12HFF/QCLK/GLI/OHalf Full Flag. A multifunction pin, (OM_SEL[1:0] = 1, 0) is a FIFO
13AEFOAlmost Empty Flag. A FIFO control signal, it indicates when the FIFO
16CLKINIAsynchronous FIFO Clock. This asynchronous clock is used to output
17, 18, 34, 35 GPO[3:0]OGeneral-Purpose Outputs controlled via I C
25LLCREFOClock Reference Output. This is a clock qualifier distributed by the inter-
26LLC2OLine-Locked Clock System Output Clock/2 (13.5 MHz)
27LLC1/PCLKOLine-Locked Clock System Output Clock. A dual-function pin (27 MHz 5%)
28XTAL1OSecond terminal for crystal oscillator; not connected if external clock
29XTALIInput terminal for 27MHz crystal oscillator or connection for external
36PWRDNIPower-Down Enable. A logical low will place part in a power-down status.
37ELPFIThis pin is used for the External Loop Filter that is required for the LLC PLL.
38PVDD
39PVSSG
P
HS or Horizontal Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is a
programmable horizontal sync output signal. The rising and falling edges
can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The polarity
of the HS signal is controlled by the PHS bit. HACTIVE (OM_SEL[1:0]=
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video line. The active portion of a video line is programmable on
the ADV7183. The polarity of HACTIVE is controlled by PHS bit.
16-bit YCrCb pixel port (P15-P8 = Y and P7-P0 = Cb,Cr).
reached the almost full margin set by the user (use FFM[4:0]). The polarity
of this signal is controlled by the PFF bit.
control signal that indicates when the FIFO is half full. The QCLK
(OM_SEL[1:0] = 0, 1) pin function is a qualified pixel output clock when
using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0, 0) function
(Genlock output) is a signal that contains a serial stream of data that contains
information for locking the subcarrier frequency. The polarity of HFF signal
is controlled by PFF bit.
has reached the almost empty margin set by the user (use FFM[4:0]). The
polarity of this signal is controlled by PFF bit.
data onto the P19-P0 bus and other control signals.
2
nal CGC for a data rate of LLC2. The polarity of LLCREF is controlled
by the PLLCREF bit.
or a FIFO output clock ranging from 20 MHz to 35 MHz.
source is used.
oscillator with CMOS-compatible square wave clock signal
Page 78
TX-SR574
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-18
Q4001 : ADV7183
(Advanced Video Decoder with 10-Bit ADC and Component Input Support)-3/3
TERMINAL DESCRIPTION (2/2)
PinMnemonicInput/OutputFunction
40, 47, 53, 56,
63
41, 43, 45, 57,
59, 61
42, 44, 46, 58,
60, 62
48, 49
50
51
52
54, 55
64
65
66
67
68
69
70
77
78
79
80
AVSS
AVSS1-6
AIN1-6
CAPY1-2
AV D D
REFOUT
CML
CAPC1-2
RESET
ISO
ALSB
SDATA
SCLK
VREF/VRESET
HREF/HRESET
RD
DV
OE
FIELD
G
G
I
I
P
O
O
I
I/O
I
I
I/O
I
O
O
I
O
I
O
Ground for Analog Supply
Analog Input Channels. Ground if single-ended mode is selected. These
pins should be connected directly to REFOUT when differential mode is
selected.
Video Analog Input Channels
ADC Capacitor Network
Analog Supply Voltage (5 V)
Internal Voltage Reference Output
Common-Mode Level for ADC
ADC Capacitor Network
System Reset Input. Active Low.
Input Switch Over. A low to high transition on this input indicates to the
decoder core that the input video source has been changed externally and
configures the decoder to reacquire the new timing information of the new
source. This is useful in applications where external video muxes are used.
This input gives the advantage of faster locking to the external muxed
video sources. A low to high transition triggers this input.
TTL Address Input. Selects the MPU address:
MPU address = 88h ALSB = 0, disables I C filter
MPU address = 8Ah ALSB = 1, enables I C filter
MPU Port Serial Data Input/Output
MPU Port Serial Interface Clock Input
VREF or Vertical Reference Output Signal. Indicates start of next field.
VRESET or Vertical Reset Output is a signal that indicates the beginning
of a new field. In SCAPI/CAPI mode this signal is one clock wide and
active low relative to CLKIN. It immediately follows the HRESET pixel,
and indicates that the next active pixel is the first active pixel of the next field.
HREF or Horizontal Reference Output Signal. A dual-function pin
(enabled when Line-Locked Interface is selected, OM_SEL[1:0] = 0,0),
this signal is used to indicate data on the YUV output. The positive slope
indicates the beginning of a new active line; HREF is always 720 Y samples
long. HRESET or Horizontal Reset Output (enabled when SCAPI or
CAPI is selected, OM_SEL[1:0] = 0, 1 or 1, 0) is a signal that indicates the
beginning of a new line of video. In SCAPI/CAPI this signal is one clock
cycle wide and is output relative to CLKIN. It immediately follows the last
active pixel of a line. The polarity is controlled via PHVR.
Asynchronous FIFO Read Enable Signal. A logical high on this pin enables
a read from the output of the FIFO.
DV or Data Valid Output Signal. In SCAPI/CAPI mode, DV performs to
functions, depending on whether SCAPI or CAPI is selected. It toggles
high when the FIFO has reached the AFF margin set by the user, and
remains high until the FIFO is empty. The alternative mode is where it can
be used to control FIFO reads for bursting information out of the FIFO. In
API mode DV indicates valid data in the FIFO, which includes both pixel
information and control codes. The polarity of this pin is controlled via PDV.
Output Enable Controls Pixel Port Outputs. A logic high will three-state
P19-P0.
ODD/EVEN Field Output Signal. An active state indicates that an even
field is being digitized. The polarity of this signal is controlled by the PF bit.
2
2
Page 79
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -19
Q4002 : AN15881A (Video SW for TV with Multi-signal 14 Inputs and 4 Outputs)
BLOCK DIAGRAM
TX-SR574
V1
V2
V3
V4
V5
V6
V7
V8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
C1
C2
C3
C4
C5
C6
C7
C8
4/6dB
6dB
4/6dB
6dB
4/6dB
6dB
Buf
75<E
75<E
75<E
Buf
75<E
75<E
75<E
Buf
75<E
75<E
75<E
Vout1
Vout2
Vout2-FB
Vout3
Vout3-FB
Vout4
Vout4-FB
Yout1
Yout2
Yout2-FB
Yout3
Yout3-FB
Yout4
Yout4-FB
Cout4
Cout1
Cout2
Cout3
CY1
CY2
CY3
CY4
CY5
CY6
PB1
PB2
PB3
PB4
PB5
PB6
PR1
PR2
PR3
PR4
PR5
PR6
SDA
SCL
O1 O2
Logic
6dB
6dB
6dB
6dB
6dB
6dB
BIAS
75<E
75<E
75<E
75<E
75<E
75<E
VCCGNDMUTE
CYout2
CYout2-FB
CYout3
CYout3-FB
PBout1
PBout2
PRout1
PRout2
Page 80
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -20
Q4002: AN15881A (Video SW for TV with Multi-signal 14 Inputs and 4 Outputs)
TERMINAL DESCRIPTION (1/3)
De sc rip tio nTypePin namePin No.
Luminance signal input 3InY31
Luminance signal input 4InY42
Luminance signal input 5InY53
Luminance signal input 6InY64
Luminance signal input 7InY75
Luminance signal input 8InY86
5.0V power supplyPower supplyVCC17
Chrominance signal inpu t 1InC18
Chrominance signal inpu t 2InC29
Chrominance signal inpu t 3InC310
Chrominance signal inpu t 4InC411
Chrominance signal inpu t 5InC512
GroundGroundGND113
Chrominance signal inpu t 6InC614
Chrominance signal input 7InC715
Chrominance signal input 8InC816
TX-SR574
Bias voltageOutputBIAS17
CY1 signal inputInCY118
CY2 signal inputInCY219
CY3 signal inputInCY320
CY4 signal inputInCY421
CY5 signal inputInCY522
CY6 signal inputInCY623
PB1 signal inputInPB124
PB2 signal inputInPB225
PB3 signal inputInPB326
PB4 signal inputInPB427
PB5 signal inputInPB528
PB6 signal inputInPB629
PR1 signal inputInPR130
PR2 signal inputInPR231
PR3 signal inputInPR332
PR4 signal inputInPR433
PR5 signal inputInPR534
PR6 signal inputInPR635
Page 81
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -21
Q4002: AN15881A (Video SW for TV with Multi-signal 14 Inputs and 4 Outputs)
TERMINAL DESCRIPTION (2/3)
DescriptionTypePin namePin No.
Mute control pinInMUTE36
PROUT2 signal outputOutPROUT237
General output 1OutO138
PROUT1 signal outputOutPROUT139
General output 2OutO240
PBOUT2 signal outputOutPBOUT241
PBOUT1 signal outputOutPBOUT142
GroundGroundGND243
CYOUT3 feedback inputInCYOUT3-FB44
CYOUT3 signal outputOutCYOUT345
CYOUT2 feedback inputInCYOUT2-FB46
CYOUT2 signal outputOutCYOUT247
COUT4 signal outputOutCOUT448
5.0V power supplyPower supplyVCC249
COUT3 signal outputOutCOUT350
COUT2 signal outputOutCOUT251
COUT1 signal outputOutCOUT152
GroundGroundGND353
YOUT4 feedback inputInYOUT4-FB54
YOUT4 signal outputOutYOUT455
YOUT3 feedback inputInYOUT3-FB56
YOUT3 signal outputOutYOUT357
YOUT2 feedback inputInYOUT2-FB58
YOUT2 signal outputOutYOUT259
YOUT1 signal outputOutYOUT160
5.0V power supplyPower supplyVCC361
VOUT4 feedback inputInVOUT4-FB62
VOUT4 signal outputOutVOUT463
2
I
C bus data inputInSDA64
VOUT3 feedback inputInVOUT3-FB65
VOUT3 signal outputOutVOUT366
VOUT2 feedback inputInVOUT2-FB67
VOUT2 signal outputOutVOUT268
VOUT1 signal outputOutVOUT169
2
I
C bus clock inputInSCL70
TX-SR574
Page 82
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -22
Q4002: AN15881A (Video SW for TV with Multi-signal 14 Inputs and 4 Outputs)
TERMINAL DESCRIPTION (3/3)
DescriptionTypePin namePin No.
Video composite si gnal input 1InV171
Video composite si gnal input 2InV272
Video composite signal input 3InV373
Video composite signal input 4InV474
Video composite si gnal input 5InV575
Video composite si gnal input 6InV676
Video composite si gnal input 7InV777
Video composite signal input 8InV878
Luminance signal input 1InY179
Luminance signal input 2InY280
TX-SR574
PIN CONFIGURATION
SCL
V1
V2
V3
V4
V5
V6
V7
V8
Y1
Y2
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VOUT3-FB
VOUT3
VOUT2-FB
VOUT2
VOUT1
SDA
64
1
Y3
VOUT4
63
2
Y4
VOUT4-FB
VCC3
626160
3
4
Y5
Y6
YOUT1
5
Y7
YOUT3
YOUT2
YOUT2-FB
YOUT3-FB
59585756555453
6
789
C1
Y8
VCC1
YOUT4
YOUT4-FB
COUT1
GND3
525150
AN15881A
10
C3C2C5
11
C4
12
13
GND1
COUT2
14
C6
VCC2
COUT4
COUT3
48
49
17
15
16
C8
C7
BIAS
CYOUT2-FB
CYOUT2
474645
181920
CY1
CY2
CYOUT3
CY3
CYOUT3-FB
444342
212223
CY4
PBOUT1
GND2
CY5
CY6
PBOUT2
41
40
O2
39
PROUT1
38
O1
37
PROUT2
36
MUTE
35
PR6
34
PR5
33
PR4
32
PR3
31
PR2
30
PR1
29
PB6
28
PB5
27
PB4
26
PB3
25
PB2
24
PB1
Page 83
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -23
Q4003: ADV7172 (Digital PAL/NTSC Video Encoder with six DACs)
BLOCK DIAGRAM
TX-SR574
FIELD/
TTX
TTXREQ
V
AA
P0
COLOR
DATA
P7
PAL
CLOCK
4:2:2 TO
4:4:4
INTER-
POLATOR
NTSC
VIDEO TIMING
GENERATOR
TELETEXT
INSERTION BLOCK
8
YCrCb
8
TO
YUV
MATRIX
8
Y
8
U
8
V
8
CLAMP
SCLOCK SDATA
I2C MPU PORT
BRIGHTNESS AND
CONTRAST CONTROL
SATURATION CONTROL
+
ADD SYNC
+
INTERPOLATOR
+
ADD BURST
+
INTERPOLATOR
CONTROL CIRCUIT
REAL-TIME
SCRESET/RTC
ALSB
PROGRAMMABLE
10
SHARPNESS
10
PROGRAMMABLE
CHROMA
10
LUMA
FILTER
+
FILTER
FILTER
GND
YUV TO
RBG
MATRIX
+
YUV
LEVEL
CONTROL
BLOCK
MODULATOR
+
HUE
CONTROL
1010
SIN/COS
DDS BLOCK
M
10
10
U
10-BIT
L
DAC
T
10
10
I
10-BIT
P
DAC
L
E
10
10
10-BIT
X
DAC
E
R
DAC
CONTROL
M
BLOCK
U
L
10
10-BIT
T
I
P
L
E
X
E
R
10
10-BIT
10
10-BIT
DAC
CONTROL
BLOCK
DAC
DAC
DAC
10
10
10
DAC A
DAC B
DAC C
V
REF
R
SET2
COMP2
DAC E
DAC F
DAC D
R
SET1
COMP1
PIN CONFIGURATION
V
AA
P0
P1
P2
P3
P4
P5
P6
P7
CSO_HSO
V
AA
GND
AA
RESET
VSO
CLOCK
GND
48 47 46 45 4439 38 3743 42 41 40
1
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
GND
HSYNC
V
BLANK
PAL NTSC
CLAMP
ADV7172
TOP VIEW
V
GND
ALSB
TTX
AA
SCLOCK
FIELD/VSYNC
SET1
R
SCRESET/RTC
TTXREQ
SET2
R
SDATA
COMP2
REF
V
DAC F
36
35
34
33
32
31
30
29
28
27
26
25
COMP1
DAC A
V
AA
DAC B
V
AA
GND
V
AA
DAC C
DAC D
V
AA
GND
DAC E
Page 84
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -24
Q4003: ADV7172 (Digital PAL/NTSC Video Encoder with six DACs)
TERMINAL DESCRIPTION
TX-SR574
Mnemonic
Input/OutputFunction
P7–P0I8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7ÐP0) P0 represents the LSB.
CLOCKITTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alter-
natively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
HSYNC
FIELD/VSYNCI/ODual Function FIELD (Mode 1) and
I/O
HSYNC
(Modes 1 and 2) Control Signal. This pin may be configured to output (Master
Mode) or as an input and accept (Slave Mode) Sync signals.
VSYNC
configured to output (Master Mode) or as an input (Slave Mode) and accept these
(Mode 2) Control Signal. This pin may be
control signals.
BLANK
I/OVideo Blanking Control Signal. The pixel inputs are ignored when this is Logic Level "0."
This signal is optional.
SCRESET/RTCIThis pin can be configured as an input by setting MR42 and MR41 of Mode Register 4. It
can be configured as a subcarrier reset pin, in which case a low-to-high transition on this
pin will reset the subcarrier phase to Field 0. Alternatively it may be configured as a Real-
Time Control (RTC) Input.
V
R
REF
SET1
I/OVoltage Reference Input for DACs or Voltage Reference Output (1.235 V).
IA 150 resistor connected from this pin to GND is used to control full-scale amplitudes of
the Video Signals from DACs A, B, and C (the "large" DACs).
R
SET2
IA 600 resistor connected from this pin to GND is used to control full-scale amplitudes of
the Video Signals from DACs D, E, and F (the "small" DACs).
COMP1OCompensation Pin for DACs A, B, and C. Connect a 0.1 uF Capacitor from COMP to
. For Optimum Dynamic Performance in Low Power Mode, the value of the
V
AA
COMP1 capacitor can be lowered to as low as 2.2 nF.
COMP2OCompensation Pin for DACs D, E, and F. Co nnect a 0.1 uF Capacitor from COMP to V
AA
.
DAC AOGREEN/Composite/Y Analog Output. This DAC is capable of providing 34.66 mA output.
DAC BOBLUE/S-Video Y/U Analog Output. This DAC is capable of providing 34.66 mA output.
DAC CORED/S-Video C/V Analog Output. This DAC is capable of providing 34.66 mA output.
DAC DOGREEN/Composite/Y Analog Output. This DAC is capable of providing 8.66 mA output.
DAC EOBLUE/S-Video Y/U Analog Output. This DAC is capable of providing 8.66 mA output.
DAC FORED/S-Video C/V Analog Output. This DAC is capable of providing 8.66 mA output.
SCLOCKIMPU Port Serial Interface Clock Input.
SDATAI/OMPU Port Serial Data Input/Output.
CLAMPOTTL Output Signal to external circuitry to enable clamping of all video signals.
PAL_NTSCIInput signal to select PAL or NTSC mode of operation, pin set to Logic "1" selects PAL.
VSO
CSO_HSO
O VSO TTL Output Sync Signal.
ODual Function
or HSO TTL Output Sync Signal.
CSO
ALSBITTL Address Input. This signal sets up the LSB of the MPU address.
RESET
IThe input resets the on-chip timing generator and sets the ADV7172/ADV 7173 into
default mode. This is NTSC operation, Timing Slave Mode 0, DACs A, B, and C powered
OFF, DACs D, E, and F powered ON, Composite and S-Video out.
TTXITeletext Data Input Pin.
TTXREQOTeletext Data Request output signal used to control teletext data transfer.
V
AA
GND
PPower Supply (3 V to 5 V).
G
Ground Pin.
Page 85
TX-SR574
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-25
Q5501 : R2S15211FP (8 ch Electronic Volume and 11 Input Selector and Tone Control)-1/3
SYSTEM BLOCK DIAGRAM
Multi
Rin
Multi
Lin
Out L
ADC
Out R
for
ADC
for
Volume
Volume
Multi
SBLin
Multi
SBRin
Multi
Cin
Multi
SWin
Multi
SLin
Multi
SRin
Rch Tone
Bass &
Treble
Treble
Bass &
Treble
Tone
Lch Tone
Volume
Volume
CLOCKDATA
Volume
Volume
MCU I/F
Volume
Volume
Volume
Volume
Volume
Volume
Lout
Rout
SBLout
SBRout
Cout
SWout
SLout
SRout
Lch
mono
Rch
REC
1
2
3
4
5
6
7
8
9
10
11
Input selector
SUB
Input
ATT
1
2
3
4
5
6
7
8
9
10
11
Input selector
Input
ATT
REC
SUB
AGND
AVEE
AVCC
Page 86
TX-SR574
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-26
Q5501 : R2S15211FP (8 ch Electronic Volume and 11 Input Selector and Tone Control)-2/3
BLOCK DIAGRAM AND PIN CONFIGURATION
2
1
DGND
DATA
CLOCK
AVEE
INR1
INL1
INR2
INL2
INR3
INL3
INR4
INL4
INR5
INL5
41
42
43
44
45
46
47
48
49
50
51
52
53
54
I/F
MCU
40
MONO
MAIN
SUBL
39
SUB
38
SUBR
ADCR
37 36
ATT
ADCL
35
0/-6/-12/-18dB
FRIN2
FLIN2
3433
SRIN2
32
SLIN2
31
Bass/ Treble
0~-95dB,
(1dBstep)
SWIN2
CIN2
29
30
-14~+14dB
(2dB step)
0~-95dB
(1dBstep)
SBRIN2
28
Tone
-14~+14dB
(2dB step)
+16~-95dB
(1dBstep)
+16~-95dB
(1dBstep)
+16~-95dB
(1dBstep)
SBLIN2
TRER
27
Tone
Bass/ Treble
BASSR
26
+16~0dB
(1dBstep)
BASSR
25
+16~0dB
(1dBstep)
AVCC
24
AVCC
23
TREL
22
BASSL2
21
BASSL1
FRC
20
FROUT
19
AGND
18
FLOUT
17
16
FLC
15
6-C
6-OUT (SR OUT)
14
AGND
13
5-OUT (SL OUT)
12
5-C
11
INR6
INL6
INR7
INL7
INR8
INL8
INRA/RECR1
INLA/RECL1
INR9
INL9
55
56
57
58
59
60
61
62
63
64
6566
INRB/RECR2
REC
67
INLB/RECL2
INR10/RECR4
68
697071
INL10/RECL4
INR11/RECR5
72
RECR3
INL11/RECL5
73
RECL3
747576
FLIN1
FRIN1
CIN1
+16~-95dB
(1dBstep)
+16~-95dB
(1dBstep)
+16~-95dB
(1dBstep)
77
SWIN1
7879
SLIN1
4-C
10
4-OUT (SW OUT)
9
AGND
8
3-OUT (C OUT)
7
3-C
6
2-C
5
2-OUT (SBR OUT)
4
AGND
3
1-OUT (SBL OUT)
2
1-C
1
80
SRIN1
SBLIN1
SBRIN1
Page 87
TX-SR574
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-27
Q5501 : R2S15211FP (8 ch Electronic Volume and 11 Input Selector and Tone Control)-3/3