H. DESCRIPTION OF MECHANISM
C-700 Ultra Zoom
H. DESCRIPTION OF MECHANISM
[1] CA1 CIRCUIT DESCRIPTION ................................................................................ H-2
[2] CA2 CIRCUIT DESCRIPTION ................................................................................ H-5
[3] ST1 POWER CIRCUIT DESCRIPTION ..................................................................H-7
[4] ST1 STROBE CIRCUIT DESCRIPTION................................................................. H-8
[5] SYA CIRCUIT DESCRIPTION ................................................................................ H-9
H-1 Ver.1
H. DESCRIPTION OF MECHANISM C-700 Ultra Zoom
[1] CA1 CIRCUIT DESCRIPTION
1. IC Configuration
IC903 (ICX284AK) CCD imager
IC902 (74ACT04MTC) H driver
IC904 (CXD3400N) V driver
IC905 (AD9806) CDS, AGC, A/D converter
2. IC903 (CCD)
[Structure]
Interline type CCD image sensor
Optical size 1/2.7 type
Effective pixels 1636 (H) X 1236 (V)
Pixels in total 1688 (H) X 1248 (V)
Optical black
Horizontal (H) direction: Front 4 pixels, Rear 48 pixels
Vertical (V) direction: Front 10 pixels, Rear 2 pixels
Dummy bit number Horizontal : 28 Vertical :1
(only even number field)
Pin 1
2
3A
φ
V
1
φ
H
4
φ
V
1
(Note)
16
2
φ
H
1B
φ
OUT
V
7
8
9
10
DD
V
φ
V
GND
6
Ye
Ye
Ye
Vertical register
11
SUB
GND
φ
V
4
5
Cy
G
Mg
Cy
Mg
G
Cy
G
Mg
Horizontal register
13
12
SUB
C
(Note) : Photo sensor
φ
φ
V
V
3
2
Ye
Cy
G
Mg
Ye
Cy
G
Mg
Ye
Cy
G
Mg
14
RG
φ
15
L
V
3B
2
1A
V
4
Pin 11
H
48
Fig. 1-1.Optical Black Location (Top View)
Pin No.
1
2, 3
4
5, 6
7, 10
8
9
11
12
13
14
15
16
Symbol
V
φ
V
3A, Vφ3B
V
φ
V
1A, Vφ1B
GND
OUT
V
VDD
φ
SUB
SUB
C
VL
φ
RG
H
H
φ
Vertical register transfer clock
4
Vertical register transfer clock
φ
Vertical register transfer clock
2
Vertical register transfer clock
GND
Signal output
Circuit power
Substrate clock
Substrate bias
Protection transistor bias DC
Reset gate clock
φ
Horizontal register transfer clock
1
φ
Horizontal register transfer clock
2
Pin Description
10
Fig. 1-2. CCD Block Diagram
Waveform
GND 0 V
DC
DC
DC
Voltage
-7.5 V, 0 V
-7.5 V, 0 V, 15 V
-7.5 V, 0 V
-7.5 V, 0 V, 15 V
Aprox. 10 V
15 V
Aprox. 8 V
Aprox. 8V
(Different from every CCD)
12.5 V, 16 V
0 V, 3.3 V
0 V, 3.3 V
Table 1-1. CCD Pin Description
H-2 Ver. 1
When sensor read-out
H. DESCRIPTION OF MECHANISMC-700 Ultra Zoom
3. IC902 (H Driver) and IC904 (V Driver)
An H driver (IC902) and V driver (IC904) are necessary in
order to generate the clocks (vertical transfer clock, horizontal transfer clock and electronic shutter clock) which
driver the CCD.
IC902 is an inverter IC which drives the horizontal CCDs
(H1 and H2). In addition the XV1-XV4 signals which are
output from IC102 are the vertical transfer clocks, and the
XSG1 and XSG signal which is output from IC102 is superimposed onto XV1 and XV3 at IC904 in order to generate a
ternary pulse. In addition, the XSUB signal which is output
from IC102 is used as the sweep pulse for the electronic
shutter, and the RG signal which is output from IC102 is
the reset gate clock.
14
CC
1A
1Y
2A
2Y
3A
1
2
3
4
5
V
13
6A
12
6Y
11
5A
10
5Y
4. IC905 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to
Pins (26) and (27) of IC905. There are S/H blocks inside
IC905 generated from the XSHP and XSHD pulses, and it
is here that CDS (correlated double sampling) is carried
out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally
into a 10-bit signal, and is then input to IC102 of the CA2
circuit board.
CCDIN
CLPDM
DAC1
DAC2
PBLK
0-34 dB
CDS
CLAMP
8B DAC
8B DAC
PGA
10B DAC
INTF
3
3-W INTF ADCIN
Fig. 1-5. IC905 Block Diagram
MUX
PGA
AUXIN
CLP B
CLP
S/H
0-15 dB
CLAMP
AD9806
ADC
REF
TIMING
GENERAT R
SHD
ADCCLK
SHP
10
DOUT
VRT
VRB
6
3Y
7
GND
Fig. 1-3. IC902 Block Diagram
V
DD
1
Input
Buffer
2
3
4
5
6
7
8
9
10
XSHT
XV3
XSG3B
XSG3A
XV1
XSG1B
XSG1A
XV4
XV2
9
8
SHT
V3B
V
V3A
V1B
V
V1A
V4
V2
GND
4A
4Y
20
19
L
18
17
16
H
15
14
13
12
11
Ver. 1
Fig. 1-4. IC904 Block Diagram
H-3
H. DESCRIPTION OF MECHANISM C-700 Ultra Zoom
5. Transfer of Electric Charge by the Horizontal CCD
The transfer system for the horizontal CCD emplays a 2-phase drive method.
The electric charges sent to the final stage of the horizontal CCD are transferred to the floating diffusion, as shown in Fig. 1-
6. RG is turned on by the timing in (1), and the floating diffusion is charged to the potential of PD. The RG is turned off by the
timing in (2). In this condition, the floating diffusion is floated at high impedance. The H1 potential becomes shallow by the
timing in (3), and the electric charge now moves to the floating diffusion.
Here, the electric charges are converted into voltages at the rate of V = Q/C by the equivalent capacitance C of the floating
diffusion. RG is then turned on again by the timing in (1) when the H1 potential becomes deep.
Thus, the potential of the floating diffusion changes in proportion to the quantity of transferred electric charge, and becomes
CCD output after being received by the source follower. The equivalent circuit for the output circuit is shown in Fig. 1-7.
(1)
H1 H2 H1 H2 H1 HOG RG
CCD OUT
Floating diffusion
(2)
H1 H2 H1 H2 H1 HOG RG
PD
H1
H2
CCD OUT
PD
RG
(1) (2) (3)
3.5V
0V
3.5V
0V
13.5V
0V
(3)
H1 H2 H1 H2 H1 HOG RG
Reset gate pulse
Direction of transfer
H Register
Electric
charge
Floating diffusion gate is
floated at a high impedance.
CCD OUT
CCD OUT
Fig. 1-6. Horizontal Transfer of CCD Imager and Extraction of Signal Voltage
The shutter hold signal(VCTRL) which is output from the
12V Pre-charge drain bias (PD)
ASIC (IC102) is restricted the shutter electric current. (maintenance electric current)
6-2. Iris drive
The iris stepping motor drive signals (ACTRL1, ACTRL2,
ACTRL3 and ACTRL4) which are output from the ASIC
(IC102) are used to drive by the motor driver (IC954). Detection of the standard iris positions is carried out by means
Voltage output
of the photointerruptor (PI2) inside the lens block.
6-3. Focus drive
The focus stepping motor drive signals (LDIN1, LDIN2, LDIN3
C is charged
equivalently
and LDIN4) which are output from the ASIC expansion port
(IC107) are used to drive by the motor driver (IC953). Detection of the standard focusing positions is carried out by
means of the photointerruptor (PI) inside the lens block.
RG pulse leak signal
Signal voltage
Black level
Fig. 1-7. Theory of Signal Extraction Operation
6. Lens drive block
6-1. Shutter drive
The shutter drive signal (PCTRL) which is output from the
ASIC expansion port (IC106) is drived the shutter constant
level driver, and then shutter plunger is opened and closed.
6-4. Zoom drive
The zoom stepping motor drive signals (ZIN1, ZIN2, ZIN3
and ZIN4) which are output from the ASIC expansion port
(IC107) are used to drive by the motor driver (IC953). Detection of the zoom positions is carried out by means of
photoreflector (PR1 and PR2) inside the lens block.
H-4 Ver. 1