NEC UPA1852GR-9JG Datasheet

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

N-CHANNEL MOS FIELD EFFECT TRANSISTOR

FOR SWITCHING

PA1852

µµµµ

DESCRIPTION

The µPA1852 is a switching device which can be
driven directly by a 2.5
The

PA1852 features a low on-state resistance and

µ

-

V power source.

excellent switching characteristics, and is suitable for
applications such as power switch of portable machine
and so on.

FEATURES

Can be driven by a 2.5-V power source

•

Low on-state resistance

•

DS(on)1

R

= 40 mΩ MAX. (VGS = 4.5 V, ID = 3.0 A)

DS(on)2

R

= 45 mΩ MAX. (VGS = 4.0 V, ID = 3.0 A)

DS(on)3

R

= 60 mΩ MAX. (VGS = 2.5 V, ID = 3.0 A)

Built-in G-S protection diode against ESD

•

ORDERING INFORMATION

PART NUMBER PACKAGE

PA1852GR-9JG Power TSSOP8

µ

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

Drain to Source Voltage V
Gate to Source Voltage V
Drain Current (DC) I
Drain Current (pulse)
Total Power Dissipation

Note1

Note2

Channel Temperature T
Storage Temperature T

Notes 1.

PW ≤ 10

2.

Mounted on ceramic substrate of 5000

s, Duty Cycle ≤ 1 %

µ

DSS

GSS

D(DC)

D(pulse)

I

P

ch

stg

T

–55 to +150 °C

20 V

12 V

±

6.0 A

±

24

±

2.0 W

150 °C

mm2 x 1.1 mm

PACKAGE DRAWING (Unit : mm)

85

14

3.15 ±0.15

3.0 ±0.1

0.65

+0.03

0.27

–0.08

A

Gate1

Gate
Protection
Diode

1 :Drain1
2, 3 :Source1
4 :Gate1
5 :Gate2
6, 7 :Source2
8 :Drain2

±0.055

0.145

0.8 MAX.

0.10 M

EQUIVALENT CIRCUIT

Drain1

Body
Diode

Source1

1.2 MAX.

1.0±0.05

3°

0.1±0.05

6.4 ±0.2

4.4 ±0.1

Gate2

Gate
Protection
Diode

+5°
–3°

0.5

0.6

Drain2

Source2

0.25

+0.15
–0.1

1.0 ±0.2

0.1

Body
Diode

Remark

The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. D12803EJ1V0DS00 (1st edition)
Date Published October 1999 NS CP(K)
Printed in Japan

©

1997, 1999

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

µµµµ

PA1852

Drain Cut-off Current I
Gate Leakage Current I
Gate Cut-off Voltage V

DSS

VDS = 20 V, VGS = 0 V10
VGS = ±12 V, VDS = 0 V

GSS

GS(off)VDS

µ

10

±

µ

= 10 V, ID = 1 mA 0.5 0.74 1.5 V

A
A

Forward Transfer Admittance | yfs |VDS = 10 V, ID = 3.0 A110S
Drain to Source On-state Resi stance R

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q

DS(on)1VGS

DS(on)2VGS

R

DS(on)3VGS

R

iss

oss

rss

d(on)

r

d(off)

f

G

GS

GD

F(S-D)IF

rr

rr

= 4.5 V, ID = 3.0 A2940m
= 4.0 V, ID = 3.0 A3145m
= 2.5 V, ID = 3.0 A3960m

Ω
Ω
Ω

VDS = 10 V 420 pF
VGS = 0 V 265 pF
f = 1 MHz 120 pF
VDD = 10 V55ns
ID = 1.5 A 160 ns

GS(on)

V

= 4.0 V 385 ns

RG = 10

Ω

355 ns
VDD = 10 V6nC
ID = 6.0 A2nC
VGS = 4.0 V3nC

= 6.0 A, VGS = 0 V0.74V
IF = 6.0 A, VGS = 0 V20ns
di/dt = 15 A /

s2nC

µ

TEST CIRCUIT 1 SWITCHING TIME TEST CIRCUIT 2 GATE CHARGE

IG = 2 mA

50 Ω

D.U.T.

R

L

V

DD

PG.

V

GS

RG = 10 Ω

0

τ

τ = 1 s

µ

Duty Cycle ≤ 1 %

R

G

D.U.T.

V

L

R

V

Wave Form

V

DD

I

D

Wave Form

GS

GS

0

10 %

V

GS(on)

90 %

PG.

90 %

D

I

10 %

0

t

r

t

d(on)

t

on

90 %

I

D

t

d(off)

10 %

t

f

t

off

2

Data Sheet D12803EJ1V0DS00

TYPICAL CHARACTERISTICS (TA = 25°C)

µµµµ

PA1852

DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA

100

80

60

40

dT - Derating Factor - %

20

0

30

60

TA - Ambient Temperature -

DRAIN CURRENT vs.

25

DRAIN TO SOURCE VOLTAGE

20

15

10

- Drain Current - A

D

I

5

V

90

GS

= 4.5 V

120

˚C

4.0 V

2.5 V

150

FORWARD BIAS SAFE OPERATING AREA

100

Limited

4.5

=

10

DS(on)

GS

R

(@V

1

- Drain Current - A

D

I

0.1

Single Pulse
Mounted on Ceramic
Substrate of 50cm x 1.1mm

D

(FET1) : PD(FET2) = 1:1

P

0.01

0.1
V

DS

TRANSFER CHARACTERISTICS

100

V

DS

= 10 V

10

1

0.1

- Drain Current - A

D

I

0.01

I

D

(pulse)

V)

I

D

(

DC

)

2

1.0

PW

=

1

ms

10

ms

100 ms

DC

10.0 100.0

- Drain to Source Voltage - V

= 125 ˚C

A

T

75 ˚C

25 ˚C

˚C

−25

0

0.20

V

GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE

1.5
V

DS

= 10 V

I

D

= 1 mA

0.4

DS

- Drain to Source Voltage - V

0.6

1

0.5

- Gate to Source Cut-off Voltage - V

GS(off)

0

V

−50
T

ch

- Channel Temperature - ˚C

50 1000

0.8 1

150

0.001
01234

VGS - Gate to Source Voltage - V

FORWARD TRANSFER ADMMITTANCE vs.
DRAIN CURRENT

100

V

DS

= 10 V

TA = −25 ˚C

10

25 ˚C

75 ˚C

125 ˚C

1

| - Forward Transfer Admittance - S

fs

| y

0.1

0.1

1

ID - Drain Current - A

10 100

Data Sheet D12803EJ1V0DS00

3