NEC UPA1850GR-9JG Datasheet

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

P-CHANNEL MOS FIELD EFFECT TRANSISTOR

FOR SWITCHING

PA1850

µµµµ

DESCRIPTION

The µPA1850 is a switching device which can be
driven directly by a 2.5
The

PA1850 features a low on-state resistance and

µ

-

V power source.

excellent switching characteristics, and is suitable for
applications such as power switch of portable machine
and so on.

FEATURES

Can be driven by a 2.5-V power source

•

Low on-state resistance

•

DS(on)1

R

= 115 mΩ MAX. (VGS = –4.5 V, ID = –1.5 A)

DS(on)2

R

= 130 mΩ MAX. (VGS = –4.0 V, ID = –1.5 A)

DS(on)3

R

= 200 mΩ MAX. (VGS = –2.5 V, ID = –1.5 A)

Built-in G-S protection diode against ESD

•

ORDERING INFORMATION

PART NUMBER PACKAGE

PA1850GR-9JG Power TSSOP8

µ

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

Drain to Source Voltage V
Gate to Source Voltage V
Drain Current (DC) I
Drain Current (pulse)
Total Power Dissipation

Note1

Note2

Channel Temperature T
Storage Temperature T

Notes 1.

PW ≤ 10

2.

Mounted on ceramic substrate of 5000

s, Duty Cycle ≤ 1 %

µ

DSS

GSS

D(DC)

D(pulse)

I

P

ch

stg

–10/+5 V

T

–55 to +150 °C

–12 V

2.5

#

1

0

#

2.0 W

150 °C

mm2 x 1.1 mm

PACKAGE DRAWING (Unit : mm)

85

14

3.15 ±0.15

3.0 ±0.1

0.65

+0.03

0.27

–0.08

A
A

Gate1

Gate
Protection
Diode

1 :Drain1
2, 3 :Source1
4 :Gate1
5 :Gate2
6, 7 :Source2
8 :Drain2

±0.055

0.145

0.8 MAX.

0.10 M

EQUIVALENT CIRCUIT

Drain1

Body
Diode

Source1

1.2 MAX.

1.0±0.05

3°

0.1±0.05

6.4 ±0.2

4.4 ±0.1

Gate2

Gate
Protection
Diode

+5°
–3°

0.5

0.6

Drain2

Source2

0.25

+0.15
–0.1

1.0 ±0.2

0.1

Body
Diode

Remark

The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. D11818EJ2V0DS00 (2nd edition)
Date Published January 2000 NS CP(K)
Printed in Japan

The mark ★ shows major revised points.

©

1997, 2000

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

µµµµ

PA1850

Drain Cut-off Current I
Gate Leakage Current I

★

Gate to Source Cut-off Voltage V

★

Forward Transfer Admittance | yfs |VDS = –10 V, ID = –1.5 A 2.0 5.0 S
Drain to Source On-state Resi stance R

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Diode Forward Voltage V

★

Reverse Recovery Time t

★

Reverse Recovery Charge Q

DSS

GSS

GS(off)VDS

DS(on)1VGS

DS(on)2VGS

R

DS(on)3VGS

R

iss

oss

rss

d(on)

r

d(off)

f

G

GS

GD

F(S-D)IF

rr

rr

VDS = –12 V, VGS = 0 V –10
VGS = #10 V, VDS = 0 V

= –10 V, ID = –1 mA –0.5 –1.0 –1.5 V

= –4.5 V, ID = –1.5 A 80 115 m
= –4.0 V, ID = –1.5 A 85 130 m

= –2.5 V, ID = –1.5 A 127 200 m
VDS = –10 V 260 pF
VGS = 0 V 300 pF
f = 1 MHz 45 pF
VDD = –10 V 120 ns
ID = –1.5 A 420 ns

GS(on)

V

= –4.0 V 520 ns

RG = 10

Ω

430 ns
VDD = –10 V 12 nC
ID = –2.5 A 2 nC
VGS = –4.0 V 5 nC

= 2.5 A, VGS = 0 V 0.80 V
IF = 2.5 A, VGS = 0 V 750 ns
di/dt = 10 A /

s 950 nC

µ

A

µ

10

A

µ

#

Ω
Ω
Ω

TEST CIRCUIT 1 SWITCHING TIME

D.U.T.

L

R

R

PG.

GS

(−)

V

0

τ = 1 s

µ

Duty Cycle ≤ 1 %

G

V

DD

τ

V

GS

Wave Form

I

D

Wave Form

TEST CIRCUIT 2 GATE CHARGE

D.U.T.

V

GS

(−)

10 %

0

I

90 %

D

(−)

10 %

0

t

d(on)

r

t

on

t

90 %

V

GS

(on)

PG.

90 %

I

D

t

d(off)

10 %

t

f

t

off

IG = −2 mA

50 Ω

R

L

V

DD

2

Data Sheet D11818EJ2V0DS00

★

TYPICAL CHARACTERISTICS (TA = 25°C)

µµµµ

PA1850

DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA

100

80

60

40

dT - Derating Factor - %

20

0

TRANSFER CHARACTERISTICS

−10
V

DS

= −10 V

−1

−0.1

- Drain Current - A

D

I

−0.01

30

60

90

TA - Ambient Temperature -

= 125 ˚C

A

T

75 ˚C
25 ˚C

˚C

−25

120

˚C

150

FORWARD BIAS SAFE OPERATING AREA

−100

I

D

(pulse)

V)

R

DS(on)

(@V

Limited

−4.0

=

GS

I

D

(

DC

)

−10

−1

- Drain Current - A

D

I

−0.1

Single Pulse
Mounted on Ceramic
Substrate of 5000 mm x 1.1mm

D

(FET1) : PD(FET2) = 1:1

P

−0.01

−0.1

V

DS

GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE

−1.5
V

DS

= −10 V

I

D

= −1 mA

2

−1.0

- Drain to Source Voltage - V

PW

=

10

ms

100 ms

DC

−10.0 −100.0

−1

−0.5

1

ms

−0.001
0 −1 −2 −3

VGS - Gate to Source Voltage - V

FORWARD TRANSFER ADMMITTANCE vs.
DRAIN CURRENT

100

V

DS

= −10 V

TA = −25 ˚C

10

25 ˚C

75 ˚C

125 ˚C

1

| - Forward Transfer Admittance - S

fs

| y

0.1

−1

ID - Drain Current - A

−10 −100−0.1

- Gate to Source Cut-off Voltage - V

GS(off)

0

V

−50
T

ch

- Channel Temperature - ˚C

50 1000

DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT

250

V

GS

= −2.5 V

200

TA = 125˚C

150

100

- Drain to Source On-state Resistance - mΩ

DS(on)

R

50

75˚C
25˚C

−25˚C

−1

D

- Drain Current - A

I

−10 −100−0.1

150

Data Sheet D11818EJ2V0DS00

3