The MC10EP101 is a Quad 4–input OR/NOR gate. The device is
functionally equivalent to the E101. With AC performance faster than
the E101 device, the EP101 is ideal for applications requiring the
fastest AC performance available. All VCC and VEE pins must be
externally connected to power supply to guarantee proper operation.
• 250ps T ypical Propagation Delay
• High Bandwidth to 3 Ghz T ypical
• PECL mode: 3.0V to 5.5V V
• ECL mode: 0V V
with VEE = –3.0V to –5.5V
CC
• 75kΩ Internal Input Pulldown Resistors
• ESD Protection: >4KV HBM, >100V MM
• Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 173 devices
LOGIC DIAGRAM
D
0a
D
0b
D
0c
D
0d
D
1a
D
1b
D
1c
D
1d
with VEE = 0V
CC
Q
0
Q
0
Q
1
Q
1
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32–LEAD TQFP
FA SUFFIX
CASE 873A
MARKING DIAGRAM*
MC10
EP101
AWLYYWW
32
1
*For additional information, see Application Note
AND8002/D
A= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN DESCRIPTION
PIN
D0a–D3d
Q0–Q3, Q0–Q3
VCC
VBBReference Voltage Output
VEENegative, 0 Supply
FUNCTION
ECL Data Inputs
ECL Data Outputs
Positive Supply
D
2a
D
2b
D
2c
D
2d
D
3a
D
3b
D
3c
D
3d
Semiconductor Components Industries, LLC, 1999
March, 2000 – Rev . 1
Q
2
Q
2
Q
3
Q
3
DnaDnbDncDndQnQn
LLLLLH
HXXXHL
XHXXHL
XXHXHL
XXXHHL
HHHHHL
TRUTH TABLE
ORDERING INFORMATION
DevicePackageShipping
MC10EP101FATQFP250 Units/Tray
MC10EP101FAR2TQFP2000 Tape & Reel
1Publication Order Number:
MC10EP101/D
D0c
MC10EP101
2423222120191817
25
D2cD2bD2aD1dD1cD1bD0d D1a
16
D2d
D0b
D0a
VEE
26
27
28
15
14
13
D3a
D3b
VCC
MC10EP101
Q0
Q0
VCC
VCC
29
30
31
32
12345678
Q1
Q2Q2Q1VCC
Figure 1. 32–Lead TQFP Pinout
(Top View)
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
MAXIMUM RATINGS*
SymbolParameterValueUnit
V
EE
V
CC
V
I
V
I
I
out
T
A
T
stg
θ
JA
θ
JC
T
sol
* Maximum Ratings are those values beyond which damage to the device may occur.
Power Supply (VCC = 0V)–6.0 to 0VDC
Power Supply (VEE = 0V)6.0 to 0VDC
Input Voltage (VCC = 0V, VI not more negative than VEE)–6.0 to 0VDC
Input Voltage (VEE = 0V, VI not more positive than VCC)6.0 to 0VDC
Output CurrentContinuous
Surge
Operating Temperature Range–40 to +85°C
Storage Temperature–65 to +150°C
Thermal Resistance (Junction–to–Ambient)Still Air
500lfpm
Thermal Resistance (Junction–to–Case)12 to 17°C/W
Solder Temperature (<2 to 3 Seconds: 245°C desired)265°C
12
11
10
9
VCCQ3Q3
D3c
D3d
VEE
NC
50
100
80
55
mA
°C/W
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2
MC10EP101
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V, VEE = –5.5V to –3.0V) (Note 3.)
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
1. VCC = 0V, VEE = V
2. All loading with 50 ohms to VCC –2.0 volts.
3. Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 1.)
Output HIGH Voltage
(Note 2.)
Output LOW Voltage
(Note 2.)
Input HIGH Voltage Single Ended–1210–885–1145–820–1085–760mV
Input LOW Voltage Single Ended–1935–1610–1870–1545–1810–1485mV
Input HIGH Current150150150µA
Input LOW Current–150–150–150µA
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
EEmin
to V
, all other pins floating.
EEmax
DC CHARACTERISTICS, LVPECL (VCC = 3.3V ± 0.3V, VEE = 0V) (Note 6.)
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
4. VCC = 3.0V, VEE = 0V, all other pins floating.
5. All loading with 50 ohms to VCC –2.0 volts.
6. Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 4.)
Output HIGH Voltage
(Note 5.)
Output LOW Voltage
(Note 5.)
Input HIGH Voltage Single Ended209024152155248022152540mV
Input LOW Voltage Single Ended136516901430175514901815mV
Input HIGH Current150150150µA
Input LOW Current–150–150–150µA
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
455775455875455975mA
–1135–1060–885–1070–945–820–1010–885–760mV
–1995–1810–1685–1995–1745–1620–1995–1685–1560mV
–40°C25°C85°C
455775455875455975mA
216522402415223023552480229024152540mV
130514901615130515551680130516151740mV
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3
MC10EP101
DC CHARACTERISTICS, PECL (VCC = 5.0V ± 0.5V, VEE = 0V) (Note 9.)
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
7. VCC = 5.0V, VEE = 0V, all other pins floating.
8. All loading with 50 ohms to VCC –2.0 volts.
9. Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 7.)
Output HIGH Voltage
(Note 8.)
Output LOW Voltage
(Note 8.)
Input HIGH Voltage Single Ended379041153855418039154240mV
Input LOW Voltage Single Ended306533903130345531903515mV
Input HIGH Current150150150µA
Input LOW Current–150–150–150µA
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
AC CHARACTERISTICS (VCC = 3.0V to 5.5V; VEE = 0V) or (VCC = 0V; VEE = –3.0V to –5.5V)
11.Skew is measured between outputs under identical transitions.
Maximum Toggle
Frequency (Note 10.)
,
PropagationD –>Q, Q
Delay
Device SkewQ, Q
Part–to–Part (Note 11.)
Cycle–to–Cycle JitterTBDTBDTBDps
Output Rise and Fall Times
(20% – 80%)Q, Q
guaranteed for functionality only.
max
455775455875455975mA
386539404115393040554180399041154240mV
300531903315300532553380300533153440mV
–40°C25°C85°C
3.03.03.0GHz
125225325150250370170300420ps
TBD
TBD
100150200100170250120190270ps
TBD
TBD
TBD
TBD
ps
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4
MC10EP101
P ACKAGE DIMENSIONS
TQFP
FA SUFFIX
32–LEAD PLASTIC PACKAGE
CASE 873A–02
ISSUE A
SEATING
PLANE
9
C
–T–
B1
–AB–
–AC–
E
A
A1
32
1
4X
25
T–U0.20 (0.008)ZAB
–T–, –U–, –Z–
–U–
VB
AE
P
DETAIL Y
8
9
–Z–
S1
S
G
0.10 (0.004) AC
_
8X
M
H
W
R
K
X
DETAIL AD
17
4X
_
Q
V1
DETAIL AD
0.250 (0.010)
GAUGE PLANE
T–U0.20 (0.008)Z
AC
BASE
METAL
N
DF
J
SECTION AE–AE
T–U
M
0.20 (0.008)ZAC
AE
DETAIL Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE
DETERMINED AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL
BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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MC10EP101/D
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