Motorola MC100SX1230 Datasheet
SEMICONDUCTOR TECHNICAL DATA
The MC100SX1230 device consists of a Binary to CMI Coder and CMI
to Binary Decoder with integrated loop back capability. The device is
designed for CMI (Code Mark Inversion) interfaces in transmission
applications supporting either 139.26 Mbit/s E4 or 155.52 Mbit/s STM1
line rates.
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• Binary-to-CMI Coder and CMI-to-Binary Decoder
• Internal Loop Back Test Capability
• Supports SDH or PDH Applications
• Low Power
• Fully Differential 100K Compatible I/O
• V
Reference Available
BB
• 75kΩ Input Pulldown Resistors
• +5V PECL or –5V ECL Operation
• 28-Pin Surface Mount PLCC Package
• Asynchronous Reset
In normal operation, the coder and decoder operate independently.
Both the coder and decoder operate from a 2X line rate clock. The device
incorporates test circuitry to support loop back bypass so either the coder
input can be routed to the decoder output or the decoder input can be
routed to the coder output. The part is fabricated using Motorola’s proven
MOSAIC III advanced bipolar process.
The device provides a VBB output for accepting single-ended inputs.
The VBB pin should only be used as a bias for the
current sink/source capability is limited. Whenever used, the VBB pin
should be bypassed to ground via a 0.01µF capacitor.
CCLK
QCMI
QCMI
22
QBIN
21
LCMI
LBIN
V
EE
V
EE
CCLK
26
27
28
1
out
out
24
25
23
Pinout: 28-Lead PLCC
(Top View)
DCLK
DCLK
2
in
3
in
V
4
BB
5
7
6
8
MC100SX1230 as its
QBIN
DCLK
out
19
20
18
17
16
15
14
13
12
11109
DCLK
V
CC
V
CC
V
CCO
V
CCO
N/C
N/C
out
CMI CODER/DECODER
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776-02
PIN NAMES
Pins
CMIin, CMI
DCLKin, DCLK
QBIN, QBIN
DCLK
BINin, BIN
CCLKin, CCLK
QCMI, QCMI
CCLK
RESET
LBIN
LCMI
out
out
in
, DCLK
in
, CCLK
Function
CMI Input to Decoder
Decoder Clock Input
in
Binary Output From Decoder
Decoder Clock Output
out
Binary Input to Coder
Coder Clock Input
in
CMI Output from Coder
Coder Clock Output
out
Asynchronous Reset
Control Input for Binary
Loop Back
Control Input for CMI
Loop Back
RESET
MOSAIC III is a trademark of Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
4/94
CMI
CMI
in
in
BIN
BIN
in
in
CCLK
in
CCLK
in
Motorola, Inc. 1994
REV 0
MC100SX1230
CMI
CMI
DCLK
DCLK
LBIN
RESET
LCMI
BIN
BIN
BLOCK DIAGRAM
in
in
in
in
in
in
DECODER
÷
2
÷
2
H
D
C
R
R
D
C
R
CODER
QBIN
QBIN
DCLK
DCLK
CMI
CMI
out
out
DELAY
CCLK
CCLK
in
in
÷
2
FUNCTION TABLE
RESET LBIN LCMI
H X X Reset, All Output Pairs Set to Logic Low State
L L L Independent Coder and Decoder Operation
L L H CMI Input Routed to Coder Output
L H L Binary Input and Clock Routed to Decoder Outputs
Alarm Indication Signal Output from Coder
L H H Illegal, Undefined Operation
Function
CCLK
CCLK
out
out
MOTOROLA High Performance Frequency
2
Control Products — BR1334
MC100SX1230
ABSOLUTE MAXIMUM RATINGS
1
Symbol Parameter Value Unit
V
EE
V
I
I
OUT
T
A
V
EE
Power Supply (VCC = 0V) –8 to 0 Vdc
Input Voltage (VCC = 0V) 0 to –6 Vdc
Output Current Continuous
Surge
50
100
mA
Operating Temperature Range 0 to +85 °C
Operating Range
2
–5.7 to 4.2 V
1 Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
2 Parametric values specified at: –4.2 to 5.46V
DC CHARACTERISTICS (VCC = V
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Condition
V
OH
V
OL
V
OHA
V
OLA
V
IH
V
IL
V
BB
I
IH
I
IL
I
EE
1. 100SX circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is mounted in a test socket
or mounted on a printed circuit board and transverse air greater than 500lfm is maintained.
2. All outputs are loaded with 50Ω to VCC – 2V.
Output HIGH Voltage –1025 –955 –880 –1025 –955 –880 –1025 –955 –880 mV Vin = V
Output LOW Voltage –1810 –1705 –1620 –1810 –1705 –1620 –1810 –1705 –1620 mV Vin = V
Output HIGH Voltage –1035 –1035 –1035 mV Vin = V
Output LOW Voltage –1610 –1610 –1610 mV Vin = V
Input HIGH Voltage –1165 –880 –1165 –880 –1165 –880 mV
Input LOW Voltage –1810 –1475 –1810 –1475 –1810 –1475 mV
Reference Voltage –1380 –1260 –1380 –1260 –1380 –1260 V
Input HIGH Current 200 200 200 µA
Input LOW Current 0.5 0.5 0.5 µA
Supply Current 61 122 61 122 70 141 mA
= GND; VEE = –4.2 to 5.46V)
CCO
0°C 25°C 85°C
IH(max)
IH(max)
IH(max)
IH(max)
or V
or V
or V
or V
IL(min)
IL(min)
IL(min)
IL(min)
AC CHARACTERISTICS (VCC = V
= GND; VEE = –4.2 to 5.46V)
CCO
0 to 85°C
Symbol Characteristic Min Typ Max Unit Condition Notes
F
max
t
pd
Propagation CCLKin to CCLK
Delay CCLKin to QCMI
DCLKin to DCLK
DCLKin to QBIN
CCLKin to DCLK
CCLKin to QBIN
DCLKin to QCMI
t
s
Setup Time BINin to CCLK
CMIin to DCLK
t
h
Hold Time CCLKin to BIN
DCLKin to CMI
V
PP
V
CMR
tr, t
1. 100SX circuits are designed to meet the AC specifications shown in the table after thermal equilibrium has been established. The circuit is mounted in a test socket
or mounted on a printed circuit board and transverse air greater than 500lfm is maintained.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range
and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range is dependent on VEE and is equal to VEE + 3.0V.
Minimum Input Swing 250 mV
Common Mode Range –0.4 Note V
Rise/Fall Times 150 700 ps 20% – 80%
f
700 MHz
650
out
1000
550
out
1000
out
1100
800
–375
in
140
in
in
in
1550
1750
1700
1800
2700
1700
1000
120
ps
LCMI=LBIN=‘L’
LCMI=LBIN=‘L’
LCMI=LBIN=‘L’
LCMI=‘L’, LBIN=‘H’
LCMI=‘L’, LBIN=‘L’
LCMI=‘H’, LBIN=‘L’
ps
ps
Add 3 CCLKin-Cycles to Delay
Add 4 DCLKin-Cycles to Delay
Add 3 CCLKin-Cycles to Delay
Add 5 DCLKin-Cycles to Delay
Control Products — BR1334
MOTOROLAHigh Performance Frequency
3
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