MOTOROLA MC100LVEP210FAR2, MC100LVEP210FA Datasheet
MC100LVEP210
Low-V oltage 1:5 Dual Diff.
LVECL/LVPECL/LVEPECL/HSTL
Clock Driver
The MC100LVEP210 is a low skew 1–to–5 dual differential driver,
designed with clock distribution in mind. The LVECL/LVPECL input
signals can be either differential or single–ended if the VBB output is
used. The signal is fanned out to 5 identical differential outputs. HSTL
inputs can be used when the EP210 is operating in LVPECL mode.
The LVEP210 specifically guarantees low output–to–output skew.
Optimal design, layout, and processing minimize skew within a device
and from lot to lot.
To ensure the tight skew specification is realized, both sides of the
differential output need to be terminated identically into 50Ω even if
only one side is being used. When fewer than all ten pairs are used,
identically terminate all the output pairs on the same package side
whether used or unused. If no outputs on a single side are used, then
leave these outputs open (unterminated). This will maintain minimum
output skew. Failure to do this will result in a 10–20ps loss of skew
margin (propagation delay) in the output(s) in use.
The MC100LVEP210, as with most other LVECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP210 to be used for high performance clock distribution in
+3.3V or +2.5V systems. Single ended input operation is limited to a
VCC ≥ 3.0V in PECL mode, or VEE ≤ –3.0V in ECL mode.
Designers can take advantage of the LVEP210’s performance to
distribute low skew clocks across the backplane or the board. In a
LVPECL environment, series or Thevenin line terminations are
typically used as they require no additional power supplies. For more
information on using PECL, designers should refer to Application
Note AN1406/D.
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32–LEAD TQFP
FA SUFFIX
CASE 873A
MARKING DIAGRAM*
MC100
LVEP210
AWLYYWW
32
1
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
• 100ps Part–to–Part Skew
• 35ps Output–to–Output Skew
• Dif ferential Design
• V
BB
Output
• 475ps Typical Propagation Delay
• High Bandwidth to 1.5GHz Typical
• LVPECL and HSTL mode: 2.375V to 3.8V V
• LVECL mode: 0V V
with VEE = –2.375V to –3.8V
CC
with VEE = 0V
CC
• Internal Input Resistors: Pulldown on D, D
• Pullup and Pulldown on CLK
• ESD Protection: >2KV HBM, >100V MM
• Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 461 devices
Semiconductor Components Industries, LLC, 1999
March, 2000 – Rev . 2
Device Package Shipping
MC100L VEP210FA TQFP 250 Units/Tray
MC100L VEP210FAR2 TQFP 2000 Tape & Reel
1 Publication Order Number:
MC100L VEP210/D
VCC
Qb1Qb1Qb0Qb0Qa4Qa4Qa3 Qa3
Qa2
Qa2
Qa1
Qa1
Qa0
Qa0
VCC
24 23 22 21 20 19 18 17
25
26
27
28
MC100LVEP210
29
30
31
32
12345678
MC100LVEP210
16
15
14
13
12
11
10
9
VCC
Qb2
Qb2
Qb3
Qb3
Qb4
Qb4
VCC
PIN DESCRIPTION
PIN
CLKn/CLKn
Qn0:4/Qn0:4 LVECL/LVPECL Outputs
VBB
VCC Positive Supply
VEE Negative, 0 Supply
LVECL/LVPECL/HSTL CLK Inputs
FUNCTION
Reference Voltage Output
NC
CLKbVBBCLKaCLKaVCC
VEECLKb
Figure 1. 32–Lead TQFP Pinout (Top View)
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
CLKa
CLKa
Qa0
Qa0
Qa1
Qa1
Qa2
Qa2
Qa3
Qa3
Qa4
Qa4
CLKb
CLKb
V
BB
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qb3
Qb3
Qb4
Qb4
Figure 2. Logic Symbol
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
EE
V
CC
V
I
V
I
I
out
I
BB
T
A
T
stg
θ
JA
θ
JC
T
sol
* Maximum Ratings are those values beyond which damage to the device may occur.
{
Use for inputs of same package only.
Power Supply (VCC = 0V) –6.0 to 0 VDC
Power Supply (VEE = 0V) 6.0 to 0 VDC
Input Voltage (VCC = 0V, VI not more negative than VEE) –6.0 to 0 VDC
Input Voltage (VEE = 0V, VI not more positive than VCC) 6.0 to 0 VDC
Output Current Continuous
VBB Sink/Source Current
Operating Temperature Range –40 to +85 °C
Storage Temperature –65 to +150 °C
Thermal Resistance (Junction–to–Ambient) Still Air
Thermal Resistance (Junction–to–Case) 12 to 17 °C/W
Solder Temperature (<2 to 3 Seconds: 245°C desired) 265 °C
{
Surge
500lfpm
50
100
± 0.5 mA
80
55
mA
°C/W
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MC100LVEP210
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V; VEE = –3.3(+0.925, –0.5)V) (Note 5.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
1. VCC = 0V, VEE = V
2. All loading with 50 ohms to VCC–2.0 volts.
3. Single ended input operation is limited VEE ≤ –3.0V in ECL/LVECL mode.
4. V
5. Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 1.)
Output HIGH Voltage
(Note 2.)
Output LOW Voltage
(Note 2.)
Input HIGH Voltage
Single Ended
Input LOW Voltage
Single Ended
Output Voltage Reference (Note 3.) –1525 –1425 –1325 –1525 –1425 –1325 –1525 –1425 –1325 mV
Input HIGH Voltage Common Mode
Range (Note 4.)
Input HIGH Current 150 150 150 µA
Input LOW Current CLK
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
min varies 1:1 with VEE, max varies 1:1 with VCC.
IHCMR
EEmin
to V
CLK
, all other pins floating.
EEmax
60 70 90 60 70 90 60 70 90 mA
–1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895 mV
–1995 –1820 –1650 –1995 –1820 –1650 –1995 –1820 –1650 mV
–1165 –880 –1165 –880 –1165 –880 mV
–1810 –1625 –1810 –1625 –1810 –1625 mV
VEE+1.2 0.0 VEE+1.2 0.0 VEE+1.2 0.0 V
0.5
–150
0.5
–150
0.5
–150
µA
DC CHARACTERISTICS, LVPECL (VCC = 3.3V ± 0.5V, VEE = 0V) (Note 10.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
6. VCC = 3.3V ± 0.5V , VEE = 0V, all other pins floating.
7. All loading with 50 ohms to VCC–2.0 volts.
8. Single ended input operation is limited VCC ≥ –3.0V in PECL mode.
9. V
10.Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 6.)
Output HIGH Voltage
(Note 7.)
Output LOW Voltage
(Note 7.)
Input HIGH Voltage
Single Ended
Input LOW Voltage
Single Ended
Output Voltage Reference (Note 8.) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV
Input HIGH Voltage Common Mode
Range (Note 9.)
Input HIGH Current 150 150 150 µA
Input LOW Current CLK
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
min varies 1:1 with VEE, max varies 1:1 with VCC.
IHCMR
CLK
60 70 90 60 70 90 60 70 90 mA
2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
1305 1480 1650 1305 1480 1650 1305 1480 1650 mV
2135 2420 2135 2420 2135 2420 mV
1490 1675 1490 1675 1490 1675 mV
1.2 3.3 1.2 3.3 1.2 3.3 V
0.5
–150
0.5
–150
0.5
–150
µA
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