Mitac 8355 Service Manual

SERVICE MANUAL FOR

8355

83558355

8355

83558355

8355

83558355

BY:

Repair Technology Research Department /EDVD

Nov.2003

Rain Li

Contents

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1. Hardware Engineering Specification …………………………………………………………………

1.1 Introduction ………………………………………………………………………………………………………….

1.2 System Hardware Part……………………………………………………………………………………………….

1.3 Other Functions ………………………………………………………………………………………………………

1.4 Peripheral Components………………………………………………………………………………………………

1.5 Power Management…………………………………………………………………………………………………..

1.6 Appendix 1 : VT8235 GPIO Definition……………………………………………………………………………...

1.7 Appendix 2 : H8 Pins Definition …………………………………………………………………………………….

1.8 Appendix 3 : 8355 Product Specification ……………………………………………………………………………

2. System View and Disassembly ………………………………………………………………………...

2.1 System View …………………………………………………………………………………………………………

2.2 System Disassembly …………………………………………………………………………………………………

3. Definition & Location of Connectors / Switches ……………………………………………………..

3.1 Mother Board ………………………………………………………………………………………………………..

4. Definition & Location of Major Components ………………………………………………………..

4.1 Mother Board ………………………………………………………………………………………………………..

5. Pin Description of Major Component …….………………………………………………………….

5.1 AMD AthlonTM64 Processor ……………………………………………………………………………………….

5.2 K8T800M (VT8385) North Bridge …………………………………………………………………………………

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5.3 VT8235 South Bridge ……………………………………………………………………………………………….

6. System Block Diagram ………………………………………………………………………………..

7. Maintenance Diagnostics ………………………………………………………………………………

7.1 Introduction …………………………………………………………………………………………………………

7.2 Error Codes …………………………………………………………………………………………………………

7.3 Debug Tool …………………………………………………………………………………………………………..

8. Trouble Shooting ………………………………………………………………………………………

8.1 No Power …………………………………………………………………………………………………………….

8.2 Battery Can not Be Changed ………………………………………………………………………………………

8.3 No Display ……………………………………………………………………………………………………………

8.4 AGP Controller Failure LCD No Display …………………………………………………………………………

8.5 External Monitor No Display ………………………………………………………………………………………

8.6 Memory Test Error …………………………………………………………………………………………………

8.7 Keyboard (K/B) Touch-Pad (T/P) Test Error ……………………………………………………………………..

8.8 Hard Driver Test Error ……………………………………………………………………………………………..

8.9 CD-ROM Driver Test Error…………………………………………………………………………………………

8.10 USB Port Test Error ………………………………………………………………………………………………..

8.11 PC Card Socket Failure ……………………………………………………………………………………………

8.12 Memory-Card Socket Failure ……………………………………………………………………………………..

8.13 IEEE1394 Test Error……………………………………………………………………………………………….

8.14 LAN Test Error……………………………………………………………………………………………………..

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8.13 Audio Failure ………….……………………………………………………………………………………………

9. Spare Parts List ………………………………………………………………………………………..

10. System Exploded Views ………………………………………………………………………………

11. Circuit Diagram ………………………………………………………………………………………

12. Reference Material …………………………………………………………………………………...

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1. Hardware Engineering Specification

1.1 Introduction

The 8355 motherboard would support the AMD ClawHammer K8 processor with uPGA Package,

2700+/3000+/3300+/3600+/3900+/4200+, FSB 800MHz

This system is based on PCI architecture, which have standard hardware peripheral interface. The power management

complies with Advanced Configuration and Power Interface (ACPI) 2.0. It also provides easy configuration through

CMOS setup, which is built in system BIOS software and can be pop-up by pressing F2 at system start up or warm

reset. System also provides ico LEDs to display system status, such as AC Power, Battery Power, Battery status, CD-

ROM, HDD, NUM LOCK, CAP LOCK, SCROLL LOCK, WIRELESS LAN status. It also equipped 4 USB2.0 ports.

The memory subsystem supports 0MB on board; Expandable up to 1024MB Expandable with combination of optional

128/256/512 MB memory 200-pin DDR 266/333/400 Memory Module x2, PC-2100/2700/3200 specification

The K8T800 North Bridge plus VT8235 South Bridge chipset is a high performance, cost-effective and energy

efficient solution for the implementation of desktop personal computer systems with 8 / 16-bit 800 / 600 / 400 / 200

MHz HyperTransport. CPU host interface based on AMD K8 / ClawHammer. processors.

The VT8235 “V-Link Client Controller” is a highly integrated PCI /LPC controller. Its internal bus structure is based

on a 66 MHz PCI bus that provides 2x bandwidth compared to previous generation PCI bridge chips. The VT8235

also provides a 533 MB/sec bandwidth Host / Client V-Link interface with V-Link-PCI and V-Link-LPC controllers.

It supports six PCI slots of arbitration and decoding for all integrated functions and LPC bus.

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The RADEON MOBILITY 9600 provides the fastest and most advanced 2D, 3D, and multimedia graphics

performance for the latest applications in full 32-bit color. Its architecture introduces the latest achievements in the

graphics industry, which enable the use of the progressive new features in upcoming applications, but without

compromising performance. ATI’s exclusive support of DirectX® 9.0 features, highly optimized OpenGL® support,

and flexible memory configurations allow implementations targeted at both gaming enthusiast and workstation

platforms.

To provide for the increasing number of multimedia applications, the AC97 CODEC CMI9738-S is integrated onto

the motherboard

A full set of software drivers and utilities are available to allow advanced operating systems such as Windows XP and

Windows 2000 to take full advantage of the hardware capabilities such as bus mastering IDE, Windows 95-ready Plug

& Play, Advanced Power Management (APM) and Advance configuration and power interface (ACPI).

Following chapters will have more detail description for each individual sub-systems and functions.

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1.2 System Hardware Part

CPU AMD ClawHammer K8 processor with uPGA Package

2700+/3000+/3300+/3600+/3900+/4200+

FSB 800MHz Core logic VIA K8T800 + VT8235 VGA Control ATI M10P with 64MB External VRAM (Reserve for 128MB VRAM) System BIOS Insyde 256 KB Flash EPROM (Include System BIOS and VGA BIOS)

ACPI 2.0; DMI 2.3.1 compliant

Plug & Play capability Memory 0MB on board; Expandable up to 1024MB

Expandable with combination of optional 128/256/512 MB memory

200-pin DDR 266/333/400 DRAM Memory Module x2,

PC-2100/2700/3200 specification Clock Generator IEEE1394 VT6307L Audio System AC97 CODEC: C-MEDIA ELECTRONICS INC., CMI9738-S

Super I/O PC87397 Modem 56Kbps(V.90, worldwide) MDC Modem PHY of LAN VT6103 10/100 base -T PHY PCMCIA ENE710 CARD READER

ICS 950403

Power Amplifier: Anpec APA2020

ENE710

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1.2.1 CPU_ ClawHammer PROCESSOR

The ClawHammer processor family is designed to support performance desktop and workstation applications. It

provides a high-performance HyperTransport. link to I/O, as well as a single 64-bit high-performance DDR

memory controller.

Compatible with Existing 32-bit Code Base

Including support for SSE, SSE2, MMX

Runs existing operating systems and drivers

Local APIC on-chip

AMD x86-64 Technology

AMD.s 64-bit x86 instruction set extensions

64-bit integer registers, 48-bit virtual addresses, 40-bit physical addresses

Eight new 64-bit integer registers (16 total)

Eight new 128-bit SSE/SSE2 registers (16 total)

Integrated Memory Controller

Low-latency, high-bandwidth

72-bit DDR at 200, 266, 333, and 400 MHz (64-bits + 8-bits ECC)

, 3DNow!TM, technology and all legacy x86 instructions

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HyperTransport. Technology to I/O Devices

Two 8-bit links each support 1600 mega-transfers (MT) per second or 1.6 Gbytes/s in each direction

Can be configured as single 16-bit link supporting 1600 MT/s or 3.2 Gbytes/s in each direction

64-Kbyte 2-way Associative ECC-Protected L1 Data Cache

Two 64-bit operations per cycle, 3-cycle latency

64-Kbyte 2-way Associative Parity-Protected L1 Instruction Cache

With advanced branch prediction

16-way Associative ECC-Protected L2 Cache

Exclusive cache architecture.storage in addition to L1 caches

256 KB, 512 KB, and 1 MB options

Machine Check Architecture

Includes hardware scrubbing of major ECC-protected arrays

Power Management

Multiple low-power states

System Management Mode (SMM)

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ACPI 2.0 compliant, including support for processor performance states

Power Supplies

VDD (core): 1.50-V at 52 Amps (max)

VDDIO: 2.5-V at 3.0 Amps (max) for DDR I/O

VLDT: 1.2-V at 0.5 Amps for HyperTransport

VTT: 1.25-V at 0.5 Amps required for 2.5-V I/Os

Target CPU Core Power: 78.00 Watts

Target Maximum Thermal Power: 89 Watts

Electrical Interfaces

HyperTransport. Technology: LVDS-like differential, unidirectional

DDR: SSTL per JEDEC DDR specification

Clock, reset, and test signals also use DDR-like electrical specifications

Packaging

754-pin lidded micro PGA

1.27-mm pin pitch

29x29 row pin array

40mm x 40mm organic substrate, Organic C4 die attach

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1.2.2 System frequency

1.2.2.1 System frequency synthesizer_ICS950402

Programmable Timing Control Hub™ AMD-K8™ processor

General Description

The ICS950403 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all

necessary clock signals for Clawhammer and Sledgehammer systems.

The ICS950403 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control

Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality.

Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring

the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output

strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with

resolution up to 0.1MHz increment.

Recommended Application:

AMD K8 System Clock with AMD or VIA Chipset

Output Features:

2 - Differential pair push-pull K8 CPU clocks

9 - PCICLK (Including 1 free running) @3.3V

3 - Selectable PCICLK/HTTCLK @3.3V

1 - HTTCLK @3.3V

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1 - 48MHz, @3.3V fixed.

1 - 24/48MHz @ 3.3V

3 - REF @3.3V, 14.318MHz.

Features:

Programmable output frequency.

Programmable output divider ratios.

Programmable output rise/fall time.

Programmable output skew..

Programmable spread percentage for EMI control.

Watchdog timer technology to reset system if system malfunctions.

Programmable watch dog safe frequency.

Support I2C Index read/write and block read/write operations.

Uses external 14.318MHz crystal.

Supports Hyper Transport Technology (HTTCLK).

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1.2.3 VIA K8T800+VT8235

1.2.3.1 K8T800

The K8T800 is a high performance, cost-effective and energy efficient solution for the implementation of desktop

personal computer systems with 8 / 16-bit 800 / 600 / 400 / 200 MHz HyperTransport. CPU host interface based on

AMD K8 / ClawHammer. processors.

Defines Highly Integrated Solutions for Performance PC Desktop Designs

High performance North Bridge with HyperTransport. interface to AMD. K8 CPU plus AGP 8x external bus to

external Graphics Controller plus high-speed V-Link interface to chipset South Bridge

Combines with VIA K8T400M V-Link South Bridge for integrated LAN, Audio, ATA133 IDE, and 6 USB 2.0

ports

578 Ball Grid Array package with 35 x 35 mm body size, 1.27mm ball pitch, and heat spreader

2.5V core, 0.22 u process

High Performance K8 CPU Interface

Chipset support for AMD. K8 / ClawHammer. processor

Processor interface via HyperTransport. bus

Separate transmit and receive buses for no lost bus turnaround cycles

All transmit and receive signals use 2 pin low-voltage-swing differential signalling for high-reliability and high

speed

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8 or 16-bit control / address / data transfer both directions

800 / 600 / 400 / 200 MHz Double Data Rate operation both directions

Default 8-bit / 200 MHz operation on startup for high reliability with speedup to dual 16-bit, 800 MHz operation (3.2

GB/sec total bandwidth) under software control (transmit and receive may be different widths and / or speeds)

Full Featured Accelerated Graphics Port (AGP) 8x Controller

Supports 533 MHz 8x, 266 MHz 4x, and 133 MHz 2x transfer modes for AD and SBA signaling

AGP v3.0 compliant with 8x transfer mode

Pseudo-synchronous with the host CPU bus with optimal skew control

Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)

AGP pipelined split-transaction long-burst transfers up to 1GB/sec

Eight level read request queue

Four level posted-write request queue

Thirty-two level (quadwords) read data FIFO (256 bytes)

Sixteen level (quadwords) write data FIFO (128 bytes)

Intelligent request reordering for maximum AGP bus utilization

Supports Flush/Fence commands

Graphics Address Relocation Table (GART)

One level TLB structure

Sixteen entry fully associative page table

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LRU replacement scheme

Independent GART lookup control for host / AGP / PCI master accesses

Windows 95 OSR-2 VXD and integrated Windows 98 / 2000 / XP miniport driver support

High Bandwidth 533 MB / Sec 8-bit V-Link Host Controller South Bridge Interface

Supports 66 MHz V-Link Host interface with total bandwidth of 533 MB/sec

Operates in 2x, 4x, and 8x modes

Full duplex commands with separate command / strobe

Request / Data split transaction

Configurable outstanding transaction queue for Host to V-Link Client accesses

Supports Defer / Defer-Reply transactions

Transaction assurance for V-Link Host to Client access eliminates V-Link Host-Client Retry cycles

Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency

All V-Link transactions for both Host and Client have a consistent view of transaction data depth and buffer size to

avoid data overflow

Highly efficient V-Link arbitration with minimum overhead

All V-Link transactions have predictable cycle length with known command / data duration

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1.2.3.2 VT8235

The VT8235 South Bridge is a high integration, high performance, power-efficient, and high compatibility device

that supports Intel and non-Intel based processor to V-Link bus bridge functionality to make a complete Microsoft

PC2001-compliant PCI/LPC system. The VT8235 includes standard intelligent peripheral controllers:

a) IEEE 802.3 compliant 10 / 100 Mbps PCI bus master Ethernet MAC with standard MII interface to external

PHYceiver.

b) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands.

Dedicated FIFO coupled with scatter and gather master mode operation allows high performance transfers between

PCI and IDE devices. In addition to standard PIO and DMA mode operation, the VT8235 also supports the

UltraDMA-133, 100, 66, and 33 standards to allow reliable data transfer at rates up to 133 MB/sec. The IDE

controller is SFF-8038i v1.0 and Microsoft Windows-family compliant.

c) Universal Serial Bus controller that is USB v2.0 / 1.1 and Universal HCI v2.0 / 1.1 compliant. The VT8235

includes three root hubs with six function ports with integrated physical layer transceivers. The USB controller

allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support.

The controller also implements legacy keyboard and mouse support so that legacy software can run transparently in

a non-USB-aware operating system environment.

d) Keyboard controller with PS2 mouse support.

e) Real Time Clock with 256 byte extended CMOS. In addition to the standard ISA RTC functionality, the

integrated RTC also includes the date alarm, century field, and other enhancements for compatibility with the ACPI

standard.

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f) Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple

sleep states (power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic

wake-up. Additional functionality includes event monitoring, CPU clock throttling and stop (Intel processor

protocol), PCI bus clock stop control, modular power, clock and leakage control, hardware-based and software-

based event handling, general purpose I/O, chip select and external SMI.

g) Full System Management Bus (SMBus) interface.

h) Integrated bus-mastering dual full-duplex direct-sound AC97-link-compatible sound system.

i) Plug and Play controller that allows complete steerability of all PCI interrupts and internal interrupts / DMA

channels to any interrupt channel. One additional steerable interrupt channel is provided to allow plug and play and

reconfigurability of onboard peripherals for Windows family compliance. The VT8235 also enhances the

functionality of the standard ISA peripherals. The integrated interrupt controller supports both edge and level

triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to

standard ISA DMA modes. Compliant with the PCI-2.2 specification, the VT8235 supports delayed transactions

and remote power management so that slower ISA peripherals do not block the traffic of the PCI bus. Special

circuitry is built in to allow concurrent operation without causing dead lock even in a PCI-to-PCI bridge

environment. The chip also includes eight levels (doublewords) of line buffers from the PCI bus to the ISA bus to

further enhance overall system performance.

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1.2.4 RADEON MOBILITY 9600

General Description

The RADEON MOBILITY 9600 provides the fastest and most advanced 2D, 3D, and multimedia graphics

performance for the latest applications in full 32-bit color. Its architecture introduces the latest achievements in the

graphics industry, which enable the use of the progressive new features in upcoming applications, but without

compromising performance. ATI’s exclusive support of DirectX® 9.0 features, highly optimized OpenGL® support,

and flexible memory configurations allow implementations targeted at both gaming enthusiast and workstation

platforms.

SMARTSHADER™ — Advanced Shader Technology

Provides complete hardware-accelerated support for the new DirectX® 9.0 programmable shader model,

enabling more complex and realistic texture and lighting effects than ever before.

Significant improvement over first-generation shaders introduced in DirectX® 9.0, with a much more powerful

and intuitive instruction set.

Offers full support for this feature in OpenGL® applications.

SMOOTHVISION™ — Flexible Anti-Aliasing and Anisotropic Filtering

The most flexible and efficient anti-aliasing implementation available to date.

Eliminates “jaggies” on the edges of objects, shimmering pixels on distant surfaces, and other visual artifacts for

smoother-looking images.

Offers full support for this feature in OpenGL® applications.

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SMOOTHVISION™ — Flexible Anti-Aliasing and Anisotropic Filtering

The most flexible and efficient anti-aliasing implementation available to date.

Eliminates “jaggies” on the edges of objects, shimmering pixels on distant surfaces, and other visual artifacts

for smoother-looking images.

Unique adaptive process can independently select the anti-aliasing pattern for each pixel within a 4x4 region,

rather than relying on a fixed pattern for the whole image.

Better visual quality with minimal performance degradation.

Supports DirectX® 9.0 multisampling and related effects, including motion blur and depth-of-field.

High Performance Memory Support

Incorporates support for DDR SDRAM/SGRAM at up to 350 MHz.

Features ATI’s second generation HYPER Z™III technology that conserves memory bandwidth for improved

performance in demanding applications.

Boosts effective memory bandwidth by over 20%.

Dual Display Support

Leading-edge technology, fully optimized with HYDRA VISION™, flexibly supports multiple combinations of

traditional CRT monitors, flat panel displays and TV.

Features Dual Channel DVI support.

32-bit PCI bus (Rev 2.2), 3.3 V with bus mastering support.

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Comprehensive AGP support including 1.5 Volt (AGP 4X) and 0.8 Volt (AGP8X) mode operation, sideband

addressing, AGP texturing (direct memory execution), and support for AGP reads and writes, including fast write

capability.

Single channel 128/64-bit memory interface using SGRAM or SDRAM to build 8/16/32/64 MB configurations.

Operating frequency is 67MHz minimum to 350MHz maximum, SDR or DDR.

16-bit Zoom Video port.

Support for ROM or Flash RAM parallel or serial video BIOS.

Two independent CRT controllers to support two asynchronous simultaneous display paths.

Integrated DAC for CRT with stereoscopic display support.

Integrated second DAC for the second CRT (TV) support.

Integrated LVDS interface: single and dual pixel per clock, up to 85MHz per channel.

LCD panel detection.

Integrated TMDS transmitter running up to 165MHz (when matched with coherently clocked receiver; otherwise,

135MHz) for support up to 1600x1200 at 60Hz. Fully compliant with DVI and DFP connection standards.

Radiometric expansion.

Ideal for Windows 2000 and Windows XP

RADEON MOBILITY 9600 provides comprehensive support for all new Windows 2000 and Windows XP

display-oriented features, including acceleration of new GDI extensions like Alpha BLTs, Transparent BLTs,

and Gradient Fills, as well as exclusive, patent-pending hardware alpha cursor support.

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1.2.4.1 General and Interfacing Features

32-bit PCI bus (Rev 2.2), 3.3 V with bus mastering support.

Comprehensive AGP support including 1.5 Volt (AGP 4X) and 0.8 Volt (AGP8X) mode operation, sideband

addressing, AGP texturing (direct memory execution), and support for AGP reads and writes, including fast

write capability.

Single channel 128/64-bit memory interface using SGRAM or SDRAM to build 8/16/32/64 MB configurations.

Operating frequency is 67MHz minimum to 350MHz maximum, SDR or DDR.

16-bit Zoom Video port.

Support for ROM or Flash RAM parallel or serial video BIOS.

Two independent CRT controllers to support two asynchronous simultaneous display paths.

Integrated DAC for CRT with stereoscopic display support.

Integrated second DAC for the second CRT (TV) support.

Integrated LVDS interface: single and dual pixel per clock, up to 85MHz per channel.

LCD panel detection.

Integrated TMDS transmitter running up to 165MHz (when matched with coherently clocked receiver;

otherwise, 135MHz) for support up to 1600x1200 at 60Hz. Fully compliant with DVI and DFP connection

standards. Ratiometric expansion.

Support for external TMDS transmitter via 24-bit digital output to drive most popular TMDS transmitters up to

165MHz frequency.

Internal and external Spread Spectrum support.

Integrated enhanced TV encoder with 10-bit DAC (shared between second CRT DAC and TV).

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Independent DDC lines for DAC and TMDS connections. Also full AppleSense support on DAC connection.

Static and dynamic Power Management support (APM as well as ACPI) with full VESA DPMS and Energy

Star compliance.

PCI bus power management 1.1 and AGP Busy and Stop signals Rev 1.61 and Solano 2-M.

Full POWERPLAYTM and POWER ON DEMAND support.

Comprehensive testability including full internal scan, memory BIST, I/O XOR tree and Iddq. Ideal accelerator

for Windows 2000 and Windows XP - includes patent pending hardware support for the Windows 2000 and

Windows XP alpha cursor, as well as acceleration of new GDI extensions such as Alpha BLTs, Transparent

BLTs, and Gradient Fills.

Fully compliant with PC 2001 requirements.

Fully compliant with Mobile PCI rev 1.0.

Full ACPI 1.0b, OnNow, and IAPC (Instantly Available PC) power management, including PCI power

management registers.

Bi-endian support for compliance on a variety of processor platforms.

Unique enhanced TCA (Triple-Cache Architecture) incorporates texture, pixel and vertex caches to maximize

effective memory bandwidth.

CCE high-speed pull architecture software interface optimized for Pentium III/4 and Athlon systems:

• Bus mastering of 2D&3D display lists.

• Direct walk of Direct3D/OpenGL vertex list.

• Ultra-thin driver layer.

• Maximizes concurrency between RADEON MOBILITY 9000 and host.

Triple 10-bit palette DAC supports pixel rates to 400MHz.

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DDC1 and DDC2ci for plug and play monitors.

Hydravision for dual monitor support.

Hardware I2C.

Integrated hardware diagnostic tests performed automatically upon initialization.

High quality components through at-speed testing, built-in Scan, Iddq, CRC, chip diagnostics, and XOR tree.

Single chip solution in 0.15 micron, 1.2V-1.5V CMOS technology in 696 BGA and 648 BGA package.

Flexible memory support:

• SGRAM or SDRAM.

• SDR or DDR.

• DDR support for both system memory SDRAM and graphics SGRAM devices.

• 128-bit or 64-bit interface.

• 8MB to 64MB.

Comprehensive HDKs, SDKs and utilities augmented by full engineering support.

Complete local language support (contact ATI for current list).

Dual RGB CRT output with DDC.

Integrated enhanced TV encoder based on Rage Theater support at 1024x768.

HDCP 1.0 support on integrated TMDS transmitter.

Digital interface with external TMDS Tx with dedicated DDC, configurable as a 24 bit SDR bus or a 12 bit DDR bus.

Independent h/w icon & h/w cursor on both display paths (simultaneous h/w cursor & icon).

IEEE 1149.1 Scan path interface.

VIP 2.0 with multi channel DMA transfer. Support for Rage Theater via VIP.

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1.2.5 AC’97 AUDIO SYSTEM: C-MEDIA ELECTRONICS INC., CMI9738-S

The CMI9738-S is an 18-bit, full duplex AC'97 2.2 compatible stereo audio CODEC designed for PC multimedia

systems,including host/soft audio and AMR/CNR based designs. The CMI9738-S incorporates proprietary converter

technology to achieve a high SNR, greater than 90 dB. The CMI9738-S AC'97 CODEC supports multiple CODEC

extensions with independent variable sampling rates and built-in 3D effects. The CMI9738-S CODEC provides two

pairs of stereo outputs with independent volume controls, a mono output, and multiple stereo and mono inputs, along

with flexible mixing, gain and mute functions to provide a complete integrated audio solution for PCs.

Features

Single chip audio CODEC with high S/N ratio (>90dB)

Compliant with AC’97 2.2 & WHQL specifications

Support of S/PDIF out is compliant with AC’97 rev2.2 specifications

Meets performance requirements for audio on PC2001 systems

Meets Microsoft PC99 & WLP 2.0 audio requirements

18-bit Stereo full-duplex CODEC with independent and variable sampling rate

18-bit ADC and 20-bit DAC resolution

Four analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, VIDEO, AUX

High quality differential CD input

Two analog line-level mono input: PC_BEEP,PHONE_IN

Supports double sampling rate (96KHz) of DVD audio playback

Two software selectable MIC inputs

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+30dB boost preamplifier for MIC input

Stereo output with 6-bit volume control

Mono output with 5-bit volume control

Headphone output with 50mW/8. Driving capability

Line output with 50mW/8. driving capability

Headphone jack-detect function to mute LINE/MONO/HP output, and to control S/PDIF output

3D Stereo Enhancement

Multiple CODEC extension capability

External Amplifier Power Down (EAPD) capability

High performance converter technology

Power management and enhanced power saving features

2 GPIO pins

No external crystal/clock required

14.318MHz 24.576MHz PLL saves crystal

DC Voltage volume control

Auxiliary power (VAUX ) to support Power Off CD function

Power support: Digital: 3.3V; Analog: 3.3V/5V

Standard 48-Pin LQFP Package

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1.2.6 MDC: PCTel MODEM DAUGHTER CARD PCT2303W

The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. The

combination of PC-TEL’s well proven PCT2303W chipset and the HSP56TM MR software modem driver allows

systems manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while maintaining

higher system performance.

PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating with the

Pentium class processors, HSP becomes part of the host computer’s system software. It requires less power to operate

and less physical space than standard modem solutions. PC-TEL’s HSP modem is an easily integrated, cost-effective

communications solution that is flexible enough to carry you into the future.

The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a programmable

line interface to meet international telephone line requirements. The PCT2303W chip set is available in two 16-pin

small outline packages (AC’97 interface on PCT303A and phone-line interface on PCT303W). The chip set eliminates

the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to 4-wire hybrid. The PCT2303W chip set

dramatically reduces the number of discrete components and cost required to achieve compliance with international

regulatory requirements. The PCT2303W complies with AC’97 Interface specification Rev. 2.1.

The chip set is fully programmable to meet worldwide telephone line interface requirements including those described

by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable parameters of the

PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer threshold. The

PCT2303W chip set has been designed to meet stringent worldwide requirements for out-of-band energy, billing-tone

immunity, lightning surges, and safety requirements.

8355 N/B MAINTENANCE

Operating System Compatibility

Windows 98 / NT4.0 /Win 2K /Win XP

Compatibility

ITU-T V.90 56000,54667,53333,52000,50667,49333,48000,46667,45333,

42667,41333,40000,38667,37333,36000,34667,33333,32000,

30667,29333, 28000bps

K56Flex 56000,54000,52000,50000,48000,46000,44000,42000,40000,

38000,36000, 32000bps.

ITU-T V.34Annex 33600,31200 bps.

ITU-T V.34 28800 bps

ITU-T V.32bis 14400 bps

ITU-T V.32 9600,4800 bps

ITU-T V.22bis 2400 bps

ITU-T V.22 1200 bps

ITU-T V.21 300 bps

ITU-T V.23 1200/75 bps

ITU-T V.17 14400,12000,9600,7200 bps

ITU-T V.29 9600,7200 bps

ITU-T V.27ter 4800,2400 bps

8355 N/B MAINTENANCE

Bell 212A 1200 bps

Bell 103 300 bps

Modulation

56000bps(V90&K56Flex) PCM

33600 bps (V.34Annex) TCM

28800 bps (V.34) TCM

14400 bps (V.32bis) TCM

12000 bps (V.32bis) TCM

9600 bps (V.32bis) TCM

7200 bps (V.32bis) QAM

9600 bps (V.32) TCM, QAM

4800 bps (V.32) QAM

14400 bps (V.17) TCM

12000 bps (V.17) TCM

9600 bps (V.29) QAM

7200 bps (V.29) QAM

4800 bps (V.27ter) DPSK

2400 bps (V.27ter) DPSK

2400 bps (V.22bis) QAM

8355 N/B MAINTENANCE

1200/75bps (V.23) FSK

1200bps(V.22/Bell 212A) DPSK

300bps(V.21/Bell 103) FSK

Data Compression

V.42bis, MNP5

Error Correction

V.42 LAPM, MNP 2-4

DTE interface

DTMF Tone Frequency

Low Group Frequency (Hz)

697 770 852 941 High Group 1209 1 4 7 * Frequency 1336 2 5 8 0 (Hz) 1477 3 6 9 # 1633 A B C D

DTMF signal level

8355 N/B MAINTENANCE

2.6.1.1 High group -10+/-2dBm

2.6.1.2 Low group -12+/-2dBm

Dialing Type

Tone or pulse dialing

Telephone Line interface

RJ-11

Return Loss

300HZ - 3400HZ >= 10db

Flow Control

XOFF/XON or RTS/CTS

Receive Level

-35 +/- 2dBm

+ 178 hidden pages

Mitac 8355 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual