Atmel ATmega328P Datasheet

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Features

ATmega328P

8-bit AVR Microcontroller with 32K Bytes In-System

Programmable Flash

DATASHEET

● High performance, low power AVR

8-bit microcontroller

● Advanced RISC architecture

● 131 powerful instructions – most single clock cycle execution

● 32  8 general purpose working registers

● Fully static operation

● Up to 16MIPS throughput at 16MHz

● On-chip 2-cycle multiplier

● High endurance non-volatile memory segments

● 32K bytes of in-system self-programmable flash program memory

● 1Kbytes EEPROM

● 2Kbytes internal SRAM

● Write/erase cycles: 10,000 flash/100,000 EEPROM

● Optional boot code section with independent lock bits

● In-system programming by on-chip boot program

● True read-while-write operation

● Programming lock for software security

● Peripheral features

● Two 8-bit Timer/Counters with separate prescaler and compare mode

● One 16-bit Timer/Counter with separate prescaler, compare mode, and capture

mode

● Real time counter with separate oscillator

● Six PWM channels

● 8-channel 10-bit ADC in TQFP and QFN/MLF package

● Temperature measurement

● Programmable serial USART

● Master/slave SPI serial interface

● Byte-oriented 2-wire serial interface (Phillips I

● Programmable watchdog timer with separate on-chip oscillator

● On-chip analog comparator

● Interrupt and wake-up on pin change

C compatible)

● Special microcontroller features

● Power-on reset and programmable brown-out detection

● Internal calibrated oscillator

● External and internal interrupt sources

● Six sleep modes: Idle, ADC noise reduction, power-save, power-down, standby,

and extended standby

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I/O and packages

●

● 23 programmable I/O lines

● 32-lead TQFP, and 32-pad QFN/MLF

● Operating voltage:

● 2.7V to 5.5V for ATmega328P

● Temperature range:

● Automotive temperature range: –40°C to +125°C

● Speed grade:

● 0 to 8MHz at 2.7 to 5.5V (automotive temperature range: –40°C to +125°C)

● 0 to 16MHz at 4.5 to 5.5V (automotive temperature range: –40°C to +125°C)

● Low power consumption

● Active mode: 1.5mA at 3V - 4MHz

● Power-down mode: 1µA at 3V

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1. Pin Configurations

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

GND

VCC

GND

VCC 6

32 31 30 29 28 27 26 25

9 10111213141516

24 PC1 (ADC1/PCINT9)

(PCINT21/OC0B/T1) PD5

(PCINT0/CLKO/ICP1) PB0

(PCINT23/AIN1) PD7

(PCINT1/OC1A) PB1

(PCINT2/SS/OC1B) PB2

(PCINT3/OC2A/MOSI) PB3

(PCINT4/MISO) PB4

(PCINT22/OC0A/AIN0) PD6

PC0 (ADC0/PCINT8)

AVC C

PB5 (SCK/PCINT5)

ADC7

GND

AREF

ADC6

PD2 (INT0/PCINT18)

PD1 (TXD/PCINT17)

PD0 (RXD/PCINT16)

PC6 (RESET/PCINT14)

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

GND

VCC

GND

VCC

NOTE: Bottom pad should be soldered to ground.

32 31 30 29

32 MLF Top View

28 27 26 25

9 10111213141516

24 PC1 (ADC1/PCINT9)

(PCINT21/OC0B/T1) PD5

(PCINT0/CLKO/ICP1) PB0

(PCINT23/AIN1) PD7

(PCINT1/OC1A) PB1

(PCINT2/SS/OC1B) PB2

(PCINT3/OC2A/MOSI) PB3

(PCINT4/MISO) PB4

PC0 (ADC0/PCINT8)

AVC C

PB5 (SCK/PCINT5)

ADC7

GND

AREF

ADC6

PD2 (INT0/PCINT18)

PD1 (TXD/PCINT17)

PD0 (RXD/PCINT16)

PC6 (RESET/PCINT14)

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

TQFP Top View

Figure 1-1. Pinout

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1.1 Pin Descriptions

1.1.1 VCC

Digital supply voltage.

1.1.2 GND

Ground.

1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting oscillator amplifier.

If the internal calibrated RC oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of port B are elaborated in Section 13.3.1 “Alternate Functions of Port B” on page 65 and

Section 8. “System Clock and Clock Options” on page 24.

1.1.4 Port C (PC5:0)

Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5..0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

1.1.5 PC6/RESET

If the RSTDISBL fuse is programmed, PC6 is used as an input pin. If the RSTDISBL fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 28-4 on page 261. Shorter pulses are not guaranteed to generate a reset.

The various special features of port C are elaborated in Section 13.3.2 “Alternate Functions of Port C” on page 68.

1.1.6 Port D (PD7:0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, port D pins that are externally pulled low will source current if the pull-up resistors are activated. The port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

The various special features of port D are elaborated in Section 13.3.3 “Alternate Functions of Port D” on page 70.

1.1.7 AV

AVCC is the supply voltage pin for the A/D converter, PC3:0, and ADC7:6. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to V supply voltage, V

through a low-pass filter. Note that PC6..4 use digital

1.1.8 AREF

AREF is the analog reference pin for the A/D converter.

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1.1.9 ADC7:6 (TQFP and QFN/MLF Package Onl y)

In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels.

1.2 Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of actual ATmega328P AVR® microcontrollers manufactured on the typical process technology. automotive min and max values are based on characterization of actual ATmega328P AVR microcontrollers manufactured on the whole process excursion (corner run).

1.3 Automotive Quality Grade

The ATmega328P have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (temperature and voltage). The quality and reliability of the ATmega328P have been verified during regular product qualification as per AEC-Q100 grade 1. As indicated in the ordering information paragraph, the products are available in only one temperature.

Table 1-1. Temperature Grade Identification for Automotive Products

T emperature Temperature Identifier Comments

–40°C; +125°C Z Full automotive temperature range

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2. Overview

The Atmel® ATmega328P is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega328P achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

GND VCC

DATA BUS

Watchdog

Timer

Watchdog

Oscillator

Circuits/

Clock

Generation

EEPROM

8-bit T/C 2

Power

Supervision

POR/ BOD

and

RESET

Flash

AVR

Analog

Comp.

debugWIRE

CPU

Program

Logic

SRAM

A/D Conv.16-bit T/C 18-bit T/C 0

Internal

Bandgap

AVC C

AREF

GND

USART 0 SPI TWI

PORT D (8) PORT B (8) PORT C (7)

RESET

XTAL[1..2]

PD[0..7] PB[0..7] PC[0..6] ADC[6..7]

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The AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The Atmel

ATmega328P provides the following features: 32K bytes of in-system programmable flash with read-while-write capabilities, 1K bytes EEPROM, 2K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byteoriented 2-wire serial interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable watchdog timer with internal oscillator, and five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire serial interface, SPI port, and interrupt system to continue functioning. The power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC noise reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured using Atmel high density non-volatile memory technology. The on-chip ISP flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the application flash memory. Software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8-bit RISC CPU with in-system self-programmable flash on a monolithic chip, the Atmel ATmega328P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega328P AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

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3. Resources

A comprehensive set of development tools, application notes and datasheets are available for download on

http://www.atmel.com/avr.

4. Data Retention

Reliability qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

5. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

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6. AVR CPU Core

Status and

Control

Interrupt

Unit

32 x 8 General Purpose

Registers

ALU

Data Bus 8-bit

Data

SRAM

SPI Unit

Instruction

Decoder

Watchdog

Timer

Analog

Comparator

EEPROM

I/O Lines

I/O Module n

Control Lines

Direct Addressing

Indirect Addressing

I/O Module 2

I/O Module 1

Program

Counter

Flash Program Memory

6.1 Overview

This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Figure 6-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system reprogrammable flash memory.

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The fast-access register file contains 32  8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle arithmetic logic unit (ALU) operation. In a typical ALU operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR 32-bit instruction.

Program flash memory space is divided in two sections, the boot program section and the application program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that writes into the application flash memory section must reside in the boot program section.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The stack pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5F. In addition, the ATmega328P has extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

instructions have a single 16-bit word format. Every program memory address contains a 16- or

6.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Section “” on page 281 for a detailed description.

6.3 Status Register

The status register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

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6.3.1 SREG – AVR Status Register

The AVR status register – SREG – is defined as:

Bit 76543210

0x3F (0x5F) I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

• Bit 7 – I: Global Interrupt Enable

The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The bit copy instructions BLD (bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The half carry flag H indicates a half carry in some arithmetic operations. Half carry Is useful in BCD arithmetic. See Section

“” on page 281 for detailed information.

• Bit 4 – S: Sign Bit, S = N

 V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See Section “”

on page 281 for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See Section “” on page 281 for detailed information.

• Bit 2 – N: Negative Flag

The negative flag N indicates a negative result in an arithmetic or logic operation. See Section “” on page 281 for detailed information.

• Bit 1 – Z: Zero Flag

The zero flag Z indicates a zero result in an arithmetic or logic operation. See Section “” on page 281 for detailed information.

• Bit 0 – C: Carry Flag

The carry flag C indicates a carry in an arithmetic or logic operation. See Section “” on page 281 for detailed information.

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6.4 General Purpose Register File

The register file is optimized for the AVR® enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the register file:

● One 8-bit output operand and one 8-bit result input

● Two 8-bit output operands and one 8-bit result input

● Two 8-bit output operands and one 16-bit result input

● One 16-bit output operand and one 16-bit result input

Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6-2. AVR CPU General Purpose Working Registers

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 6-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

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6.4.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6-3.

Figure 6-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

6.5 Stack Pointer

The stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the stack is implemented as growing from higher to lower memory locations. The stack pointer register always points to the top of the stack. The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks are located. A stack PUSH command will decrease the stack pointer.

The stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. initial stack pointer value equals the last address of the internal SRAM and the stack pointer must be set to point above start of the SRAM, see Figure 7-2 on page 18.

See Table 6-1 for stack pointer details.

Table 6-1. Stack Pointer instructions

Instruction Stack pointer Description

PUSH Decremented by 1 Data is pushed onto the stack

CALL ICALL

Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt

RCALL

POP Incremented by 1 Data is popped from the stack

RET RETI

Incremented by 2

The AVR stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR

Return address is popped from the stack with return from subroutine or return from interrupt

architecture is so small that only

SPL is needed. In this case, the SPH register will not be present.

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6.5.1 SPH and SPL – Stack Pointer High and Stack Point er Low Register

clk

CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

T1 T2 T3 T4

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

clk

CPU

Result Write Back

ALU Operation Execute

Total Execution Time

T2 T3 T4

Bit 151413121110 9 8

0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/WR/WR/WR/WR/WR/WR/WR/W

Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

6.6 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR® CPU is driven by the CPU clock clk

Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the

fast-access register file concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 6-4. The Parallel Instruction Fetches and Instruction Executions

, directly generated from the selected clock source for the chip. No internal clock division is used.

CPU

Figure 6-5 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register

operands is executed, and the result is stored back to the destination register.

Figure 6-5. Single Cycle ALU Operation

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6.7 Reset and Interrupt Handling

The AVR® provides several different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. Depending on the program counter value, interrupts may be automatically disabled when boot lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the Section 27. “Memory Programming” on page 241 for details.

The lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. The complete list of vectors is shown in Section 11. “Interrupts” on page 49. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the external interrupt request 0. The interrupt vectors can be moved to the start of the boot flash section by setting the IVSEL bit in the MCU control register (MCUCR). Refer to Section 11. “Interrupts” on page 49 for more information. The reset vector can also be moved to the start of the boot flash section by programming the BOOTRST fuse, see Section 26. “Boot Loader

Support – Read-While-Write Self-Programming” on page 229.

When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a return from interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

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When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */

6.7.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR® interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the program counter is pushed onto the stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the I-bit in SREG is set.

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7. AVR Memories

0x0000

0x3FFF

Boot Flash Section

Program Memory

Application Flash Section

7.1 Overview

This section describes the different memories in the ATmega328P. The AVR® architecture has two main memory spaces, the data memory and the program memory space. In addition, the ATmega328P features an EEPROM memory for data storage. All three memory spaces are linear and regular.

7.2 In-System Reprogrammable Flash Program Memory

The ATmega328P contains 32Kbytes on-chip in-system reprogrammable flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the flash is organized as 16K 16. For software security, the flash program memory space is divided into two sections, boot loader section and application program section in ATmega328P. See SELFPRGEN description in Section 25.3.1 “SPMCSR – Store Program Memory Control and Status Register” on page 228 and Section

26.9.1 “SPMCSR – Store Program Memory Control and Status Register” on page 239 for more details.

The flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega328P program counter (PC) is 14 bits wide, thus addressing the 16K program memory locations. The operation of boot program section and associated boot lock bits for software protection are described in detail in Section 25. “Self-Programming the Flash, ATmega328P” on page

223 and Section 26. “Boot Loader Support – Read-While-Write Self-Programming” on page 229. Section 27. “Memory Programming” on page 241 contains a detailed description on flash programming in SPI- or parallel programming mode.

Constant tables can be allocated within the entire program memory address space (see the LPM – load program memory instruction description).

Timing diagrams for instruction fetch and execution are presented in Section 6.6 “Instruction Execution Timing” on page 14.

Figure 7-1. Program Memory Map ATmega328P

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7.3 SRAM Data Memory

32 Registers

Data Memory

0x0000 - 0x001F

0x0020 - 0x005F

0x0060 - 0x00FF

0x0100

0x08FF

64 I/O Registers

160 Ext I/O Registers

Internal SRAM

(1048 x 8)

Figure 7-2 shows how the ATmega328P SRAM memory is organized.

The ATmega328P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower 2303 data memory locations address both the register file, the I/O memory, extended I/O memory, and the internal data SRAM. The first 32 locations address the register file, the next 64 location the standard I/O memory, then 160 locations of extended I/O memory, and the next 2048 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, indirect with displacement, indirect, indirect with pre-decrement, and indirect with post-increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The indirect with displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, 160 extended I/O registers, and the 2048 bytes of internal data SRAM in the ATmega328P are all accessible through all these addressing modes. The register file is described in

Section 6.4 “General Purpose Register File” on page 12.

Figure 7-2. Data Memory Map

7.3.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

cycles as described in Figure 7-3.

CPU

Figure 7-3. On-chip Data SRAM Access Cycles

clk

CPU

ddress

Data

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Memory Access Instruction

T2 T3

Address validCompute Address

Write

Read

Next Instruction

7.4 EEPROM Data Memory

The Atmel® ATmega328P contains 1Kbyte of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM address registers, the EEPROM data register, and the EEPROM control register.

Section 27. “Memory Programming” on page 241 contains a detailed description on EEPROM programming in SPI or

parallel programming mode.

7.4.1 EEPROM Read/Write Access

The EEPROM access registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 7-2 on page 22. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See Section 7.4.2 “Preventing EEPROM Corruption” on page 19 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM control register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

7.4.2 Preventing EEPROM Corruption

is likely to rise or fall slowly on power-up/down. This

During periods of low V EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal brown-out detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V operation will be completed provided that the power supply voltage is sufficient.

7.5 I/O Memory

The I/O space definition of the ATmega328P is shown in Section “” on page 275.

All ATmega328P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega328P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the

CC,

reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write

, the CBI and SBI

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7.5.1 General Purpose I/O Registers

The Atmel® ATmega328P contains three general purpose I/O registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. General purpose I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

7.6 Register Description

7.6.1 EEARH and EEARL – The EEPROM Address Register

Bit 151413121110 9 8

0x22 (0x42) –––––––EEAR8EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/Write R R R R R R R R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 X

XXXXXXXX

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the Atmel ATmega328P and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM address registers – EEARH and EEARL specify the EEPROM address in the 256/512/512/1K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 255/511/511/1023. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

EEAR8 is an unused bit in ATmega328P and must always be written to zero.

7.6.2 EEDR – The EEPROM Data Register

Bit 76543210

0x20 (0x40) MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

7.6.3 EECR – The EEPROM Control Register

Bit 76543210

0x1F (0x3F) – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 X X 0 0 X 0

• Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the Atmel ATmega328P and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations in two different operations. The programming times for the different modes are shown in Table 7-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

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Table 7-1. EEPROM Mode Bits

EEPM1 EEPM0 Programming Time Operation

0 0 3.4ms Erase and write in one operation (atomic operation)

0 1 1.8ms Erase only

1 0 1.8ms Write only

1 1 – Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM ready interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM ready interrupt generates a constant interrupt when EEPE is cleared. The interrupt will not be generated during EEPROM write or SPM.

• Bit 2 – EEMPE: EEPROM Master Write Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Write Enable

The EEPROM Write enable signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.

2. Wait until SELFPRGEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the flash memory. The software must check that the flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the flash. If the flash is never being updated by the CPU, step 2 can be omitted. See

Section 26. “Boot Loader Support – Read-While-Write Self-Programming” on page 229 for details about boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM master write enable

will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM read enable signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register.

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The calibrated oscillator is used to time the EEPROM accesses. Table 7-2 lists the typical programming time for EEPROM access from the CPU.

Table 7-2. EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles Typical Programming Time

EEPROM write (from

CPU)

26,368 3.3ms

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18 out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData) {

/* Wait for completion of previous write */ while(EECR & (1<<EEPE)) ; /* Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18 out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress) {

/* Wait for completion of previous write */

while(EECR & (1<<EEPE)) ; /* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

7.6.4 GPIOR2 – General Purpose I/O Register 2

Bit 76543210

0x2B (0x4B) MSB LSB GPIOR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

7.6.5 GPIOR1 – General Purpose I/O Register 1

Bit 76543210

0x2A (0x4A) MSB LSB GPIOR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

7.6.6 GPIOR0 – General Purpose I/O Register 0

Bit 76543210

0x1E (0x3E) MSB LSB GPIOR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

Figure 8-1 presents the principal clock systems in the AVR® and their distribution. All of the clocks need not be active at a

given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in Section 9. “Power Management and Sleep Modes” on page 34. The clock systems are detailed below.

Figure 8-1. Clock Distribution

Asynchronous Timer/Counter

Timer/Counter

Oscillator

General I/O

Modules

clk

I/O

clk

ASY

External Clock

ADC

clk

ADC

AVR Clock

Control Unit

System Clock

Prescaler

Source clock Watchdog clock

Clock

Multiplexer

Oscillator

Crystal

CPU Core

clk

CPU

clk

FLASH

Reset Logic Watchdog Timer

RAM

Watchdog

Oscillator

Low-frequency

Crystal Oscillator

Flash and EEPROM

Calibrated RC

Oscillator

8.1.1 CPU Clock – clk

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the general purpose register file, the status register and the data memory holding the stack pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

8.1.2 I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that start condition detection in the USI module is carried out asynchronously when clk

8.1.3 Flash Clock – clk

The flash clock controls operation of the flash interface. The flash clock is usually active simultaneously with the CPU clock.

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CPU

FLASH

is halted, TWI address recognition in all sleep modes.

I/O

8.1.4 Asynchronous Ti mer Clock – clk

The asynchronous timer clock allows the asynchronous Timer/Counter to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode.

ASY

8.1.5 ADC Clock – clk

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

8.2 Clock Sources

The device has the following clock source options, selectable by flash fuse bits as shown below. The clock from the selected source is input to the AVR

Table 8-1. Device Clocking Options Select

Device Clocking Option CKSEL3..0

Low power crystal oscillator 1111 - 1000

Full swing crystal oscillator 0111 - 0110

Low frequency crystal oscillator 0101 - 0100

Internal 128kHz RC oscillator 0011

Calibrated internal RC oscillator 0010

External clock 0000

Reserved 0001 Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

8.2.1 Default Clock Source

The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = “0010”, SUT = “10”, CKDIV8 = “0”). The default setting ensures that all users can make their desired clock source setting using any available programming interface.

clock generator, and routed to the appropriate modules.

(1)

8.2.2 Clock Startup Sequence

Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it can be considered stable.

To ensure sufficient V all other reset sources. Section 10. “System Control and Reset” on page 40 describes the start conditions for the internal reset. The delay (t CKSELx fuse bits. The selectable delays are shown in Table 8-2. The frequency of the watchdog oscillator is voltage dependent as shown in Section 29. “Typical Characteristics” on page 268.

Table 8-2. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V actual voltage and it will be required to select a delay longer than the V external brown-out detection circuit should be used. A BOD circuit will ensure sufficient V the time-out delay can be disabled. Disabling the time-out delay without utilizing a brown-out detection circuit is not recommended.

, the device issues an internal reset with a time-out delay (t

) is timed from the watchdog oscillator and the number of cycles in the delay is set by the SUTx and

TOUT

0ms 0ms 0

4.1ms 4.3ms 512

65ms 69ms 8K (8,192)

) after the device reset is released by

TOUT

. The delay will not monitor the

rise time. If this is not possible, an internal or

before it releases the reset, and

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The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple

XTAL2 (TOSC2)

XTAL1 (TOSC1)

GND

counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from power-save or power-down mode, V start-up time is included.

8.3 Low Power Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 8-2. Either a quartz crystal or a ceramic resonator may be used.

This crystal oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. In these cases, refer to the Section 8.4 “Full Swing Crystal Oscillator” on page 27.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 8-3. For ceramic resonators, the capacitor values given by the manufacturer should be used.

Figure 8-2. Crystal Oscillator Connections

is assumed to be at a sufficient level and only the

The low power oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-3.

Table 8-3. Low Power Crystal Oscillator Operating Modes

Frequency Range

(MHz)

Recommended Range for

Capacitors C1 and C2 (pF)

0.4 to 0.9 – 100

(2)

CKSEL3..1

(1)

0.9 to 3.0 12 to 22 101

3.0 to 8.0 12 to 22 110

8.0 to 16.0 12 to 22 111

Notes: 1. .This option should not be used with crystals, only with ceramic resonators.

2. If 8MHz frequency exceeds the specification of the device (depends on V

), the CKDIV8 fuse can be

programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device.

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The CKSEL0 fuse together with the SUT1..0 fuses select the start-up times as shown in Table 8-4.

Table 8-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection

Oscillator Source / Power Conditions

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Ceramic resonator, BOD enabled

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Start-up Time from Power-

down and Power-save

258CK 14CK + 4.1ms

258CK 14CK + 65ms

1KCK 14CK

1KCK 14CK + 4.1ms

1KCK 14CK + 65ms

Additional Delay from

Reset (V

= 5.0V) CKSEL0 SUT1..0

(1)

(2)

0 00

0 01

0 10

0 11

1 00

Crystal oscillator, BOD enabled 16KCK 14CK 1 01

Crystal oscillator, fast rising power

Crystal oscillator, slowly rising power

16KCK 14CK + 4.1ms 1 10

16KCK 14CK + 65ms 1 11

Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and

only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

8.4 Full Swing Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 8-2 on page 26. Either a quartz crystal or a ceramic resonator may be used.

This crystal oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is useful for driving other clock inputs and in noisy environments. The current consumption is higher than the Section 8.3 “Low Power Crystal Oscillator” on

page 26. Note that the full swing crystal oscillator will only operate for V

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 8-6 on page 28. For ceramic resonators, the capacitor values given by the manufacturer should be used.

The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-5.

Table 8-5. Full Swing Crystal Oscillator operating modes

Frequency Range

0.4 - 16 12 - 22 011

Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.

2. If 8MHz frequency exceeds the specification of the device (depends on V programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device.

(1)

(MHz)

= 2.7 to 5.5V.

(2)

Recommended Range for

Capacitors C1 and C2 (pF) CKSEL3..1

), the CKDIV8 fuse can be

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Figure 8-3. Crystal Oscillator Connections

XTAL2 (TOSC2)

XTAL1 (TOSC1)

GND

Table 8-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection

Oscillator Source /

Power Conditions

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Ceramic resonator, BOD enabled

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Start-up Time from Power-

down and Power-save

258CK 14CK + 4.1ms

258CK 14CK + 65ms

1KCK 14CK

1KCK 14CK + 4.1ms

1KCK 14CK + 65ms

Additional Delay from

Reset (VCC = 5.0V) CKSEL0 SUT1..0

(1)

(2)

0 00

0 01

0 10

0 11

1 00

Crystal oscillator, BOD enabled 16KCK 14CK 1 01

Crystal oscillator, fast rising power

Crystal oscillator, slowly rising power

16KCK 14CK + 4.1ms 1 10

16KCK 14CK + 65ms 1 11

Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and

only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

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8.5 Low Frequency Crystal Oscillator

C2CL C

–=

The low-frequency crystal oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load capacitance and crystal’s equivalent series resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega328P oscillator is optimized for very low power consumption, and thus when selecting crystals, see Table 8-7 for maximum ESR recommendations on 6.5pF, 9.0pF and 12.5pF crystals

Table 8-7. Maximum ESR Recommendation for 32.768 kHz Crystal

Crystal CL (pF) Max ESR [k]

6.5 75

9.0 65

12.5 30

Note: 1. Maximum ESR is typical value based on characterization

The low-frequency crystal oscillator provides an internal load capacitance of typical 6pF at each TOSC pin. The external capacitance (C) needed at each TOSC pin can be calculated by using:

(1)

where CL is the load capacitance for a 32.768kHz crystal specified by the crystal vendor and C

is the total stray

capacitance for one TOSC pin.

Crystals specifying load capacitance (CL) higher than 6pF, require external capacitors applied as described in

Figure 8-2 on page 26.

The low-frequency crystal oscillator must be selected by setting the CKSEL fuses to “0110” or “0111”, as shown in Ta b le 8 - 9 . Start-up times are determined by the SUT fuses as shown in Table 8-8.

Table 8-8. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

SUT1..0 Additional Delay from Reset (VCC = 5.0V) Recommended Usage

00 4CK Fast rising power or BOD enabled

01 4CK + 4.1ms Slowly rising power

10 4CK + 65ms Stable frequency at start-up

11 Reserved

Table 8-9. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

Start-up Time from

CKSEL3..0

(1)

0100

Power-down and Power-save

1KCK

Recommended Usage

0101 32KCK Stable frequency at start-up

Note: 1. This option should only be used if frequency stability at start-up is not important for the application

8.6 Calibrated Internal RC Oscillator

By default, the internal RC oscillator provides an approximate 8.0MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 28-1 on page 260 for more details. The device is shipped with the CKDIV8 fuse programmed. See Section 8.11 “System Clock Prescaler” on page 32 for more details.

This clock may be selected as the system clock by programming the CKSEL fuses as shown in Table 8-10 on page 30. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL register and thereby automatically calibrates the RC oscillator. The accuracy of this calibration is shown as factory calibration in Table 28-1 on page 260.

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By changing the OSCCAL register from SW, see Section 8.12.1 “OSCCAL – Oscillator Calibration Register” on page 32, it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in Table 28-1 on page 260.

When this oscillator is used as the chip clock, the watchdog oscillator will still be used for the watchdog timer and for the reset time-out. For more information on the pre-programmed calibration value, see Section 27.4 “Calibration Byte” on page

244.

Table 8-10. Internal Calibrated RC Oscillator Operating Modes

Nominal Frequency (MHz) CKSEL3..0

8 0010

Notes: 1. The device is shipped with this option selected.

2. If 8MHz frequency exceeds the specification of the device (depends on V programmed in order to divide the internal frequency by 8.

When this oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 8-11.

Table 8-11. Start-up Times for the Internal calibrated RC Oscillator Clock Selection

Power Conditions

BOD enabled 6CK 14CK

Fast rising power 6CK 14CK + 4.1ms 01

Slowly rising power 6CK 14CK + 65ms

Notes: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to

14CK + 4.1ms to ensure programming mode can be entered.

The device is shipped with this option selected.

8.7 128 kHz Internal Oscillator

The 128kHz internal oscillator is a low power oscillator providing a clock of 128kHz. The frequency is nominal at 3V and 25°C. This clock may be select as the system clock by programming the CKSEL fuses to “11” as shown in Table 8-12.

Table 8-12. 128kHz Internal Oscillator Operating Modes

(1)(2)

Start-up Time from Power-down and

Power-save

Reserved 11

), the CKDIV8 fuse can be

Additional Delay from Reset

(VCC = 5.0V) SUT1..0

(1)

(2)

Nominal Frequency CKSEL3..0

128kHz 0011

When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 8-13.

Table 8-13. Start-up Times for the 128 kHz Internal Oscillator

Start-up Time from Power-down and

Power Conditions

BOD enabled 6CK 14CK

Power-save Additional Delay from Reset SUT1..0

(1)

Fast rising power 6CK 14CK + 4ms 01

Slowly rising power 6CK 14CK + 64ms 10

Reserved 11

Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to

14CK + 4.1ms to ensure programming mode can be entered.

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8.8 External Clock

XTAL2

XTAL1

GND

EXTERNAL

CLOCK

SIGNAL

To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 8-4. To run the device on an external clock, the CKSEL fuses must be programmed to “0000” (see Table 8-14).

Table 8-14. Crystal Oscillator Clock Frequency

Figure 8-4. External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 8-15.

Table 8-15. Start-up Times for the External Clock Selection

Frequency CKSEL3..0

0 to 16MHz 0000

Power Conditions

BOD enabled 6CK 14CK 00

Fast rising power 6CK 14CK + 4.1ms 01

Slowly rising power 6CK 14CK + 65ms 10

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in reset during the changes.

Note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to Section 8.11 “System Clock Prescaler” on page 32 for details.

8.9 Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC oscillator, can be selected when the clock is output on CLKO. If the system clock prescaler is used, it is the divided system clock that is output.

Start-up Time from Power-down and

Power-save

Reserved 11

Additional Delay from Reset

(VCC = 5.0V) SUT1..0

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8.10 Timer/Counter Oscillator

Atmel® ATmega328P uses the same crystal oscillator for low-frequency oscillator and Timer/Counter oscillator. See Section

8.5 “Low Frequency Crystal Oscillator” on page 29 for details on the oscillator and crystal requirements.

Atmel ATmega328P share the Timer/Counter oscillator pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. When using the Timer/Counter oscillator, the system clock needs to be four times the oscillator frequency. Due to this and the pin sharing, the Timer/Counter oscillator can only be used when the calibrated internal RC oscillator is selected as system clock source.

Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR register is written to logic one. See Section

17.9 “Asynchronous Operation of Timer/Counter2” on page 126 for further description on selecting external clock as input

instead of a 32.768kHz watch crystal.

8.11 System Clock Prescaler

The Atmel ATmega328P has a system clock prescaler, and the system clock can be divided by setting the Section 8.12.2

“CLKPR – Clock Prescale Register” on page 33. This feature can be used to decrease the system clock frequency and the

power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk a factor as shown in Table 28-4 on page 261.

When switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2  T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1. Write the clock prescaler change enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.

I/O

, clk

ADC

, clk

CPU

, and clk

are divided by

FLASH

8.12 Register Description

8.12.1 OSCCAL – Oscillator Calibration Register

Bit 76543210

(0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value Device Specific Calibration Value

• Bits 7..0 – CAL7..0: Oscillator Calibration Va lue

The oscillator calibration register is used to trim the calibrated internal RC oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the factory calibrated frequency as specified in Table 28-1 on page 260. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 28-1 on page 260. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and flash write accesses, and these write times will be affected accordingly. If the EEPROM or flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM or flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range.

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8.12.2 CLKPR – Clock Prescale Register

Bit 76543210

(0x61) CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

Read/Write R/W R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 8-16.

The CKDIV8 fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 fuse setting. The application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 fuse programmed.

Table 8-16. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0 0 0 0 1

0 0 0 1 2

0 0 1 0 4

0 0 1 1 8

0 1 0 0 16

0 1 0 1 32

0 1 1 0 64

0 1 1 1 128

1 0 0 0 256

1 0 0 1 Reserved

1 0 1 0 Reserved

1 0 1 1 Reserved

1 1 0 0 Reserved

1 1 0 1 Reserved

1 1 1 0 Reserved

1 1 1 1 Reserved

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9. Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR® provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.

When enabled, the brown-out detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes. See Section 9.2 “BOD Disable” on page 35 for more details.

9.1 Sleep Modes

Figure 8-1 on page 24 presents the different clock systems in the Atmel® ATmega328P, and their distribution. The figure is

helpful in selecting an appropriate sleep mode. Table 9-1 shows the different sleep modes, their wake up sources BOD disable ability.

Table 9-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains Oscillators Wake-up Sources

CPU

Sleep Mode

clk

FLASH

clk

Idle X X X X X

ADC noise Reduction

Power-down X

Power-save X X

Standby

(1)

Extended Standby

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. If Timer/Counter2 is running in asynchronous mode.

3. For INT1 and INT0, only level interrupt.

ADC

ASY

clkIOclk

clk

X X X X

X X

(2)

X X

Main Clock

Source Enabled

Timer Oscillator

Enabled

(2)

X X X X X X X

(3)

INT1, INT0 and

Pin Change

TWI Address

Match

X X

Timer2

SPM/EEPROM

Ready

(2)

X X X

X X X X

X X X

X X X X

ADC

WDT

Software

BOD Disable

Other/O

To enter any of the six sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR register select which sleep mode (idle, ADC noise reduction, powerdown, power-save, standby, or extended standby) will be activated by the SLEEP instruction. See Table 9-2 on page 38 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the reset vector.

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9.2 BOD Disable

When the brown-out detector (BOD) is enabled by BODLEVEL fuses, Table 27-7 on page 244, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 9-1 on page 34. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe operation in case the V

level has dropped during the sleep period.

When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60µs to ensure that the BOD is working correctly before the MCU continues executing code.

BOD disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see Section 9.11.2 “MCUCR – MCU

Control Register” on page 38. Writing this bit to one turns off the BOD in relevant sleep modes, while a zero in this bit keeps

BOD active. Default setting keeps BOD active, i.e. BODS set to zero.

Writing to the BODS bit is controlled by a timed sequence and an enable bit, see Section 9.11.2 “MCUCR – MCU Control

9.3 Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter idle mode, stopping the CPU but allowing the SPI, USART, analog comparator, ADC, 2-wire serial interface, Timer/Counters, watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the timer overflow and USART transmit complete interrupts. If wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the ACD bit in the analog comparator control and status register – ACSR. This will reduce power consumption in idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

CPU

and clk

, while allowing the other clocks to run.

FLASH

9.4 ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC noise reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-wire serial interface address watch, Timer/Counter2 watchdog to continue operating (if enabled). This sleep mode basically halts clk other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC conversion complete interrupt, only an external reset, a watchdog system reset, a watchdog interrupt, a brown-out reset, a 2-wire serial interface address match, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or INT1 or a pin change interrupt can wake up the MCU from ADC noise reduction mode.

Note: 1. Timer/Counter2 will only keep running in asynchronous mode, see Section 17. “8-bit Timer/Counter2 with

PWM and Asynchronous Operation” on page 116 for details.

9.5 Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter power-down mode. In this mode, the external oscillator is stopped, while the external interrupts, the 2-wire serial interface address watch, and the watchdog continue operating (if enabled). Only an external reset, a watchdog system reset, a watchdog interrupt, a brown-out reset, a 2-wire serial interface address match, an external level interrupt on INT0 or INT1, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the MCU. Refer to Section 12. “External Interrupts” on page 53 for details.

When waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL fuses that define the reset time-out period, as described in Section 8.2 “Clock Sources” on page 25.

I/O

, clk

CPU

, and clk

, while allowing the

FLASH

(1)

, and the

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9.6 Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter power-save mode. This mode is identical to power-down, with one exception:

If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either timer overflow or output compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the global interrupt enable bit in SREG is set.

If Timer/Counter2 is not running, power-down mode is recommended instead of power-save mode.

The Timer/Counter2 can be clocked both synchronously and asynchronously in power-save mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter oscillator is stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in power-save, this clock is only available for Timer/Counter2.

9.7 Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter standby mode. This mode is identical to power-down with the exception that the oscillator is kept running. from standby mode, the device wakes up in six clock cycles.

9.8 Extended Standby Mode

When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter extended standby mode. This mode is identical to power-save with the exception that the oscillator is kept running. From extended standby mode, the device wakes up in six clock cycles.

9.9 Power Reduction Register

The power reduction register (PRR), see Section 9.11.3 “PRR – Power Reduction Register” on page 38, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped.

9.10 Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an AVR® controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

9.10.1 Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to Section

23. “Analog-to-Digital Converter” on page 205 for details on ADC operation.

9.10.2 Analog Comparator

When entering Idle mode, the analog comparator should be disabled if not used. When entering ADC noise reduction mode, the analog comparator should be disabled. In other sleep modes, the analog comparator is automatically disabled. However, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. Otherwise, the internal voltage reference will be enabled, independent of sleep mode. Refer to Section 22.

“Analog Comparator” on page 202 for details on how to configure the analog comparator.

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9.10.3 Brown-out Detector

If the brown-out detector is not needed by the application, this module should be turned off. If the brown-out detector is enabled by the BODLEVEL fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Section 10.5 “Brown-out Detection”

on page 42 for details on how to configure the brown-out detector.

9.10.4 Internal Vol tage Reference

The internal voltage reference will be enabled when needed by the brown-out detection, the analog comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to Section 10.7 “Internal Voltage

Reference” on page 43 for details on the start-up time.

9.10.5 Watchdog Timer

If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Section 10.8 “Watchdog Timer” on page 43 for details on how to configure the watchdog timer.

9.10.6 Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the Section

13.2.5 “Digital Input Enable and Sleep Modes” on page 62 for details on which pins are enabled. If the input buffer is enabled

and the input signal is left floating or have an analog signal level close to V

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the digital input disable registers (DIDR1 and DIDR0). Refer to Section 22.3.3 “DIDR1 – Digital Input Disable Register 1” on page 204 and

Section 23.9.5 “DIDR0 – Digital Input Disable Register 0” on page 220 for details.

) and the ADC clock (clk

I/O

/2, the input buffer will use excessive power.

) are stopped,

ADC

9.10.7 On-chip Debug System

If the on-chip debug system is enabled by the DWEN fuse and the chip enters sleep mode, the main clock source is enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.

9.11 Register Description

9.11.1 SMCR – Sleep Mode Control Register

The sleep mode control register contains control bits for power management.

Bit 76543210

0x33 (0x53) ––––SM2SM1SM0SESMCR

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 7..4 Res: Reserved Bits

These bits are unused bits in the Atmel

ATmega328P, and will always read as zero.

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• Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 9-2 on page 38.

Table 9-2. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

0 0 0 Idle

0 0 1 ADC noise reduction

0 1 0 Power-down

0 1 1 Power-save

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Standby

1 1 1 External standby

Note: 1. Standby mode is only recommended for use with external crystals or resonators.

• Bit 0 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the sleep enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.

9.11.2 MCUCR – MCU Control Register

Bit 7 6 5 4 3 2 1 0

0x35 (0x55) – BODS BODSE

Read/Write R R R R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

(1)

PUD – – IVSEL IVCE MCUCR

• Bit 6 – BODS: BOD Sleep

The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 9-1 on page 34. Writing to the BODS bit is controlled by a timed sequence and an enable bit, BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to zero within four clock cycles.

The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.

• Bit 5 – BODSE: BOD Sleep Enable

BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence.

9.11.3 PRR – Power Reduction Register

Bit 765 4 32 1 0

(0x64) PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC PRR

Read/Write R/W R/W R/W R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 - PRTWI: Power Reduction TWI

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.

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• Bit 6 - PRTIM2: Power Reduction Timer/Counter2

Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.

• Bit 5 - PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.

• Bit 4 - Res: Reserved bit

This bit is reserved in Atmel

ATmega328P and will always read as zero.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

If using debugWIRE on-chip debug system, this bit should not be written to one.

Writing a logic one to this bit shuts down the serial peripheral interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation.

• Bit 1 - PRUSART0: Power Reduction USART0

Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the USART again, the USART should be re initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.

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10. System Control and Reset

Power-on Reset

Circuit

Brown-out

Reset Circuit

MCU Status

Reset Circuit

Pull-up Resistor

BODLEVEL [2..0]

DATA BUS

SUT[1:0]

CKSEL[3:0]

RSTDISBL

COUNTER RESET

INTERNAL RESET

TIMEOUT

SPIKE

FILTER

RESET

VCC

Delay Counters

Watchdog

Timer

Watchdog

Oscillator

Clock

Generator

PORF

BORF

WDRF

EXTRF

10.1 Resetting the AVR

During reset, all I/O registers are set to their initial values, and the program starts execution from the reset vector. For the

Atmel

ATmega328P, the instruction placed at the reset vector must be an RJMP – relative jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section. The circuit diagram in Figure 10-1 shows the reset logic. Table 28-4 on page 261 defines the electrical parameters of the reset circuitry. The I/O ports of the AVR source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL fuses. The different selections for the delay period are presented in Section 8.2 “Clock Sources” on page 25.

10.2 Reset Sources

The Atmel ATmega328P has four sources of reset:

● Power-on reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V

● External reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse

length.

● Watchdog system reset. The MCU is reset when the watchdog timer period expires and the watchdog system reset

mode is enabled.

● Brown-out reset. The MCU is reset when the supply voltage V

brown-out detector is enabled.

are immediately reset to their initial state when a reset

POT

is below the brown-out reset threshold (V

) and the

BOT

Figure 10-1. Reset Logic

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10.3 Power-on Reset

A power-on reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in Section 28.6

“System and Reset Characteristics” on page 261. The POR is activated whenever V

circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage.

A power-on reset (POR) circuit ensures that the device is reset from power-on. Reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V is activated again, without any delay, when V

decreases below the detection level.

is below the detection level. The POR

rise. The RESET signal

Figure 10-2. MCU Start-up, RESET

RESET

Time-out

Internal

Reset

Figure 10-3. . MCU Start-up, RESET

RESET

Time-out

Internal

Reset

Tied to VCC

POT

RST

TOUT

Extended Externally

POT

RST

TOUT

Table 10-1. Power On Reset Specifications

Symbol Parameter Min Typ Max Units

POT

PORMAX

PORMIN

CCRR

Note: 1. Before rising, the supply has to be between V

Power-on reset threshold voltage (rising) 1.4 V

Power-on reset threshold voltage (falling)

VCC Max. start voltage to ensure internal power-on reset signal

VCC Min. start voltage to ensure internal power-on reset signal

(1)

1.0 1.3 1.6 V

0.4 V

-0.1 V

VCC rise rate to ensure power-on reset 0.01 V/ms

PORMIN

and V

to ensure a reset

PORMAX

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10.4 External Reset

TOUT

RESET

INTERNAL

RESET

TIME-OUT

RST

An external reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see

Section 28.6 “System and Reset Characteristics” on page 261) will generate a reset, even if the clock is not running. Shorter

pulses are not guaranteed to generate a reset. When the applied signal reaches the reset threshold voltage – V positive edge, the delay counter starts the MCU after the time-out period – t disabled by the RSTDISBL fuse, see Table 27-7 on page 244.

Figure 10-4. External Reset During Operation

10.5 Brown-out Detection

Atmel® ATmega328P has an on-chip brown-out detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL fuses. The trigger level has a hysteresis to ensure spike free brown-out detection. The hysteresis on the detection level should be interpreted as V

= V

BOT+

BOT

+ V trigger level (V (V

in Figure 10-5), the delay counter starts the MCU after the time-out period t

BOT+

The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than t

28.6 “System and Reset Characteristics” on page 261.

/2 and V

HYST

in Figure 10-5), the brown-out reset is immediately activated. When VCC increases above the trigger level

BOT-

BOT–

= V

BOT

– V

has expired. The external reset can be

TOUT –

/2.When the BOD is enabled, and VCC decreases to a value below the

HYST

has expired.

TOUT

given in Section

BOD

– on its

RST

Figure 10-5. Brown-out Reset During Operation

RESET

TIME-OUT

INTERNAL

RESET

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BOT-

BOT+

TOUT

10.6 Watchdog System Reset

When the watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period t operation of the watchdog timer.

Figure 10-6. Watchdog System Reset During Operation

RESET

WDT

TIME-OUT

RESET

Time-OUT

INTERNAL

RESET

10.7 Internal Voltage Reference

Atmel® ATmega328P features an internal bandgap reference. This reference is used for brown-out detection, and it can be used as an input to the analog comparator or the ADC.

. Refer to Section 10.8 “Watchdog Timer” on page 43 for details on

TOUT

1 CK Cycle

TOUT

10.7.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Section

28.6 “System and Reset Characteristics” on page 261. To save power, the reference is not always turned on. The reference

is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).

2. When the bandgap reference is connected to the analog comparator (by setting the ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the analog comparator or ADC is used. To reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode.

10.8 Watchdog Timer

10.8.1 Features

Clocked from separate on-chip oscillator

●

● 3 operating modes

● Interrupt

● System reset

● Interrupt and system reset

● Selectable time-out period from 16ms to 8s

● Possible hardware fuse watchdog always on (WDTON) for fail-safe mode

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10.8.2 Overview

Atmel® ATmega328P has an enhanced watchdog timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR - watchdog timer reset - instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.

Figure 10-7. Watchdog Timer

OSC/4K

OSC/8K

Watchdog

Prescaler

OSC/64K

OSC/16K

OSC/32K

OSC/128K

OSC/256K

OSC/512K

OSC/1024K

WDP0 WDP1 WDP2 WDP3

MCU RESET

INTERRUPT

128kHz

Oscillator

OSC/2K

WATCHDOG

RESET

WDE

WDIF

WDIE

In interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In system reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and system reset mode, combines the other two modes by first giving an interrupt and then switch to system reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset.

The watchdog always on (WDTON) fuse, if programmed, will force the watchdog timer to system reset mode. With the fuse programmed the system reset mode bit (WDE) and interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the watchdog set-up must follow timed sequences.

The sequence for clearing WDE and changing time-out configuration is as follows:

1. In the same operation, write a logic one to the watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, write the WDE and watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation.

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The following code example shows one assembly and one C function for turning off the watchdog timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.

Assembly Code Example

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in r16, MCUSR andi r16, (0xff & (0<<WDRF)) out MCUSR, r16

; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional time-out

lds r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) sts WDTCSR, r16

; Turn off WDT

ldi r16, (0<<WDE) sts WDTCSR, r16

; Turn on global interrupt

sei ret

C Code Example

(1)

void WDT_off(void) {

__disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out

WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt();

}

(1)

Note: 1. See Section 5. “About Code Examples” on page 8.

2. Note: If the watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the watchdog timer will stay enabled. If the code is not set up to handle the watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the watchdog system reset flag (WDRF) and the WDE control bit in the initialization routine, even if the watchdog is not in use.

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The following code example shows one assembly and one C function for changing the time-out value of the watchdog timer.

Assembly Code Example

(1)

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

lds r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) sts WDTCSR, r16

; -- Got four cycles to set the new values from here ; Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0) sts WDTCSR, r16

; -- Finished setting new values, used 2 cycles ; Turn on global interrupt

sei ret

C Code Example

(1)

void WDT_Prescaler_Change(void) {

__disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */ WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt();

}

Note: 1. See Section 5. “About Code Examples” on page 8.

2. The watchdog timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period.

10.9 Register Description

10.9.1 MCUSR – MC U Status Register

The MCU status register provides information on which reset source caused an MCU reset.

Bit 76543210

0x35 (0x55) – – – – WDRF BORF EXTRF PORF MCUSR

Read/Write RRRRR/WR/WR/WR/W

Initial Value 0 0 0 0 See Bit Description

• Bit 7..4: Res: Reserved Bits

These bits are unused bits in the Atmel

• Bit 3 – WDRF: Watchdog System Reset Flag

This bit is set if a watchdog system reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

ATmega328P, and will always read as zero.

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• Bit 1 – EXTRF: External Reset Flag

This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

10.9.2 WDTCSR – Watchdog Timer Control Register

Bit 76543210

(0x60) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 X 0 0 0

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the watchdog timer and the watchdog timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the watchdog time-out interrupt is executed.

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the status register is set, the watchdog interrupt is enabled. If WDE is cleared in combination with this setting, the watchdog timer is in interrupt mode, and the corresponding interrupt is executed if time-out in the watchdog timer occurs. If WDE is set, the watchdog timer is in interrupt and system reset mode. The first time-out in the watchdog timer will set WDIF.

Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the watchdog goes to system reset mode). This is useful for keeping the watchdog timer security while using the interrupt. To stay in interrupt and system reset mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the watchdog system reset mode. If the interrupt is not executed before the next time-out, a system reset will be applied.

Table 10-2. Watchdog Timer Configuration

WDTON

(1)

WDE WDIE Mode Action on Time-out

1 0 0 Stopped None

1 0 1 Interrupt mode Interrupt

1 1 0 System reset mode Reset

1 1 1 Interrupt and system reset mode

Interrupt, then go to system reset mode

0 x x System reset mode Reset

Note: 1. WDTON fuse set to “0” means programmed and “1” means unprogrammed.

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

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• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.

• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3..0 bits determine the watchdog timer prescaling when the watchdog timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 10-3.

Table 10-3. Watchdog Timer Prescale Select

WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V

0 0 0 0 2K (2048) cycles 16ms

0 0 0 1 4K (4096) cycles 32ms

0 0 1 0 8K (8192) cycles 64ms

0 0 1 1 16K (16384) cycles 0.125s

0 1 0 0 32K (32768) cycles 0.25s

0 1 0 1 64K (65536) cycles 0.5s

0 1 1 0 128K (131072) cycles 1.0s

0 1 1 1 256K (262144) cycles 2.0s

1 0 0 0 512K (524288) cycles 4.0s

1 0 0 1 1024K (1048576) cycles 8.0s

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

Reserved

1 1 1 0

1 1 1 1

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11. Interrupts

This section describes the specifics of the interrupt handling as performed in Atmel® ATmega328P. For a general explanation of the AVR

interrupt handling, refer to Section 6.7 “Reset and Interrupt Handling” on page 15.

● Each interrupt vector occupies two instruction words in Atmel ATmega328P.

● In Atmel ATmega328P, the reset vector is affected by the BOOTRST fuse, and the interrupt vector start address is

affected by the IVSEL bit in MCUCR.

11.1 Interrupt Vectors in ATmega328P

Table 11-1. Reset and Interrupt Vectors in ATmega328P

Vector No . Program Address Source Interrupt Definition

1 0x0000 RESET

2 0x002 INT0 External interrupt request 0

3 0x0004 INT1 External interrupt request 1

4 0x0006 PCINT0 Pin change interrupt request 0

5 0x0008 PCINT1 Pin change interrupt request 1

6 0x000A PCINT2 Pin change interrupt request 2

7 0x000C WDT Watchdog time-out interrupt

8 0x000E TIMER2 COMPA Timer/Counter2 compare match A

9 0x0010 TIMER2 COMPB Timer/Counter2 compare match B

10 0x0012 TIMER2 OVF Timer/Counter2 overflow

11 0x0014 TIMER1 CAPT Timer/Counter1 capture event

12 0x0016 TIMER1 COMPA Timer/Counter1 compare match A

13 0x0018 TIMER1 COMPB Timer/Counter1 compare match B

14 0x001A TIMER1 OVF Timer/Counter1 overflow

15 0x001C TIMER0 COMPA Timer/Counter0 compare match A

16 0x001E TIMER0 COMPB Timer/Counter0 compare match B

17 0x0020 TIMER0 OVF Timer/Counter0 overflow

18 0x0022 SPI, STC SPI serial transfer complete

19 0x0024 USART, RX USART Rx complete

20 0x0026 USART, UDRE USART, data register empty

21 0x0028 USART, TX USART, Tx complete

22 0x002A ADC ADC conversion complete

23 0x002C EE READY EEPROM ready

24 0x002E ANALOG COMP Analog comparator

25 0x0030 TWI 2-wire serial interface

26 0x0032 SPM READY Store program memory ready

External pin, power-on reset, brown-out reset and watchdog system reset

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Table 11-2 shows reset and interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings. If the

program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa.

Table 11-2. Reset and Interrupt Vectors Placement in AT mega328P

(1)

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x000 0x002

1 1 0x000 Boot reset address + 0x0002

0 0 Boot reset address 0x002

0 1 Boot reset address Boot reset address + 0x0002

Note: 1. For the BOOTRST fuse “1” means unprogrammed while “0” means programmed.

The most typical and general program setup for the reset and interrupt vector addresses in Atmel

Address Labels Code Comments 0x0000 jmp RESET ; Reset Handler 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x0004 jmp EXT_INT1 ; IRQ1 Handler 0x0006 jmp PCINT0 ; PCINT0 Handler 0x0008 jmp PCINT1 ; PCINT1 Handler 0x000A jmp PCINT2 ; PCINT2 Handler 0x000C jmp WDT ; Watchdog Timer Handler 0x000E jmp TIM2_COMPA ; Timer2 Compare A Handler 0x0010 jmp TIM2_COMPB ; Timer2 Compare B Handler 0x0012 jmp TIM2_OVF ; Timer2 Overflow Handler 0x0014 jmp TIM1_CAPT ; Timer1 Capture Handler 0x0016 jmp TIM1_COMPA ; Timer1 Compare A Handler 0x0018 jmp TIM1_COMPB ; Timer1 Compare B Handler 0x001A jmp TIM1_OVF ; Timer1 Overflow Handler 0x001C jmp TIM0_COMPA ; Timer0 Compare A Handler 0x001E jmp TIM0_COMPB ; Timer0 Compare B Handler 0x0020 jmp TIM0_OVF ; Timer0 Overflow Handler 0x0022 jmp SPI_STC ; SPI Transfer Complete Handler 0x0024 jmp USART_RXC ; USART, RX Complete Handler 0x0026 jmp USART_UDRE ; USART, UDR Empty Handler 0x0028 jmp USART_TXC ; USART, TX Complete Handler 0x002A jmp ADC ; ADC Conversion Complete Handler 0x002C jmp EE_RDY ; EEPROM Ready Handler 0x002E jmp ANA_COMP ; Analog Comparator Handler 0x0030 jmp TWI ; 2-wire Serial Interface Handler 0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler ; 0x0033 RESET: ldi r16, high(RAMEND); Main program start 0x0034 out SPH,r16 ; Set Stack Pointer to top of RAM 0x0035 ldi r16, low(RAMEND) 0x0036 out SPL,r16 0x0037 sei ; Enab le interrupts 0x0038 <instr> xxx

... ... ... ...

ATmega328P is:

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When the BOOTRST fuse is unprogrammed, the boot section size set to 2Kbytes and the IVSEL bit in the MCUCR register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in Atmel

ATmega328P is:

Address Labels Code Comments 0x0000 RESET: ldi r16,high(RAMEND); Main program start 0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x0002 ldi r16,low(RAMEND) 0x0003 out SPL,r16 0x0004 sei ; Enab le interrupts 0x0005 <instr> xxx ; .org 0x3C02 0x3C02 jmp EXT_INT0 ; IRQ0 Handler 0x3C04 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x3C32 jmp SPM_RDY ; Store Program Memory Ready Handler

When the BOOTRST fuse is programmed and the boot section size set to 2Kbytes, the most typical and general program setup for the reset and interrupt vector addresses in Atmel ATmega328P is:

Address Labels Code Comments .org 0x0002 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x0004 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler ; .org 0x3C00 0x3C00 RESET: ldi r16,high(RAMEND); Main program start 0x3C01 out SPH,r16 ; Set Stack Pointer to top of RAM 0x3C02 ldi r16,low(RAMEND) 0x3C03 out SPL,r16 0x3C04 sei ; Enable interrupts 0x3C05 <instr> xxx

When the BOOTRST fuse is programmed, the boot section size set to 2Kbytes and the IVSEL bit in the MCUCR register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in Atmel ATmega328P is:

Address Labels Code Comments ; .org 0x3C00 0x3C00 jmp RESET ; Reset handler 0x3C02 jmp EXT_INT0 ; IRQ0 Handler 0x3C04 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x3C32 jmp SPM_RDY ; Store Program Memory Ready Handler ; 0x3C33 RESET: ldi r16,high(RAMEND); Main program start 0x3C34 out SPH,r16 ; Set Stack Pointer to top of RAM 0x3C35 ldi r16,low(RAMEND) 0x3C36 out SPL,r16 0x3C37 sei ; Enable interrupts 0x3C38 <instr> xxx

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11.2 Register Description

11.2.1 Moving Interrupts Between Application and Boot Space

The MCU control register controls the placement of the interrupt vector table.

11.2.2 MCUCR – MCU Control Register

Bit 76543210

0x35 (0x55)

Read/Write R R R R/W R R R/W R/W

Initial Value00000000

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the flash memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of the flash. The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. Refer to the Section 26. “Boot Loader Support – Read-While-

Write Self-Programming” on page 229 for details. To avoid unintentional changes of interrupt vector tables, a special write

procedure must be followed to change the IVSEL bit:

a. Write the interrupt vector change enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the status register is unaffected by the automatic disabling.

Note: If interrupt vectors are placed in the boot loader section and boot lock bit BLB02 is programmed, interrupts are

This bit is not available in Atmel

– BODS BODSE PUD – – IVSEL IVCE MCUCR

disabled while executing from the application section. If interrupt vectors are placed in the application section and boot lock bit BLB12 is programed, interrupts are disabled while executing from the boot loader section. Refer to the Section 26. “Boot Loader Support – Read-While-Write Self-Programming” on page 229 for details on boot lock bits.

ATmega328P.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See code example below.

Assembly Code Example

Move_interrupts:

; Enable change of Interrupt Vectors

ldi r16, (1<<IVCE) out MCUCR, r16

; Move interrupts to Boot Flash section

ldi r16, (1<<IVSEL) out MCUCR, r16 ret

C Code Example

void Move_interrupts(void) {

/* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL);

}

This bit is not available in Atmel ATmega328P.

ATmega328P [DATASHEET]

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12. External Interrupts

The external interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles. The pin change interrupt PCI0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK2, PCMSK1 and PCMSK0 registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT23..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the external interrupt control register A – EICRA. When the INT0 or INT1 interrupts are enabled and are configured as level triggered, the interrupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires the presence of an I/O clock, described in Section 8.1 “Clock Systems and their

Distribution” on page 24. Low level interrupt on INT0 and INT1 is detected asynchronously. This implies that this interrupt

can be used for waking the part also from sleep modes other than idle mode. The I/O clock is halted in all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL fuses as described in Section 8. “System Clock and Clock Options” on page 24.

12.1 Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 12-1.

Figure 12-1. Timing of Pin Change Interrupts

PCINT(0)

clk

PCINT(0)

pin_lat

pin_sync

pcint_in_(0)

pcint_syn

pcint_setflag

pin_lat pin_sync

PCINT(0) in PCMSK(x)

pcint_in_(0)

clk

pcint_sync

pcint_setflag

PCIF

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12.2 Register Description

12.2.1 EICRA – External Interrupt Control Register A

The external interrupt control register A contains control bits for interrupt sense control.

Bit 76543210

(0x69) – – – – ISC11 ISC10 ISC01 ISC00 EICRA

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7..4 – Res: Reserved Bits

These bits are unused bits in the Atmel

• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The external interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 12-1. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.

T able 12-1. Interrupt 1 Sense Control

ISC11 ISC10 Description

0 0 The low level of INT1 generates an interrupt request.

0 1 Any logical change on INT1 generates an interrupt request.

1 0 The falling edge of INT1 generates an interrupt request.

1 1 The rising edge of INT1 generates an interrupt request.

ATmega328P, and will always read as zero.

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The external interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 12-2. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.

Table 12-2. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request.

0 1 Any logical change on INT0 generates an interrupt request.

1 0 The falling edge of INT0 generates an interrupt request.

1 1 The rising edge of INT0 generates an interrupt request.

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12.2.2 EIMSK – External Interrupt Mask Register

Bit 76543210

0x1D (0x3D) ––––––INT1INT0EIMSK

Read/Write R R RRRRR/WR/W

Initial Value00000000

• Bit 7..2 – Res: Reserved Bits

These bits are unused bits in the Atmel

ATmega328P, and will always read as zero.

• Bit 1 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the status register (SREG) is set (one), the external pin interrupt is enabled. The interrupt sense control1 bits 1/0 (ISC11 and ISC10) in the external interrupt control register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of external interrupt request 1 is executed from the INT1 interrupt vector.

• Bit 0 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the status register (SREG) is set (one), the external pin interrupt is enabled. The interrupt sense control0 bits 1/0 (ISC01 and ISC00) in the external interrupt control register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of external interrupt request 0 is executed from the INT0 interrupt vector.

12.2.3 EIFR – External Interrupt Flag Register

Bit 76543210

0x1C (0x3C) ––––––INTF1INTF0EIFR

Read/Write R R RRRRR/WR/W

Initial Value00000000

• Bit 7..2 – Res: Reserved Bits

These bits are unused bits in the Atmel ATmega328P, and will always read as zero.

• Bit 1 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt.

• Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt.

ATmega328P [DATASHEET]

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12.2.4 PCICR – Pin Change Interrupt Control Register

Bit 76543210

(0x68) – – – – – PCIE2 PCIE1 PCIE0 PCICR

Read/Write R R R R R R/W R/W R/W

Initial Value00000000

• Bit 7..3 - Res: Reserved Bits

These bits are unused bits in the Atmel

ATmega328P, and will always read as zero.

• Bit 2 - PCIE2: Pin Change Interrupt Enable 2

When the PCIE2 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an interrupt. The corresponding interrupt of pin change interrupt request is executed from the PCI2 interrupt vector. PCINT23..16 pins are enabled individually by the PCMSK2 register.

• Bit 1 - PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT14..8 pin will cause an interrupt. The corresponding interrupt of pin change interrupt request is executed from the PCI1 interrupt vector. PCINT14..8 pins are enabled individually by the PCMSK1 register.

• Bit 0 - PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of pin change interrupt request is executed from the PCI0 interrupt vector. PCINT7..0 pins are enabled individually by the PCMSK0 register.

12.2.5 PCIFR – Pin Change Interrupt Flag Register

Bit 76543210

0x1B (0x3B) –––––PCIF2PCIF1PCIF0PCIFR

Read/Write R R R R R R/W R/W R/W

Initial Value00000000

• Bit 7..3 - Res: Reserved Bits

These bits are unused bits in the Atmel ATmega328P, and will always read as zero.

• Bit 2 - PCIF2: Pin Change Interrupt Flag 2

When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bit 1 - PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bit 0 - PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

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12.2.6 PCMSK2 – Pin Change Mask Register 2

Bit 76543210

(0x6D) PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16

Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

12.2.7 PCMSK1 – Pin Change Mask Register 1

Bit 76543210

(0x6C) – PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – Res: Reserved Bit

This bit is an unused bit in the Atmel® ATmega328P, and will always read as zero.

• Bit 6..0 – PCINT14..8: Pin Change Enable Mask 14..8

Each PCINT14..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT14..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT14..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

12.2.8 PCMSK0 – Pin Change Mask Register 0

Bit 76543210

(0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0

Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

ATmega328P [DATASHEET]

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13. I/O-Ports

Pxn

Logic

See Figure

”General Digital I/O”

for Details

13.1 Overview

All AVR® ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both V

Figure 13-1. Refer to Section 28. “Electrical Characteristics” on page 258 for a complete list of parameters.

Figure 13-1. I/O Pin Equivalent Schematic

and Ground as indicated in

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in port B, here documented generally as PORTxn. The physical I/O registers and bit locations are listed in Section 13.4 “Register Description” on page 72.

Three I/O memory address locations are allocated for each port, one each for the data register – PORTx, data direction register – DDRx, and the port input pins – PINx. The port input pins I/O location is read only, while the data register and the data direction register are read/write. However, writing a logic one to a bit in the PINx register, will result in a toggle in the corresponding bit in the data register. In addition, the pull-up disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.

Using the I/O port as general digital I/O is described in Section 13.2 “Ports as General Digital I/O” on page 59. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Section 13.3 “Alternate Port Functions” on page 63. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.

ATmega328P [DATASHEET]

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13.2 Ports as General Digital I/O

WRx

RRx

WPx

Pxn

CLR

RESET

Synchronizer

DATA BUS

PORTxn

PINxn

RESET

RPx

WDx: WRITE DDRx

WRx:

WPx:

RPx:

RRx: READ PORTx REGISTER

READ PORTx PIN WRITE PINx REGISTER

RDx:

WRITE PORTx

READ DDRx

PUD: PULLUP DISABLE

CLK

I/O

SLEEP:

I/O CLOCK

SLEEP CONTROL

RDx

CLK

I/O

PUD

WDx

SLEEP

CLR

DDxn

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of one I/O-port pin, here generically called Pxn.

Figure 13-2. General Digital I/O

(1)

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

are common to all ports.

13.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in Section 13.4 “Register Description” on

page 72, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn

bits at the PINx I/O address.

The DDxn bit in the DDRx register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

, SLEEP, and PUD

I/O

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13.2.2 Toggling the Pin

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX XXX

0x00 0xFF

in r17, PINx

pd, max

pd, min

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

13.2.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedance environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 13-1 summarizes the control signals for the pin value.

Table 13-1. Port Pin Configurations

DDxn PORTxn PUD (in MCUCR) I/O Pull-up Comment

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes Pxn will source current if ext. pulled low.

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output low (sink)

1 1 X Output No Output high (source)

13.2.4 Reading the Pin Value

Independent of the setting of data direction bit DDxn, the port pin can be read through the PINxn register bit. As shown in

Figure 13-2, the PINxn register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if

the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 13-3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t

pd,max

and t

respectively.

pd,min

Figure 13-3. Synchronization when Reading an Externally Applied Pin Value

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 13-4 on page 61. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

ATmega328P [DATASHEET]

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Figure 13-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

r16

r17

out PORTx, r16 nop

0x00 0xFF

0xFF

in r17, PINx

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.

Assembly Code Example

(1)

...

; Define pull-ups and set outputs high ; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB,r16 out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB ...

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0); DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0); /* Insert nop for synchronization*/ __no_operation(); /* Read port pins */ i = PINB;

...

Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins

0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

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13.2.5 Digital Input Enable and Sleep Modes

As shown in Figure 13-2, the digital input signal can be clamped to ground at the input of the Schmitt trigger. The signal denoted SLEEP in the figure, is set by the MCU sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to V

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in Section 13.3

“Alternate Port Functions” on page 63.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “interrupt on rising edge, falling

edge, or any logic change on pin” while the external interrupt is not enabled, the corresponding external interrupt flag will be

set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change.

13.2.6 Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (reset, active mode and idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to V the pin is accidentally configured as an output.

/2.

or GND is not recommended, since this may cause excessive currents if

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13.3 Alternate Port Functions

WRx

RRx

WPx

PTOExn

Pxn

CLR

RESET

Synchronizer

DATA BUS

PORTxn

SET

CLR CLR

PINxn

RESET

RPx

Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE

PUD: PULL-UP DISABLEPUOExn:

Pxn PORT VALUE OVERRIDE VALUEPVOVxn:

Pxn PORT VALUE OVERRIDE ENABLEPVOExn:

Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE

DDOExn: DDOVxn:

SLEEP CONTROLSLEEP: Pxn, PORT TOGGLE OVERRIDE ENABLEPTOExn:

Pxn DIGITAL INPUT ENABLE OVERRIDE VALUEDIEOVxn:

Pxn DIGITAL INPUT ENABLE OVERRIDE ENABLEDIEOExn:

I/O CLOCK

RDx:

RPx:

WRITE PINx

WRx:

ANALOG INPUT/OUTPUT PIN n ON PORTx

DIGITAL INPUT PIN n ON PORTx

RRx: READ PORTx REGISTER

WPx:

WRITE PORTx

AIOxn:

DIxn:

READ PORTx PIN

WDx:

READ DDRx

WRITE DDRxPUOVxn:

RDx

CLK

I/O

DIxn AIOxn

CLK:

I/O

DIEOVxn

DIEOExn

PVOExn

DDOVxn

PVOVxn

PUOExn

PUOVxn

DDOExn

SLEEP

PUD

WDx

CLR

DDxn

Most port pins have alternate functions in addition to being general digital I/Os. Figure 13-5 shows how the port pin control signals from the simplified Figure 13-2 on page 59 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.

Figure 13-5. Alternate Port Functions

(1)

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

are common to all ports. All other signals are unique for each pin.

ATmega328P [DATASHEET]

, SLEEP, and PUD

I/O

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Table 13-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 13-5 on page 63 are not

shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.

Table 13-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

If this signal is set, the pull-up enable is controlled by the PUOV signal. If

PUOE Pull-up override enable

this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.

PUOV Pull-up override value

DDOE

DDOV

PVOE

Data direction override enable

Data direction override value

Port value override enable

PVOV Port value override value

PTOE

DIEOE

DIEOV

Port toggle override enable

Digital input enable override enable

Digital input enable override value

If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD register bits.

If this signal is set, the output driver enable is controlled by the DDOV signal. If this signal is cleared, the output driver is enabled by the DDxn register bit.

If DDOE is set, the output driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn register bit.

If this signal is set and the output driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the output driver is enabled, the port value is controlled by the PORTxn register bit.

If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn register bit.

If PTOE is set, the PORTxn register bit is inverted.

If this bit is set, the digital input enable is controlled by the DIEOV signal. If this signal is cleared, the digital input enable is determined by MCU state (normal mode, sleep mode).

If DIEOE is set, the digital input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (normal mode, sleep mode).

This is the digital input to alternate functions. In the figure, the signal is

DI Digital input

connected to the output of the schmitt trigger but before the synchronizer. Unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer.

AIO Analog input/output

This is the analog input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally.

The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.

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13.3.1 Alternate Functions of Port B

The port B pins with alternate functions are shown in Table 13-3.

Table 13-3. Port B Pins Alternate Functions

Port Pin Alternate Functions

XTAL2 (chip clock oscillator pin 2)

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

TOSC2 (timer oscillator pin 2) PCINT7 (pin change interrupt 7)

XTAL1 (chip clock oscillator pin 1 or external clock input) TOSC1 (timer oscillator pin 1) PCINT6 (pin change interrupt 6)

SCK (SPI bus master clock input) PCINT5 (pin change interrupt 5)

MISO (SPI bus master input/slave output) PCINT4 (pin change interrupt 4)

MOSI (SPI bus master output/slave input) OC2A (Timer/Counter2 output compare match A output) PCINT3 (pin change interrupt 3)

SS (SPI bus master slave select) OC1B (Timer/Counter1 output compare match B output) PCINT2 (pin change interrupt 2)

OC1A (Timer/Counter1 output compare match A output) PCINT1 (pin change interrupt 1)

ICP1 (Timer/Counter1 input capture input) CLKO (divided system clock output) PCINT0 (pin change interrupt 0)

The alternate pin configuration is as follows:

• XT A L2/TOSC2/PCINT7 – Port B, Bit 7

XTAL2: Chip clock oscillator pin 2. Used as clock pin for crystal oscillator or low-frequency crystal oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

TOSC2: Timer oscillator pin 2. Used only if internal calibrated RC oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the AS2 bit in ASSR is set (one) and the EXCLK bit is cleared (zero) to enable asynchronous clocking of Timer/Counter2 using the crystal oscillator, pin PB7 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin cannot be used as an I/O pin.

PCINT7: Pin change interrupt source 7. The PB7 pin can serve as an external interrupt source.

If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0.

• XT A L1/TOSC1/PCINT6 – Port B, Bit 6

XTAL1: Chip clock oscillator pin 1. Used for all chip clock sources except internal calibrated RC oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

TOSC1: Timer oscillator pin 1. Used only if internal calibrated RC oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PB6 is disconnected from the port, and becomes the input of the inverting oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin.

PCINT6: Pin change interrupt source 6. The PB6 pin can serve as an external interrupt source.

If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.

ATmega328P [DATASHEET]

7810D–AVR–01/15

• SCK/PCINT5 – Port B, Bit 5

SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit.

PCINT5: Pin change interrupt source 5. The PB5 pin can serve as an external interrupt source.

• MISO/PCINT4 – Port B, Bit 4

MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB4. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB4. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit.

PCINT4: Pin change interrupt source 4. The PB4 pin can serve as an external interrupt source.

• MOSI/OC2/PCINT3 – Port B, Bit 3

MOSI: SPI master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB3. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB3 bit.

OC2, output compare match output: The PB3 pin can serve as an external output for the Timer/Counter2 compare match. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer function.

PCINT3: Pin change interrupt source 3. The PB3 pin can serve as an external interrupt source.

•SS

/OC1B/PCINT2 – Port B, Bit 2

SS: Slave select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit.

OC1B, output compare match output: The PB2 pin can serve as an external output for the Timer/Counter1 compare match B. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

PCINT2: Pin change interrupt source 2. The PB2 pin can serve as an external interrupt source.

• OC1A/PCINT1 – Port B, Bit 1

OC1A, output compare match output: The PB1 pin can serve as an external output for the Timer/Counter1 compare match A. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

PCINT1: Pin change interrupt source 1. The PB1 pin can serve as an external interrupt source.

• ICP1/CLKO/PCINT0 – Port B, Bit 0

ICP1, input capture pin: The PB0 pin can act as an input capture pin for Timer/Counter1.

CLKO, divided system clock: The divided system clock can be output on the PB0 pin. The divided system clock will be output if the CKOUT fuse is programmed, regardless of the PORTB0 and DDB0 settings. It will also be output during reset.

PCINT0: Pin change interrupt source 0. The PB0 pin can serve as an external interrupt source.

Table 13-4 on page 67 and Table 13-5 on page 67 relate the alternate functions of Port B to the overriding signals shown in Figure 13-5 on page 63. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into

SPI MSTR OUTPUT and SPI SLAVE INPUT.

ATmega328P [DATASHEET]

7810D–AVR–01/15

Table 13-4. Overriding Signals for Alternate Functions in PB7..PB4

Signal Name

PB7/XTAL2/ TOSC2/PCINT7

(1)

PB6/XTAL1/ TOSC1/PCINT6

(1)

PB5/SCK/ PCINT5

PB4/MISO/ PCINT4

PUOE INTRC  EXTCK + AS2 INTRC + AS2 SPE  MSTR SPE  MSTR PUOV 0 0 PORTB5  PUD PORTB4  PUD DDOE INTRC  EXTCK + AS2 INTRC + AS2 SPE  MSTR SPE  MSTR

DDOV 0 0 0 0 PVOE 0 0 SPE  MSTR SPE  MSTR

PVOV 0 0 SCK OUTPUT SPI SLAVE OUTPUT

DIEOE

INTRC  EXTCK + AS2 + PCINT7  PCIE0

INTRC + AS2 + PCINT6  PCIE0

PCINT5  PCIE0 PCINT4  PCIE0

DIEOV (INTRC + EXTCK)  AS2 INTRC  AS2 1 1

DI PCINT7 INPUT PCINT6 INPUT

PCINT5 INPUT SCK INPUT

PCINT4 INPUT SPI MSTR INPUT

AIO Oscillator output Oscillator/clock input – – Note: 1. INTRC means that one of the internal RC oscillators are selected (by the CKSEL fuses), EXTCK means that

external clock is selected (by the CKSEL fuses)

Table 13-5. Overriding Signals for Alternate Functions in PB3..PB0

Signal Name

PB3/MOSI/ OC2/PCINT3

PB2/SS/ OC1B/PCINT2

PB1/OC1A/ PCINT1

PB0/ICP1/ PCINT0

PUOE SPE  MSTR SPE  MSTR 0 0 PUOV PORTB3  PUD PORTB2  PUD 0 0 DDOE SPE  MSTR SPE  MSTR 0 0

DDOV 0 0 0 0

PVOE

PVOV

SPE  MSTR + OC2A ENABLE

SPI MSTR OUTPUT + OC2A

OC1B ENABLE OC1A ENABLE 0

OC1B OC1A 0

DIEOE PCINT3  PCIE0 PCINT2  PCIE0 PCINT1  PCIE0 PCINT0  PCIE0

DIEOV 1 1 1 1

PCINT3 INPUT SPI SLAVE INPUT

PCINT2 INPUT SPI SS PCINT1 INPUT

PCINT0 INPUT ICP1 INPUT

AIO – – – –

ATmega328P [DATASHEET]

7810D–AVR–01/15

13.3.2 Alternate Functions of Port C

The port C pins with alternate functions are shown in Table 13-6.

Table 13-6. Port C Pins Alternate Functions

Port Pin Alternate Function

PC6

PC5

PC4

PC3

PC2

PC1

PC0

The alternate pin configuration is as follows:

RESET (reset pin) PCINT14 (pin change interrupt 14)

ADC5 (ADC input channel 5) SCL (2-wire serial bus clock line) PCINT13 (pin change interrupt 13)

ADC4 (ADC input channel 4) SDA (2-wire serial bus data input/output line) PCINT12 (pin change interrupt 12)

ADC3 (ADC input channel 3) PCINT11 (pin change interrupt 11)

ADC2 (ADC input channel 2) PCINT10 (pin change interrupt 10)

ADC1 (ADC input channel 1) PCINT9 (pin change interrupt 9)

ADC0 (ADC input channel 0) PCINT8 (pin change interrupt 8)

• RESET

RESET on power-on reset and brown-out reset as its reset sources. When the RSTDISBL fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an input pin.

If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0.

PCINT14: Pin change interrupt source 14. The PC6 pin can serve as an external interrupt source.

• SCL/ADC5/PCINT13 – Port C, Bit 5

SCL, 2-wire serial interface clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire serial interface, pin PC5 is disconnected from the port and becomes the serial clock I/O pin for the 2-wire serial interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation.

PC5 can also be used as ADC input channel 5. Note that ADC input channel 5 uses digital power.

PCINT13: Pin change interrupt source 13. The PC5 pin can serve as an external interrupt source.

• SDA/ADC4/PCINT12 – Port C, Bit 4

SDA, 2-wire serial interface data: When the TWEN bit in TWCR is set (one) to enable the 2-wire serial interface, pin PC4 is disconnected from the port and becomes the serial data I/O pin for the 2-wire serial interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation.

PC4 can also be used as ADC input Channel 4. Note that ADC input channel 4 uses digital power.

PCINT12: Pin change interrupt source 12. The PC4 pin can serve as an external interrupt source.

• ADC3/PCINT11 – Port C, Bit 3

PC3 can also be used as ADC input Channel 3. Note that ADC input channel 3 uses analog power.

PCINT11: Pin change interrupt source 11. The PC3 pin can serve as an external interrupt source.

/PCINT14 – Port C, Bit 6

, Reset pin: When the RSTDISBL fuse is programmed, this pin functions as an input pin, and the part will have to rely

ATmega328P [DATASHEET]

7810D–AVR–01/15

• ADC2/PCINT10 – Port C, Bit 2

PC2 can also be used as ADC input channel 2. Note that ADC input channel 2 uses analog power.

PCINT10: Pin change interrupt source 10. The PC2 pin can serve as an external interrupt source.

• ADC1/PCINT9 – Port C, Bit 1

PC1 can also be used as ADC input channel 1. Note that ADC input channel 1 uses analog power.

PCINT9: Pin change interrupt source 9. The PC1 pin can serve as an external interrupt source.

• ADC0/PCINT8 – Port C, Bit 0

PC0 can also be used as ADC input channel 0. Note that ADC input channel 0 uses analog power.

PCINT8: Pin change interrupt source 8. The PC0 pin can serve as an external interrupt source.

Table 13-7 and Table 13-8 relate the alternate functions of port C to the overriding signals shown in Figure 13-5 on page 63.

Table 13-7. Overriding Signals for Alternate Functions in PC6..PC4

(1)

Signal Name PC6/RESET/PCINT14 PC5/SCL/ADC5/PCINT13 PC4/SDA/ADC4/PCINT12

PUOE RSTDISBL TWEN TWEN PUOV 1 PORTC5  PUD PORTC4  PUD

DDOE RSTDISBL TWEN TWEN

DDOV 0 SCL_OUT SDA_OUT

PVOE 0 TWEN TWEN

PVOV 0 0 0 DIEOE RSTDISBL + PCINT14  PCIE1 PCINT13  PCIE1 + ADC5D PCINT12  PCIE1 + ADC4D DIEOV RSTDISBL PCINT13  PCIE1 PCINT12  PCIE1

DI PCINT14 INPUT PCINT13 INPUT PCINT12 INPUT

AIO RESET INPUT ADC5 INPUT / SCL INPUT ADC4 INPUT / SDA INPUT Note: 1. When enabled, the 2-wire serial interface enables slew-rate controls on the output pins PC4 and PC5. This is

not shown in the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module.

Table 13-8. Overriding Signals for Alternate Functions in PC3..PC0

Signal Name

PC3/ADC3/ PCINT11

PC2/ADC2/ PCINT10

PC1/ADC1/ PCINT9

PC0/ADC0/ PCINT8

PUOE 0 0 0 0

PUOV 0 0 0 0

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE 0 0 0 0

PVOV 0 0 0 0

DIEOE

PCINT11  PCIE1 + ADC3D

PCINT10  PCIE1 + ADC2D

PCINT9  PCIE1 + ADC1D

PCINT8  PCIE1 + ADC0D

DIEOV PCINT11  PCIE1 PCINT10  PCIE1 PCINT9  PCIE1 PCINT8  PCIE1

DI PCINT11 INPUT PCINT10 INPUT PCINT9 INPUT PCINT8 INPUT

AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT

ATmega328P [DATASHEET]

7810D–AVR–01/15

13.3.3 Alternate Functions of Port D

The port D pins with alternate functions are shown in Table 13-9.

Table 13-9. Port D Pins Alternate Functions

Port Pin Alternate Function

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

AIN1 (analog comparator negative input) PCINT23 (Pin Change Interrupt 23)

AIN0 (analog comparator positive input) OC0A (Timer/Counter0 output compare match A output) PCINT22 (pin change interrupt 22)

T1 (Timer/Counter 1 external counter input) OC0B (Timer/Counter0 output compare match B output) PCINT21 (pin change interrupt 21)

XCK (USART external clock input/output) T0 (Timer/Counter 0 external counter input) PCINT20 (pin change interrupt 20)

INT1 (external interrupt 1 input) OC2B (Timer/Counter2 output compare match B output) PCINT19 (pin change interrupt 19)

INT0 (external interrupt 0 input) PCINT18 (pin change interrupt 18)

TXD (USART output pin) PCINT17 (pin change interrupt 17)

RXD (USART input pin) PCINT16 (pin change interrupt 16)

The alternate pin configuration is as follows:

• AIN1/OC2B/PCINT23 – Port D, Bit 7

AIN1, analog comparator negative input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.

PCINT23: Pin change interrupt source 23. The PD7 pin can serve as an external interrupt source.

• AIN0/OC0A/PCINT22 – Port D, Bit 6

AIN0, analog comparator positive input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.

OC0A, output compare match output: The PD6 pin can serve as an external output for the Timer/Counter0 compare match A. The PD6 pin has to be configured as an output (DDD6 set (one)) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.

PCINT22: Pin change interrupt source 22. The PD6 pin can serve as an external interrupt source.

• T1/OC0B/PCINT21 – Port D, Bit 5

T1, Timer/Counter1 counter source.

OC0B, output compare match output: The PD5 pin can serve as an external output for the Timer/Counter0 compare match B. The PD5 pin has to be configured as an output (DDD5 set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function.

PCINT21: Pin change interrupt source 21. The PD5 pin can serve as an external interrupt source.

• XCK/T0/PCINT20 – Port D, Bit 4

XCK, USART external clock.

T0, Timer/Counter0 counter source.

PCINT20: Pin change interrupt source 20. The PD4 pin can serve as an external interrupt source.

ATmega328P [DATASHEET]

7810D–AVR–01/15

• INT1/OC2B/PCINT19 – Port D, Bit 3

INT1, external interrupt source 1: The PD3 pin can serve as an external interrupt source.

OC2B, output compare match output: The PD3 pin can serve as an external output for the Timer/Counter0 compare match B. The PD3 pin has to be configured as an output (DDD3 set (one)) to serve this function. The OC2B pin is also the output pin for the PWM mode timer function.

PCINT19: Pin change interrupt source 19. The PD3 pin can serve as an external interrupt source.

• INT0/PCINT18 – Port D, Bit 2

INT0, external interrupt source 0: The PD2 pin can serve as an external interrupt source.

PCINT18: Pin change interrupt source 18. The PD2 pin can serve as an external interrupt source.

• TXD/PCINT17 – Port D, Bit 1

TXD, transmit Data (data output pin for the USART). When the USART transmitter is enabled, this pin is configured as an output regardless of the value of DDD1.

PCINT17: Pin change interrupt source 17. The PD1 pin can serve as an external interrupt source.

• RXD/PCINT16 – Port D, Bit 0

RXD, Receive Data (data input pin for the USART). When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0 bit.

PCINT16: Pin change interrupt source 16. The PD0 pin can serve as an external interrupt source.

Table 13-10 and Table 13-11 on page 72 relate the alternate functions of port D to the overriding signals shown in Figure 13-5 on page 63.

Table 13-10. Overriding Signals for Alternate Functions PD7..PD4

Signal Name PD7/AIN1/PCINT23 PD6/AIN0/OC0A/PCINT22 PD5/T1/OC0B/PCINT21 PD4/XCK/T0/PCINT20

PUOE 0 0 0 0

PUO 0 0 0 0

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE 0 OC0A ENABLE OC0B ENABLE UMSEL

PVOV 0 OC0A OC0B XCK OUTPUT DIEOE PCINT23  PCIE2 PCINT22  PCIE2 PCINT21  PCIE2 PCINT20  PCIE2

DIEOV 1 1 1 1

DI PCINT23 INPUT PCINT22 INPUT

PCINT21 INPUT T1 INPUT

PCINT20 INPUT XCK INPUT T0 INPUT

AIO AIN1 INPUT AIN0 INPUT – –

ATmega328P [DATASHEET]

7810D–AVR–01/15

Table 13-11. Overriding Signals for Alternate Functions in PD3..PD0

Signal Name

PD3/OC2B/INT1/ PCINT19

PUOE 0 0 TXEN RXEN PUO 0 0 0 PORTD0  PUD

DDOE 0 0 TXEN RXEN

DDOV 0 0 1 0

PVOE OC2B ENABLE 0 TXEN 0

PVOV OC2B 0 TXD 0

DIEOE

INT1 ENABLE + PCINT19  PCIE2

DIEOV 1 1 1 1

PCINT19 INPUT INT1 INPUT

AIO – – – –

13.4 Register Description

13.4.1 MCUCR – MCU Control Register

Bit 7 6 5 4 3 2 1 0

0x35 (0x55)

Read/Write R R R R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

– BODS BODSE PUD – – IVSEL IVCE MCUCR

PD2/INT0/ PCINT18

INT0 ENABLE + PCINT18  PCIE1

PCINT18 INPUT INT0 INPUT

PD1/TXD/ PCINT17

PD0/RXD/ PCINT16

PCINT17  PCIE2 PCINT16  PCIE2

PCINT17 INPUT

PCINT16 INPUT RXD

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See Section 13.2.1 “Configuring the Pin” on page 59 for more details about this feature.

13.4.2 PORTB – The Port B Data Register

Bit 76543210

0x05 (0x25) PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

13.4.3 DDRB – The Port B Data Direction Register

Bit 76543210

0x04 (0x24) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

13.4.4 PINB – The Port B Input Pins Address

Bit 76543210

0x03 (0x23) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

Read/Write R R R R R R R R

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

ATmega328P [DATASHEET]

7810D–AVR–01/15

13.4.5 PORTC – The Port C Data Register

Bit 76543210

0x08 (0x28) – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

13.4.6 DDRC – The Port C Data Direction Register

Bit 76543210

0x07 (0x27) – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

13.4.7 PINC – The Port C Input Pins Address

Bit 76543210

0x06 (0x26) – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC

Read/Write R R R R R R R R

Initial Value 0 N/A N/A N/A N/A N/A N/A N/A

13.4.8 PORTD – The Port D Data Register

Bit 76543210

0x0B (0x2B) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

13.4.9 DDRD – The Port D Data Direction Register

Bit 76543210

0x0A (0x2A) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

13.4.10 PIND – The Port D Input Pins Address

Bit 76543210

0x09 (0x29) PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND

Read/Write R R R R R R R R

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

ATmega328P [DATASHEET]

7810D–AVR–01/15

14. 8-bit Timer/Counter0 with PWM

14.1 Features

● Two independent output compare units

● Double buffered output compare registers

● Clear timer on compare match (auto reload)

● Glitch free, phase correct pulse width modulator (PWM)

● Variable PWM period

● Frequency generator

● Three independent interrupt sources (TOV0, OCF0A, and OCF0B)

14.2 Overview

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent output compare units, and with PWM support. It allows accurate program execution timing (event management) and wave generation.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual placement of I/O pins, refer to

Section 1-1 “Pinout” on page 3. CPU accessible I/O registers, including I/O bits and I/O pins, are shown in bold.

The device-specific I/O register and bit locations are listed in the Section 14.9 “Register Description” on page 84.

The PRTIM0 bit in Section 9.10 “Minimizing Power Consumption” on page 36 must be written to zero to enable Timer/Counter0 module.

Figure 14-1. 8-bit Timer/Counter Block Diagram

Direction

Count

Clear

Control Logic

clk

TOVn (Int. Req.)

Clock Select

Edge

Detector

DATA BUS

TOP BOTTOM

Timer/Counter

TCNTn

= = 0

OCRnA

OCRnB

TCCRnA TCCRnB

Fixed

TOP

Val ue

(from Prescaler)

OCnA (Int. Req.)

Waveform

Generation

OCnB (Int. Req.)

Waveform

Generation

OCnA

OCnB

ATmega328P [DATASHEET]

7810D–AVR–01/15

14.2.1 Definitions

Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the output compare unit, in this case compare unit A or compare unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.

The definitions in Table 14-1 are also used extensively throughout the document.

Table 14-1. Definitions

Parameter Definition

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

14.2.2 Registers

The Timer/Counter (TCNT0) and output compare registers (OCR0A and OCR0B) are 8-bit registers. interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the timer interrupt flag register (TIFR0). All interrupts are individually masked with the timer interrupt mask register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The clock select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk

The double buffered output compare registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the output compare pins (OC0A and OC0B). See Section 15.7.3 “Using the Output Compare Unit” on page 99 for details. The compare match event will also set the compare flag (OCF0A or OCF0B) which can be used to generate an output compare interrupt request.

The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A register. The assignment is dependent on the mode of operation.

14.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter control register (TCCR0B). For details on clock sources and prescaler, see Section 16. “Timer/Counter0 and Timer/Counter1 Prescalers” on page 114.

14.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 14-2 shows a block diagram of the counter and its surroundings.

Figure 14-2. Counter Unit Block Diagram

DATA BUS

TCNTn

count

clear

direction

Control Logic

TOVn (Int. Req.)

topbottom

clk

Clock Select

Edge

Detector

(from Prescaler)

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Signal description (internal signals):

OCFnx (Int. Req.)

(8-bit Comparator)

OCRnx

Waveform Generator

TCNTn

OCnx

top

bottom

FOCn

WGMn1:0 COMnx1:0

DATA BUS

count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clk

Timer/Counter clock, referred to as clkT0 in the following.

top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk clk

can be generated from an external or internal clock source, selected by the clock select bits (CS02:0). When no clock

source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk

is present or not. A CPU write overrides (has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter control register (TCCR0A) and the WGM02 bit located in the Timer/Counter control register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OC0A and OC0B. For more details about advanced counting sequences and waveform generation, see Section 14.7

“Modes of Operation” on page 78.

The Timer/Counter overflow flag (TOV0) is set according to the mode of operation selected by the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.

14.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the output compare registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the output compare flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. The output compare flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM02:0 bits and compare output mode (COM0x1:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (Section 14.7 “Modes of Operation” on page 78).

Figure 14-3 shows a block diagram of the output compare unit.

Figure 14-3. Output Compare Unit, Block Diagram

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The OCR0x registers are double buffered when using any of the pulse width modulation (PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x compare registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0x register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x buffer register, and if double buffering is disabled the CPU will access the OCR0x directly.

14.5.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (FOC0x) bit. Forcing compare match will not set the OCF0x flag or reload/clear the timer, but the OC0x pin will be updated as if a real compare match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled).

14.5.2 Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled.

14.5.3 Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the output compare unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down counting.

The setup of the OC0x should be performed before setting the data direction register for the port pin to output. The easiest way of setting the OC0x value is to use the force output compare (FOC0x) strobe bits in normal mode. The OC0x registers keep their values even when changing between waveform generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately.

14.6 Compare Match Output Unit

The compare output mode (COM0x1:0) bits have two functions. The waveform generator uses the COM0x1:0 bits for defining the output compare (OC0x) state at the next compare match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 14-4 on page 78 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x register, not the OC0x pin. If a system reset occur, the OC0x register is reset to “0”.

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Figure 14-4. Compare Match Output Unit, Schematic

DATA BUS

COMnx1

COMnx0

FOCnx

OCnx

Waveform Generator

PORT

DDR

OCnx

clk

I/O

The general I/O port function is overridden by the output compare (OC0x) from the waveform generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the data direction register (DDR) for the port pin. The data direction register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independent of the waveform generation mode.

The design of the output compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See Section 14.9 “Register Description” on page

14.6.1 Compare Output Mode and Waveform Generation

The waveform generator uses the COM0x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the waveform generator that no action on the OC0x register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 14-2 on page 84. For fast PWM mode, refer to

Table 14-3 on page 84, and for phase correct PWM refer to Table 14-4 on page 84.

A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.

14.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the waveform generation mode (WGM02:0) and compare output mode (COM0x1:0) bits. The compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. The COM0x1:0 bits control whether the

PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (see Section 14.6 “Compare Match Output

Unit” on page 77).

For detailed timing information refer to Section 14.8 “Timer/Counter Timing Diagrams” on page 82.

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14.7.1 Normal Mode

OCnx

clk_I/O

2N 1 OCRnx+

--------------------------------------------------- -

The simplest mode of operation is the normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter overflow flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new counter value can be written anytime.

The output compare unit can be used to generate interrupts at some given time. Using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the CPU time.

14.7.2 Clear Timer on Compare Match (CTC) Mode

In clear timer on compare or CTC mode (WGM02:0 = 2), the OCR0A register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 14-5. The counter value (TCNT0) increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.

Figure 14-5. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCn

(Toggle)

Period

(COMnA1:0 = 1)

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of f

OC0

= f

/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation:

clk_I/O

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00.

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14.7.3 Fast PWM Mode

1234567

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

Period

OCRnx Update and

TOVn Interrupt Flag Set

OCRnx Interrupt

Flag Set

OCnxPWM

clk_I/O

N 256

-------------------

The fast pulse width modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-inverting compare output mode, the output compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x, and set at BOTTOM. In inverting compare output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0.

Figure 14-6. Fast PWM Mode, Timing Diagram

The Timer/Counter overflow flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the OC0A pin to toggle on compare matches if the WGM02 bit is set. This option is not available for the OC0B pin (see Table 14-6 on page 85). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0x register at the compare match between OCR0x and TCNT0, and clearing (or setting) the OC0x register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

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The extreme values for the OCR0A register represents special cases when generating a PWM waveform output in the fast

123

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

Period

TOVn Interrupt

Flag Set

OCRnx Update

OCnx Interrupt

Flag Set

PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of f when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode.

14.7.4 Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-inverting compare output mode, the output compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x while upcounting, and set on the compare match while downcounting. In inverting output compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 14-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0.

Figure 14-7. Phase Correct PWM Mode, Timing Diagram

OC0

= f

clk_I/O

The Timer/Counter overflow flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.

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In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the

OCnxPCPWM

clk_I/O

N510

-------------------

MAX - 1

clk

I/O

(clk

I/O

/1)

TCNTn

TOVn

clk

MAX BOTTOM BOTTOM + 1

COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on compare matches if the WGM02 bit is set. This option is not available for the OC0B pin (see Table 14-7 on page 85). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0x register at the compare match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x register at compare match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 14-7 on page 81 OCnx has a transition from high to low even though there is no compare match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without compare match.

● OCRnx changes its value from MAX, like in Figure 14-7 on page 81. When the OCR0A value is MAX the OCn pin

value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an up-counting compare match.

● The timer starts counting from a value higher than the one in OCRnx, and for that reason misses the compare match

and hence the OCnx change that would have happened on the way up.

14.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set. Figure 14-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 14-8. Timer/Counter Timing Diagram, no Prescaling

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Figure 14-9 shows the same timing data, but with the prescaler enabled.

MAX - 1

clk

I/O

(clk

I/O

/8)

TCNTn

TOVn

clk

MAX BOTTOM BOTTOM + 1

OCRnx - 1

clk

I/O

(clk

I/O

/8)

TCNTn

OCRnx

OCFnx

clk

OCRnx OCRnx + 1

OCRnx Value

OCRnx + 2

TOP - 1

clk

I/O

(clk

I/O

/8)

TCNTn

(CTC)

OCRnx

OCFnx

clk

TOP BOTTOM

TOP

BOTTOM + 1

Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O

/8)

Figure 14-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where

OCR0A is TOP.

Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0 x, with Prescaler (f

clk_I/O

/8)

Figure 14-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is

TOP.

Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f

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clk_I/O

/8)

14.9 Register Description

14.9.1 TCCR0A – Timer/Counter Control Register A

Bit 7 6 5 4 3 210

0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 ––WGM01 WGM00 TCCR0A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 7:6 – COM0A1:0: Compare Match Output A Mode

These bits control the output compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. Table 14-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM).

Table 14-2. Compare Output Mode, non-PWM Mode

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

0 1 Toggle OC0A on compare match

1 0 Clear OC0A on compare match

1 1 Set OC0A on compare match

Table 14-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.

Table 14-3. Compare Output Mode, Fast PWM Mode

(1)

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

0 1

1 0

1 1

WGM02 = 0: Normal port operation, OC0A disconnected. WGM02 = 1: Toggle OC0A on compare match.

Clear OC0A on compare match, set OC0A at BOTTOM, (non-inverting mode).

Set OC0A on compare match, clear OC0A at BOTTOM, (inverting mode).

Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is

ignored, but the set or clear is done at BOTTOM. See Section 14.7.3 “Fast PWM Mode” on page 80 for more details.

Table 14-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode.

Table 14-4. Compare Output Mode, Phase Correct PWM Mode

(1)

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

0 1

1 0

1 1

WGM02 = 0: Normal port operation, OC0A disconnected. WGM02 = 1: Toggle OC0A on compare match.

Clear OC0A on compare match when up-counting. Set OC0A on compare match when down-counting.

Set OC0A on compare match when up-counting. Clear OC0A on compare match when down-counting.

Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is

ignored, but the set or clear is done at TOP. See Section 15.9.4 “Phase Correct PWM Mode” on page 103 for more details.

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• Bits 5:4 – COM0B1:0: Compare Match Output B Mode

These bits control the output compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver.

When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting. Table 14-5 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM).

Table 14-5. Compare Output Mode, non-PWM Mode

COM0B1 COM0B0 Description

0 0 Normal port operation, OC0B disconnected.

0 1 Toggle OC0B on compare match

1 0 Clear OC0B on compare match

1 1 Set OC0B on compare match

Table 14-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode.

Table 14-6. Compare Output Mode, Fast PWM Mode

(1)

COM0B1 COM0B0 Description

0 0 Normal port operation, OC0B disconnected.

0 1 Reserved

1 0

1 1

Clear OC0B on compare match, set OC0B at BOTTOM, (non-inverting mode)

Set OC0B on compare match, clear OC0B at BOTTOM, (inverting mode).

Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the compare match is

ignored, but the set or clear is done at TOP. See Section 14.7.3 “Fast PWM Mode” on page 80 for more details.

Table 14-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode.

Table 14-7. Compare Output Mode, Phase Correct PWM Mode

(1)

COM0B1 COM0B0 Description

0 0 Normal port operation, OC0B disconnected.

0 1 Reserved

1 0

1 1

Clear OC0B on compare match when up-counting. Set OC0B on compare match when down-counting.

Set OC0B on compare match when up-counting. Clear OC0B on compare match when down-counting.

Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the compare match is

ignored, but the set or clear is done at TOP. See Section 14.7.4 “Phase Correct PWM Mode” on page 81 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the Atmel

ATmega328P and will always read as zero.

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• Bits 1:0 – WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 14-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), clear timer on compare match (CTC) mode, and two types of pulse width modulation (PWM) modes (see Section 14.7 “Modes of Operation” on page 78).

Table 14-8. Waveform Generation Mode Bit Description

Mode WGM02 WGM01 WGM00

0 0 0 0 Normal 0xFF Immediate MAX

1 0 0 1 PWM, phase correct 0xFF TOP BOTTOM

2 0 1 0 CTC OCRA Immediate MAX

3 0 1 1 Fast PWM 0xFF BOTTOM MAX

4 1 0 0 Reserved – – –

5 1 0 1 PWM, phase correct OCRA TOP BOTTOM

6 1 1 0 Reserved – – –

7 1 1 1 Fast PWM OCRA BOTTOM TOP

Notes: 1. MAX = 0xFF

2. BOTTOM = 0x00

14.9.2 TCCR0B – Timer/Counter Control Register B

Bit 7 6 5 4 3 210

0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B

Read/Write W W R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate compare match is forced on the waveform generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.

The FOC0A bit is always read as zero.

Timer/Counter Mode of Operation

TOP

Update of

OCRx at

TOV Flag

(1)(2)

Set on

• Bit 6 – FOC0B: Force Output Compare B

The FOC0B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate compare match is forced on the waveform generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced compare.

A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP.

The FOC0B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits in the ATmega328P and will always read as zero.

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• Bit 3 – WGM02: Waveform Generation Mode

See the description in the Section 14.9.1 “TCCR0A – Timer/Counter Control Register A” on page 84.

• Bits 2:0 – CS02:0: Clock Select

The three clock select bits select the clock source to be used by the Timer/Counter.

Table 14-9. Clock Select Bit Description

CS02 CS01 CS00 Description

0 0 0 No clock source (Timer/Counter stopped)

0 0 1 clk

0 1 0 clk

0 1 1 clk

1 0 0 clk

1 0 1 clk

1 1 0 External clock source on T0 pin. Clock on falling edge.

1 1 1 External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.

14.9.3 TCNT0 – Timer/Counter Register

Bit 76543210

0x26 (0x46) TCNT0[7:0] TCNT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

/(no prescaling)

I/O

/8 (from prescaler)

I/O

/64 (from prescaler)

I/O

/256 (from prescaler)

I/O

/1024 (from prescaler)

I/O

The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0x registers.

14.9.4 OCR0A – Output Compare Register A

Bit 76543210

0x27 (0x47) OCR0A[7:0] OCR0A

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

The output compare register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0A pin.

14.9.5 OCR0B – Output Compare Register B

Bit 76543210

0x28 (0x48) OCR0B[7:0] OCR0B

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

The output compare register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0B pin.

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14.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register

Bit 76543 210

(0x6E) –––––OCIE0BOCIE0ATOIE0TIMSK0

Read/Write RRRR RR/WR/WR/W

Initial Value00000 0 00

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the Atmel

ATmega328P and will always read as zero.

• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the status register is set, the Timer/Counter compare match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter interrupt flag register – TIFR0.

• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the status register is set, the Timer/Counter0 compare match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 interrupt flag register – TIFR0.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the status register is set, the Timer/Counter0 overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 interrupt flag register – TIFR0.

14.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register

Bit 76543210

0x15 (0x35) –––––OCF0BOCF0ATOV0TIFR0

Read/Write R R R R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the Atmel ATmega328P and will always read as zero.

• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag

The OCF0B bit is set when a compare match occurs between the Timer/Counter and the data in OCR0B – output compare register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter compare B match interrupt enable), and OCF0B are set, the Timer/Counter compare match interrupt is executed.

• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag

The OCF0A bit is set when a compare match occurs between the Timer/Counter0 and the data in OCR0A – output compare register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 compare match interrupt enable), and OCF0A are set, the Timer/Counter0 compare match interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 overflow interrupt enable), and TOV0 are set, the Timer/Counter0 overflow interrupt is executed.

The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 14-8 on page 86, Section 14-8 “Waveform

Generation Mode Bit Description” on page 86.

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15. 16-bit Timer/Counter1 with PWM

15.1 Features

● True 16-bit design (i.e., allows 16-bit PWM)

● Two independent output compare units

● Double buffered output compare registers

● One input capture unit

● Input capture noise canceler

● Clear timer on compare match (auto reload)

● Glitch-free, phase correct pulse width modulator (PWM)

● Variable PWM period

● Frequency generator

● External event counter

● Four independent interrupt sources (TOV1, OCF1A, OCF1B, and ICF1)

15.2 Overview

The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement.

Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the output compare unit channel. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 15-1 on page 90. For the actual placement of I/O pins, refer to Section 1-1 “Pinout” on page 3. CPU accessible I/O registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O register and bit locations are listed in the Section 15.11 “Register Description” on page 108.

The PRTIM1 bit in Section 9.11.3 “PRR – Power Reduction Register” on page 38 must be written to zero to enable Timer/Counter1 module.

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Figure 15-1. 16-bit Timer/Counter Block Diagram

Control Logic

TCNTn

Timer/Counter

Count

Clear

Direction

clk

OCRnA

OCRnB

ICRn

TCCRnA TCCRnB

Edge

Detector

(from Prescaler)

Clock Select

TOP BOTTOM

TOVn (Int. Req.)

OCnA (Int. Req.)

Waveform

Generation

Fixed

TOP

Values

DATA BUS

= = 0

OCnA

OCnB (Int. Req.)

Waveform

Generation

Noise

Canceler

OCnB

(From Analog

Comparator Output)

ICFn (Int. Req.)

Edge

Detector

ICPn

(1)

15.2.1 Registers

Note: 1. Refer to Figure 1-1 on page 3,

placement and description.

Table 13-3 on page 65 and Table 13-9 on page 70 for Timer/Counter1 pin

The Timer/Counter (TCNT1), output compare registers (OCR1A/B), and input capture register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the Section

15.3 “Accessing 16-bit Registers” on page 91. The Timer/Counter control registers (TCCR1A/B) are 8-bit registers and have

no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the timer interrupt flag register (TIFR1). All interrupts are individually masked with the timer interrupt mask register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The clock select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT1).

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The double buffered output compare registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the output compare pin (OC1A/B). See Section 15.7 “Output Compare Units” on page 97. The compare match event will also set the compare match flag (OCF1A/B) which can be used to generate an output compare interrupt request.

The input capture register can capture the Timer/Counter value at a given external (edge triggered) event on either the input capture pin (ICP1) or on the analog comparator pins (see Section 22. “Analog Comparator” on page 202). The input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A register, the ICR1 register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 register can be used as an alternative, freeing the OCR1A to be used as PWM output.

15.2.2 Definitions

The following definitions are used extensively throughout the section:

Table 15-1. Definitions

Parameter Definition

BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.

MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 register. The assignment is dependent of the mode of operation.

15.3 Accessing 16-bit Registers

The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR® CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read.

Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does not involve using the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte.

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The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 registers. Note that when using “C”, the compiler handles the 16-bit access.

Assembly Code Examples

(1)

... ; Set TCNT1 to 0x01FF

ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16

; Read TCNT1 into r17:r16

in r16,TCNT1L in r17,TCNT1H

...

C Code Examples

(1)

unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ...

Note: 1. See Section 5. “About Code Examples” on page 8

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access.

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The following code examples show how to do an atomic read of the TCNT1 register contents. Reading any of the OCR1A/B or ICR1 registers can be done by using the same principle.

Assembly Code Example

(1)

TIM16_ReadTCNT1:

; Save global interrupt flag in r18,SREG ; Disable interrupts

cli

; Read TCNT1 into r17:r16

in r16,TCNT1L in r17,TCNT1H

; Restore global interrupt flag

out SREG,r18 ret

C Code Example

(1)

unsigned int TIM16_ReadTCNT1( void ) {

unsigned char sreg; unsigned int i;

/* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i;

}

Note: 1. See Section 5. “About Code Examples” on page 8.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

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The following code examples show how to do an atomic write of the TCNT1 register contents. Writing any of the OCR1A/B or ICR1 registers can be done by using the same principle.

Assembly Code Example

(1)

TIM16_WriteTCNT1:

; Save global interrupt flag in r18,SREG ; Disable interrupts

cli

; Set TCNT1 to r17:r16

out TCNT1H,r17 out TCNT1L,r16

; Restore global interrupt flag

out SREG,r18 ret

C Code Example

(1)

void TIM16_WriteTCNT1(unsigned int i) {

unsigned char sreg; unsigned int i;

/* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg;

}

Note: 1. See Section 5. “About Code Examples” on page 8.

The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1.

15.3.1 Reusing the Temporary High Byte Register

If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case.

15.4 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located in the Timer/Counter control register B (TCCR1B). For details on clock sources and prescaler, see Section 16. “Timer/Counter0 and Timer/Counter1 Prescalers” on page 114.

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15.5 Counter Unit

BOTTOMTOP

TOVn (Int. Req.)

DATA BUS (8-bit)

Control Logic

TCNTnH (8-bit)

TCNTnH (16-bit Counter)

TCNTnL (8-bit)

TEMP (8-bit)

clk

Clear

Count

Direction

Edge

Detector

(from Prescaler)

Clock Select

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 shows a block diagram of the counter and its surroundings.

Figure 15-2. Counter Unit Block Diagram

Signal description (internal signals):

Count Increment or decrement TCNT1 by 1. Direction Select between increment and decrement. Clear Clear TCNT1 (set all bits to zero). clk

TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter high (TCNT1H) containing the upper eight bits of the counter, and counter low (TCNT1L) containing the lower eight bits. The TCNT1H register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the clock select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the waveform generation mode bits (WGM13:0) located in the Timer/Counter control registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see Section 15.9 “Modes of Operation” on page 100.

The Timer/Counter overflow flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.

Timer/Counter clock.

15.6 Input Capture Unit

The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.

The input capture unit is illustrated by the block diagram shown in Figure 15-3 on page 96. The elements of the block diagram that are not directly a part of the input capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number.

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Figure 15-3. Input Capture Unit Block Diagram

TEMP (8-bit)

DATA BUS (8-bit)

ICPn

WRITE

ICRn (16-bit Register)

Analog

Comparator

ICRnL (8-bit)ICRnH (8-bit)

TCNTn (16-bit Counter)

ICNCACIC*ACO*

Noise

Canceler

ICES

Edge

Detector

TCNTnL (8-bit)TCNTnH (8-bit)

ICFn (Int. Req.)

When a change of the logic level (an event) occurs on the input capture pin (ICP1), alternatively on the analog comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the input capture register (ICR1). The input capture flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 register. If enabled (ICIE1 = 1), the input capture flag generates an input capture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 flag can be cleared by software by writing a logical one to its I/O bit location.

Reading the 16-bit value in the input capture register (ICR1) is done by first reading the low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP register.

The ICR1 register can only be written when using a waveform generation mode that utilizes the ICR1 register for defining the counter’s TOP value. In these cases the waveform generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 register. When writing the ICR1 register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L.

For more information on how to access the 16-bit registers refer to Section 15.3 “Accessing 16-bit Registers” on page 91.

15.6.1 Input Capture Trigger Source

The main trigger source for the input capture unit is the input capture pin (ICP1). Timer/Counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. The analog comparator is selected as trigger source by setting the analog comparator input capture (ACIC) bit in the analog comparator control and status register (ACSR). Be aware that changing trigger source can trigger a capture. The input capture flag must therefore be cleared after the change.

Both the input capture pin (ICP1) and the analog comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 16-1 on page 114). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a waveform generation mode that uses ICR1 to define TOP.

An input capture can be triggered by software by controlling the port of the ICP1 pin.

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15.6.2 Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector.

The noise canceler is enabled by setting the input capture noise canceler (ICNC1) bit in Timer/Counter control register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR1 register. The noise canceler uses the system clock and is therefore not affected by the prescaler.

15.6.3 Using the Input Capture Unit

The main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect.

When using the input capture interrupt, the ICR1 register should be read as early in the interrupt handler routine as possible. Even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.

Using the input capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 register has been read. After a change of the edge, the input capture flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt handler is used).

15.7 Output Compare Units

The 16-bit comparator continuously compares TCNT1 with the output compare register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the output compare flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the output compare flag generates an output compare interrupt. The OCF1x flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (WGM13:0) bits and compare output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see

Section 15.9 “Modes of Operation” on page 100).

A special feature of output compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform generator.

Figure 15-4 on page 98 shows a block diagram of the output compare unit. The small “n” in the register and bit names

indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates output compare unit (A/B). The elements of the block diagram that are not directly a part of the output compare unit are gray shaded.

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Figure 15-4. Output Compare Unit, Block Diagram

OCRnxL Buf. (8-bit)OCRnxH Buf. (8-bit)

OCRnx Buffer (16-bit Register)

TEMP (8-bit)

OCRnxL (8-bit)

OCFnx (Int. Req.)

OCRnxH (8-bit)

OCRnx (16-bit Register)

(16-bitComparator)

WGMn3:0 COMnx1:0

Waveform Generator

TCNTnL (8-bit)TCNTnH (8-bit)

TCNTn (16-bit Counter)

DATA BUS (8-bit)

OCnx

TOP

BOTTOM

The OCR1x register is double buffered when using any of the twelve pulse width modulation (PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x compare register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR1x register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x buffer register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x (buffer or compare) register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1x registers must be done via the TEMP register since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP register will be updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x compare register in the same system clock cycle.

For more information of how to access the 16-bit registers refer to Section 15.3 “Accessing 16-bit Registers” on page 91.

15.7.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (FOC1x) bit. Forcing compare match will not set the OCF1x flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or toggled).

15.7.2 Compare Match Blocking by TCNT1 Write

All CPU writes to the TCNT1 register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.

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15.7.3 Using the Output Compare Unit

Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the output compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the data direction register for the port pin to output. The easiest way of setting the OC1x value is to use the force output compare (FOC1x) strobe bits in normal mode. The OC1x register keeps its value even when changing between waveform generation modes.

Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately.

15.8 Compare Match Output Unit

The compare output mode (COM1x1:0) bits have two functions. The waveform generator uses the COM1x1:0 bits for defining the output compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 15-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x register, not the OC1x pin. If a system reset occur, the OC1x register is reset to “0”.

Figure 15-5. Compare Match Output Unit, Schematic

COMnx1

COMnx0

FOCn

clk

I/O

Waveform Generator

DATA BUS

OCnx

PORT

DDR

OCnx

The general I/O port function is overridden by the output compare (OC1x) from the waveform generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the data direction register (DDR) for the port pin. The data direction register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the waveform generation mode, but there are some exceptions. Refer to Table 15-2 on page 108, Table 15-3 on page 108 and Table 15-4 on page 109 for details.

The design of the output compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See Section 15.11 “Register Description” on page

108. The COM1x1:0 bits have no effect on the input capture unit.

ATmega328P [DATASHEET]

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15.8.1 Compare Output Mode and Waveform Generation

The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the waveform generator that no action on the OC1x register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 15-2 on page 108. For fast PWM mode refer to

Table 15-3 on page 108, and for phase correct and phase and frequency correct PWM refer to Table 15-4 on page 109.

A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits.

15.9 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the waveform generation mode (WGM13:0) and compare output mode (COM1x1:0) bits. The compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare match (see Section 15.8 “Compare Match Output

Unit” on page 99). For detailed timing information refer to Section 15.10 “Timer/Counter Timing Diagrams” on page 106.

15.9.1 Normal Mode

The simplest mode of operation is the normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter overflow flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime.

The input capture unit is easy to use in normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit.

The output compare units can be used to generate interrupts at some given time. Using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the CPU time.

15.9.2 Clear Timer on Compare Match (CTC) Mode

In clear timer on compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 15-6. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.

Figure 15-6. CTC Mode, Timing Diagram

TCNTn

OCnA

(Toggle)

Period

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

(COMnA1:0 = 1)

100

ATmega328P [DATASHEET]

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Atmel ATmega328P Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Pin Configurations

1.1 Pin Descriptions

1.1.1 VCC

1.1.2 GND

1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2

1.1.4 Port C (PC5:0)

1.1.5 PC6/RESET

1.1.6 Port D (PD7:0)

1.1.8 AREF

1.1.9 ADC7:6 (TQFP and QFN/MLF Package Onl y)

1.2 Disclaimer

1.3 Automotive Quality Grade

2. Overview

2.1 Block Diagram

3. Resources

4. Data Retention

5. About Code Examples

6. AVR CPU Core

6.1 Overview

6.2 ALU – Arithmetic Logic Unit

6.3 Status Register

6.3.1 SREG – AVR Status Register

6.4 General Purpose Register File

6.4.1 The X-register, Y-register, and Z-register

6.5 Stack Pointer

6.5.1 SPH and SPL – Stack Pointer High and Stack Point er Low Register

6.6 Instruction Execution Timing

6.7 Reset and Interrupt Handling

6.7.1 Interrupt Response Time

7. AVR Memories

7.1 Overview

7.2 In-System Reprogrammable Flash Program Memory

7.3 SRAM Data Memory

7.3.1 Data Memory Access Times

7.4 EEPROM Data Memory

7.4.1 EEPROM Read/Write Access

7.4.2 Preventing EEPROM Corruption

7.5 I/O Memory

7.5.1 General Purpose I/O Registers

7.6 Register Description

7.6.1 EEARH and EEARL – The EEPROM Address Register

7.6.2 EEDR – The EEPROM Data Register

7.6.3 EECR – The EEPROM Control Register

7.6.4 GPIOR2 – General Purpose I/O Register 2

7.6.5 GPIOR1 – General Purpose I/O Register 1

7.6.6 GPIOR0 – General Purpose I/O Register 0

8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

8.2 Clock Sources

8.2.1 Default Clock Source

8.2.2 Clock Startup Sequence

8.3 Low Power Crystal Oscillator

8.4 Full Swing Crystal Oscillator

8.5 Low Frequency Crystal Oscillator

8.6 Calibrated Internal RC Oscillator

8.7 128 kHz Internal Oscillator

8.8 External Clock

8.9 Clock Output Buffer

8.10 Timer/Counter Oscillator

8.11 System Clock Prescaler

8.12 Register Description

8.12.1 OSCCAL – Oscillator Calibration Register

8.12.2 CLKPR – Clock Prescale Register

9. Power Management and Sleep Modes

9.1 Sleep Modes

9.2 BOD Disable

9.3 Idle Mode

9.4 ADC Noise Reduction Mode

9.5 Power-down Mode

9.6 Power-save Mode

9.7 Standby Mode

9.8 Extended Standby Mode

9.9 Power Reduction Register

9.10 Minimizing Power Consumption

9.10.1 Analog to Digital Converter