Datasheet SY89874U Datasheet (Micrel)

Micrel, Inc.

FEATURES

2.5GHz ANY DIFF. IN-TO-LVPECL

Precision Edge

PROGRAMMABLE CLOCK DIVIDER/
FANOUT BUFFER WITH INTERNAL TERMINATION

Precision Edge

®

SY89874U

SY89874U

®

■ Integrated programmable clock divider and 1:2

fanout buffer

■ Guaranteed AC performance over temperature and

voltage:

• > 2.5GHz f

• < 250ps tr/t

MAX

f

• < 15ps within device skew

■ Low jitter design:

• < 10psPP total jitter

• < 1ps

cycle-to-cycle jitter

RMS

■ Unique input termination and VT pin for DC-coupled

and AC-coupled Inputs; CML, PECL, LVDS and
HSTL

■ TTL/CMOS inputs for select and reset

■ 100k EP compatible LVPECL outputs

■ Parallel programming capability

■ Programmable divider ratios of 1, 2, 4, 8 and 16

■ Low voltage operation 2.5V or 3.3V

■ Output disable function

■ –40°C to 85°C temperature range

■ Available in 16-pin (3mm

××

× 3mm) MLF™ package

××

Precision Edge

®

DESCRIPTION

This low-skew, low-jitter device is capable of accepting a
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or
HSTL clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency­locked, lower speed version of the input clock. Available divider
ratios are 2, 4, 8 and 16, or straight pass-through. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz or 38MHz auxiliary clock
components.

The differential input buffer has a unique internal termination
design that allows access to the termination network through
a VT pin. This feature allows the device to easily interface to
different logic standards. A V
AC-coupled applications.

The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /N).

reference is included for

REF-AC

APPLICATIONS

■ SONET/SDH line cards

■ Transponders

■ High-end, multiprocessor sensors

FUNCTIONAL BLOCK DIAGRAM

S2

/RESET

IN

R0

V

T

R1

/IN

S0

S1

V

REF-AC

Precision Edge is a registered trademark of Micrel, Inc.

Micro

LeadFrame and MLF are trademarks of Amkor Technology, Inc.

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Decoder

Enable

FF

Enable

MUX

Divided

by

2, 4, 8

or 16

MUX

Q0
/Q0

Q1
/Q1

TYPICAL PERFORMANCE

OC-12 to OC-3

Translator/Divider

LVDS
622MHz
Clock In

IN

/IN

Q0

/Q0

1

Divide-by-4

155.5MHz Out

LVPECL

155.5MHz
Clock Out

622MHz In

Rev.: C Amendment: /0
Issue Date: October 2005

Micrel, Inc.

/

/

/

PACKAGE/ORDERING INFORMATION

Precision Edge

SY89874U

®

S1

S0

VCC

13141516

1

Q0
Q0

2
3

Q1

4

Q1

8765

S2

NC

VCC

16-Pin MLF™ (MLF-16)

GND

12
11
10

9

RESET

IN
VT
VREF-AC
/IN

Ordering Information

Part Number Type Range Marking Finish

SY89874UMI MLF-16 Industrial 874U Sn-Pb
SY89874UMITR
SY89874UMG

SY89874UMGTR

Notes:

1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.

2. Tape and Reel.

3. Pb-Free package is recommended for new designs.

(2)

(3)

(2, 3)

(1)

Package Operating Package Lead

MLF-16 Industrial 874U Sn-Pb
MLF-16 Industrial 874U with NiPdAu

Pb-Free bar line indicator Pb-Free

MLF-16 Industrial 874U with NiPdAu

Pb-Free bar line indicator Pb-Free

PIN DESCRIPTION

Pin Number Pin Name Pin Function

12, 9 IN, /IN Differential Input: Internal 50Ω termination resistors to VT input. Flexible input accepts any

differential input. See “Input Interface Applications” section.

1, 2, 3, 4 Q0, /Q0 Differential Buffered LVPECL Outputs: Divided by 1, 2, 4, 8 or 16. See “Truth Table.”

Q1, /Q1 Unused PECL outputs may be left floating with no impact on jitter performance.

16, 15, 5 S0, S1, S2 Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25kΩ pull-up

resistor. Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is VCC/2.
6 NC No Connect.
8 /RESET LVTTL/CMOS Logic Levels: Internal 25kΩ pull-up resistor. Logic HIGH if left unconnected.

/DISABLE Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a synchronous

disable/enable function. The reset and disable function occurs on the next high-to-low

clock input transition. Input threshold is VCC/2.

10 VREF-AC Reference Voltage: Equal to VCC–1.4V (approx.). Used for AC-coupled applications only.

Decouple the V

11 VT Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, see

Figures 2a to 2f “Input Interface Applications” section.

7, 14 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitor.

13 GND Ground.

pin with a 0.01µF capacitor. See “Input Interface Applications” section.

REF-AC

TRUTH TABLE

/RESET

Note 1. Reset/Disable function is asserted on the next clock input

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S2 S1 S0 Outputs

1 0 X X Reference Clock (pass through)
1 1 0 0 Reference Clock ÷2
1 1 0 1 Reference Clock ÷4
1 1 1 0 Reference Clock ÷8
1 1 1 1 Reference Clock ÷16

(1)

0

1 X X Q = LOW, /Q = HIGH

Clock Disable

(IN, /IN) high-to-low transition.

2

Micrel, Inc.

Precision Edge

SY89874U

®

Absolute Maximum Ratings

(Note 1)

Supply Voltage (VCC) .................................. –0.5V to +4.0V

Input Voltage (VIN) .................................. –0.5V to VCC+0.3

ECL Output Current (I

OUT

)

Continuous .........................................................50mA

Surge................................................................100mA

Input Current IN, /IN (IIN)..........................................±50mA

VT Current (IVT) ......................................................±100mA

V

REF-AC

Sink/Source Current (I

VREF-AC

), Note 3.......±2mA

Operating Ratings

Supply Voltage (VCC) ................+3.3V ±10% or +2.5V ±5%

Ambient Temperature (TA).........................–40°C to +85°C

Package Thermal Resistance

MLF™ (θJA)

Still-Air .............................................................60°C/W

500lfpm............................................................54°C/W

MLF™ (ψJB), Note 4

Junction-to-Board ............................................32°C/W

(Note 2)

Lead Temperature (soldering 20 sec.) ...................... 260°C

Storage Temperature (TS) .......................–65°C to +150°C

Note 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is

Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3. Due to the limited drive capability use for input of the same package only.
Note 4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the pcb.

TA= –40°C to +85°C; Unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

V

CC

I

CC

R

V

IH

V

IL

V

IN

V

DIFF_IN

|IIN| Input Current (IN, /IN) Note 3 ––45 mA
V

REF-AC

Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2. Specification for packaged product only.
Note 3. Due to the internal termination (see

Note 4. See
Note 5. See
Note 6. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin.

not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng
conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

(Notes 1, 2)

Power Supply 2.375 3.63 V
Power Supply Current No load, max. V

IN

Differential Input Resistance 90 100 110 Ω

CC

50 75 mA

(IN-to-/IN)
Input High Voltage (IN, /IN) Note 3 0.1 – VCC+0.3 V
Input Low Voltage (IN, /IN) Note 3 –0.3 – VCC+0.2 V
Input Voltage Swing Notes 3, 4 0.1 – 3.6 V
Differential Input Voltage Swing Notes 3, 4, 5 0.2 – V

Reference Voltage Note 6 VCC–1.525 VCC–1.425 VCC–1.325 V

a combination of voltages that causes the input current to exceed the maximum limit!

“Timing Diagram”
“Typical Operating Characteristics”

for VIN definition. VIN (Max) is specified when VT is floating.

“Input Structures”

section for V

) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply

definition.

DIFF

(100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS

(Notes 1, 2)

VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C, RL = 50Ω to VCC –2V; Unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

V

OH

V

OL

V

OUT

V

DIFF_OUT

Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2. Specification for packaged product only.

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Output High Voltage VCC–1.145 VCC–1.020 VCC–0.895 V
Output Low Voltage VCC–1.945 VCC–1.820 VCC–1.695 V
Output Voltage Swing 550 800 1050 mV
Differential Output Voltage Swing 1.10 1.60 2.10 V

3

Micrel, Inc.

Precision Edge

SY89874U

®

LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS

(Notes 1, 2)

VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

V

IH

V

IL

I

IH

I

IL

Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2. Specification for packaged product only.

Input HIGH Voltage 2.0 V
Input LOW Voltage 0.8 V
Input HIGH Current –125 20 µA
Input LOW Current –300 µA

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Precision Edge

SY89874U

®

AC ELECTRICAL CHARACTERISTICS

(Notes 1, 2)

VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

f

MAX

Maximum Output Toggle Frequency Output Swing ≥ 400mV 2.5 GHz
Maximum Input Frequency Divide by 2, 4, 8, 16 3.2 GHz

t

PD

t

SKEW

Differential Propagation Delay Input Swing < 400mV 540 650 790 ps
IN to Q

Input Swing ≥ 400mV 480 600 730 ps

Within-Device Skew (diff.) Note 3 715 ps
Q0–Q1

Part-to-Part Skew (diff.) Note 3 250 ps

t

RR

T

jitter

tr,t

f

Note 1. Measured with 400mV input signal, 50% duty cycle, all outputs loaded with 50Ω to VCC–2V, unless otherwise stated.
Note 2. Specification for packaged product only.
Note 3. Skew is measured between outputs under identical transitions.
Note 4. See
Note 5. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T

Note 6. Total jitter definition: with an ideal clock input, of frequency ≤ f

Reset Recovery Time Note 4 600 ps
Cycle-to-Cycle Jitter Note 5 1ps
Total Jitter Note 6 10 ps
Rise/Fall Time (20% to 80%) 70 150 250 ps

“Timing Diagram.”

where T is the time between rising edges of the output signal.

than the specified peak-to-peak jitter value.

(device), no more than one output edge in 1012 output edges will deviate by more

MAX

jitter_cc=Tn–Tn+1

RMS

PP

,

TIMING DIAGRAM

/RESET

/IN

V

CC/2

t

RR

IN

V

IN

V

Swing

IN

/Q

Q

t

PD

V

Swing

OUT

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TYPICAL OPERATING CHARACTERISTICS

VCC = 3.3V, VIN = 400mV, TA = 25°C, unless otherwise stated.

Precision Edge

SY89874U

®

QA Output Amplitude

900
800
700
600
500
400
300
200

QA AMPLITUDE (mV)

100

0

vs. Frequency

0

500

1000

FREQUENCY (MHz)

1500

2000

622MHz Output

2500

3000

3500

IN to Q Propagation Delay

900
800
700
600
500
400
300
200
100

PROPAGATION DELAY (ps)

vs. Input Swing

0

0 200 400 600 800 1000 1200

INPUT SWING (mV)

IN to Q Propagation Delay

800

700

600

500

PROPAGATION DELAY (ps)

400

1.25GHz Output

vs. Temperature

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

/Q

(100mV/div.)

Output Swing

Q

TIME (200ps/div.)

/Q

(100mV/div.)

Output Swing

Q

2.5GHz Output

TIME (100ps/div.)

/Q

(100mV/div.)

Output Swing

Q

TIME (200ps/div.)

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DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING

V

IN, VOUT

800mV
(typical)

Figure 1a. Single-Ended Swing Figure 1b. Differential Swing

Precision Edge

V

DIFF_IN, VDIFF_OUT

1600mV (typical)

®

SY89874U

INPUT BUFFER STRUCTURE

V

CC

1.86kΩ

IN

50Ω

50Ω

GND

/IN

V

T

Figure 2a. Simplified Differential Input Buffer

1.86kΩ

1.86kΩ1.86kΩ

V

CC

R25kΩ

S0
S1
S2

/RESET

GND

R

Figure 2b. Simplified TTL/CMOS Input Buffer

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INPUT INTERFACE APPLICATIONS

Precision Edge

SY89874U

®

V

CC

V

CC

IN

CML

/IN

SY89874U

GND

NC

V

T

V

NC

REF-AC

Figure 3a. DC-Coupled CML

Input Interface

V

CC

IN

PECL

/IN

R

GND

*Note. 3.3V = R

2.5V =

pd

R

R

*

*

pd

V

CC

GND V

0.01µF

= 100Ω

pd

= 50Ω

pd

V

T

REF-AC

V

CC

SY89874U

V

CC

V

CC

IN

CML

/IN

SY89874U

GND

V

V
V

T

REF-AC

CC

0.01µF

Figure 3b. AC-Coupled CML

Input Interface

V

CC

LVDS

GND

NC
NC

V

CC

IN

/IN

SY89874U

V

T

V

REF-AC

V

CC

V

CC

IN

PECL

/IN

SY89874U

GND

0.01µF

V

VCC–2V*

50Ω

NC

CC

* Bypass with 0.01µF to GND

VT

V

REF-AC

Figure 3c. DC-Coupled PECL

Input Interface

V

CC

HSTL

GND

NC V

GND

V

CC

IN

/IN

SY89874U

V

T

REF-AC

Figure 3d. AC-Coupled PECL

Input Interface

Figure 3e. LVDS

Input Interface

Figure 3f. HSTL

Input Interface

RELATED PRODUCT AND SUPPORT DOCUMENTATION

Part Number Function Data Sheet Link

SY89871U 2.5GHz Any Diff. In-to-LVPECL http://www.micrel.com/product-info/products/sy89871u.shtml

Programmable Clock Divider/Fanout Buffer
w/Internal Termination

MLF™ Application Note http://www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf

HBW Solutions New Products and Applications http://www.micrel.com/product-info/products/solutions.shtml

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LVPECL OUTPUT TERMINATION RECOMMENDATIONS

+3.3V

Precision Edge

SY89874U

®

+3.3V

Figure 4a. Parallel Termination–Thevenin Equivalent

Note 1. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω

+3.3V +3.3V

“source”“destination”

Figure 4b. Three-Resistor “Y–Termination”

Z

Z

O

= 50Ω

O

= 50Ω

Z = 50Ω

Z = 50Ω

R1
130Ω

R2
82Ω

50Ω 50Ω

50Ω

R1
130Ω

R2
82Ω

R

b

+3.3V

V

= V

t

(Optional)
C1

CC

—2V

0.01µF

Note 1. Power-saving alternative to Thevenin termination.
Note 2. Place termination resistors as close to destination inputs as possible.
Note 3. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46Ω to 50Ω. For +2.5V systems Rb = 39Ω
Note 4. C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches.

+3.3V +3.3V

V

= V

—1.3V

t

CC

+3.3V +3.3V

R1
130Ω

Q

Z

= 50Ω

O

/Q

V

= V

—2V

t

CC

R2
82Ω

R1
130Ω

R2
82Ω

R3
1kΩ

R4

1.6kΩ

Figure 4d. Terminating Unused I/O

Note 1. Unused output (/Q) must be terminated to balance the output.
Note 2. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ.

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Precision Edge

SY89874U

®

16 LEAD

Micro

LeadFrame™ (MLF-16)

Package

EP- Exposed Pad

Die

CompSide Island

Heat Dissipation

Heat Dissipation

Heavy Copper Plane

Heavy Copper Plane

V

EE

V

EE

PCB Thermal Consideration for 16-Pin MLF™ Package

(Always solder, or equivalent, the exposed pad to the PCB)

Package Notes:
Note 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form.
Note 2. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 [phone] FAX + 1 [phone] WEB http://www.micrel.com

The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s

use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

© 2005 Micrel, Incorporated.

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