Datasheet SY88923V Datasheet (MICREL)

5V/3.3V 2.5Gbps HIGH-SPEED
LIMITING POST AMPLIFIER

SY88923V

FEATURES

■ 3.3V and 5V power supply options

■ Up to 2.5Gbps operation

■ Low noise

■ Chatter-Free LOS Generation

■ Open Collector TTL LOS Output

■ TTL /EN Input

■ Differential PECL inputs for data

■ Single power supply

■ Designed for use with (Micrel-Synergy laser diode

driver and controller)

■ Available in a tiny 10-pin (3mm) MSOP

PIN CONFIGURATION

DIN

/DIN

VREF

LOSLVL

1/EN
2

MSOP

3

K10-1

4
5

10 VCC

DOUT

9

/DOUT

8

LOS

7

GND

6

DESCRIPTION

The SY88923V limiting post amplifier with its high gain
and wide bandwidth is ideal for use as a post amplifier in
fiber-optic receivers with data rates up to 2.5Gbps.
Signals as small as 5mVp-p can be amplified to drive
devices with PECL inputs. The SY88923V generates a
chatter-free Loss of Signal (LOS) open collector TTL
output.

The SY88923V incorporates a programmable level detect
function to identify when the input signal has been lost.
The LOS output will change from logic “LOW” to logic
“HIGH” when input signal is smaller than the swing set by
LOS
of the device to maintain stability under loss of signal
condition. Using LOS
detection can be adjusted. The LOS
by connecting a resistor divider between VCC and V
show in Figure 3. Figure 4, 5, 6, and 7 show the relationship
between input level sensitivity and the voltage set on
LOS

requires a pull-up resistor for proper operation, Figure 1.

. This information can be fed back to the EN input

LVL

pin, the sensitivity of the level

LVL

LVL.

voltage can be set

LVL

REF

The LOS output is a TTL open collector output that

V

SY88923V

LOS

CC

2k

APPLICATIONS

■ 1.25Gbps and 2.5Gbps Gigabit Ethernet

■ 531Mbps, 1062Mbps and 2.12Gbps Fibre Channel

■ 622Mbps SONET

■ Gigabit Interface Converter

■ 2.5Gbps SDH/SONET

■ 2.5Gbps Proprietary Links

Figure 1. LOS Output with Desired Rise Time

BLOCK DIAGRAM

D

IN

Limiting

/D

V

REF

V

GND

LOS

LVL

1

Amplifer

IN

CC

ECL
Buffer

Level
Detect

D

OUT

/D

OUT

Enable

/EN

LOS

Rev.: B Amendment: /0
Issue Date: August 2000

Micrel

SY88923V

PIN NAMES

Pin Type Function

D

IN

/D

IN

LOS
/EN TTL Input Output Enable (Active Low)
LOS TTL Output Loss of Signal Indicator

GND Ground Ground
/D

OUT

D

OUT

V

CC

V

REF

ABSOLUTE MAXIMUM RATINGS

Data Input Data Input
Data Input Inverting Data Input
Input LOS Limit Set

LVL

(Open Collector) (Active High)

PECL Output Inverting Data Output
PECL Output Data Output
Power Supply Positive Power Supply
Output Reference Voltage Output for

LOS Level Set (see Fig. 3)

(1)

GENERAL DESCRIPTION

General

The SY88923V is an integrated limiting amplifier intended
for high-frequency fiber-optic applications. The circuit
connects to typical trans-impedance amplifiers found within
a fiber-optics link. The linear signal output from a trans­impedance amplifier can contain significant amounts of noise,
and may vary in amplitude over time. The SY88923V limiting
amplifier quantizes the signal and outputs a voltage-limited
waveform.

The /EN pin allows the user to disable the output signal
without removing the input signal.

Symbol Rating Value Unit

V

CC

DIN, /D

IN

D

, /D

OUT

OUT

/EN Input Voltage 0 to V
LOS

LVL

V

REF

T

A

T

store

NOTE:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended
periods may affect device reliability.

Power Supply Voltage 0 to +7.0 V
Input Voltage 0 to V

CC

V

Output Voltage (with 50Ω load) VCC –2.5 to VCC +0.3 V

CC

Input Voltage 0 to V

CC

Output Voltage VCC –2.0 to V

CC

V
V

V
Operating Temperature Range –40 to +85 °C
Storage Temperature Range –55 to +125 °C

2

Micrel

SY88923V

DC ELECTRICAL CHARACTERISTICS

VCC = +5V ±10% or +3.3V ±10%, R

Symbol Parameter Min. Max. Min. Max. Min. Typ. Max. Min. Max. Unit

I

CC

I

IL

I

IH

V

CMR

V

offset

LOS
V

OL

I

OH

V

OH

V

OL

V

REF

I

REF

V

IH

V

IL

NOTES:

1. No output load

2. IOL = + 2mA

3. VOH = 5.5V

Power Supply 5V

(1)

Current

3.3V — 40 — 40 — 28 40 — 45
/EN Input LOW Current
/EN Input HIGH Current

Common Mode Range
Differential Output Offset — ±100 — ±100 — ±17 ±100 — ±100 mV
LOS

LVL

LOS Output Low Level
LOS Output Leakage
D

HIGH Output
D

LOW Output

Level V

LVL

and /D

OUT

OUT

and /D

OUT

OUT

(2)

(3)

Reference Supply
V

Output Current –0.8 0.5 –0.8 0.5 –0.8 — 0.5 –0.8 0.5 mA

REF

/EN Input HIGH Voltage
/EN Input LOW Voltage

= 50Ω to VCC –2V

LOAD

= –40°CT

T

A

= 0°CT

A

= +25°CT

A

= +85°C

A

— 40 — 40 — 30 40 — 45 mA

(6)

–0.3

— 20
— 100

GND +2.0

REF

—–0.3

(4)

(5)

V

CC

V

CC

(6)

— 20
— 100

GND +2.0

V

REF

—–0.3

(4)

(5)

V

GND +2.0

CC

V

CC

(6)

——–0.3

——20
——100

— V

V

REF

— V

(4)

(5)

CC

CC

(6)

— 20
— 100

GND +2.0

V

REF

— mA

(4)

(5)

V

CC

V

CC

— 0.5 — 0.5 ——0.5 — 0.5 V
— 100 — 100 ——100 — 100 uA

VCC–1085 VCC–880 VCC–1025 VCC–880 VCC–1025 VCC–955 VCC–880 VCC–1025 VCC–880

VCC –1830 VCC–1555 VCC–1810 VCC–1620 VCC–1810 VCC–1705 VCC–1620 VCC–1810 VCC–1620

VCC–1.38 VCC–1.26 VCC–1.38 VCC–1.26 VCC–1.38 VCC–1.32 VCC–1.26 VCC–1.38 VCC–1.26

2.0 — 2.0 — 2.0 ——2.0 — V
— 0.8 — 0.8 ——0.8 — 0.8 V

4. VIN = 2.7V

5. VIN = V

6. VIN = 0.5V

CC

µA

V

V

mV

mV

V

AC ELECTRICAL CHARACTERISTICS

VCC = +5V ±10% or +3.3V ±10%, R

Symbol Parameter Min. Max. Min. Max. Min. Typ. Max. Min. Max. Unit Conditions

PSRR Power Supply

Rejection Ratio 55MHz

V

ID

V

OD

t

OFFL

t

ONL

t

OFFH

V

SR

Input Voltage Range 5 1800 5 1800 5 — 1800 5 1800 mVp-p
Differential Output —————700 ———mV VID = 15mVp-p

Voltage Swing
LOS Release Time

Minimum Input
LOS Assert Time
LOS Release Time

Maximum Input
LOS Sensitivity Range 5 50 5 50 5 — 50 5 50 mVp-p 223-1 pattern

HYS LOS Hysteresis 2 8 2 8 2 4.6 8 2 8 dB 223-1 pattern

, t

t

r

f

NOTES:

1. Input referred noise = RMS output noise/low frequency gain.

2. Input is a 622MHz square wave.

Output Rise/Fall Time — 175 — 175 — 150 175 — 175 ps VID > 100mVp-p

(1)

(2)

(3)

(3)

(4)

= 50Ω to VCC –2V

LOAD

TA = –40°CTA = 0°CT

= +25°CT

A

= +85°C

A

—————35 ———dB Input referred,

—————300 ———mV VID = 5mVp-p
— 0.5 — 0.5 — 0.1 0.5 — 0.5 µs

— 0.5 — 0.5 — 0.2 0.5 — 0.5 µs
— 0.5 — 0.5 — 0.1 0.5 — 0.5 µs

—————t

3. Input is a 200MHz square wave, tr < 300ps, 8mVp-p.

4. Input is a 200MHz square wave, tr < 300ps, 1.8Vp-p.

rin,tfin

——— VID < 100mVp-p

3

Micrel

DESIGN PROCEDURE

SY88923V

Output Termination

The SY88923V outputs must be terminated with a 50Ω

load to VCC – 2V (or Thevenin equivalent).

Layout and PCB Design

Since the SY88923V is a high-frequency component,
performance can largely be determined by board layout
and design. A common problem with high-gain amplifiers is
feedback from the large swing outputs to the input via the
power supply.

0.1µF

0.1µF

0.1µF

Figure 2. Differential Input Configuration

D

IN+

D

IN–

50Ω50Ω

V

REF

The SY88923V ground pin should be connected to the
circuit board ground. Use multiple PCB vias close to the
part to connect to ground. Avoid long, inductive runs which
can degrade performance.

V

CC

R1

LOS

LVL

R2

V

REF

Figure 3. LOS

Circuit

LVL

NOTES:

LOS

= VCC -1.32V +

LVL

R1 + R2 ≥ 2.6kΩ

R2 × 1.32V

R1 + R2

PRODUCT ORDERING CODE

Ordering Package Operating

Code Type Range

SY88923VKC K10-1 Commercial
SY88923VKCTR K10-1 Commercial

4

Micrel

PERFORMANCE CURVE

SY88923V

LOS Assert and Deassert

100

INPUT LEVEL (mVp-p)

Levels vs LOS

90
80
70
60
50
40
30
20
10

0

0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2

LOS

3.3V
T

2.5Gbps
Pattern 2

= VCC – V (V)

LVL

= 25°C

A

Figure 4.

LOS Assert and Deassert

100

INPUT LEVEL (mVp-p)

Levels vs LOS

90
80
70
60
50
40
30
20
10

0

0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2

LOS

3.3V
T

2.5Gbps
Pattern 2

= VCC – V (V)

LVL

= 25°C

A

LVL

LVL

LOS Assert and Deassert

100

23

-1

INPUT LEVEL (mVp-p)

Levels vs LOS

90
80
70
60
50
40
30
20
10

0

0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2

LOS

LVL

LVL

5.0V
T

= 25°C

A

2.5Gbps
Pattern 2

= VCC– V (V)

23

-1

Figure 5.

LOS Assert and Deassert

100

7

-1

INPUT LEVEL (mVp-p)

Levels vs LOS

90
80
70
60
50
40
30
20
10

0

0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2

LOS

LVL

LVL

5.0V
T

= 25°C

A

2.5Gbps
Pattern 2

= VCC – V (V)

7

-1

Figure 6.

Figure 7.

5

Micrel

10 LEAD MSOP (K10-1)

SY88923V

Rev. 00

6

Micrel

SY88923V

7

Micrel

SY88923V

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA

TEL + 1 [phone] FAX + 1 [phone] WEB http://www.synergysemi.com http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.

© 2000 Micrel Incorporated

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