Intel MFS2600KIB User Manual

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Intel® Compute Module MFS2600KI

Technical Product Specification

Intel order number: G51989-002

Revision 1.0

June, 2012

Enterprise Platforms and Services Division

Revision History Intel® Compute Module MFS2600KI TPS

 

 

 

Revision History

 

 

 

 

 

 

Date

Revision

Modifications

 

 

 

Number

 

 

 

April, 2012

0.5

Initial release.

 

 

 

 

 

 

 

June, 2012

1.0

Corrected BMC LAN settings.

 

 

 

 

 

 

Disclaimers

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel®’s Terms and Conditions of Sale for such products, Intel® assumes no liability whatsoever, and Intel® disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel® products are not intended for use in medical, lifesaving, or life sustaining applications. Intel® may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or “undefined”. Intel® reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel® Compute Module MFS2600KI may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Intel Corporation server baseboards support peripheral components and contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel®’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel® developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the compute module does not operate correctly when used outside any of their published operating or non-operating limits.

Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.

*Other brands and names may be claimed as the property of others.

Copyright © Intel Corporation 2012.

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Intel® Compute Module MFS2600KI TPS Table of Contents

Table of Contents

1.

Introduction ........................................................................................................................

1

 

1.1

Chapter Outline ......................................................................................................

1

2.

Product Overview ...............................................................................................................

2

 

2.1

Intel® Compute Module MFS2600KI Feature Set....................................................

2

 

2.2

Compute Module Layout ........................................................................................

3

 

2.2.1

Connector and Component Locations ....................................................................

3

 

2.2.2

External I/O Connector Locations...........................................................................

4

3.

Functional Architecture .....................................................................................................

5

 

3.1

Intel® Xeon® processor ...........................................................................................

5

 

3.1.1

Processor Support .................................................................................................

5

 

3.1.2

Processor Initialization Error Summary...................................................................

7

 

3.2

Processor Functions Overview ...............................................................................

9

 

3.2.1

Intel® QuickPath Interconnect...............................................................................

10

 

3.2.2

Intel® Hyper-Threading Technology......................................................................

10

 

3.3

Processor Integrated I/O Module (IIO)..................................................................

10

 

3.3.1

PCI Express Interfaces.........................................................................................

10

 

3.3.2

DMI2 Interface to the PCH ...................................................................................

11

 

3.3.3

Integrated IOAPIC................................................................................................

11

 

3.3.4

Intel® QuickData Technology................................................................................

11

 

3.4

Memory Subsystem..............................................................................................

11

 

3.4.1

Integrated Memory Controller (IMC) and Memory Subsystem ..............................

11

 

3.4.2

Publishing Compute Module Memory ...................................................................

15

 

3.4.3

Memory Map and Population Rules......................................................................

15

 

3.4.4

Memory RAS........................................................................................................

19

 

3.5

Intel® C602-J Chipset Overvew ............................................................................

20

 

3.5.1

Digital Media Interface (DMI)................................................................................

21

 

3.5.2

PCI Express* Interface .........................................................................................

21

 

3.5.3

Serial ATA (SATA) Controller ...............................................................................

21

 

3.5.4

Low Pin Count (LPC) Interface.............................................................................

21

 

3.5.5

Serial Peripheral Interface (SPI) ...........................................................................

21

 

3.5.6

Advanced Programmable Interrupt Controller (APIC) ...........................................

21

 

3.5.7

Universal Serial Bus (USB) Controllers ................................................................

22

 

3.6

Integrated Baseboard Management Controller Overview .....................................

22

 

3.6.1

Super I/O Controller .............................................................................................

22

 

3.6.2

Graphics Controller and Video Support ................................................................

23

 

3.6.3

Baseboard Management Controller......................................................................

24

 

3.7

Network Interface Controller (NIC) .......................................................................

25

 

3.8

Intel® Virtualization Technology for Directed I/O (Intel® VT-d) ...............................

26

 

 

 

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4.

System Security................................................................................................................

 

27

 

4.1

BIOS Password Protection ...................................................................................

 

27

 

4.2

Trusted Platform Module (TPM) Support ..............................................................

 

28

 

4.2.1

TPM security BIOS ...............................................................................................

 

28

 

4.2.2

Physical Presence ................................................................................................

 

29

 

4.2.3

TPM Security Setup Options ................................................................................

 

29

 

4.3

Intel ® Trusted Execution Technology ....................................................................

 

30

5. Connector/Header Locations and Pin-outs ....................................................................

 

31

 

5.1

Board Connector Information ...............................................................................

 

31

 

5.2

Power Connectors ................................................................................................

 

31

 

5.3

I/O Connector Pin - out Definition ...........................................................................

 

32

 

5.3.1

VGA Connector ....................................................................................................

 

32

 

5.3.2

I/O Mezzanine Card Connector ............................................................................

 

32

 

5.3.3

Midplane Signal Connector ..................................................................................

 

36

 

5.3.4

Serial Port Connector ...........................................................................................

 

37

 

5.3.5

USB 2.0 Connectors .............................................................................................

 

37

 

5.3.6

Low Profile eUSB SSD Support ...........................................................................

 

38

6.

Jumper Block Settings.....................................................................................................

 

39

 

6.1

CMOS Clear and Password Clear Usage Procedure ............................................

40

 

6.2

Integrated BMC Force Update Procedure ............................................................

 

41

 

6.3

Integrated BMC Initialization .................................................................................

 

41

 

6.4

ME Force Update Jumper ....................................................................................

 

41

 

6.5

BIOS Recovery Jumper ........................................................................................

 

42

7.

Product Regulatory Requirements..................................................................................

 

43

 

7.1

Product Regulatory Requirements ........................................................................

 

43

 

7.2

Product Regulatory Compliance and Safety Markings ..........................................

43

 

7.3

Product Environmental/Ecology Requirements .....................................................

 

43

Appendix A: Integration and Usage Tips ..............................................................................

 

44

Appendix B: POST Code Diagnostic LED Decoder ..............................................................

 

45

Appendix C: POST Error Code...............................................................................................

 

50

Appendix D: Supported Intel® Modular Server System ........................................................

 

56

Glossary

..................................................................................................................................

 

57

Reference ............................................................................................................Documents

 

60

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List of Figures

List of Figures

 

Figure 1. Component and Connector Location Diagram..............................................................

3

Figure 2. Intel® Compute Module MFS2600KI Front Panel Layout ..............................................

4

Figure 3. Intel® Compute Module MFS2600KI Functional Block Diagram....................................

5

Figure 4. Processor Socket Assembly.........................................................................................

6

Figure 5.

Intergrated Memory Controller (IMC) and Memory Subsystem...................................

11

Figure 6.

DIMM Slot Order ........................................................................................................

18

Figure 7.

Integrated BMC Functional Block Diagram.................................................................

22

Figure 8. eUSB SSD Support....................................................................................................

38

Figure 9.

Recovery Jumper Blocks............................................................................................

39

Figure 10. POST Code Diagnostic LED Decoder ......................................................................

45

Figure 11. Intel® Modular Server System MFSYS25V2 .............................................................

56

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List of Tables

Intel® Compute Module MFS2600KI TPS

List of Tables

 

 

Table 1. Intel® compute module MFS2600KI Feature Set ...........................................................

 

2

Table 2. Mixed Processor Configurations....................................................................................

 

8

Table 3. Intel® Compute Module MFS2600KI PCIe Bus Segment Characteristics.....................

11

Table 4. UDIMM Support Guidelines (Preliminary. Subject to Change) .....................................

13

Table 5. RDIMM Support Guidelines (Preliminary. Subject to Change) .....................................

14

Table 6. LRDIMM Support Guidelines (Preliminary. Subject to Change) ...................................

14

Table 7. DDR3 RDIMM Population within a Channel.................................................................

 

16

Table 8. DDR3L Low Voltage RDIMM Population within a Channel ..........................................

16

Table 9. DDR3 UDIMM Population within a Channel.................................................................

 

17

Table 10. DDR3L Low Voltage UDIMM Poplulation within a Channel .......................................

17

Table 11. Intel® Compute Module MFS2600KI DIMM Nomenclature.........................................

18

Table 12. Video Modes .............................................................................................................

 

23

Table 13. Video mode ...............................................................................................................

 

24

Table 14. NIC LED BEHAVIOR.................................................................................................

 

25

Table 15. Board Connector Matrix.............................................................................................

 

31

Table 16. Power Connector Pin-out (J1A1) ...............................................................................

 

31

Table 17. VGA Connector Pin-out (J2K1)..................................................................................

 

32

Table 18. 120-pin I/O Mezzanine Card Connector Pin-out ........................................................

 

33

Table 19. 120-pin I/O Mezzanine Card Connector Signal Definitions ........................................

34

Table 20. 40-pin I/O Mezzanine Card Connector Pin-out ..........................................................

 

36

Table 21. 96-pin Midplane Signal Connector Pin-out.................................................................

 

36

Table 22. Internal 9-pin Serial Header Pin-out (J4K1) ...............................................................

 

37

Table 23. External USB Connector Pin-out ...............................................................................

 

38

Table 24. Pin-out of Internal USB Connector for low-profile Solid State Drive (J1K1)................

38

Table 25. Recovery Jumpers ....................................................................................................

 

40

Table 26. POST Progress Code LED Example .........................................................................

 

45

Table 27. POST Progress Codes ..............................................................................................

 

46

Table 28. MRC Progress Codes ...............................................................................................

 

48

Table 29. MRC Fatal Error Codes .............................................................................................

 

48

Table 30. POST Error Codes and Messages ............................................................................

 

50

Table 31. POST Error Beep Codes ...........................................................................................

 

55

Table 32. Integrated BMC Beep Codes.....................................................................................

 

55

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Intel® Compute Module MFS2600KI TPS

Introduction

1.Introduction

This Technical Product Specification (TPS) provides board-specific information detailing the features, functionality, and high-level architecture of the Intel® Compute Module MFS2600KI.

1.1Chapter Outline

This document is divided into the following chapters:

Chapter 1 – Introduction

Chapter 2 – Product Overview

Chapter 3 – Functional Architecture

Chapter 4 – System Security

Chapter 5 – Connector/Header Locations and Pin-outs

Chapter 6 – Jumper Block Settings

Chapter 7 – Product Regulatory Requirements

Appendix A – Integration and Usage Tips

Appendix B – POST Code Diagnostic LED Decoder

Appendix C – Post Error Code

Appendix D – Supported Intel® Modular Server System

Glossary

Reference Documents

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Product Overview

Intel® Compute Module MFS2600KI TPS

2.Product Overview

The Intel® Compute Module MFS2600KI is a monolithic printed circuit board with features that were designed to support the high-density compute module market.

2.1Intel® Compute Module MFS2600KI Feature Set

Table 1. Intel® compute module MFS2600KI Feature Set

Feature

 

Description

Processors

Support for one or two Intel® Xeon® Processor E5-2600 series with up to 95W Thermal

 

Design Power (TDP).

 

8.0 GT/s, and 6.4 GT/s Intel® QuickPath Interconnect (Intel® QPI)

 

Enterprise Voltage Regulator-Down (EVRD) 12.0

Memory

Support for 1067/1333/1600 MT/s ECC registered (RDIMM), unbuffered (UDIMM)

 

and LRDIMM DDR3 memory.

 

16 DIMMs total across 8 memory channels (4 channels per processor).

 

Note: Mixed memory is not tested or supported. Non-ECC memory is not tested and is

 

not supported in a server environment.

 

 

 

Chipset

Intel® C602-J Chipset

 

 

On-board

External connections:

Connectors/Headers

Four USB 2.0 ports

 

 

 

DB-15 Video connector

 

Internal connectors/headers:

 

One low-profile USB Type-A connector to support low-profile USB solid state drives

 

One internal 7pin SATA connector for embedded SATA Flash Drive

 

One eUSB for embedded USB device

 

Intel® I/O Mezzanine connectors supporting Dual Gigabit NIC Intel® I/O Expansion

 

 

Module (Optional)

 

 

On-board Video

Integrated Matrox* G200 Core, one DB15 Video port (Front)

 

 

On-board Hard Drive

LSI* 1064e SAS controller

Controller

 

 

 

 

LAN

Intel® I350 Dual 1GbE Network Controller

 

 

 

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Product Overview

2.2Compute Module Layout

2.2.1Connector and Component Locations

The following figure shows the board layout of the Intel® Compute Module MFS2600KI. Each connector and major component is identified by a number or letter. A description of each identified item is provided below the figure.

A

CPU 1 DIMM Slots

I

CPU 1 Socket

 

 

 

 

B

CPU 2 DIMM Slots

J

Power/Fault LEDs

 

 

 

 

C

Mezzanine Card Connector 1

K

Power Button

 

 

 

 

D

Mezzanine Card Connector 2

L

Battery

 

 

 

 

E

Midplane Power Connector

M

Activity and ID LEDs

 

 

 

 

F

Midplane Signal Connector

N

Video Connector

 

 

 

 

G

Midplane Guide Pin Receptacle

O

USB Ports 2 and 3

 

 

 

 

H

CPU 2 Socket

P

USB1 Ports 0 and 1

 

 

 

 

Figure 1. Component and Connector Location Diagram

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2.2.3External I/O Connector Locations

The following drawing shows the layout of the external I/O components for the Intel® Compute Module MFS2600KI.

A

USB ports 0 and 1

G

NIC 1 LED

 

 

 

 

B

USB ports 2 and 3

H

Hard Drive Activity LED

 

 

 

 

C

Video

I

ID LED

 

 

 

 

D

I/O Mezzanine NIC 4 LED

J

Power button

 

 

 

 

E

I/O Mezzanine NIC 3 LED

K

Power and Fault LEDs

 

 

 

 

F

NIC 2 LED

 

 

 

 

 

 

Figure 2. Intel® Compute Module MFS2600KI Front Panel Layout

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Functional Architecture

3.Functional Architecture

The architecture of the Intel® Compute Module MFS2600KI is developed around the integrated features and functions of the Intel® Xeon® processor E5-2600 product family the Intel® C602-J chipset, the Intel® Ethernet Controller I350 GbE controller chip and the Baseboard Management Controller.

The following diagram provides an overview of the compute module architecture, showing the features and interconnects of each of the major sub-system components.

Figure 3. Intel® Compute Module MFS2600KI Functional Block Diagram

3.1Intel® Xeon® processor

3.1.1Processor Support

The compute module includes two Socket-R (LGA2011) processor sockets and can support one or two of the Intel® Xeon® processor E5-2600 product family, with a Thermal Design Power (TDP) of up to 95W processors.

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3.1.1.1Processor Socket Assembly

Each processor socket of the server board is pre-assembled with an Independent Latching Mechanism (ILM) and Back Plate which allow for secure placement of the processor and processor heat to the server board.

The illustration below identifies each sub-assembly component.

Heat Sink

Server Board

Independent Latching

Mechanism (ILM)

Back Plate

Figure 4. Processor Socket Assembly

3.1.1.2Processor Population Rules

Note: Although the Compute Module does support dual-processor configurations consisting of different processors that meet the defined criteria below, Intel® does not perform validation testing of this configuation. For optimal performance in dual-processor configurations, Intel® recommends that identical processors be installed.

When using a single processor configuration, the processor must be installed into the processor socket labeled CPU1.

When two processors are installed, the following population rules apply:

Both processors must be of the same processor family.

Both processors must have the same number of cores.

Both processors must have the same cache sizes for all levels of processor cache memory.

Processors with different core frequencies can be mixed in a system, given the prior rules are met. If this condition is detected, all processor core frequencies are set to the lowest common denominator (highest common speed) and an error is reported.

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Functional Architecture

Processors which have different Intel® Quickpath (QPI) Link Frequencies may operate together if they are otherwise compatible and if a common link frequency can be selected. The common link frequency would be the highest link frequency that all installed processors can achieve.

Processor stepping within a common processor family can be mixed as long as it is listed in the processor specification updates published by Intel Corporation.

3.1.2Processor Initialization Error Summary

The following table describes mixed processor conditions and recommended actions for the MFS2600KIdesigned around the Intel® Xeon® processor E5-2600 product family and Intel® C602-J chipset product family architecture. The errors fall into one of the following categories:

Fatal: If the system can boot, it pauses at a blank screen with the text “Unrecoverable fatal error found. System will not boot until the error is resolved” and “Press <F2> to enter setup”, regardless of whether the “Post Error Pause” setup option is enabled or disabled.

When the operator presses the <F2> key on the keyboard, the error message is displayed on the Error Manager screen, and an error is logged to the System Event Log (SEL) with the POST Error Code.

The system cannot boot unless the error is resolved. The user needs to replace the faulty part and restart the system.

For Fatal Errors during processor initialization, the System Status LED will be set to a steady Amber color, indicating an unrecoverable system failure condition.

Major: If the “Post Error Pause” setup option is enabled, the system goes directly to the

Error Manager to display the error, and logs the POST Error Code to SEL. Operator intervention is required to continue booting the system.

Otherwise, if “POST Error Pause” is disabled, the system continues to boot and no prompt is given for the error, although the Post Error Code is logged to the Error Manager and in a SEL message.

Minor: The message is displayed on the screen or on the Error Manager screen, and the POST Error Code is logged to the SEL. The system continues booting in a degraded state. The user may want to replace the erroneous unit. The POST Error Pause option setting in the BIOS setup does not have any effect on this error.

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Table 2. Mixed Processor Configurations

 

 

 

 

 

 

Error

Severity

System Action

 

 

Processor family not

Fatal

The BIOS detects the error condition and responds as follows:

 

 

Identical

 

 

 

 

 

 

 

 

 

Logs the POST Error Code into the System Event Log (SEL).

 

 

 

 

Alerts the BMC to set the System Status LED to steady Amber.

 

 

 

 

Displays “0194: Processor family mismatch detected

 

 

 

 

message in the Error Manager.

 

 

 

 

Takes Fatal Error action (see above) and will not boot until the

 

 

 

 

fault condition is remedied.

 

 

 

 

 

 

 

Processor model not

Fatal

The BIOS detects the error condition and responds as follows:

 

 

Identical

 

 

 

 

 

 

 

 

 

Logs the POST Error Code into the System Event Log (SEL).

 

 

 

 

Alerts the BMC to set the System Status LED to steady Amber.

 

 

 

 

Displays “0196: Processor model mismatch detected

 

 

 

 

message in the Error Manager.

 

 

 

 

Takes Fatal Error action (see above) and will not boot until the

 

 

 

 

fault condition is remedied.

 

 

 

 

 

 

 

Processor cores/threads not

Fatal

The BIOS detects the error condition and responds as follows:

 

 

identical

 

 

 

 

 

 

 

 

 

Logs the POST Error Code into the SEL.

 

 

 

 

Alerts the BMC to set the System Status LED to steady Amber.

 

 

 

 

Displays “0191: Processor core/thread count mismatch

 

 

 

 

detected” message in the Error Manager.

 

 

 

 

Takes Fatal Error action (see above) and will not boot until the

 

 

 

 

fault condition is remedied.

 

 

 

 

 

 

 

Processor cache not

Fatal

The BIOS detects the error condition and responds as follows:

 

 

identical

 

 

 

 

 

 

 

 

 

Logs the POST Error Code into the SEL.

 

 

 

 

Alerts the BMC to set the System Status LED to steady Amber.

 

 

 

 

Displays “0192: Processor cache size mismatch detected

 

 

 

 

message in the Error Manager.

 

 

 

 

Takes Fatal Error action (see above) and will not boot until the

 

 

 

 

fault condition is remedied.

 

 

 

 

 

 

 

Processor frequency (speed)

Fatal

The BIOS detects the processor frequency difference, and responds

 

 

not identical

 

 

 

 

as follows:

 

 

 

 

 

 

 

 

Adjusts all processor frequencies to the highest common

 

 

 

 

frequency.

 

 

 

 

No error is generated – this is not an error condition.

 

 

 

 

Continues to boot the system successfully.

 

 

 

 

If the frequencies for all processors cannot be adjusted to be the

 

 

 

 

same, then this is an error, and the BIOS responds as follows:

 

 

 

 

Logs the POST Error Code into the SEL.

 

 

 

 

Alerts the BMC to set the System Status LED to steady Amber.

 

 

 

 

Does not disable the processor.

 

 

 

 

Displays “0197: Processor speeds unable to synchronize

 

 

 

 

message in the Error Manager.

 

 

 

 

Takes Fatal Error action (see above) and will not boot until the fault

 

 

 

 

condition is remedied.

 

 

 

 

 

 

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Functional Architecture

 

 

 

 

 

 

Error

Severity

System Action

 

 

Processor Intel® QuickPath

Fatal

The BIOS detects the QPI link frequencies and responds as follows:

 

 

Interconnect link frequencies

 

 

 

 

 

 

 

not identical

 

Adjusts all QPI interconnect link frequencies to highest common

 

 

 

 

frequency.

 

 

 

 

No error is generated – this is not an error condition.

 

 

 

 

Continues to boot the system successfully.

 

 

 

 

If the link frequencies for all QPI links cannot be adjusted to be the

 

 

 

 

same, then this is an error, and the BIOS responds as follows:

 

 

 

 

Logs the POST Error Code into the SEL.

 

 

 

 

Alerts the BMC to set the System Status LED to steady Amber.

 

 

 

 

Displays “0195: Processor Intel® QPI link frequencies unable

 

 

 

 

to synchronize” message in the Error Manager.

 

 

 

 

Does not disable the processor.

 

 

 

 

Takes Fatal Error action (see above) and will not boot until the fault

 

 

 

 

condition is remedied.

 

 

 

 

 

 

3.2Processor Functions Overview

With the release of the Intel® Xeon® processor E5-2600 product family, several key system components, including the CPU, Integrated Memory Controller (IMC), and Integrated IO Module (IIO), have been combined into a single processor package and feature per socket; two Intel® QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to 40 lanes of Gen 3 PCI Express* links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* Gen 2 interface with a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space and 48-bit of virtual address space.

The following sections will provide an overview of the key processor features and functions that help to define the architecture, performance and supported functionality of the server board. For more comprehensive processor specific information, refer to the Intel® Xeon® processor E52600 product family documents listed in the Reference Document list in Chapter 1.

Processor Core Features:

Up to 8 execution cores

Each core supports two threads (Intel® Hyper-Threading Technology), up to 16 threads per socket

46-bit physical addressing and 48-bit virtual addressing

1 GB large page support for server applications

A 32-KB instruction and 32-KB data first-level cache (L1) for each core

A 256-KB shared instruction/data mid-level (L2) cache for each core

Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores

Supported Technologies:

Intel® Virtualization Technology (Intel® VT)

Intel® Virtualization Technology for Directed I/O (Intel® VT-d)

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Functional Architecture

Intel® Compute Module MFS2600KI TPS

Intel® Trusted Execution Technology (Intel® TXT)

Intel® 64 Architecture

Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)

Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)

Intel® Advanced Vector Extensions (Intel® AVX)

Intel® Hyper-Threading Technology

Execute Disable Bit

Intel® Turbo Boost Technology

Intel® Intelligent Power Technology

Enhanced Intel® SpeedStep Technology

3.2.1Intel® QuickPath Interconnect

The Intel® QuickPath Interconnect (QPI) is a high speed, packetized, point-to-point interconnect used in the processor. The narrow high-speed links stitch together processors in distributed shared memory and integrated I/O platform architecture. It offers much higher bandwidth with low latency. The Intel® QuickPath Interconnect has an efficient architecture allowing more interconnect performance to be achieved in real systems. It has a snoop protocol optimized for low latency and high scalability, as well as packet and lane structures enabling quick completions of transactions. Reliability, availability, and serviceability features (RAS) are built into the architecture.

The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional links to complete the connection between two components. This supports traffic in both directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as having five layers: Physical, Link, Routing, Transport, and Protocol.

The Intel® QuickPath Interconnect includes a cache coherency protocol to keep the distributed memory and caching structures coherent during system operation. It supports both low-latency source snooping and a scalable home snoop behavior. The coherency protocol provides for direct cache-to-cache transfers for optimal latency.

3.2.2Intel® Hyper-Threading Technology

Most Intel® Xeon® processors support Intel® Hyper-Threading Technology. The BIOS detects processors that support this feature and enables the feature during POST.

If the processor supports this feature, the BIOS Setup provides an option to enable or disable this feature. The default is enabled.

3.3Processor Integrated I/O Module (IIO)

The processor’s integrated I/O module provides features traditionally supported through chipset components. The integrated I/O module provides the following features:

3.3.1PCI Express Interfaces

The integrated I/O module incorporates the PCI Express interface and supports up to 40 lanes of PCI Express. The following tables list the CPU PCIe port connectivity of the Intel® Compute Module MFS2600KI.

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Intel order number: G51989-002

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