Desktop Board D815EGEW may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current
The Intel
characterized errata are documented in the Intel Desktop Board D815EGEW Specification Update.
October 2001
Order Number A73971-001
Revision History
Revision Revision History Date
-001 First release of the Intel® Desktop Board D815EGEW Technical Product
Specification
This product specification applies to only standard D815EGEW boards with BIOS identifier
EW81520A.86A.
Changes to this specification will be published in the Intel Desktop Board D815EGEW
Specification Update before being incorporated into a revision of this document.
®
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
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®
The Intel
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
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Intel, Celeron and LANDesk are registered trademarks of Intel Corporation or its subsidiaries in the United States and other
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†
Other names and brands may be claimed as the property of others.
Copyright 2001, Intel Corporation. All rights reserved.
Desktop Board D815EGEW may contain design defects or errors known as errata that may cause the product to
PRODUCTS. EXCEPT AS
October 2001
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and the BIOS for the Intel Desktop Boards D815EGEW.
It describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the D815EGEW board and its
components to the vendors, system integrators, and other engineers and technicians who need this
level of information. It is specifically not intended for general audiences.
What This Document Contains
Chapter Description
1 A description of the hardware used on the D815EGEW board
2 A map of the resources of the board
3 The features supported by the BIOS Setup program
4 The contents of the BIOS Setup program’s menus and submenus
5 A description of the BIOS error messages, beep codes, and POST codes
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions, which if not observed, can cause personal injury.
# Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX) When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the D815EGEW board, and X is the instance of the particular
part at that general location. For example, J5J1 is a connector, located at 5J. It is the first
connector in the 5J area.
GB Gigabyte (1,073,741,824 bytes)
KB Kilobyte (1024 bytes)
Kbit Kilobit (1024 bits)
kbits/sec 1000 bits per second
MB Megabyte (1,048,576 bytes)
MB/sec Megabytes per second
Mbit Megabit (1,048,576 bits)
Mbit/sec Megabits per second
xxh An address or data value ending with a lowercase h indicates a hexadecimal value.
x.x V Volts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
respective owners.
Table 1 summarizes the D815EGEW board’s major features.
Table 1. Feature Summary
Form Factor
Processor
Memory
Chipsets
I/O Control
Video
Audio
Peripheral
Interfaces
Expansion
Capabilities
BIOS
Instantly Available
PC
microATX (9.20 inches by 7.65 inches)
Support for either an Intel
(FC-PGA) package or an Intel® Celeron® processor in an FC-PGA package
• Two 168-pin SDRAM Dual Inline Memory Module (DIMM) sockets
• Support for up to 512 MB system memory
• Support for single-sided or double-sided DIMMs
• The D815EGEW board includes the Intel 815EG Chipset, consisting of:
Intel
Intel
Intel
National Semiconductor PC87360 LPC bus I/O controller
Intel 82815G integrated graphics support
• Intel 82801BA ICH2 digital controller (AC link output)
• Analog Devices AD1885 Audio Codec
• Two Universal Serial Bus (USB) ports
• One serial port
• One parallel port
• Two IDE interfaces with Ultra DMA, ATA-66/100 support
• One diskette drive interface
• PS/2
Four PCI bus add-in card connectors (PCI bus connector 2 includes SMBus
signals and is S5 wake-enabled)
• Intel/AMI BIOS (Intel 82802AB 4 Mbit FWH)
• Support for Advanced Configuration and Power Interface (ACPI), Plug and Play,
and SMBIOS
• Support for PCI Local Bus Specification Revision 2.2
• Suspend to RAM support
• Wake on PS/2 keyboard and USB ports
®
82815G Graphics and Memory Controller Hub (GMCH)
®
82801BA I/O Controller Hub (ICH2)
®
82802AB 4 Mbit Firmware Hub (FWH)
†
keyboard and mouse ports
®
Pentium® III processor in a Flip Chip Pin Grid Array
For information about Refer to
The board’s compliance level with ACPI, Plug and Play, and SMBIOS Table 3, page 17
12
Product Description
1.1.2 Manufacturing Options
Table 2 describes the D815EGEW board’s manufacturing options. Not every manufacturing
option is available in all marketing channels. Please contact your Intel representative to determine
which manufacturing options are available to you.
Table 2. Manufacturing Options
®
LAN Subsystem
Chassis Fan
Connector
Chassis Intrusion
Connector
SCSI LED
Connector
Speaker
Standby power
indicator LED
Wake on LAN†
Technology
Connector
Intel
82562ET 10/100 Mbit/sec Platform LAN Connect (PLC) device
Connector for an additional cooling fan
Connector for sensing chassis intrusion
Allows add-in SCSI host bus adapters to use the same LED as the onboard I/O
controller
47 Ω inductive speaker that provides audible error code (beep code) information
during Power On Self Test (POST)
Shows that power is still present at the DIMM and PCI bus connectors, even when
the computer appears to be off
Support for system wake up using an add-in network interface card with remote wake
up capability
Figure 1 shows the location of the major components on the D815EGEW board.
BA
C
D
E
F
G
W
H
V
U
T
S
R
I
Q
N
P
O
A AD1885 audio codec M Battery
B ATAPI-style audio connectors N Speaker (optional)
C Back panel connectors O SCSI LED connector (optional)
D Wake from PS/2 and USB jumper blocks P Front panel connector
E Processor fan connector Q Chassis intrusion connector (optional)
F BIOS Setup Configuration jumper R Front panel power LED connector
G Intel 82815G GMCH S Chassis fan connector (optional)
H Processor socket T Wake on LAN technology connector (optional)
I DIMM sockets U Intel 82801BA I/O Controller Hub (ICH2)
J Power connector V Intel 82802AB 4 Mbit Firmware Hub (FWH)
K Diskette drive connector W PCI bus add-in card connectors
L IDE connectors
M
L
KJ
OM12802
14
Figure 1. Board Components
1.1.4 Block Diagram
Figure 2 is a block diagram of the major functional areas of the D815EGEW board.
The D815EGEW board supports drivers for all of the onboard hardware and subsystems under the
following operating systems:
†
• Microsoft Windows
• Windows ME
• Windows NT
• Windows 2000
• Windows XP
For information about Refer to
Supported drivers Section 1.3
†
98SE – ACPI mode
4.0
NOTE
✏
Third party vendors may offer other drivers.
16
1.4 Design Specifications
Table 3 lists the specifications applicable to the D815EGEW board.
Table 3. Specifications
Reference
Name
AC ’97 Audio Codec ’97 Revision 2.1,
ACPI Advanced Configuration
AMI BIOS American Megatrends
ATA/
ATAPI-5
ATX ATX Specification Version 2.03,
BIS Boot Integrity Services Version 1.0 for WfM 2.0
EPP IEEE Std 1284.1-1997
El Torito Bootable CD-ROM Format
LPC Low Pin Count Interface
MicroATX microATX Motherboard
Specification
Title
and Power Interface
Specification
BIOS Specification
Information Technology AT Attachment with Packet
Interface - 5
(ATA/ATAPI-5)
(Enhanced Parallel Port)
Specification
Specification
Interface Specification
Version, Revision Date,
and Ownership
May 1998,
Intel Corporation.
Version 2.0,
July 27, 2000,
Compaq Computer
Corporation,
Intel Corporation,
Microsoft Corporation,
Phoenix Technologies
Limited, and
Toshiba Corporation.
AMIBIOS 99,
1999,
American Megatrends, Inc.
Revision 3,
February 29, 2000,
Contact: T13 Chair,
Seagate Technology.
December 1998,
Intel Corporation.
August 1999,
Intel Corporation.
Version 1.7,
1997,
Institute of Electrical and
Electronic Engineers.
Version 1.0,
January 25, 1995,
Phoenix Technologies
Limited and International
Business Machines
Corporation.
Version 1.0,
September 29, 1997,
Intel Corporation.
Version 2.2,
December 18, 1998,
PCI Special Interest Group.
Version 1.1,
December 18, 1998,
PCI Special Interest Group.
Version 1.0a,
May 5, 1994,
Compaq Computer Corporation,
Phoenix Technologies Limited,
and Intel Corporation.
Revision 1.0,
February 1998,
Intel Corporation.
November 1999,
Intel Corporation.
Revision 1.2B,
November 1999,
Intel Corporation.
Version 2.3.1,
March 16, 1999,
American Megatrends
Incorporated,
Award Software International
Incorporated,
Compaq Computer Corporation,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
and SystemSoft Corporation.
Revision 1.1,
March 1996,
Intel Corporation.
Version 1.1,
September 23, 1998,
Compaq Computer Corporation,
Intel Corporation,
Microsoft Corporation, and
NEC Corporation.
Version 2.0,
December 18, 1998,
Intel Corporation.
Use only the processors listed below. Use of unsupported processors can damage the board, the
processor, and the power supply. See the Intel
most up-to-date list of supported processors for the D815EGEW board.
The D815EGEW board supports a single Pentium III or Celeron processor. The system bus
frequency is automatically selected. The board supports the processors listed in Table 4.
Table 4. Supported Processors
Type Designation System Bus Frequency L2 Cache Size
1.00, 1.13, and 1.20 GHz 133 MHz 256 KB Pentium III processor in
Before installing or removing memory, make sure that AC power is disconnected by unplugging
the power cord from the computer. Failure to do so could damage the memory and the board.
NOTE
✏
To be fully compliant with all applicable Intel® SDRAM memory specifications, the board should
be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. If your
memory modules do not support SPD, you will see a notification to this effect on the screen at
power up. The BIOS will attempt to configure the memory controller for normal operation.
However, DIMMs may not function under the determined frequency.
NOTE
✏
Because the main system memory is also used as video memory, the board requires a 100 MHz
SDRAM DIMM even though the host bus frequency is 66 MHz. It is highly recommended that an
SPD DIMM be used, since this allows the BIOS to read the SPD data and program the chipset to
accurately configure memory settings for optimum performance. If non-SPD memory is installed,
the BIOS will attempt to correctly configure the memory settings, but performance and reliability
may be impacted.
The D815EGEW board has two DIMM sockets and supports the following memory features:
• 3.3 V (only) 168-pin SDRAM DIMMs with gold-plated contacts
• Unbuffered single-sided or double-sided DIMMs
• Capacity:
Maximum system memory: 512 MB
Minimum system memory: 64 MB
• 133 MHz SDRAM or 100 MHz SDRAM
• Serial Presence Detect (SPD) and non-SPD memory
• Non-ECC and ECC DIMMs (ECC DIMMs will operate in non-ECC mode only)
• Suspend to RAM
When installing memory, note the following:
• Non-SPD DIMMs will always revert to a 100 MHz with 3-3-3 timing SDRAM bus.
• Mixing Non-SPD DIMMs with SPD DIMMs will always revert to a 100 MHz with 3-3-3
timing SDRAM bus.
• The BIOS will not initialize installed memory above 512 MB. At boot, the BIOS displays a
message indicating that any installed memory above 512 MB has not been initialized.
• Mixed memory speed configurations (133 and 100 MHz) will default to 100 MHz.
• 133 MHz SDRAM operation requires a 133 MHz system bus frequency processor.
• 100 MHz SDRAM may be populated with four rows of SDRAM (two double-sided DIMMs).
For information about Refer to
Obtaining the PC Serial Presence Detect (SPD) SpecificationTable 3, page 17
20
Product Description
Table 5 lists the supported DIMM configurations.
Table 5. Supported Memory Configurations
SDRAM
Density
DIMM
Capacity
Number of
(Note 1)
Sides
32 MB DS 16 Mbit 2 M x 8/2 M x 8 16
32 MB SS 64 Mbit 4 M x 16/empty 4
48 MB DS 64/16 Mbit 4 M x 16/2 M x 8 12
64 MB DS 64 Mbit 4 M x 16/4 M x 16 8
64 MB SS 64 Mbit 8 M x 8/empty 8
64 MB SS 128 Mbit 8 M x 16/empty 4
96 MB DS 64 Mbit 8 M x 8/4 M x 16 12
96 MB DS 128/64 Mbit 8 M x 16/4 M x 16 8
128 MB DS 64 Mbit 8 M x 8/8 M x 8 16
128 MB DS 128 Mbit 8 M x 16/8 M x 16 8
128 MB SS 128 Mbit 16 M x 8/empty 8
128 MB SS 256 Mbit 16 M x 16/empty 4
192 MB DS 128 Mbit 16 M x 8/8 M x 16 12
192 MB DS 128/64 Mbit 16 M x 8/8 M x 8 16
256 MB DS 128 Mbit 16 M x 8/16 M x 8 16
256 MB DS 256 Mbit 16 M x 16/16 M x 16 8
256 MB SS 256 Mbit 32 M x 8/empty 8
512 MB DS 256 Mbit 32 M x 8/32 M x 8 16
Notes:
1. “DS” refers to double-sided memory modules (containing two rows of SDRAM) and “SS” refers to single-sided memory
modules (containing one row of SDRAM).
2. If the number of SDRAM devices is greater than nine, the DIMM will be double sided.
3. Front side population/back side population indicated for SDRAM density and SDRAM organization.
The Intel® 815EG chipset consists of the following devices:
• 82815G Graphics and Memory Controller Hub (GMCH) with Accelerated Hub Architecture
(AHA) bus
• 82801BA I/O Controller Hub (ICH2) with AHA bus
• Intel 82802AB 4 Mbit Firmware Hub (FWH)
The GMCH is a centralized controller for the system bus, the memory bus, and the AHA bus. The
ICH2 is a centralized controller for the board’s I/O paths. The FWH provides the nonvolatile
storage of the BIOS.
The Intel 815EG chipset provides the interfaces shown in Figure 3.
ATA-66/100
System Bus
SDRAM Bus
Network
USB
815EG Chipset
82815G
Graphics and
Memory Controller
Hub (GMCH)
Video
Bus
AHA
Bus
82801BA
I/O Controller Hub
(ICH2)
82802AB 4 Mbit
Firmware Hub
(FWH)
LPC Bus
AC LinkPCI BusSMBus
OM12838
Figure 3. Intel 815EG Chipset Block Diagram
For information about Refer to
The Intel 815EG chipset http://developer.intel.com/design/chipsets/815eg
The resources used by the chipset Chapter 2
The chipset’s compliance with ACPI and AC ’97 Table 3, page 17
22
Product Description
1.7.1 IDE Interfaces
The ICH2’s IDE controller has two independent bus-mastering IDE interfaces that can be
independently enabled. The IDE interfaces support the following modes:
• Programmed I/O (PIO): CPU controls data transfer.
• 8237-style DMA: DMA offloads the CPU, supporting transfer rates of up to 16 MB/sec.
• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
• ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
• ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH2 ATA-100
logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to
88 MB/sec.
✏ NOTE
ATA-66 and ATA-100 are faster timings and require a specialized cable to reduce reflections,
noise, and inductive coupling.
The IDE interfaces also support ATAPI devices (such as CD-ROM drives) and ATA devices using
the transfer modes listed in Table 64 on page 95.
The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The D815EGEW board supports Laser Servo (LS-120) diskette technology through its IDE
interfaces. The LS-120 drive can be configured as a boot device by setting the BIOS Setup
program’s Boot menu to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
For information about Refer to
The location of the IDE connectors Figure 9, page 54
The signal names of the IDE connectors Table 37, page 56
BIOS Setup program’s Boot menu Table 71, page 103
1.7.2 USB
The D815EGEW board has two USB ports; one USB peripheral can be connected to each port.
For more than two USB devices, an external hub can be connected to any of the ports. The
D815EGEW board’s two USB ports are implemented with stacked back panel connectors, routed
through the ICH2. The board contains a jumper block for enabling/disabling the Wake from USB
feature.
The D815EGEW board fully supports the Universal Hub Controller Interface (UHCI).
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
For information about Refer to
The location of the USB connectors on the back panel Figure 7, page 46
The signal names of the back panel USB connectors Table 20, page 47
The USB specification and UHCI Table 3, page 17
The Wake from USB jumper block Section 2.9, page 61
1.7.3 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock provides a time-of-day clock and a multicentury calendar with alarm features.
The real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are
reserved for BIOS use.
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
✏ NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded into CMOS
SRAM at power-on.
1.8 I/O Controller
The D815EGEW board includes the National Semiconductor PC87360 I/O controller. The I/O
controller’s features include:
• Low pin count (LPC) interface
• 3.3 V operation
• One serial port
• One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support
• PS/2-style mouse and keyboard interfaces
• Interface for one 1.2 MB, 1.44 MB, or 2.88 MB diskette drive
• One fan control output
The BIOS Setup program provides configuration options for the I/O controller.
For information about Refer to
National Semiconductor PC87360 I/O controller http://www.natsemi.com
24
Product Description
1.8.1 Serial Port
Serial port A is located on the back panel. The serial port supports data transfers at speeds up to
115.2 kbits/sec with BIOS support. The serial port can be assigned as COM1 (3F8h), COM2
(2F8h), COM3 (3E8h), or COM4 (2E8h).
For information about Refer to
The location of the serial port A connector Figure 7, page 46
The signal names of the serial port A connector Table 23, page 48
1.8.2 Parallel Port
The connector for the parallel port is a 25-pin D-Sub connector located on the back panel. In the
BIOS Setup program, the parallel port can be set to the following modes:
†
• Output only (PC AT
• Bi-directional (PS/2 compatible)
• EPP
• ECP
For information about Refer to
The location of the parallel port connector Figure 7, page 46
The signal names of the parallel port connector Table 22, page 48
Setting the parallel port’s mode Table 62, page 92
-compatible mode)
1.8.3 Diskette Drive Controller
The I/O controller supports one diskette drive that is compatible with the 82077 diskette drive
controller and supports both PC-AT and PS/2 modes.
For information about Refer to
The location of the diskette drive connector Figure 9, page 54
The signal names of the diskette drive connector Table 36, page 56
The supported diskette drive capacities and sizes Table 65, page 97
1.8.4 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel. The +5 V lines to these
connectors are protected with a thermistor, which limits the current to a specified amperage.
NOTE
✏
The keyboard and mouse will function in either PS/2 connector, but the connectors are colorcoded for ease of installation. Power to the computer should be turned off before a keyboard or
mouse is connected or disconnected.
The keyboard controller contains the AMI keyboard and mouse controller code, provides the
keyboard and mouse control functions, and supports password protection for power-on/reset. A
power-on/reset password can be specified in the BIOS Setup program.
The keyboard controller also supports the hot-key sequence <Ctrl><Alt><Del> for a software reset
(operating system dependent). This key sequence resets the computer’s software by jumping to the
beginning of the BIOS code and running the power-on self-test (POST).
The board contains a jumper block for enabling/disabling the Wake from PS/2 feature.
For information about Refer to
The location of the keyboard and mouse connectors Figure 7, page 46
The signal names of the keyboard and mouse connectors Table 19, page 47
Overcurrent protection for back panel connectors Table 18, page 47
The Wake from PS/2 jumper block Section 2.9, page 61
1.9 Graphics Subsystem
The 82815G GMCH features the following:
• Integrated graphics controller
3-D Hyperpipelined architecture
Full 2-D hardware acceleration
Motion video acceleration
• 3-D graphics visual and texturing enhancement
• Display
Integrated 24-bit 230 MHz RAMDAC
Display Data Channel Standard, Version 3.0, Level 2B protocols compliant
• Video
Hardware motion compensation for software MPEG2 decode
Software DVD at 30 fps
• Integrated graphics memory controller
26
Table 6 lists the refresh frequencies supported by the graphics subsystem.
D = DirectDraw
3 = Direct3D
O = Overlay
F = Digital Display Device only. A mode will be supported on both analog CRTs and digital
display devices (KD3O applies to both types of displays), unless indicated otherwise.
256 colors
†
†
and OpenGL†
Available Refresh
Frequencies (Hz)
60, 70, 72, 75 KD
Notes
For information about Refer to
Obtaining graphics software and utilities Section 1.2, page 16
28
1.10 Audio Subsystem
The D815EGEW board includes an Audio Codec ’97 (AC ’97) compatible audio subsystem
consisting of these devices:
• Intel 82801BA I/O Controller Hub (ICH2)
• Analog Devices AD1885 analog codec
1.10.1 AD1885 Audio Codec
The AD1885 is a fully AC ’97 compliant codec. The codec’s features include:
• > 85 dB signal-to-noise ratio sound quality
• Power management support for ACPI 1.0 (driver dependant)
• Playback sample rates up to 48 kHz
• 16 bit stereo full-duplex codec
• Software compatible with Windows 98 SE, Windows 2000, Windows NT 4.0,
Windows Millennium (Me), and Windows XP
• Full-duplex operation at asynchronous hardware record/playback samples rates
• Frequency response: 20 Hz to 20 kHz (± 0.1 dB)
Figure 4 is a block diagram of the D815EGEW board’s audio subsystem, including the
Intel 82801BA ICH2 digital controller, the AD1885 analog codec, and the audio connectors.
Product Description
Line In
82801BA
I/O Controller Hub
(ICH2)
AC ’97 Link
Analog Devices
AD1885
Analog Codec
Line Out
Mic In
Auxiliary Line In
CD-ROM
OM12985
Figure 4. Block Diagram of Audio Subsystem
For information about Refer to
Obtaining the AC ’97 specification Table 3, page 16
• ATAPI-style connectors:
CD-ROM
Auxiliary line in
• Back panel audio connectors:
Line in
Line out
1.10.2.1 ATAPI CD-ROM Connector
Mic in
For information about Refer to
The back panel audio connectors Section 2.8.1, page 46
A 1 x 4-pin ATAPI-style connector connects an internal ATAPI CD-ROM drive to the audio
mixer.
For information about Refer to
The location of the ATAPI CD-ROM connector Figure 8, page 51
The signal names of the ATAPI CD-ROM connector Table 29, page 52
1.10.2.2 Auxiliary Line In Connector
A 1 x 4-pin ATAPI-style connector connects the left and right channel signals of an internal audio
device to the audio subsystem.
For information about Refer to
The location of the auxiliary line in connector Figure 8, page 51
The signal names of the auxiliary line in connector Table 28, page 52
30
Product Description
1.11 LAN Subsystem (Optional)
The network interface controller subsystem consists of the ICH2, with integrated LAN Media
Access Controller (MAC), and a physical layer interface device. Features of the LAN subsystem
include:
• PCI Bus Master Interface
• CSMA/CD Protocol Engine
• Serial CSMA/CD unit interface that supports the 82562ET platform LAN connect device
• PCI Power Management
Supports ACPI technology
1.11.1 Intel® 82562ET Platform LAN Connect Device
Supports Wake up from suspend state (optional Wake on LAN technology)
For information about Refer to
Obtaining LAN software and drivers Section 1.2, page 16
The Intel 82562ET component provides an interface to the back panel RJ-45 connector with
integrated LEDs. This physical interface may alternately be provided through the CNR connector.
The Intel 82562ET provides the following functions:
• Basic 10/100 Ethernet LAN Connectivity
• Supports RJ-45 connector with status indicator LEDs
• Full driver compatibility
• Advanced Power Management support
• Programmable transit threshold
• Configuration EEPROM that contains the MAC address
1.11.2 RJ-45 LAN Connector LEDs
Two LEDs are built into the RJ-45 LAN connector. Table 7 describes the LED states when the
board is powered up and the LAN subsystem is operating.
Table 7. LAN Connector LED States
LED Color LED State Condition
Off 10 Mbit/sec data rate is selected. Green
On 100 Mbit/sec date rate is selected.
Yellow
Off LAN link is not established.
On (steady state) LAN link is established.
On (brighter and pulsing) The computer is communicating with another computer on
The I/O controller provides fan control output for the optional chassis fan (fan 2). Monitoring and
control can be implemented using third-party software.
For information about Refer to
The functions of the fan connectors Section 1.13.2.2, page 36
The location of the fan connectors Figure 8, page 51
The signal names of the fan connectors Section 2.8.2.2, page 51
1.13 Power Management
Power management is implemented at several levels, including:
• Software support through Advanced Configuration and Power Interface (ACPI)
• Hardware support:
Power connector
Fan connectors
Wake on LAN technology (optional)
Instantly Available technology
Resume on Ring
Wake from USB
Wake on Keyboard
Wake on PME#
1.13.1 ACPI
ACPI gives the operating system direct control over the power management and Plug and Play
functions of a computer. The use of ACPI with the D815EGEW board requires an operating
system that provides full ACPI support. ACPI features include:
• Plug and Play (including bus and device enumeration)
• Power management control of individual devices, add-in boards (some add-in boards may
require an ACPI-aware driver), video displays, and hard disk drives.
• Methods for achieving less than 15-watt system operation in the power-on/standby sleeping
state.
• A soft-off feature that enables the operating system to power-off the computer.
• Support for multiple wake up events (see Table 10 on page 34).
• Support for a front panel power and sleep mode switch. Table 8 lists the system states based
on how long the power switch is pressed, depending on how ACPI is configured with an
ACPI-aware operating system.
32
Product Description
Table 8. Effects of Pressing the Power Switch
If the system is in this state…
Off
(ACPI G2/G5 – soft-off)
On
(ACPI G0 – working state)
On
(ACPI G0 – working state)
Sleep
(ACPI G1 – sleeping state)
Sleep
(ACPI G1 – sleeping state)
…and the power switch is
pressed for
Less than seven seconds Power-on
Less than seven seconds Soft-off/Standby
More than seven seconds Fail safe power-off
Less than seven seconds Wake up
More than seven seconds Power-off
…the system enters this state
(ACPI G0 – working state)
(ACPI G1 – sleeping state)
(ACPI G2/G5 – soft-off)
(ACPI G0 – working state)
(ACPI G2/G5 – soft-off)
For information about Refer to
The D815EGEW board’s compliance level with ACPI Table 3, page 17
1.13.1.1.1 System States and Power States
Under ACPI, the operating system directs all system and device power state transitions. The
operating system puts devices in and out of low-power states based on user preferences and
knowledge of how devices are being used by applications. Devices that are not being used can be
turned off. The operating system uses information from applications and user settings to put the
system as a whole into a low-power state.
Table 9 lists the power states supported by the D815EGEW board along with the associated system
power targets. See the ACPI specification for a complete description of the various system and
power states.
1. Total system power is dependent on the system configuration, including add-in boards and peripherals
powered by the system chassis’ power supply.
2. Dependent on the standby power consumption of wake-up devices used in the system.
CPU States Device States
state
D1, D2, D3 –
grant
device
specification
specific.
No power D3 – no power
except for wake
up logic.
No power D3 – no power
except for wake
up logic.
No power D3 – no power for
wake up logic,
except when
provided by
battery or external
source.
Targeted System Power
(Note 1)
Full power > 30 W
5 W < power < 30 W
Power < 5 W
Power < 5 W
(Note 2)
(Note 2)
No power to the system so
that service can be
performed.
1.13.1.1.2 Wake Up Devices and Events
Table 10 lists the devices or specific events that can wake the computer from specific states.
Table 10. Wake Up Devices and Events
These devices/events can wake up the computer… …from this state
Power switch S1, S3, S5
RTC alarm S1, S3, S5
Wake on LAN technology connector (optional) S1, S3, S5
PME# S1, S3, S5
Modem (back panel serial port A) S1, S3
(Notes 3 and 4)
USB
PS/2 keyboard
Notes:
1. S5 events are supported only on PCI bus connector 2.
2. For the Wake on LAN technology connector and PME#, S5 is disabled by default in the BIOS Setup program. Setting
these options to Power On will enable a wake-up event from LAN in the S5 state.
3. Wake from USB requires the use of a USB peripheral that supports Wake from USB.
4. To enable Wake from USB, set the Wake from USB jumper to enabled and set ACPI Suspend State option to S3 in
the ACPI Submenu.
5. To enable Wake from PS/2, set the Wake from PS/2 jumper to enabled and set ACPI Suspend State option to S3 in
the ACPI Submenu.
S1, S3
(Note 5)
S1, S3
(Note 1)
(Notes 1 and 2)
(Notes 1 and 2)
34
Product Description
For information about Refer to
The Wake from USB and Wake from PS/2 jumper blocks Section 2.9, page 61
The ACPI Submenu in the BIOS Setup program Section 4.6.1, page 102
NOTE
✏
The use of these wake up events from an ACPI state requires an operating system that provides full
ACPI support. In addition, software, drivers, and peripherals must fully support ACPI wake
events.
NOTE
✏
Wake up from PS/2 mouse is peripheral, operating system, and driver dependent.
1.13.1.1.3 Plug and Play
In addition to power management, ACPI provides controls and information so that the operating
system can facilitate Plug and Play device enumeration and configuration. ACPI is used only to
enumerate and configure D815EGEW board devices that do not have other hardware standards for
enumeration and configuration. PCI devices on the D815EGEW board, for example, are not
enumerated by ACPI.
1.13.2 Hardware Support
CAUTION
If the Wake on LAN and Instantly Available technology features are used, ensure that the power
supply provides adequate +5 V standby current. Failure to do so can damage the power supply.
The total amount of standby current required depends on the wake devices supported and
manufacturing options. Refer to Section 2.11.3 on page 68 for additional information.
The boards provides several hardware features that support power management, including:
• Power connector
• Fan connectors
• Wake on LAN technology connector (optional)
• Instantly Available technology
• Resume on Ring
• Wake from USB
• Wake from PS/2 keyboard
• PME# wakeup support
Wake on LAN technology and Instantly Available technology require power from the +5 V
standby line. The sections discussing these features describe the incremental standby power
requirements for each.
Resume on Ring enables telephony devices to access the computer when it is in a power-managed
state. The method used depends on the type of telephony device (external or internal).
The use of Resume on Ring and Wake from USB technologies from an ACPI state requires an
operating system that provides full ACPI support.
1.13.2.1 Power Connector
When used with an ATX-compliant power supply that supports remote power on/off, the
D815EGEW board can turn off the system power through software control. To enable soft-off
control in software, power management must be enabled in the BIOS Setup program and in the
operating system. When the system BIOS receives the correct command from the operating
system, the BIOS turns off power to the computer.
With soft-off enabled, if power to the computer is interrupted by a power outage or a disconnected
power cord, when power resumes, the computer returns to the power state it was in before power
was interrupted (on or off). The computer’s response can be set using the After Power Failure
feature in the BIOS Setup program’s Power menu.
For information about Refer to
The location of the power connector Figure 8, page 51
The signal names of the power connector Table 31, page 52
The BIOS Setup program’s Power menu Section 4.6, page 101
The ATX specification Table 3, page 17
1.13.2.2 Fan Connectors
The D815EGEW board has two fan connectors. The functions of these connectors are described in
Table 11.
Table 11. Fan Connector Descriptions
Connector Function
Processor fan (fan 1) Provides +12 V DC for a processor fan or active fan heatsink.
Optional chassis fan
(fan 2)
Provides +12 V DC for a system or chassis fan. The fan voltage can be switched
on or off, depending on the power management state of the computer.
For information about Refer to
The location of the fan connectors Figure 8, page 51
The signal names of the fan connectors Section 2.8.2.2, page 51
1.13.2.3 Wake on LAN Technology (Optional)
CAUTION
For Wake on LAN technology, the +5 V standby line for the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
implementing Wake on LAN technology can damage the power supply. Refer to Section 2.11.3 on
page 68 for additional information.
36
Product Description
NOTE
✏
The Wake on LAN technology connector is present only on boards that do not have the Intel
82562ET PLC device, which is part of the optional onboard LAN subsystem.
Wake on LAN technology enables remote wakeup of the computer through a network. The LAN
subsystem PCI bus network adapter monitors network traffic at the Media Independent Interface.
†
Upon detecting a Magic Packet
frame, the LAN subsystem asserts a wakeup signal that powers up
the computer. Depending on the LAN implementation, the D815EGEW board supports Wake on
LAN technology in the following ways:
• Through the Wake on LAN technology connector
• Through the PCI bus PME# signal for PCI 2.2 compliant LAN designs (ACPI only)
• Through the onboard LAN subsystem when enabled in Setup (ACPI only)
The optional Wake on LAN technology connector can be used with PCI bus network adapters that
have a remote wake up connector, as shown in Figure 5. Network adapters that are PCI 2.2
compliant assert the wakeup signal through the PCI bus signal PME# (pin A19 on the PCI bus
connectors).
Network
Interface
Card
PCI Slot
Figure 5. Using the Wake on LAN Technology Connector
For information about Refer to
The location of the optional Wake on LAN technology connector Figure 8, page 51
The signal names of the optional Wake on LAN technology connector Table 32, page 53
Remote
Wake up
connector
Desktop Board
Wake on
LAN
technology
connector
OM09129
1.13.2.4 Instantly Available Technology
CAUTION
For Instantly Available technology, the +5 V standby line for the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
implementing Instantly Available technology can damage the power supply. Refer to
Section 2.11.3 on page 68 for additional information.
Instantly Available technology enables the D815EGEW board to enter the ACPI S3 (suspend-toRAM) sleep-state. While in the S3 sleep-state, the computer will appear to be off (the power
supply is off, the fans are off, and the front panel LED is amber if dual-color, or off if single-
color.) When signaled by a wake-up device or event, the system quickly returns to its last known
wake state.
The D815EGEW board supports the PCI Bus Power Management Interface Specification. Add-in
boards that also support this specification can participate in power management and can be used to
wake the computer.
The use of Instantly Available technology requires operating system support and PCI 2.2
compliant add-in cards and drivers.
The optional standby power indicator LED shows that power is still present at the DIMM and PCI
bus connectors, even when the computer appears to be off. Figure 6 shows the location of the
optional standby power indicator LED on the D815EGEW.
CR6E1
Figure 6. Location of the Optional Standby Power Indicator LED
For information about Refer to
The devices and events that can wake the computer from the S3 state Table 10, page 34
The PCI Bus Power Management Interface SpecificationTable 3, page 17
1.13.2.5 Resume on Ring
The operation of Resume on Ring can be summarized as follows:
• Resumes operation from the ACPI S1 state
• Requires only one call to access the computer
• Detects incoming call similarly for external and internal modems
• Requires modem interrupt be unmasked for correct operation
Sections 2.2 - 2.6 contain several standalone tables. Table 12 describes the system memory map,
Table 13 shows the I/O map, Table 14 lists the DMA channels, Table 15 defines the PCI
configuration space map, and Table 16 describes the interrupts. The remaining sections in this
chapter are introduced by text found with their respective section headings.
2.2 Memory Map
Table 12. System Memory Map
Address Range (decimal) Address Range (hex) Size Description
1024 K - 524288 K 100000 - 1FFFFFFF 511 MB Extended memory
960 K - 1024 K F0000 - FFFFF 64 KB Runtime BIOS
896 K - 960 K E0000 - EFFFF 64 KB Reserved
800 K - 896 K C8000 - DFFFF 96 KB Available high DOS memory (open
to the PCI bus)
640 K - 800 K A0000 - C7FFF 160 KB Video memory and BIOS
639 K - 640 K 9FC00 - 9FFFF 1 KB Extended BIOS data (movable by
memory manager software)
512 K - 639 K 80000 - 9FBFF 127 KB Extended conventional memory
0 K - 512 K 00000 - 7FFFF 512 K Conventional memory
12 Onboard mouse port (if present, else user available)
13 Reserved, math coprocessor
14 Primary IDE (if present, else user available)
15 Secondary IDE (if present, else user available)
Note: Default, but can be changed to another IRQ.
(Note)
(Note)
(Note)
Technical Reference
2.7 PCI Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected between the
PCI bus connectors and onboard PCI devices. The PCI specification specifies how interrupts can
be shared between devices attached to the PCI bus. In most cases, the small amount of latency
added by interrupt sharing does not affect the operation or throughput of the devices. In some
special cases where maximum performance is needed from a device, a PCI device should not share
an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt
with a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
• INTA: By default, all add-in cards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
• INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is
classified as INTB. (This is not an absolute requirement.)
• INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a
The ICH2 has eight programmable interrupt request (PIRQ) input signals. All PCI interrupt
sources either onboard or from a PCI add-in card connect to one of these PIRQ signals. Some PCI
interrupt sources are electrically tied together on the D815EGEW board and therefore share the
same interrupt. Table 17 shows an example of how the PIRQ signals are routed on the
D815EGEW board.
For example, using Table 17 as a reference, assume that an add-in card using INTA is plugged into
PCI bus connector 3. In PCI bus connector 3, INTA is connected to PIRQH. The add-in card in
PCI bus connector 3 now shares interrupts with these onboard interrupt sources.
Table 17. PCI Interrupt Routing Map
PCI Interrupt Source
GMCH INTB INTA to PIRQA
ICH2 USB controller #1 INTD to PIRQD
SMBus controller INTB
ICH2 audio/modem INTB
ICH2 LAN INTA to PIRQE
PCI bus connector 1 INTA INTB INTC INTD
PCI bus connector 2 INTD INTA INTB INTC
PCI bus connector 3 INTC INTD INTA INTB
PCI bus connector 4 INTB INTC INTD INTA
PIRQF PIRQG PIRQH PIRQB Other
ICH PIRQ Signal Name
✏ NOTE
The ICH2 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 10, 11, 12,
14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt.
However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ
lines to be connected to the same IRQ signal.
44
Technical Reference
2.8 Connectors
CAUTION
Only the back panel connectors of the D815EGEW board have overcurrent protection. The
board’s internal connectors are not overcurrent protected and should connect only to devices
inside the computer’s chassis, such as fans and internal peripherals. Do not use these connectors
to power devices external to the computer’s chassis. A fault in the load presented by an external
device may result in a high output current that could damage the board, the interconnecting cable,
and the external device itself.
For information about Refer to
Overcurrent protection for the board’s back panel connectors Table 18, page 47
This section describes the board’s connectors. The connectors can be divided into the following
groups:
• Back panel I/O connectors (see page 46)
PS/2 keyboard and mouse
USB (two)
VGA
Parallel port
Serial port A
LAN (optional)
Audio (line in, line out, and mic in)
• Internal I/O connectors (see page 50)
Audio (auxiliary line input and ATAPI CD-ROM)
Fans (two)
Power
Wake on LAN technology (optional)
Add-in boards (four PCI bus connectors)
IDE (two)
Diskette drive
• External I/O connectors (see page 58)
SCSI LED (optional)
Front panel (power/sleep/message waiting LED, power switch, hard drive activity LED,
Figure 7 shows the location of the back panel connectors on the D815EGEW board. The back
panel connectors are color-coded in compliance with PC 99 recommendations. The figure legend
below lists the colors used.
A
C
F
HBIJEGD
OM12804
Item Description Color For more information see:
A PS/2 mouse port Green Table 19
B PS/2 keyboard port Purple Table 19
C LAN (optional) Black Table 24
D USB ports Black Table 20
E VGA port Dark blue Table 21
F Parallel port Burgundy Table 22
G Serial port A Teal Table 23
H Audio line out Lime green Table 26
I Audio line in Light blue Table 27
J Mic in Pink Table 25
Figure 7. Back Panel Connectors
46
Technical Reference
✏ NOTE
The back panel audio line out connector is designed to power headphones or amplified speakers
only. Poor audio quality occurs if passive (non-amplified) speakers are connected to this output.
Table 18 lists the overcurrent protection for the D815EGEW board. Overcurrent protection is
provided to the board’s back panel connectors through thermistors.
Table 18. Overcurrent Protection for Back Panel Connectors
Connectors Maximum Current
PS/2 keyboard and mouse 1.5 A (total for both ports combined)
USB back panel 1.5 A (total for both ports combined)
The internal I/O connectors are divided into the following functional groups:
• Audio, power, and hardware control (see page 51)
Auxiliary line in
ATAPI CD-ROM
Fans (two)
Power
Wake on LAN technology (optional)
• Add-in boards and peripheral interfaces (see page 54)
PCI bus (four)
IDE (two)
Diskette drive
2.8.2.1 Expansion Slots
The board has four PCI Local Bus connectors (compliant with PCI Rev. 2.2 specification). The
SMBus is routed to PCI bus connector 2 (expansion slot 5). PCI add-in cards with SMBus support
can access sensor data and other information residing on the desktop board.
✏ NOTE
This document refers to back-panel slot numbering with respect to processor location on the
desktop board. PCI slots are identified as “PCI slot #x”, starting with the slot closest to the
processor.
The ATX/microATX specifications identify expansion slot locations with respect to the far edge of a
full-sized ATX chassis. The ATX specification and the board’s silkscreen are opposite and could
cause confusion. The ATX numbering convention is made without respect to slot type but refers to
an actual connector location on a chassis. Figure 9 on page 54 illustrates the board’s PCI
connector numbering.
50
2.8.2.2 Audio, Video, Power, and Hardware Control Connectors
Figure 8 shows the location of the audio, power, and hardware control connectors on the
D815EGEW boards.
Technical Reference
BA
1
4
1
1
1
1
1
11
10
20
C
1
E
F
G
D
OM12805
Item Description Color For more information see:
A Auxiliary line in, ATAPI style White Table 28
B ATAPI CD-ROM Black Table 29
C Processor fan (fan 1) N/A Table 30
D Power N/A Table 31
E Wake on LAN technology (optional) N/A Table 32
F System fan (optional) N/A Table 33
G Chassis Intrusion (optional) N/A Table 34
Figure 8. Audio, Hardware Control, and Fan Connectors
2.8.2.3 Add-in Board and Peripheral Interface Connectors
Figure 9 shows the location of the add-in board connectors and peripheral interface connectors on
the D815EGEW board. Note the following considerations for the PCI bus connectors:
• All of the PCI bus connectors are bus master capable.
• PCI bus connector 2 is S5 wake enabled.
• PCI bus connector 2 has SMBus signals routed to it. This enables PCI bus add-in boards with
SMBus support to access sensor data on the board. The specific SMBus signals are as follows:
The SMBus clock line is connected to pin A40
The SMBus data line is connected to pin A41
ABCD
2
1
2
1
1
2
1
34
33
40
39
40
39
GEFH
Item Description For more information see:
A PCI bus connector 4
35
B PCI bus connector 3 Table 35
C PCI bus connector 2 Table 35
D PCI bus connector 1 Table 35
E Diskette drive Table 36
F Primary IDE Table 37
G Secondary IDE Table 37
H SCSI LED (optional) Table 38
Figure 9. Add-in Board and Peripheral Interface Connectors
OM12806
54
Technical Reference
Table 35. PCI Bus Connectors
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A1 Ground (TRST#)* B1 -12 V A32 AD16 B32 AD17
A2 +12 V B2 Ground (TCK)* A33 +3.3 V B33 C/BE2#
A3 +5 V (TMS)* B3 Ground A34 FRAME# B34 Ground
A4 +5 V (TDI)* B4 Not connected (TDO)* A35 Ground B35 IRDY#
A5 +5 V B5 +5 V A36 TRDY# B36 +3.3 V
A6 INTA# B6 +5 V A37 Ground B37 DEVSEL#
A7 INTC# B7 INTB# A38 STOP# B38 Ground
A8 +5 V B8 INTD# A39 +3.3 V B39 LOCK#
A9 Reserved B9 Not connected
(PRSNT1#)*
A10 +5 V (I/O) B10 Reserved A41 Reserved *** B41 +3.3 V
A11 Reserved B11 Not connected
(PRSNT2#)*
A12 Ground B12 Ground A43 PAR B43 +3.3 V
A13 Ground B13 Ground A44 AD15 B44 C/BE1#
A14 +3.3 V aux **** B14 Reserved A45 +3.3 V B45 AD14
A15 RST# B15 Ground A46 AD13 B46 Ground
A16 +5 V (I/O) B16 CLK A47 AD11 B47 AD12
A17 GNT# B17 Ground A48 Ground B48 AD10
A18 Ground B18 REQ# A49 AD09 B49 Ground
A19 PME# B19 +5 V (I/O) A50 Key B50 Key
A20 AD30 B20 AD31 A51 Key B51 Key
A21 +3.3 V B21 AD29 A52 C/BE0# B52 AD08
A22 AD28 B22 Ground A53 +3.3 V B53 AD07
A23 AD26 B23 AD27 A54 AD06 B54 +3.3 V
A24 Ground B24 AD25 A55 AD04 B55 AD05
A25 AD24 B25 +3.3 V A56 Ground B56 AD03
A26 IDSEL B26 C/BE3# A57 AD02 B57 Ground
A27 +3.3 V B27 AD23 A58 AD00 B58 AD01
A28 AD22 B28 Ground A59 +5 V (I/O) B59 +5 V (I/O)
A29 AD20 B29 AD21 A60 REQ64C# B60 ACK64C#
A30 Ground B30 AD19 A61 +5 V B61 +5 V
A31 AD18 B31 +3.3 V A62 +5 V B62 +5 V
Notes: These signals (in parentheses) are optional in the PCI specification and are not currently implemented.
** On PCI bus connector 2, this pin is connected to the SMBus clock line.
*** On PCI bus connector 2, this pin is connected to the SMBus data line.
**** During S5 state, this pin is active only on PCI bus connector 2.
17 Not connected 18 FDDIR# (Stepper Motor Direction)
19 Ground 20 FDSTEP# (Step Pulse)
21 Ground 22 FDWD# (Write Data)
23 Ground 24 FDWE# (Write Enable)
25 Ground 26 FDTRK0# (Track 0)
27 Not connected 28 FDWPD# (Write Protect)
29 Ground 30 FDRDATA# (Read Data)
31 Ground 32 FDHEAD# (Side 1 Select)
33 Ground 34 DSKCHG# (Diskette Change)
Table 37. IDE Connectors
Pin Signal Name Pin Signal Name
1 Reset IDE 2 Ground
3 Data 7 4 Data 8
5 Data 6 6 Data 9
7 Data 5 8 Data 10
9 Data 4 10 Data 11
11 Data 3 12 Data 12
13 Data 2 14 Data 13
15 Data 1 16 Data 14
17 Data 0 18 Data 15
19 Ground 20 Key
21 DDRQ0 [DDRQ1] 22 Ground
23 I/O Write# 24 Ground
25 I/O Read# 26 Ground
27 IOCHRDY 28 Ground
29 DDACK0# [DDACK1#] 30 Ground
31 IRQ 14 [IRQ 15] 32 Reserved
33 DAG1 (Address 1) 34 GPIO_DMA66_Detect_Pri (GPIO_DMA66_Detect_Sec)
35 DAG0 (Address 0) 36 DAG2 (Address 2)
37 Chip Select 1P# [Chip Select 1S#] 38 Chip Select 3P# [Chip Select 3S#]
39 Activity# 40 Ground
Note: Signal names in brackets ([ ]) are for the secondary IDE connector.
56
Technical Reference
2.8.2.4 SCSI Hard Drive Activity LED Connector (Optional)
The optional SCSI hard drive activity LED connector is a 1 x 3-pin connector that allows add-in
SCSI host bus adapter to use the same LED as the IDE controller. This connector can be
connected to the LED output of the add-in controller card. The LED will indicate when data is
being read or written using the add-in controller. Table 38 lists the signal names of the SCSI hard
drive activity LED connector.
Figure 10 shows the locations of the external I/O connectors on the D815EGEW board.
A
1
15
1
2
16
B
Item Description For more information see:
A Auxiliary front panel power LED Table 39
B Front panel Table 40
Figure 10. External I/O Connectors
2.8.3.1 Auxiliary Front Panel Power LED Connector
This connector duplicates the signals on pins 2 and 4 of the front panel connector.
Table 39. Auxiliary Front Panel Power LED Connector
Pin Signal Name In/Out Description
1 HDR_BLNK_GRN Out Front panel green LED
2 Not connected
3 HDR_BLNK_YEL Out Front panel yellow LED
OM12807
58
Technical Reference
2.8.3.2 Front Panel Connector
This section describes the functions of the front panel connector. Table 40 lists the signal names
of the front panel connector.
Table 40. Front Panel Connector
Pin Signal In/Out Description Pin Signal In/Out Description
1 HD_PWR Out Hard disk LED pull-
up (330 Ω) to +5 V
3 I# Out Hard disk activity
LED
5 GND Ground 6 FPBUT_IN In Power switch
7 FP_RESET# In Reset switch 8 GND Ground
9 +5 V Out Power 10 N/C Not connected
11 Reserved Not connected 12 GND Ground
13 GND Ground 14 (pin removed) Not connected
15 Reserved Not connected 16 +5 V Out Power
2 HDR_BLNK_
GRN
4 HDR_BLNK_
YEL
Out Front panel green
LED
Out Front panel yellow
LED
2.8.3.2.1 Reset Switch Connector
Pins 5 and 7 can be connected to a momentary SPST type switch that is normally open. When the
switch is closed, the D815EGEW board resets and runs the POST.
2.8.3.2.2 Hard Drive Activity LED Connector
Pins 1 and 3 can be connected to an LED to provide a visual indicator that data is being read from
or written to a hard drive. For the LED to function properly, an IDE drive must be connected to
the onboard IDE interface. The LED will also show activity for devices connected to the SCSI
hard drive activity LED connector.
For information about Refer to
The optional SCSI hard drive activity LED connector Section 2.8.2.4, page 57
2.8.3.2.3 Power/Sleep/Message Waiting LED Connector
Pins 2 and 4 can be connected to a single-colored or dual-colored LED. Table 41 shows the
possible states for a single-colored LED. Table 42 shows the possible states for a dual-colored
LED.
To use the message waiting function, ACPI must be enabled in the operating system and a
message-capturing application must be invoked.
2.8.3.2.4 Power Switch Connector
Pins 6 and 8 can be connected to a front panel momentary-contact power switch. The switch must
pull the SW_ON# pin to ground for at least 50 ms to signal the power supply to switch on or off.
(The time requirement is due to internal debounce circuitry on the D815EGEW board.) At least
two seconds must pass before the power supply will recognize another on/off signal.
60
2.9 Jumper Blocks
CAUTION
Do not move any jumpers with the power on. Always turn off the power and unplug the power
cord from the computer before changing a jumper setting. Otherwise, the board could be
damaged.
Figure 11 shows the location of the jumper blocks on the D815EGEW board.
This jumper block enables/disables Wake from PS/2 devices (PS/2 mouse and keyboard). Table
43 describes the settings of this jumper block. To enable Wake from PS/2, set the Wake from PS/2
jumper to enabled and set ACPI Suspend State option to S3 in the ACPI Submenu.
Table 43. Wake from PS/2 Jumper Settings (J2B1)
Mode Jumper Setting Description
Wake from PS/2 disabled
1-2
Wake from PS/2 enabled
2-3
1
1
For information about Refer to
The ACPI Submenu in the BIOS Setup program Section 4.6.1, page 102
PS/2 devices always powered by VCC (+5 VDC).
3
PS/2 devices always powered by +5 V standby.
3
CAUTION
If Wake from PS/2 is enabled, ensure that the power supply can provide enough standby current to
power PS/2 devices when the computer is in the S0 (working) and S1 (CPU stopped) states.
Failure to do so could result in damage to the power supply.
2.9.2 Wake from USB Jumper Block
This jumper block enables/disables Wake from USB devices. Table 44 describes the settings of
this jumper block. To enable Wake from USB, set the Wake from USB jumper to enabled and set
ACPI Suspend State option to S3 in the ACPI Submenu.
Table 44. Wake from USB Jumper Settings (J2B2)
Mode Jumper Setting Description
Wake from USB disabled
1-2
Wake from USB enabled
2-3
1
1
For information about Refer to
The ACPI Submenu in the BIOS Setup program Section 4.6.1, page 102
USB devices always powered by VCC (+5 VDC).
3
USB devices always powered by +5 V standby.
3
CAUTION
If Wake from USB is enabled, ensure that the power supply can provide enough standby current to
power USB devices when the computer is in the S0 (working) and S1 (CPU stopped) states.
Failure to do so could result in damage to the power supply.
62
Technical Reference
2.9.3 BIOS Setup Configuration Jumper Block
This 3-pin jumper block determines the BIOS Setup program’s mode. Table 45 describes the
jumper settings for the three modes: normal, configure, and recovery. When the jumper is set to
configure mode and the computer is powered-up, the BIOS compares the CPU version and the
microcode version in the BIOS and reports if the two match.
The D815EGEW board is designed to fit into a standard microATX-form-factor chassis. Figure 12
illustrates the mechanical form factor for the D815EGEW board. Dimensions are given in inches
[millimeters]. The outer dimensions are 9.20 inches by 7.65 inches [233.68 millimeters by 194.31
millimeters]. Location of the I/O connectors and mounting holes are in compliance with the
microATX specification (see Section 1.3).
6.50[165.10]
6.10[154.94]
5.20[132.08]
0.00
1.15[29.21]
0.95[24.13]
0.00
1.80
[82.30]
Figure 12. Board Dimensions
8.00
[203.20]
8.250[209.55]
OM12809
64
Technical Reference
2.10.2 I/O Shields
The back panel I/O shield for the D815EGEW board must meet specific dimension and material
requirements. Systems based on this board need the back panel I/O shield to pass emissions (EMI)
certification testing. Figure 13 and Figure 14 show the critical dimensions of the chassisdependent I/O shield. Dimensions are given in inches [millimeters], to a tolerance of ± 0.020
inches [0.508 millimeters]. These figures also indicate the position of each cutout. Additional
design considerations for I/O shields relative to chassis requirements are described in the ATX
specification.
For information about Refer to
The ATX specification Table 3, page 16
The microATX specification Table 3, page 16
✏ NOTE
An I/O shield compliant with the ATX chassis specification 2.01 is available from Intel.
REF
6.390
[162.30]
0.061
[1.55]
[22.45]
0.280
[7.10]
0.000
[0.00]
0.450
[11.43]
[14.43]
[14.43]
0.884
[22.45]
REF
0.884
0.472
0.568
0.000
[0.00]
0.020 MAX
[0.50]
0.442
[11.22]
0.787 TYP
[20.00]
1.189
[30.20]
2.071
1.799
[45.68]
[52.60]
6.268
[159.20]
3.215
[81.65]
4.783
[121.50]
5.276
[134.00]
5.768
[146.501]
Pictorial
View
8X R0.020 MIN
3X 0.335
0.465
[11.80]
[8.50]
[8.50]
(for D815EGEW Boards without Onboard LAN Subsystem)
Table 46 lists voltage and current measurements for a computer that contains the D815EGEW
board and the following:
• 1.20 GHz Intel Pentium III processor with a 256 KB cache and a 133 MHz system bus
frequency
• 256 MB SDRAM
• 3.5-inch diskette drive
• 4.3 GB ATA-33 IDE hard disk drive
• IDE CD-ROM drive
This information is provided only as a guide for calculating approximate power usage with
additional resources added.
Values for the Windows 98 ME desktop mode are measured at 640 x 480 x 256 colors and 60 Hz
refresh rate. AC watts are measured with the computer is connected to a typical 200 W power
supply, at nominal input voltage and frequency, with a true RMS wattmeter at the line input.
✏ NOTE
Actual system power consumption depends upon system configuration. The power supply should
comply with the recommendations found in the ATX Form Factor Specification document (see
Table 3 on page 17 for specification information).
Table 46 lists the power usage for a D815EGEW board with the configuration listed above and
including the optional onboard LAN subsystem. Table 47 lists the S3 state standby current values.
Table 46. Power Usage for a D815EGEW Board
DC Current at:
Mode AC Power +3.3 V +5 V +12 V -12 V +5 V (standby)
Windows 98 SE ACPI S0 50 W 2.46 A 2.79 A 0.26 A 0 A
Windows 98 SE ACPI S1 45 W 2.34 A 2.74 A 0.26 A 0 A
Windows 98 SE ACPI S3 3 W 0 A 0 A 0 A 0 A
Windows 98 SE ACPI S5 3 W 0 A 0 A 0 A 0 A
Table 47. S3 State Standby Current
Configuration
USB and PS/2 powered by VCC No No 1013 mA 1664 mA
USB powered by +5V standby Yes No 1018 mA 2172 mA
PS/2 powered by +5V standby No Yes 1313 mA 2009 mA
USB and PS/2 powered by +5V standby Yes Yes 1318 mA 2517 mA
Wake from USB
enabled?
Wake from PS/2
enabled?
Dependent on S3
support
configuration.
Refer to Table 47
for values.
The D815EGEW board is designed to provide 2 A (average) of +5 V current for each add-in board.
The total +5 V current draw for add-in boards in a fully-loaded D815EGEW board (all four
expansion slots filled) must not exceed 8 A.
2.11.3 Standby Current Requirements
CAUTION
Power supplies used with the board must provide enough standby current to support the Instantly
Available (ACPI S3 sleep state) configuration. If the standby current necessary to support
multiple wake events from the PCI and/or USB buses exceeds power supply capacity, the board
may lose register settings stored in memory and may not awaken properly.
To estimate the standby current required for a specific system configuration, the standby current
requirements of all installed components must be combined. Refer to Table 48 and follow these
steps:
1. List the board’s +5 V standby current requirement (see Table 47).
2. List the PS/2 ports’ standby current requirement (see Table 48).
3. List, from the PCI 2.2 slots (wake-enabled devices) row, the total number of wake-enabled
devices installed and multiply by the standby current requirement.
4. List, from the PCI 2.2 slots (non-wake-enabled devices) row, the total number of wake-enabled
devices installed and multiply by the standby current requirement.
5. List all additional wake-enabled devices’ and non-wake-enabled devices’ standby current
requirements as applicable.
6. Add all the listed standby current totals from steps 1 through 5 to determine the total estimated
standby current power supply requirement.
Table 48. Standby Current Requirements
Description Standby Current Requirements (mA)
Total for the board Dependent on S3 support configuration. Refer
to Table 47 for appropriate value.
Onboard LAN (optional) 95
Wake on LAN technology connector (optional)
connected to wake-enabled PCI LAN card
PS/2 ports
PCI 2.2 slots (wake-enabled devices)
PCI 2.2 slots (non-wake-enabled devices)
USB ports
Notes:
1. These values were measured in a power static state.
2. Dependent upon system configuration. See the note on the following page.
(Note 2)
345
(Note 2)
470
(Note 2)
115
(Note 2)
507.5
525
(Note 1)
68
Technical Reference
NOTE
✏
PCI requirements are calculated by totaling the following:
• One wake-enabled device @ 375 mA
• Three non-wake-enabled devices @ 20 mA each
PS/2 Ports requirements per the IBM PS/2 Port Specification (Sept 1991):
• Keyboard @ 275 mA (Actual measurements are 220 mA-300 mA, depending on the type of
keyboard and the operational state of the keyboard’s LEDs.)
• Mouse @ 70 mA
USB requirements are calculated by totaling the following:
• One wake-enabled device @ 500 mA
• Two USB non-wake-enabled devices @ 2.5 mA each
The USB ports are limited to a combined total of 700 mA.
2.11.4 Fan Connector Current Capability
The D815EGEW board is designed to supply a maximum of 225 mA per fan connector.
2.11.5 Power Supply Considerations
CAUTION
The +5 V standby line for the power supply must be capable of providing adequate +5 V standby
current. Failure to do so can damage the power supply. The total amount of standby current
required depends on the wake devices supported and manufacturing options. Refer to
Section 2.11.3 on page 68 for additional information.
System integrators should refer to the power usage values listed in Section 2.11.1, on page 67
when selecting a power supply for use with the D815EGEW board.
Measurements account only for current sourced by the D815EGEW board while running in idle
modes of the started operating systems.
Additional power required will depend on configurations chosen by the integrator.
The power supply must comply with the following recommendations found in the indicated
sections of the ATX form factor specification.
• The potential relation between 3.3 VDC and +5 VDC power rails (Section 4.2)
• The current capability of the +5 VSB line (Section 4.2.1.2)
• All timing parameters (Section 4.2.1.3)
• All voltage tolerances (Section 4.2.2)
For information about Refer to
The ATX form factor specification Table 3, page 17
An ambient temperature that exceeds the board’s maximum operating temperature by 10 oC could
cause components to exceed their maximum case temperature and malfunction. For information
about the maximum operating temperature, see the environmental specifications in Section 2.14.
CAUTION
The processor voltage regulator area (item A in Figure 15) can reach a temperature of up to 85 oC
in an open chassis. System integrators should ensure that proper airflow is maintained in the
voltage regulator circuit. Failure to do so may result in damage to the voltage regulator circuit.
Figure 15 shows the locations of the localized high temperature zones for the D815EGEW board.
D
A Processor voltage regulator area
B Processor
Intel 82815G Graphics and Memory Controller Hub (GMCH)
C
D Intel 82801BA ICH2
Figure 15. Localized High Temperature Zones
OM12810
A
B
C
70
Technical Reference
Table 49 provides maximum case temperatures for D815EGEW board components that are
sensitive to thermal changes. The operating temperature, current load, or operating frequency
could affect case temperatures. Maximum case temperatures are important when considering
proper airflow to cool the D815EGEW board.
Table 49. Thermal Considerations for Components
Component Maximum Case Temperature
Intel Pentium III processor
Intel Celeron processor
Intel 82815G GMCH 116 oC (under bias)
Intel 82801BA ICH2 109 oC (under bias)
For processor case temperature, see processor datasheets and
processor specification updates
For information about Refer to
Intel Pentium III processor datasheets and specification updates Section 1.2, page 16
The mean time between failures (MTBF) prediction is calculated using component and
subassembly random failure rates. The calculation is based on the Bellcore Reliability Prediction
Procedure, TR-NWT-000332, Issue 4, September 1991. The MTBF prediction is used to estimate
repair rates and spare parts requirements.
The Mean Time Between Failures (MTBF) data is calculated from predicted data at 35 ºC.
The D815EGEW desktop boards has the following product certification markings:
• UL joint US/Canada Recognized Component mark: Consists of small c followed by a stylized
backward UR and followed by a small US. Includes adjacent UL file number for Intel desktop
boards: E210882 (component side).
• FCC Declaration of Conformity logo mark for Class B equipment; to include Intel name and
D815EGEW model designation (solder side).
• CE mark: Declaring compliance to European Union (EU) EMC directive (89/336/EEC) and
Low Voltage directive (73/23/EEC) (component side). The CE mark should also be on the
shipping container.
• Australian Communications Authority (ACA) C-Tick mark: consists of a stylized C overlaid
with a check (tick) mark (component side), followed by Intel supplier code number, N-232.
The C-tick mark should also be on the shipping container.
• Korean EMC certification logo mark: consists of MIC lettering within a stylized elliptical
outline.
• Printed wiring board manufacturer’s recognition mark: consists of a unique UL recognized
manufacturer’s logo, along with a flammability rating (94V-0) (solder side).
• PB part number: Intel bare circuit board part number (solder side). Also includes SKU
number starting with AA followed by additional alphanumeric characters. For boards without
the onboard LAN subsystem , the PB number is A69778-001. For boards with the onboard
LAN subsystem, the PB number is A73693-001.
• Battery “+ Side Up” marking: located on the component side of the board in close proximity
to the battery holder.
The D815EGEW boards uses an Intel/AMI BIOS, which is stored in flash memory and can be
updated using a disk-based program. In addition to the BIOS, the flash memory contains the BIOS
Setup program, POST, the PCI auto-configuration utility, and Plug and Play support.
The D815EGEW board supports system BIOS shadowing, allowing the BIOS to execute from
64-bit onboard write-protected DRAM.
The BIOS displays a message during POST identifying the type of BIOS and a revision code. The
initial production BIOS is identified as EW81520A.86A.
When the D815EGEW board’s BIOS Setup configuration jumper is set to configuration mode and
the computer is powered-up, the BIOS compares the CPU version and the microcode version in the
BIOS and reports if the two match.
For information about Refer to
The D815EGEW board’s compliance level with Plug and Play Table 3, page 17
The Firmware Hub (FWH) includes a 4 Mbit (512 KB) symmetrical flash memory device.
Internally, the device is grouped into eight 64-KB blocks that are individually erasable, lockable,
and unlockable.
3.3 Resource Configuration
3.3.1 PCI Autoconfiguration
The BIOS can automatically configure PCI devices. PCI devices may be onboard or add-in cards.
Autoconfiguration lets a user insert or remove PCI cards without having to configure the system.
When a user turns on the system after adding a PCI card, the BIOS automatically configures
interrupts, the I/O space, and other system resources. Any interrupts set to Available in Setup are
considered to be available for use by the add-in card.
PCI interrupts are distributed to available ISA interrupts that have not been assigned to system
resources. The assignment of PCI interrupts to ISA IRQs is non-deterministic. PCI devices can
share an interrupt, but an ISA device cannot share an interrupt allocated to PCI or to another ISA
device. Autoconfiguration information is stored in ESCD format.
For information about the versions of PCI and Plug and Play supported by the BIOS, see
Section 1.3.
3.3.2 IDE Support
If you select Auto in the BIOS Setup program, the BIOS automatically sets up the two
IDE connectors with independent I/O channel support. The IDE interface supports hard drives up
to ATA-66/100 and recognizes any ATAPI devices, including CD-ROM drives, tape drives, and
Ultra DMA drives (see Section 1.3 for the supported version of ATAPI). The BIOS determines the
capabilities of each drive and configures them to optimize capacity and performance. To take
advantage of the high capacities typically available today, hard drives are automatically configured
for Logical Block Addressing (LBA) and to PIO Mode 3 or 4, depending on the capability of the
drive. You can override the auto-configuration options by specifying manual configuration in the
BIOS Setup program.
To use ATA-66/100 features the following items are required:
• An ATA-66/100 peripheral device
• An ATA-66/100 compatible cable
• ATA-66/100 operating system device drivers
NOTE
✏
ATA-66/100 compatible cables are backward compatible with drives using slower IDE transfer
protocols. If an ATA-66/100 disk drive and a disk drive using any other IDE transfer protocol are
attached to the same cable, the maximum transfer rate between the drives is reduced to that of the
slowest drive.
NOTE
✏
Do not connect an ATA device as a slave on the same IDE cable as an ATAPI master device. For
example, do not connect an ATA hard drive as a slave to an ATAPI CD-ROM drive.
76
Overview of BIOS Features
3.4 System Management BIOS (SMBIOS)
SMBIOS is a Desktop Management Interface (DMI) compliant method for managing computers in
a managed network.
The main component of SMBIOS is the management information format (MIF) database, which
contains information about the computing system and its components. Using SMBIOS, a system
administrator can obtain the system types, capabilities, operational status, and installation dates for
system components. The MIF database defines the data and provides the method for accessing this
®
information. The BIOS enables applications such as Intel
SMBIOS. The BIOS stores and reports the following SMBIOS information:
• BIOS data, such as the BIOS revision level
• Fixed-system data, such as peripherals, serial numbers, and asset tags
• Resource data, such as memory size, cache size, and processor speed
• Dynamic data, such as event detection and error logging
Non-Plug and Play operating systems, such as Windows NT, require an additional interface for
obtaining the SMBIOS information. The BIOS supports an SMBIOS table interface for such
operating systems. Using this support, an SMBIOS service-level application running on a
non-Plug and Play operating system can obtain the SMBIOS information.
LANDesk® Client Manager to use
For information about Refer to
The D815EGEW board’s compliance level with the SMBIOS specification Table 3, page 17
Legacy USB support enables USB devices such as keyboards, mice, and hubs to be used even
when the operating system’s USB drivers are not yet available. Legacy USB support is used to
access the BIOS Setup program, and to install an operating system that supports USB. By default,
legacy USB support is set to Enabled.
Legacy USB support operates as follows:
1. When you apply power to the computer, legacy support is disabled.
2. POST begins.
3. Legacy USB support is enabled by the BIOS allowing you to use a USB keyboard to enter and
configure the BIOS Setup program and the maintenance menu.
4. POST completes.
5. The operating system loads. While the operating system is loading, USB keyboards, mice, and
hubs are recognized and may be used to configure the operating system. (Keyboards, mice,
and hubs are not recognized during this period if legacy USB support was set to Disabled in
the BIOS Setup program.)
To install an operating system that supports USB, verify that legacy USB support in the BIOS
Setup program is set to Enabled and follow the operating system’s installation instructions.
NOTE
✏
Legacy USB support is for keyboards, mice, and hubs only. Other USB devices are not supported
in legacy mode.
78
Overview of BIOS Features
3.6 BIOS Updates
The BIOS can be updated using either of the following utilities, which are available on the Intel
World Wide Web site:
®
• Intel
• Intel
Both utilities support the following BIOS maintenance functions:
• Verifying that the updated BIOS matches the target system to prevent accidentally installing
• Updating both the BIOS boot block and the main BIOS. This process is fault tolerant to
• Updating the BIOS boot block separately.
• Changing the language section of the BIOS.
• Updating replaceable BIOS modules, such as the video BIOS module.
• Inserting a custom splash screen.
Express BIOS Update utility, which enables automated updating while in the Windows
environment. Using this utility, the BIOS can be updated from a file on a hard disk, a 1.44 MB
diskette, or a CD-ROM, or from the file location on the Web.
®
Flash Memory Update Utility, which requires creation of a boot diskette and manual
rebooting of the system. Using this utility, the BIOS can be updated from a file on a 1.44 MB
diskette (from a legacy diskette drive or an LS-120 diskette drive) or a CD-ROM.
an incompatible BIOS.
prevent boot block corruption.
NOTE
✏
Review the instructions distributed with the upgrade utility before attempting a BIOS update.
For information about Refer to
The Intel World Wide Web site Section 1.2, page 16
3.6.1 Language Support
The BIOS Setup program and help messages are supported in five languages: US English,
German, Italian, French, and Spanish. The default language is US English, which is present unless
another language is selected in the BIOS Setup program.
3.6.2 Custom Splash Screen
During POST, an Intel® splash screen is displayed by default. This splash screen can be replaced
with a custom splash screen. A utility is available from Intel to assist with creating a custom
splash screen. The custom splash screen can be programmed into the flash memory using the
BIOS upgrade utility. Information about this capability is available on the Intel Support World
Wide Web site.
For information about Refer to
The Intel World Wide Web site Section 1.2, page 16
Some types of failure can destroy the BIOS. For example, the data can be lost if a power outage
occurs while the BIOS is being updated in flash memory. The BIOS can be recovered from a
diskette using the BIOS recovery mode. When recovering the BIOS, be aware of the following:
• Because of the small amount of code available in the non-erasable boot block area, there is no
video support. You can only monitor this procedure by listening to the speaker or looking at
the diskette drive LED.
• The recovery process may take several minutes; larger BIOS flash memory devices require
more time.
• Two beeps and the end of activity in the diskette drive indicate successful BIOS recovery.
• A series of continuous beeps indicates a failed BIOS recovery.
To create a BIOS recovery diskette, a bootable diskette must be created and the BIOS update files
copied to it. BIOS upgrades and the Intel Flash Memory Upgrade utility are available from Intel
Customer Support through the Intel World Wide Web site.
NOTE
✏
If the computer is configured to boot from an LS-120 diskette (in the Setup program’s Removable
Devices submenu), the BIOS recovery diskette must be a standard 1.44 MB diskette not a 120 MB
diskette.
For information about Refer to
The BIOS recovery mode jumper settings Table 45, page 63
The Boot menu in the BIOS Setup program Section 4.7, page 103
Contacting Intel customer support Section 1.2, page 16
80
Overview of BIOS Features
3.8 Boot Options
In the BIOS Setup program, the user can choose to boot from a diskette drive, hard drives,
CD-ROM, or the network. The default setting is for the diskette drive to be the first boot device,
the hard drive second, and the ATAPI CD-ROM third. The fourth device is disabled.
3.8.1 CD-ROM and Network Boot
Booting from CD-ROM is supported in compliance to the El Torito bootable CD-ROM format
specification. Under the Boot menu in the BIOS Setup program, ATAPI CD-ROM is listed as a
boot device. Boot devices are defined in priority order. If the CD-ROM is selected as the boot
device, it must be the first device with bootable media.
The network can be selected as a boot device. This selection allows booting from a network add-in
card with a remote boot ROM installed.
For information about Refer to
The El Torito specification Table 3, page 17
3.8.2 Booting without Attached Devices
For use in embedded applications, the BIOS has been designed so that after passing the POST, the
operating system loader is invoked even if the following devices are not present:
• Video adapter
• Keyboard
• Mouse
3.9 Fast Booting Systems with Intel® Rapid BIOS Boot
There are two factors that affect system boot speed:
• Selecting and configuring peripherals properly
®
• Using an optimized BIOS, such as the Intel
The BIOS is not configured by default to boot at the fastest possible speed. Empirical
measurements have shown that some Intel Desktop boards, when optimized as described above,
can complete POST (Power-On Self-Test) in six seconds or less and boot to an active Microsoft
Windows Me operating system in 21 seconds.
In addition to the appliance-like speed that benefits end users, fast booting systems can also
increase an OEMs manufacturing line throughput.
The following techniques will help speed system boot:
• Choose a hard drive with parameters such as “power-up to data ready” less than eight seconds
†
to minimize hard drive startup delays. The Western Digital Caviar
AA or BA series are
examples of drives that meet this parameter.
• Select a CD-ROM drive with a fast initialization rate; variations can influence POST times.
• Eliminate unnecessary features such as video-company-logo displaying, screen repaints, or
mode changes. These all add time in the boot process. The Plug and Play communication
between the video BIOS and the monitor shows time variances.
• Try different monitors. Some monitors initialize more quickly, thereby enabling the system to
boot more quickly.
3.9.2 Intel Rapid BIOS Boot
There are several BIOS settings which, if adjusted, can reduce the execution time of the POST:
• Set the hard disk drive as the first boot device. As a result, the POST will not seek a diskette
drive (saving about one second from the POST time) or a CD-ROM drive (saving about two
seconds).
• Make sure that Quiet Boot is disabled, to eliminate the logo splash screen. This could save
several seconds of painting complex graphic images and changing video modes.
• Make sure the Intel Rapid BIOS Boot option (in the Boot menu of the BIOS Setup Program) is
enabled (this is typically the default setting). This feature bypasses memory count and floppy
seek.
• Disable the LAN feature PXE (Preboot eXecutable Environment) if it will not be used. Doing
so can reduce up to four seconds of option ROM boot time.
NOTE
✏
It is possible to optimize the boot process to the point where the system boots so quickly that the
Intel Logo Screen (or a custom logo splash screen) will not be seen. Monitors and hard disk
drives with minimum initialization times can also contribute to a boot time that might be so fast
that necessary logo screens and POST messages cannot be seen. If this should occur, it is possible
to introduce a programmable delay ranging from 3 to 30 seconds using the Hard Disk Pre-Delay
feature in the IDE Configuration Submenu of the BIOS Setup Program.
For information about Refer to
IDE Configuration Submenu in the BIOS Setup Program Table 63, page 94
82
Overview of BIOS Features
3.10 BIOS Security Features
The BIOS includes security features that restrict access to the BIOS Setup program and who can
boot the computer. A supervisor password and a user password can be set for the BIOS Setup
program and for booting the computer, with the following restrictions:
• The supervisor password gives unrestricted access to view and change all the Setup options in
the BIOS Setup program. This is the supervisor mode.
• The user password gives restricted access to view and change Setup options in the BIOS Setup
program. This is the user mode.
• If only the supervisor password is set, pressing the <Enter> key at the password prompt of the
BIOS Setup program allows the user restricted access to Setup.
• If both the supervisor and user passwords are set, users can enter either the supervisor
password or the user password to access Setup. Users have access to Setup respective to
which password is entered.
• Setting the user password restricts who can boot the computer. The password prompt will be
displayed before the computer is booted. If only the supervisor password is set, the computer
boots without asking for a password. If both passwords are set, the user can enter either
password to boot the computer.
Table 53 shows the effects of setting the supervisor password and user password. This table is for
reference only and is not displayed on the screen.
Table 53. Supervisor and User Password Functions
Password Set
Neither Can change all
Supervisor
only
User only N/A Can change all
Supervisor
and user set
Note: If no password is set, any user can change all Setup options.
Supervisor
Mode
options
Can change all
options
Can change all
options
(Note)
User Mode Setup Options
Can change all
options
Can change a
limited number
of options
options
Can change a
limited number
of options
(Note)
None None None
Supervisor Password Supervisor None
Enter Password
Clear User Password
Supervisor Password
Enter Password
Password to
Enter Setup
User User
Supervisor or
user
Password
During Boot
Supervisor or
user
For information about Refer to
Setting user and supervisor passwords Section 4.5, page 100
4.8 Exit Menu .................................................................................................................106
4.1 Introduction
The BIOS Setup program can be used to view and change the BIOS settings for the computer. The
BIOS Setup program is accessed by pressing the <F2> key after the Power-On Self-Test (POST)
memory test begins and before the operating system boot begins. The menu bar is shown below.
Maintenance Main Advanced Security Power Boot Exit
Table 54 lists the BIOS Setup program menu features.
Table 54. BIOS Setup Program Menu Bar
Maintenance Main Advanced Security Power Boot Exit
Selects boot
options
✏
Clears
passwords and
BIS credentials
and enables
extended
configuration
mode
NOTE
Allocates
resources for
hardware
components
Configures
advanced
features
available
through the
chipset
Sets
passwords
and security
features
Configures
power
management
features
In this chapter, all examples of the BIOS Setup program menu bar include the maintenance menu;
however, the maintenance menu is displayed only when the board is in configuration mode.
Section 2.9 on page 61 tells how to put the board in configuration mode.
Saves or
discards
changes to
Setup
program
options
Table 55 lists the function keys available for menu screens.
Table 55. BIOS Setup Program Function Keys
BIOS Setup Program Function Key Description
<←> or <→> Selects a different menu screen (Moves the cursor left or right)
<↑> or <↓> Selects an item (Moves the cursor up or down)
<Tab> Selects a field (Not implemented)
<Enter> Executes command or selects the submenu
<F9> Load the default configuration values for the current menu
<F10> Save the current values and exits the BIOS Setup program
<Esc> Exits the menu
4.2 Maintenance Menu
To access this menu, select Maintenance on the menu bar at the top of the screen.
Maintenance
Extended Configuration
The menu shown in Table 56 is for clearing Setup passwords and enabling extended configuration
mode. Setup only displays this menu in configuration mode. See Section 2.9 on page 61 for
configuration mode setting information.
Main Advanced Security Power Boot Exit
Table 56. Maintenance Menu
Feature Options Description
Clear All Passwords • Yes (default)
• No
Clear BIS Credentials • Yes (default)
• No
Extended
Configuration
CPU Microcode
Update Revision
CPU Stepping
Signature
No options Invokes the Extended Configuration submenu.
No options Displays CPU’s Microcode Update Revision.
No options Displays CPU’s Stepping Signature.
Clears the user and administrative passwords.
Clears the Wired for Management Boot Integrity Service (BIS)
credentials.
86
BIOS Setup Program
4.2.1 Extended Configuration Submenu
To access this submenu, select Maintenance on the menu bar, then Extended Configuration.
Maintenance
Extended Configuration
The submenu represented by Table 57 is for setting video memory cache mode. This submenu
becomes available when User Defined is selected under Extended Configuration.
Table 57. Extended Configuration Submenu
Feature Options Description
Extended Configuration • Default
Video Memory Cache
Mode
SDRAM AutoConfiguration
CAS# Latency • 3
SDRAM RAS# to CAS#
Delay
SDRAM RAS# Precharge • 3
Main Advanced Security Power Boot Exit
User Defined allows setting memory control and video
(default)
• User-Defined
• USWC
• UC (default)
• Auto (default)
• User Defined
• 2
• Auto (default)
• 3
• 2
• Auto (default)
• 2
• Auto (default)
memory cache mode. If selected here, will also display in
the Advanced Menu as: “Extended Menu: Used.”
Selects Uncacheable Speculative Write-Combining
(USWC) video memory cache mode. Full 32 byte contents
of the Write Combining buffer are written to memory as
required. Cache lookups are not performed. Both the
video driver and the application must support Write
Combining.
Selects UnCacheable (UC) video memory cache mode.
This setting identifies the video memory range as
uncacheable by the processor. Memory writes are
performed in program order. Cache lookups are not
performed. Well suited for applications not supporting
Write Combining.
Sets extended memory configuration options to Auto or
User Defined.
Selects the number of clock cycles required to address a
column in memory.
Selects the number of clock cycles between addressing a
row and addressing a column.
Selects the length of time required before accessing a new
row.
To access this submenu, select Advanced on the menu bar, then PCI Configuration.
Maintenance Main
Advanced
PCI Configuration
Boot Configuration
Peripheral Configuration
IDE Configuration
Diskette Configuration
Event Log Configuration
Video Configuration
The submenu represented by Table 60 is for configuring the IRQ priority of PCI slots individually.
Table 60. PCI Configuration Submenu
Feature Options Description
PCI Slot 1 IRQ Priority • Auto (default)
5
9
10
11
PCI Slot 2 IRQ Priority • Auto (default)
5
9
10
11
PCI Slot 3 IRQ Priority • Auto (default)
5
9
10
11
PCI Slot 4 IRQ Priority • Auto (default)
5
9
10
11
Security Power Boot Exit
Allows selection of IRQ priority.
Allows selection of IRQ priority.
Allows selection of IRQ priority.
Allows selection of IRQ priority.
90
BIOS Setup Program
4.4.2 Boot Configuration Submenu
To access this submenu, select Advanced on the menu bar, then Boot Configuration.
Maintenance Main
Advanced
PCI Configuration
Boot Configuration
Peripheral Configuration
IDE Configuration
Diskette Configuration
Event Log Configuration
Video Configuration
The submenu represented by Table 61 is for setting Plug and Play options, resetting configuration
data, and the power-on state of the Numlock key.
Table 61. Boot Configuration Submenu
Feature Options Description
Plug & Play O/S • No (default)
• Yes
Reset Config Data • No (default)
• Yes
Numlock • Off
• On (default)
Security Power Boot Exit
Specifies if manual configuration is desired.
No lets the BIOS configure all devices. This setting is
appropriate when using a Plug and Play operating system.
Yes lets the operating system configure Plug and Play
devices not required to boot the system. This option is
available for use during lab testing.
No does not clear the PCI/PnP configuration data stored in
flash memory on the next boot.
Yes clears the PCI/PnP configuration data stored in flash
memory on the next boot.
Specifies the power-on state of the Numlock feature on the
numeric keypad of the keyboard.
To access this submenu, select Advanced on the menu bar, then IDE Configuration.
Maintenance Main
Advanced
PCI Configuration
Boot Configuration
Peripheral Configuration
IDE Configuration
Diskette Configuration
Event Log Configuration
Video Configuration
The menu represented in Table 63 is used to configure IDE device options.
Table 63. IDE Configuration Submenu
Feature Options Description
IDE Controller • Disabled
• Primary
• Secondary
• Both (default)
PCI IDE Bus Master • Disabled
• Enabled (default)
Hard Disk Pre-Delay • Disabled (default)
• 3 Seconds
• 6 Seconds
• 9 Seconds
• 12 Seconds
• 15 Seconds
• 21 Seconds
• 30 Seconds
Primary IDE Master No options Reports type of connected IDE device. When selected,
Primary IDE Slave No options Reports type of connected IDE device. When selected,
Secondary IDE Master No options Reports type of connected IDE device. When selected,
Secondary IDE Slave No options Reports type of connected IDE device. When selected,
Security Power Boot Exit
Specifies the integrated IDE controller.
Primary enables only the primary IDE controller.
Secondary enables only the secondary IDE controller.
Both enables both IDE controllers.
Enables or disables PCI IDE bus master capability.
Specifies the hard disk drive pre-delay.
displays the Primary IDE Master submenu.
displays the Primary IDE Slave submenu.
displays the Secondary IDE Master submenu.
displays the Secondary IDE Slave submenu.
94
BIOS Setup Program
4.4.4.1 Primary/Secondary IDE Master/Slave Submenus
To access these submenus, select Advanced on the menu bar, then IDE Configuration, and then the
master or slave to be configured.
Maintenance Main
Advanced
PCI Configuration
Boot Configuration
Peripheral Configuration
IDE Configuration
Primary IDE Master
Primary IDE Slave
Secondary IDE Master
Secondary IDE Slave
Diskette Configuration
Event Log Configuration
Video Configuration
There are four IDE submenus: primary master, primary slave, secondary master, and secondary
slave. Table 64 shows the format of the IDE submenus. For brevity, only one example is shown.
Security Power Boot Exit
Table 64. Primary/Secondary IDE Master/Slave Submenus
Feature Options Description
Drive Installed None Displays the type of drive installed.
Type • None
• User
• Auto (default)
• CD-ROM
• ATAPI Removable
• Other ATAPI
• IDE Removable
Maximum Capacity None Displays the capacity of the drive.
LBA Mode Control • Disabled (default)
• Enabled
Multi-Sector Transfers • Disabled
• 2 Sectors
• 4 Sectors
• 8 Sectors
• 16 Sectors (default)
Specifies the IDE configuration mode for IDE devices.
User allows capabilities to be changed.
Auto fills-in capabilities from ATA/ATAPI device.
Enables or disables LBA mode control.
Specifies number of sectors per block for transfers from
the hard disk drive to memory.
Check the hard disk drive’s specifications for optimum
setting.
To access this menu, select Security from the menu bar at the top of the screen.
Maintenance Main Advanced
Security
The menu represented by Table 68 is for setting passwords and security features.
Table 68. Security Menu
If no password entered previously:
Feature Options Description
Supervisor Password Is No options Reports if there is a supervisor password set.
User Password Is No options Reports if there is a user password set.
Set Supervisor Password Password can be up to seven
alphanumeric characters.
Set User Password Password can be up to seven
alphanumeric characters.
Clear User Password
(Note 1)
User Access Level
(Note 2)
Unattended Start
(Notes 1, 3, and 4)
Notes:
1. This feature appears only if a user password has been set.
2. This feature appears only if a supervisor password has been set.
3. If both Legacy USB Support (in the Peripheral Configuration submenu) and Unattended Start (in the Security menu)
are enabled, USB aware operating systems can unlock a PS/2 style keyboard and mouse without requiring the user to
enter a password.
4. When Unattended Start is enabled, a USB aware operating system may override user password protection if used in
conjunction with a USB keyboard and mouse without requiring the user to enter a password.
• Yes (default)
• No
• Limited
• No Access
• View Only
• Full (default)
• Enabled
• Disabled (default)
Power Boot Exit
Specifies the supervisor password.
Specifies the user password.
Clears the user password.
Sets BIOS Setup Utility access rights for user
level.
Enabled allows system to complete the boot
process without a password. The keyboard
remains locked until a password is entered. A
password is required to boot from a diskette.
100
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