Desktop Board D815EGEW may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current
The Intel
characterized errata are documented in the Intel Desktop Board D815EGEW Specification Update.
October 2001
Order Number A73971-001
Revision History
Revision Revision History Date
-001 First release of the Intel® Desktop Board D815EGEW Technical Product
Specification
This product specification applies to only standard D815EGEW boards with BIOS identifier
EW81520A.86A.
Changes to this specification will be published in the Intel Desktop Board D815EGEW
Specification Update before being incorporated into a revision of this document.
®
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®
The Intel
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
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Intel, Celeron and LANDesk are registered trademarks of Intel Corporation or its subsidiaries in the United States and other
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†
Other names and brands may be claimed as the property of others.
Copyright 2001, Intel Corporation. All rights reserved.
Desktop Board D815EGEW may contain design defects or errors known as errata that may cause the product to
PRODUCTS. EXCEPT AS
October 2001
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and the BIOS for the Intel Desktop Boards D815EGEW.
It describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the D815EGEW board and its
components to the vendors, system integrators, and other engineers and technicians who need this
level of information. It is specifically not intended for general audiences.
What This Document Contains
Chapter Description
1 A description of the hardware used on the D815EGEW board
2 A map of the resources of the board
3 The features supported by the BIOS Setup program
4 The contents of the BIOS Setup program’s menus and submenus
5 A description of the BIOS error messages, beep codes, and POST codes
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions, which if not observed, can cause personal injury.
# Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX) When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the D815EGEW board, and X is the instance of the particular
part at that general location. For example, J5J1 is a connector, located at 5J. It is the first
connector in the 5J area.
GB Gigabyte (1,073,741,824 bytes)
KB Kilobyte (1024 bytes)
Kbit Kilobit (1024 bits)
kbits/sec 1000 bits per second
MB Megabyte (1,048,576 bytes)
MB/sec Megabytes per second
Mbit Megabit (1,048,576 bits)
Mbit/sec Megabits per second
xxh An address or data value ending with a lowercase h indicates a hexadecimal value.
x.x V Volts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
respective owners.
Table 1 summarizes the D815EGEW board’s major features.
Table 1. Feature Summary
Form Factor
Processor
Memory
Chipsets
I/O Control
Video
Audio
Peripheral
Interfaces
Expansion
Capabilities
BIOS
Instantly Available
PC
microATX (9.20 inches by 7.65 inches)
Support for either an Intel
(FC-PGA) package or an Intel® Celeron® processor in an FC-PGA package
• Two 168-pin SDRAM Dual Inline Memory Module (DIMM) sockets
• Support for up to 512 MB system memory
• Support for single-sided or double-sided DIMMs
• The D815EGEW board includes the Intel 815EG Chipset, consisting of:
Intel
Intel
Intel
National Semiconductor PC87360 LPC bus I/O controller
Intel 82815G integrated graphics support
• Intel 82801BA ICH2 digital controller (AC link output)
• Analog Devices AD1885 Audio Codec
• Two Universal Serial Bus (USB) ports
• One serial port
• One parallel port
• Two IDE interfaces with Ultra DMA, ATA-66/100 support
• One diskette drive interface
• PS/2
Four PCI bus add-in card connectors (PCI bus connector 2 includes SMBus
signals and is S5 wake-enabled)
• Intel/AMI BIOS (Intel 82802AB 4 Mbit FWH)
• Support for Advanced Configuration and Power Interface (ACPI), Plug and Play,
and SMBIOS
• Support for PCI Local Bus Specification Revision 2.2
• Suspend to RAM support
• Wake on PS/2 keyboard and USB ports
®
82815G Graphics and Memory Controller Hub (GMCH)
®
82801BA I/O Controller Hub (ICH2)
®
82802AB 4 Mbit Firmware Hub (FWH)
†
keyboard and mouse ports
®
Pentium® III processor in a Flip Chip Pin Grid Array
For information about Refer to
The board’s compliance level with ACPI, Plug and Play, and SMBIOS Table 3, page 17
12
Product Description
1.1.2 Manufacturing Options
Table 2 describes the D815EGEW board’s manufacturing options. Not every manufacturing
option is available in all marketing channels. Please contact your Intel representative to determine
which manufacturing options are available to you.
Table 2. Manufacturing Options
®
LAN Subsystem
Chassis Fan
Connector
Chassis Intrusion
Connector
SCSI LED
Connector
Speaker
Standby power
indicator LED
Wake on LAN†
Technology
Connector
Intel
82562ET 10/100 Mbit/sec Platform LAN Connect (PLC) device
Connector for an additional cooling fan
Connector for sensing chassis intrusion
Allows add-in SCSI host bus adapters to use the same LED as the onboard I/O
controller
47 Ω inductive speaker that provides audible error code (beep code) information
during Power On Self Test (POST)
Shows that power is still present at the DIMM and PCI bus connectors, even when
the computer appears to be off
Support for system wake up using an add-in network interface card with remote wake
up capability
Figure 1 shows the location of the major components on the D815EGEW board.
BA
C
D
E
F
G
W
H
V
U
T
S
R
I
Q
N
P
O
A AD1885 audio codec M Battery
B ATAPI-style audio connectors N Speaker (optional)
C Back panel connectors O SCSI LED connector (optional)
D Wake from PS/2 and USB jumper blocks P Front panel connector
E Processor fan connector Q Chassis intrusion connector (optional)
F BIOS Setup Configuration jumper R Front panel power LED connector
G Intel 82815G GMCH S Chassis fan connector (optional)
H Processor socket T Wake on LAN technology connector (optional)
I DIMM sockets U Intel 82801BA I/O Controller Hub (ICH2)
J Power connector V Intel 82802AB 4 Mbit Firmware Hub (FWH)
K Diskette drive connector W PCI bus add-in card connectors
L IDE connectors
M
L
KJ
OM12802
14
Figure 1. Board Components
1.1.4 Block Diagram
Figure 2 is a block diagram of the major functional areas of the D815EGEW board.
The D815EGEW board supports drivers for all of the onboard hardware and subsystems under the
following operating systems:
†
• Microsoft Windows
• Windows ME
• Windows NT
• Windows 2000
• Windows XP
For information about Refer to
Supported drivers Section 1.3
†
98SE – ACPI mode
4.0
NOTE
✏
Third party vendors may offer other drivers.
16
1.4 Design Specifications
Table 3 lists the specifications applicable to the D815EGEW board.
Table 3. Specifications
Reference
Name
AC ’97 Audio Codec ’97 Revision 2.1,
ACPI Advanced Configuration
AMI BIOS American Megatrends
ATA/
ATAPI-5
ATX ATX Specification Version 2.03,
BIS Boot Integrity Services Version 1.0 for WfM 2.0
EPP IEEE Std 1284.1-1997
El Torito Bootable CD-ROM Format
LPC Low Pin Count Interface
MicroATX microATX Motherboard
Specification
Title
and Power Interface
Specification
BIOS Specification
Information Technology AT Attachment with Packet
Interface - 5
(ATA/ATAPI-5)
(Enhanced Parallel Port)
Specification
Specification
Interface Specification
Version, Revision Date,
and Ownership
May 1998,
Intel Corporation.
Version 2.0,
July 27, 2000,
Compaq Computer
Corporation,
Intel Corporation,
Microsoft Corporation,
Phoenix Technologies
Limited, and
Toshiba Corporation.
AMIBIOS 99,
1999,
American Megatrends, Inc.
Revision 3,
February 29, 2000,
Contact: T13 Chair,
Seagate Technology.
December 1998,
Intel Corporation.
August 1999,
Intel Corporation.
Version 1.7,
1997,
Institute of Electrical and
Electronic Engineers.
Version 1.0,
January 25, 1995,
Phoenix Technologies
Limited and International
Business Machines
Corporation.
Version 1.0,
September 29, 1997,
Intel Corporation.
Version 2.2,
December 18, 1998,
PCI Special Interest Group.
Version 1.1,
December 18, 1998,
PCI Special Interest Group.
Version 1.0a,
May 5, 1994,
Compaq Computer Corporation,
Phoenix Technologies Limited,
and Intel Corporation.
Revision 1.0,
February 1998,
Intel Corporation.
November 1999,
Intel Corporation.
Revision 1.2B,
November 1999,
Intel Corporation.
Version 2.3.1,
March 16, 1999,
American Megatrends
Incorporated,
Award Software International
Incorporated,
Compaq Computer Corporation,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
and SystemSoft Corporation.
Revision 1.1,
March 1996,
Intel Corporation.
Version 1.1,
September 23, 1998,
Compaq Computer Corporation,
Intel Corporation,
Microsoft Corporation, and
NEC Corporation.
Version 2.0,
December 18, 1998,
Intel Corporation.
Use only the processors listed below. Use of unsupported processors can damage the board, the
processor, and the power supply. See the Intel
most up-to-date list of supported processors for the D815EGEW board.
The D815EGEW board supports a single Pentium III or Celeron processor. The system bus
frequency is automatically selected. The board supports the processors listed in Table 4.
Table 4. Supported Processors
Type Designation System Bus Frequency L2 Cache Size
1.00, 1.13, and 1.20 GHz 133 MHz 256 KB Pentium III processor in
Before installing or removing memory, make sure that AC power is disconnected by unplugging
the power cord from the computer. Failure to do so could damage the memory and the board.
NOTE
✏
To be fully compliant with all applicable Intel® SDRAM memory specifications, the board should
be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. If your
memory modules do not support SPD, you will see a notification to this effect on the screen at
power up. The BIOS will attempt to configure the memory controller for normal operation.
However, DIMMs may not function under the determined frequency.
NOTE
✏
Because the main system memory is also used as video memory, the board requires a 100 MHz
SDRAM DIMM even though the host bus frequency is 66 MHz. It is highly recommended that an
SPD DIMM be used, since this allows the BIOS to read the SPD data and program the chipset to
accurately configure memory settings for optimum performance. If non-SPD memory is installed,
the BIOS will attempt to correctly configure the memory settings, but performance and reliability
may be impacted.
The D815EGEW board has two DIMM sockets and supports the following memory features:
• 3.3 V (only) 168-pin SDRAM DIMMs with gold-plated contacts
• Unbuffered single-sided or double-sided DIMMs
• Capacity:
Maximum system memory: 512 MB
Minimum system memory: 64 MB
• 133 MHz SDRAM or 100 MHz SDRAM
• Serial Presence Detect (SPD) and non-SPD memory
• Non-ECC and ECC DIMMs (ECC DIMMs will operate in non-ECC mode only)
• Suspend to RAM
When installing memory, note the following:
• Non-SPD DIMMs will always revert to a 100 MHz with 3-3-3 timing SDRAM bus.
• Mixing Non-SPD DIMMs with SPD DIMMs will always revert to a 100 MHz with 3-3-3
timing SDRAM bus.
• The BIOS will not initialize installed memory above 512 MB. At boot, the BIOS displays a
message indicating that any installed memory above 512 MB has not been initialized.
• Mixed memory speed configurations (133 and 100 MHz) will default to 100 MHz.
• 133 MHz SDRAM operation requires a 133 MHz system bus frequency processor.
• 100 MHz SDRAM may be populated with four rows of SDRAM (two double-sided DIMMs).
For information about Refer to
Obtaining the PC Serial Presence Detect (SPD) SpecificationTable 3, page 17
20
Product Description
Table 5 lists the supported DIMM configurations.
Table 5. Supported Memory Configurations
SDRAM
Density
DIMM
Capacity
Number of
(Note 1)
Sides
32 MB DS 16 Mbit 2 M x 8/2 M x 8 16
32 MB SS 64 Mbit 4 M x 16/empty 4
48 MB DS 64/16 Mbit 4 M x 16/2 M x 8 12
64 MB DS 64 Mbit 4 M x 16/4 M x 16 8
64 MB SS 64 Mbit 8 M x 8/empty 8
64 MB SS 128 Mbit 8 M x 16/empty 4
96 MB DS 64 Mbit 8 M x 8/4 M x 16 12
96 MB DS 128/64 Mbit 8 M x 16/4 M x 16 8
128 MB DS 64 Mbit 8 M x 8/8 M x 8 16
128 MB DS 128 Mbit 8 M x 16/8 M x 16 8
128 MB SS 128 Mbit 16 M x 8/empty 8
128 MB SS 256 Mbit 16 M x 16/empty 4
192 MB DS 128 Mbit 16 M x 8/8 M x 16 12
192 MB DS 128/64 Mbit 16 M x 8/8 M x 8 16
256 MB DS 128 Mbit 16 M x 8/16 M x 8 16
256 MB DS 256 Mbit 16 M x 16/16 M x 16 8
256 MB SS 256 Mbit 32 M x 8/empty 8
512 MB DS 256 Mbit 32 M x 8/32 M x 8 16
Notes:
1. “DS” refers to double-sided memory modules (containing two rows of SDRAM) and “SS” refers to single-sided memory
modules (containing one row of SDRAM).
2. If the number of SDRAM devices is greater than nine, the DIMM will be double sided.
3. Front side population/back side population indicated for SDRAM density and SDRAM organization.
The Intel® 815EG chipset consists of the following devices:
• 82815G Graphics and Memory Controller Hub (GMCH) with Accelerated Hub Architecture
(AHA) bus
• 82801BA I/O Controller Hub (ICH2) with AHA bus
• Intel 82802AB 4 Mbit Firmware Hub (FWH)
The GMCH is a centralized controller for the system bus, the memory bus, and the AHA bus. The
ICH2 is a centralized controller for the board’s I/O paths. The FWH provides the nonvolatile
storage of the BIOS.
The Intel 815EG chipset provides the interfaces shown in Figure 3.
ATA-66/100
System Bus
SDRAM Bus
Network
USB
815EG Chipset
82815G
Graphics and
Memory Controller
Hub (GMCH)
Video
Bus
AHA
Bus
82801BA
I/O Controller Hub
(ICH2)
82802AB 4 Mbit
Firmware Hub
(FWH)
LPC Bus
AC LinkPCI BusSMBus
OM12838
Figure 3. Intel 815EG Chipset Block Diagram
For information about Refer to
The Intel 815EG chipset http://developer.intel.com/design/chipsets/815eg
The resources used by the chipset Chapter 2
The chipset’s compliance with ACPI and AC ’97 Table 3, page 17
22
Product Description
1.7.1 IDE Interfaces
The ICH2’s IDE controller has two independent bus-mastering IDE interfaces that can be
independently enabled. The IDE interfaces support the following modes:
• Programmed I/O (PIO): CPU controls data transfer.
• 8237-style DMA: DMA offloads the CPU, supporting transfer rates of up to 16 MB/sec.
• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
• ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
• ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH2 ATA-100
logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to
88 MB/sec.
✏ NOTE
ATA-66 and ATA-100 are faster timings and require a specialized cable to reduce reflections,
noise, and inductive coupling.
The IDE interfaces also support ATAPI devices (such as CD-ROM drives) and ATA devices using
the transfer modes listed in Table 64 on page 95.
The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The D815EGEW board supports Laser Servo (LS-120) diskette technology through its IDE
interfaces. The LS-120 drive can be configured as a boot device by setting the BIOS Setup
program’s Boot menu to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
For information about Refer to
The location of the IDE connectors Figure 9, page 54
The signal names of the IDE connectors Table 37, page 56
BIOS Setup program’s Boot menu Table 71, page 103
1.7.2 USB
The D815EGEW board has two USB ports; one USB peripheral can be connected to each port.
For more than two USB devices, an external hub can be connected to any of the ports. The
D815EGEW board’s two USB ports are implemented with stacked back panel connectors, routed
through the ICH2. The board contains a jumper block for enabling/disabling the Wake from USB
feature.
The D815EGEW board fully supports the Universal Hub Controller Interface (UHCI).
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
For information about Refer to
The location of the USB connectors on the back panel Figure 7, page 46
The signal names of the back panel USB connectors Table 20, page 47
The USB specification and UHCI Table 3, page 17
The Wake from USB jumper block Section 2.9, page 61
1.7.3 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock provides a time-of-day clock and a multicentury calendar with alarm features.
The real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are
reserved for BIOS use.
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
✏ NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded into CMOS
SRAM at power-on.
1.8 I/O Controller
The D815EGEW board includes the National Semiconductor PC87360 I/O controller. The I/O
controller’s features include:
• Low pin count (LPC) interface
• 3.3 V operation
• One serial port
• One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support
• PS/2-style mouse and keyboard interfaces
• Interface for one 1.2 MB, 1.44 MB, or 2.88 MB diskette drive
• One fan control output
The BIOS Setup program provides configuration options for the I/O controller.
For information about Refer to
National Semiconductor PC87360 I/O controller http://www.natsemi.com
24
Product Description
1.8.1 Serial Port
Serial port A is located on the back panel. The serial port supports data transfers at speeds up to
115.2 kbits/sec with BIOS support. The serial port can be assigned as COM1 (3F8h), COM2
(2F8h), COM3 (3E8h), or COM4 (2E8h).
For information about Refer to
The location of the serial port A connector Figure 7, page 46
The signal names of the serial port A connector Table 23, page 48
1.8.2 Parallel Port
The connector for the parallel port is a 25-pin D-Sub connector located on the back panel. In the
BIOS Setup program, the parallel port can be set to the following modes:
†
• Output only (PC AT
• Bi-directional (PS/2 compatible)
• EPP
• ECP
For information about Refer to
The location of the parallel port connector Figure 7, page 46
The signal names of the parallel port connector Table 22, page 48
Setting the parallel port’s mode Table 62, page 92
-compatible mode)
1.8.3 Diskette Drive Controller
The I/O controller supports one diskette drive that is compatible with the 82077 diskette drive
controller and supports both PC-AT and PS/2 modes.
For information about Refer to
The location of the diskette drive connector Figure 9, page 54
The signal names of the diskette drive connector Table 36, page 56
The supported diskette drive capacities and sizes Table 65, page 97
1.8.4 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel. The +5 V lines to these
connectors are protected with a thermistor, which limits the current to a specified amperage.
NOTE
✏
The keyboard and mouse will function in either PS/2 connector, but the connectors are colorcoded for ease of installation. Power to the computer should be turned off before a keyboard or
mouse is connected or disconnected.
The keyboard controller contains the AMI keyboard and mouse controller code, provides the
keyboard and mouse control functions, and supports password protection for power-on/reset. A
power-on/reset password can be specified in the BIOS Setup program.
The keyboard controller also supports the hot-key sequence <Ctrl><Alt><Del> for a software reset
(operating system dependent). This key sequence resets the computer’s software by jumping to the
beginning of the BIOS code and running the power-on self-test (POST).
The board contains a jumper block for enabling/disabling the Wake from PS/2 feature.
For information about Refer to
The location of the keyboard and mouse connectors Figure 7, page 46
The signal names of the keyboard and mouse connectors Table 19, page 47
Overcurrent protection for back panel connectors Table 18, page 47
The Wake from PS/2 jumper block Section 2.9, page 61
1.9 Graphics Subsystem
The 82815G GMCH features the following:
• Integrated graphics controller
3-D Hyperpipelined architecture
Full 2-D hardware acceleration
Motion video acceleration
• 3-D graphics visual and texturing enhancement
• Display
Integrated 24-bit 230 MHz RAMDAC
Display Data Channel Standard, Version 3.0, Level 2B protocols compliant
• Video
Hardware motion compensation for software MPEG2 decode
Software DVD at 30 fps
• Integrated graphics memory controller
26
Table 6 lists the refresh frequencies supported by the graphics subsystem.
D = DirectDraw
3 = Direct3D
O = Overlay
F = Digital Display Device only. A mode will be supported on both analog CRTs and digital
display devices (KD3O applies to both types of displays), unless indicated otherwise.
256 colors
†
†
and OpenGL†
Available Refresh
Frequencies (Hz)
60, 70, 72, 75 KD
Notes
For information about Refer to
Obtaining graphics software and utilities Section 1.2, page 16
28
1.10 Audio Subsystem
The D815EGEW board includes an Audio Codec ’97 (AC ’97) compatible audio subsystem
consisting of these devices:
• Intel 82801BA I/O Controller Hub (ICH2)
• Analog Devices AD1885 analog codec
1.10.1 AD1885 Audio Codec
The AD1885 is a fully AC ’97 compliant codec. The codec’s features include:
• > 85 dB signal-to-noise ratio sound quality
• Power management support for ACPI 1.0 (driver dependant)
• Playback sample rates up to 48 kHz
• 16 bit stereo full-duplex codec
• Software compatible with Windows 98 SE, Windows 2000, Windows NT 4.0,
Windows Millennium (Me), and Windows XP
• Full-duplex operation at asynchronous hardware record/playback samples rates
• Frequency response: 20 Hz to 20 kHz (± 0.1 dB)
Figure 4 is a block diagram of the D815EGEW board’s audio subsystem, including the
Intel 82801BA ICH2 digital controller, the AD1885 analog codec, and the audio connectors.
Product Description
Line In
82801BA
I/O Controller Hub
(ICH2)
AC ’97 Link
Analog Devices
AD1885
Analog Codec
Line Out
Mic In
Auxiliary Line In
CD-ROM
OM12985
Figure 4. Block Diagram of Audio Subsystem
For information about Refer to
Obtaining the AC ’97 specification Table 3, page 16