Intel D15343-003 User Manual

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Intel® 82854 Graphics Memory

Controller Hub (GMCH)

Datasheet

Revision 2.0

June 2005

Order Number: D15343-003

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*Other names and brands may be claimed as the property of others. Copyright © 2005, Intel Corporation

2

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Contents

Contents

 

1.0

Introduction....................................................................................................................................

 

11

 

1.1

Overview.............................................................................................................................

11

 

1.2

Terminology ........................................................................................................................

17

 

1.3

Reference Documents ........................................................................................................

19

2.0 Intel® 82854 GMCH Overview.......................................................................................................

21

 

2.1

System Architecture............................................................................................................

21

 

 

2.1.1

Intel® 82854 GMCH ...............................................................................................

21

 

2.2

Processor Host Interface ....................................................................................................

22

 

2.3

GMCH System Memory Interface.......................................................................................

22

 

2.4

Graphics Features ..............................................................................................................

23

 

2.5

Display Features.................................................................................................................

23

 

 

2.5.1 GMCH Analog Display Port ...................................................................................

23

 

 

2.5.2 GMCH Integrated DVO Ports ................................................................................

23

 

2.6

Hub Interface ......................................................................................................................

24

 

2.7

Address Decode Policies....................................................................................................

24

 

2.8

GMCH Clocking ..................................................................................................................

25

 

2.9

System Interrupts................................................................................................................

26

3.0

Signal Description..........................................................................................................................

27

 

3.1

Host Interface Signals.........................................................................................................

28

 

3.2

DDR SDRAM Interface .......................................................................................................

31

 

3.3

Hub Interface Signals .........................................................................................................

32

 

3.4

Clocks .................................................................................................................................

 

33

 

3.5

Internal Graphics Display Signals.......................................................................................

35

 

 

3.5.1 Digital Video Output B (DVOB) Port ......................................................................

35

 

 

3.5.2 Digital Video Output C (DVOC) Port......................................................................

36

 

 

3.5.3

Analog CRT Display ..............................................................................................

37

 

 

3.5.4 General Purpose Input/Output Signals ..................................................................

38

 

3.6

Voltage References, PLL Power.........................................................................................

39

4.0

Register Description ......................................................................................................................

41

 

4.1

Conceptual Overview of the Platform Configuration Structure ...........................................

41

 

4.2

Nomenclature for Access Attributes ...................................................................................

42

 

4.3

Standard PCI Bus Configuration Mechanism .....................................................................

43

 

4.4

Routing Configuration Accesses.........................................................................................

43

 

 

4.4.1 PCI Bus #0 Configuration Mechanism...................................................................

43

 

 

4.4.2 Primary PCI and Downstream Configuration Mechanism......................................

44

 

4.5

Register Definitions.............................................................................................................

44

 

4.6

I/O Mapped Registers.........................................................................................................

45

 

 

4.6.1 CONFIG_ADDRESS – Configuration Address Register........................................

45

 

 

4.6.2 CONFIG_DATA – Configuration Data Register.....................................................

47

 

4.7

VGA I/O Mapped Registers ................................................................................................

48

 

4.8

Intel 854 GMCH Host-Hub Interface Bridge Device Registers (Device #0, Function #0) ...

49

 

 

4.8.1 VID – Vendor Identification Register......................................................................

51

 

 

4.8.2 DID – Device Identification Register ......................................................................

51

 

 

4.8.3 PCICMD – PCI Command Register.......................................................................

52

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

 

4.8.4

PCI Status Register ...............................................................................................

53

4.8.5

RID – Register Identification ..................................................................................

54

4.8.6

SUBC – Sub Class Code Register ........................................................................

54

4.8.7

BCC – Base Class Code Register .........................................................................

55

4.8.8

HDR – Header Type Register................................................................................

55

4.8.9

SVID – Subsystem Vendor Identification Register ................................................

55

4.8.10

SID – Subsystem Identification Register ...............................................................

56

4.8.11

CAPPTR – Capabilities Pointer Register...............................................................

56

4.8.12

CAPID – Capabilities Identification Register (Device #0) ......................................

57

4.8.13

GMC – GMCH Miscellaneous Control Register (Device #0) .................................

58

4.8.14

GGC – GMCH Graphics Control Register (Device #0)..........................................

59

4.8.15

DAFC – Device and Function Control Register (Device #0)..................................

60

4.8.16

FDHC – Fixed DRAM Hold Control Register (Device #0)......................................

60

4.8.17

PAM(6:0) – Programmable Attribute Map Register (Device #0)............................

61

4.8.18

SMRAM – System Management RAM Control Register (Device #0) ....................

64

4.8.19

ESMRAMC – Extended System Management RAM Control (Device #0) .............

65

4.8.20

ERRSTS – Error Status Register (Device #0) .......................................................

66

4.8.21

ERRCMD – Error Command Register (Device #0)................................................

67

4.8.22

SMICMD – SMI Error Command Register (Device #0) .........................................

68

4.8.23

SCICMD – SCI Error Command Register (Device #0) ..........................................

69

4.8.24

SHIC – Secondary Host Interface Control Register (Device #0) ...........................

70

4.8.25

HEM – Host Error Control, Status, and Observation (Device #0)..........................

71

4.9Intel 854 GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function #1)72

4.9.1

VID – Vendor Identification Register......................................................................

73

4.9.2

DID – Device Identification Register ......................................................................

73

4.9.3

PCICMD – PCI Command Register.......................................................................

74

4.9.4

PCISTS – PCI Status Register ..............................................................................

75

4.9.5

RID – Revision Identification Register ...................................................................

76

4.9.6

RID – Revision Identification Register ...................................................................

76

4.9.7

BCC – Base Class Code Register .........................................................................

76

4.9.8

HDR – Header Type Register................................................................................

77

4.9.9

SVID – Subsystem Vendor Identification Register ................................................

77

4.9.10

SID – Subsystem Identification Register ...............................................................

77

4.9.11

CAPPTR – Capabilities Pointer Register...............................................................

78

4.9.12

DRB – DRAM Row (0:3) Boundary Register (Device #0)......................................

78

4.9.13

DRA – DRAM Row Attribute Register (Device #0) ................................................

79

4.9.14

DRT – DRAM Timing Register (Device #0) ...........................................................

80

4.9.15

PWRMG – DRAM Controller Power Management Control Register (Device #0)..

83

4.9.16

DRC – DRAM Controller Mode Register (Device #0) ............................................

85

4.9.17

DTC – DRAM Throttling Control Register (Device #0) ..........................................

88

4.10 Intel 854 GMCH Configuration Process Registers (Device #0, Function #3) .....................

92

4.10.1

VID – Vendor Identification Register......................................................................

92

4.10.2

DID – Device Identification Register ......................................................................

93

4.10.3

PCICMD – PCI Command Register.......................................................................

94

4.10.4

PCISTS – PCI Status Register ..............................................................................

95

4.10.5

RID – Revision Identification Register ...................................................................

96

4.10.6

SUBC – Sub-Class Code Register ........................................................................

96

4.10.7

BCC – Base Class Code Register .........................................................................

96

4.10.8

HDR – Header Type Register................................................................................

97

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Contents

 

4.10.9

SVID – Subsystem Vendor Identification Register.................................................

97

 

4.10.10

ID – Subsystem Identification Register..................................................................

97

 

4.10.11

CAPPTR – Capabilities Pointer Register...............................................................

98

 

4.10.12 HPLLCC – HPLL Clock Control Register (Device #0) ...........................................

98

4.11

Intel® 82854 GMCH Integrated Graphics Device Registers (Device #2, Function #0) .....

100

 

4.11.1

VID – Vendor Identification Register (Device #2) ................................................

101

 

4.11.2

DID – Device Identification Register (Device #2).................................................

101

 

4.11.3

PCICMD – PCI Command Register (Device #2) .................................................

102

 

4.11.4

PCISTS – PCI Status Register (Device #2).........................................................

103

 

4.11.5

RID – Revision Identification Register (Device #2)..............................................

103

 

4.11.6

CC – Class Code Register (Device #2) ...............................................................

104

 

4.11.7

CLS – Cache Line Size Register (Device #2)......................................................

104

 

4.11.8

MLT – Master Latency Timer Register (Device #2) .............................................

104

 

4.11.9

HDR – Header Type Register (Device #2)...........................................................

105

 

4.11.10 GMADR – Graphics Memory Range Address Register (Device #2)....................

105

 

4.11.11 MMADR – Memory Mapped Range Address Register (Device #2).....................

106

 

4.11.12 IOBAR – I/O Base Address Register (Device #2)................................................

106

 

4.11.13 SVID – Subsystem Vendor Identification Register (Device #2) ...........................

107

 

4.11.14 SID – Subsystem Identification Register (Device #2) ..........................................

107

 

4.11.15 ROMADR – Video BIOS ROM Base Address Registers (Device #2)..................

107

 

4.11.16 INTRLINE – Interrupt Line Register (Device #2)..................................................

108

 

4.11.17 INTRPIN – Interrupt Pin Register (Device #2) .....................................................

108

 

4.11.18 MINGNT – Minimum Grant Register (Device #2) ................................................

108

 

4.11.19 MAXLAT – Maximum Latency Register (Device #2)............................................

109

 

4.11.20 PMCAP – Power Management Capabilities Register (Device #2).......................

109

 

4.11.21 PMCS – Power Management Control/Status Register (Device #2).....................

110

5.0 Intel® 82854 GMCH System Address Map..................................................................................

111

5.1

System Memory Address Ranges ....................................................................................

111

5.2

DOS Compatibility Area....................................................................................................

112

5.3

Extended System Memory Area .......................................................................................

114

5.4

Main System Memory Address Range (0010_0000h to Top of Main Memory)................

115

 

5.4.1

15 MB-16 MB Window .........................................................................................

115

 

5.4.2

Pre-allocated System Memory.............................................................................

115

 

5.4.3

System Management Mode (SMM) Memory Range............................................

118

 

5.4.4

System Memory Shadowing ................................................................................

119

 

5.4.5

I/O Address Space...............................................................................................

119

 

5.4.6

GMCH Decode Rules and Cross-Bridge Address Mapping ................................

120

 

5.4.7

Hub Interface Decode Rules................................................................................

121

6.0 Functional Description .................................................................................................................

123

6.1

Host Interface Overview ...................................................................................................

123

6.2

Dynamic Bus Inversion .....................................................................................................

123

 

6.2.1

System Bus Interrupt Delivery .............................................................................

123

 

6.2.2

Upstream Interrupt Messages .............................................................................

124

6.3

System Memory Interface.................................................................................................

124

 

6.3.1

DDR SDRAM Interface Overview ........................................................................

124

 

6.3.2

System Memory Organization and Configuration ................................................

124

 

6.3.3

DDR SDRAM Performance Description...............................................................

125

6.4

Integrated Graphics Overview ..........................................................................................

126

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

 

 

6.4.1

3D/2D Instruction Processing ..............................................................................

126

 

6.4.2

3D Engine ............................................................................................................

127

 

6.4.3

Raster Engine ......................................................................................................

130

 

6.4.4

2D Engine ............................................................................................................

133

 

6.4.5

Planes and Engines.............................................................................................

134

 

6.4.6 Hardware Cursor Plane (Native Graphic Mode only) ..........................................

134

 

6.4.7

Overlay Plane ......................................................................................................

135

 

6.4.8

Video Functionality ..............................................................................................

137

6.5

Internal Graphic Display Interface ....................................................................................

138

 

6.5.1 Pipe A Timing Generator Unit..............................................................................

138

 

6.5.2

Blend Function.....................................................................................................

141

 

6.5.3 Interlaced Video Field display..............................................................................

141

 

6.5.4 Interlace support for Video Overlay Window .......................................................

143

 

6.5.5 Analog Display Port Characteristics ....................................................................

145

7.0 Power and Thermal Management ...............................................................................................

147

7.1

General Description of Supported CPU States.................................................................

148

7.2

General Description of ACPI States .................................................................................

148

7.3

Internal Thermal Sensor ...................................................................................................

149

 

7.3.1

Overview..............................................................................................................

149

 

7.3.2

Hysteresis Operation ...........................................................................................

149

7.4

External Thermal Sensor Input .........................................................................................

150

 

7.4.1

Usage ..................................................................................................................

150

8.0 Intel® 82854 GMCH Strap Pins ...................................................................................................

151

8.1

Strapping Configuration....................................................................................................

151

9.0 Ballout and Package Information.................................................................................................

153

9.1

VCC/VSS Voltage Groups ................................................................................................

154

9.2

Package Mechanical Information......................................................................................

164

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Contents

Figures

 

1

Intel® 854 Chipset system block diagram (Native Graphic mode) .............................................

16

2

Configuration Address Register..................................................................................................

45

3

Configuration Data Register .......................................................................................................

47

4

PAM Registers............................................................................................................................

62

5

Simplified View of System Address Map ..................................................................................

111

6

Detailed View of System Address Map.....................................................................................

112

7

Intel® 82854 GMCH Graphics Block Diagram (Native Graphic Mode only) .............................

126

8

ARIB TR-B15 Plane Resolutions ..............................................................................................

139

9

H, V Parameters .......................................................................................................................

140

10

Interlaced Timing Using HSYNC and VSYNC for Field1/Field2 Downstream Detection..........

140

11

Timing Register Switching ........................................................................................................

144

12

Intel® 82854 GMCH Ballout Diagram (Top View).....................................................................

153

13

Intel® 82854 GMCH Micro-FCBGA Package Dimensions (Top View) .....................................

164

14

Intel® 82854 GMCH Micro-FCBGA Package Dimensions (Side View) ....................................

165

15

Intel® 82854 GMCH Micro-FCBGA Package Dimensions (Bottom View) ................................

166

Tables

 

1

Terms and Descriptions..............................................................................................................

17

2

Reference Documents ................................................................................................................

19

3

DDR SDRAM Memory Capacity .................................................................................................

22

4

Intel® 82854 GMCH Interface Clocks .........................................................................................

25

5

Host Interface Signal Descriptions..............................................................................................

28

6

DDR SDRAM Interface Descriptions .........................................................................................

31

7

Hub Interface Signals ................................................................................................................

32

8

Clock Signals ..............................................................................................................................

33

9

Digital Video Output B (DVOB) Port Signal Descriptions ...........................................................

35

10

Digital Video Output C (DVOC) Port Signal Descriptions ...........................................................

36

11

DVOB and DVOC Port Common Signal Descriptions ...............................................................

37

12

Analog CRT Display Signal Descriptions....................................................................................

37

13

GPIO Signal Descriptions ...........................................................................................................

38

14

Voltage References, PLL Power ................................................................................................

39

15

Device Number Assignment .......................................................................................................

41

16

Nomenclature for Access Attributes ...........................................................................................

42

17

VGA I/O Mapped Register List ...................................................................................................

48

18

Index – Data Registers ...............................................................................................................

48

19

GMCH Configuration Space - Device #0, Function#0 ................................................................

49

20

Attribute Bit Assignment .............................................................................................................

61

21

PAM Registers and Associated System Memory Segments ......................................................

63

22

Host-Hub I/F Bridge/System Memory Controller Configuration Space (Device #0, Function#1)72

23

Configuration Process Configuration Space (Device#0, Function #3)........................................

92

24

Intel® 82854 GMCH Configurations and Some Resolution Examples: Native Graphics Mode.99

25

Integrated Graphics Device Configuration Space (Device #2, Function#0) ............................

100

26

System Memory Segments and Their Attributes ......................................................................

113

27

Table 33. Pre-allocated System Memory..................................................................................

115

28

SMM Space Transaction Handling ...........................................................................................

119

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

 

29

Relation of DBI Bits to Data Bits...............................................................................................

123

30

Data Bytes on DDR DIMM Used for Programming DRAM Registers.......................................

125

31

Dual Display Usage Model (Native Graphic Mode only) ..........................................................

134

32

DVO Control Data Bits..............................................................................................................

143

33

Strapping Signals and Configuration ........................................................................................

151

34

Intel® 82854 GMCH Straps for Frequency/CPU Configuration ................................................

152

35

Voltage Levels and Ball Out for Voltage Groups ......................................................................

154

36

Ballout Table ............................................................................................................................

155

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Contents

Revision History

Date

Revision

 

Description

 

 

 

 

March 2005

1.0

 

Initial release of this document.

 

 

 

 

June 2005

2.0

 

Add support for Genuine Intel® Processor at 1.2 GHz and

 

Genuine Intel® Processor at 1.5 GHz technology.

 

 

 

 

 

§ §

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

10

D15343-003

Introduction

1.0Introduction

This document is the datasheet for the Intel® 82854 Graphics Memory Controller Hub (GMCH).

1.1Overview

The Intel® 854 chipset is a combination of the Intel® 82854 Graphics Memory Controller Hub (GMCH) (Graphics Memory Controller Hub) and ICH4-M (I/O Controller Hub). The Intel 854 Chipset is designed to work with the Ultra Low Voltage (ULV) Intel® Celeron® M processor at 600 MHz with 512 KB of on-die L2 cache on an 0.13 micron process, Genuine Intel® Processor at 1.2 GHz, and Genuine Intel® Processor at 1.5 GHz. The Intel® 82854 GMCH provides highperformance, integrated graphics and manages the flow of information. Figure 1 depicts the Intel 854 chipset block diagram.

Processor/Host Bus Support

The Genuine Intel® Processor at 1.2 GHz and Genuine Intel® Processor at 1.5 GHz have the following key features:

High performance, low power core

AGTL+ bus driver technology with integrated AGTL+ termination resistors and low voltage operation

Supports Intel Architecture with Dynamic Execution

400-MHz, Source-Synchronous processor system bus

2x address, 4x data

On-die, primary 32-Kbyte instruction cache and 32-Kbyte write-back data cache

On-die, 512-Kbyte second level cache with Advanced Transfer Cache Architecture

Advanced Branch Prediction and Data Prefetch Logic

Streaming SIMD Extensions 2 (SSE2)

Advanced Power Management features

Memory System

Directly supports one DDR SDRAM channel, 64-bits wide

Supports 266/333-MHz DDR SDRAM devices with max of two, double-sided DIMM (four rows populated) with unbuffered PC2100/PC2700 DDR SDRAM.

Supports 128-Mbit, 256-Mbit, and 512-Mbit technologies providing maximum capacity of 2 GB with x16 devices

All supported devices have four banks

Supports up to 16 simultaneous open pages

Supports page sizes of 2 kB, 4 kB, 8 kB, and 16 kB. Page size is individually selected for every row

UMA support only

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

System Interrupts

Supports Intel 8259 and front side bus interrupt delivery mechanism

Supports interrupts signaled as upstream memory writes from PCI and Hub interface

MSI sent to the CPU through the system bus

IOxAPIC in ICH4-M provides redirection for upstream interrupts to the system bus

Video Stream Decoder

Hardware motion compensation for MPEG2

All video format decoder (18 ATSC video formats) supported

Dynamic Bob and Weave support for video streams

Software DVD at 60 Fields/second and 30 frames/second full screen

Support for standard definition DVD (i.e., NTSC pixel resolution of 720x480, and so on) quality encoding at low CPU utilization

Video Overlay

Single high quality scalable overlay and second Sprite to support second overlay

Multiple overlay functionality provided via arithmetic stretch BLT (Block Transfer)

5-tap horizontal, 3-tap vertical filtered scaling

Multiple overlay formats

Direct YUV from overlay to TV-out

Independent gamma correction

Independent brightness / contrast/ saturation

Independent tint/hue support

Destination colorkeying

Source chromakeying

12

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Introduction

Display

Analog display support

350-MHz integrated 24-bit RAMDAC that can drive a standard progressive scan analog monitor with pixel resolution up to 1600x1200 at 85 Hz and up to 2048x1536 at 75 Hz

Dual independent pipe support

Concurrent: different images and display timings on each display device

Simultaneous: same images and display timings on each display device

DVO (DVOB and DVOC) support

Digital video out ports DVOB and DVOC with 165-MHz dot clock on each 12-bit interface; two 12-bit channels can be combined to form one dual channel 24-bit interface with an effective dot clock of 330 MHz

The combined DVO B/C ports as well as individual DVO B/C ports can drive a variety of DVO devices (TV-Out Encoders, TMDS and LVDS transmitters, and so on) with pixel resolution up to 1600x1200 at 85 Hz and up to 2048x1536 at 72 Hz.

Compliant with DVI Specification 1.0

Tri-view support through DVO B, C port, and CRT

Internal Graphics Features

Up to 64 MB of dynamic video memory allocation

Display image rotation

Graphics core frequency at 200, 250 MHz

2D graphics engine

Optimized 128-bit BLT engine

Ten programmable and predefined monochrome patterns

Alpha Stretch BLT (via 3D pipeline)

Anti-aliased lines

Hardware-based BLT Clipping and Scissoring

32-bit Alpha Blended cursor

Programmable 64 x 64 3-color Transparent cursor

Color Space Conversion

Three Operand Raster BLTs

8-bit, 16-bit, and 32-bit color

ROP support

DIB translation and Linear/Tile addressing

Multiple hardware color cursor support (32-bit with alpha and legacy 2-bpp mode)

Accompanying I2C and DDC channels provided through multiplexed interface

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

3D graphics engine

3D setup and render engine

Enhanced Hardware Binning Instruction Set supported

Zone rendering

High quality performance texture engine

Viewpoint transform and perspective divide

Triangle lists, strips and fans support

Indexed vertex and flexible vertex formats

Pixel accurate fast scissoring and clipping operation

Backface culling support

Direct 3D support

Anti-Aliased lines support

Sprite points support

Provides the highest sustained fill rate performance in 32-bit color and 24-bit W mode

High quality performance texture engine

266-MegaTexel/s peak performance

Per pixel perspective corrected texture mapping

Single pass texture compositing (multi-textures)

Enhanced texture blending functions

Twelve level of detail MIP map sizes from 1x1 to 2k x 2k

Numerous texture formats

Alpha and Luminance maps

Texture chromakeying

Bilinear, trilinear, and anisotropic MIP map filtering

Cubic environment reflection mapping

Dot product bump-mapping

Embossed bump-mapping

DXTn texture decompression

FX1 texture compression

3D graphics rasterization enhancements

One Pixel per clock

Flat and Gouraud shading

Color alpha blending for transparency

Vertex and programmable pixel fog and atmospheric effects

Color specular lighting

Z Bias support

14

D15343-003

Introduction

Dithering

Line and full-scene anti-aliasing

16and 24-bit Z buffering

16and 24-bit W buffering

8-bit Stencil buffering

Double and triple render buffer support

16and 32-bit color

Destination alpha

Vertex cache

Optimal 3D resolution supported

Fast Clear support

ROP support

Hub Interface to ICH4-M

266-MB/s point-to-point Hub interface to ICH4-M

66-MHz base clock

Graphic Power Management

Dynamic Frequency Switching

Memory Self-Refresh during C3

Intel Display Power Saving Technology

Power Management

SMRAM space remapping to A0000h (128-kB)

Supports extended SMRAM space above 256-MB, additional 1-MB TSEG from top of memory, cacheable (cacheability controlled by CPU)

APM Rev 1.2 compliant power management

Supports Suspend to System Memory (S3), Suspend to Disk (S4) and Soft Off (S5)

ACPI 1.0b, 2.0 support

Optimized Clock Gating for 3D and Display Engines

On-Die Thermal Sensor

D15343-003

15

Intel® 82854 Graphics Memory Controller Hub (GMCH)

Package

732-pin Micro-FCBGA (37.5 x 37.5 mm)

Figure 1. Intel® 854 Chipset system block diagram (Native Graphic mode)

 

 

®

®

M

 

 

 

Intel

 

Celeron

 

 

 

 

Processor

 

 

 

 

 

 

 

 

VGA

 

 

 

 

400 MHz

 

512 MB DDR

 

 

 

 

 

 

Memory Down

333 MHz

Intel® 82854

VGA

 

 

 

 

 

 

(GMCH)

 

 

 

 

 

DVO

TV

 

 

 

 

 

 

 

 

 

 

 

ADD Slot

 

IDE

 

 

 

 

 

 

 

Intel® 82801DBM

 

6 USB

USB 2.0/1.1

 

(ICH4-M)

AC Link

Audio

 

 

 

 

 

 

Codec

LAN

LCI

 

 

 

PHY

 

LPC

 

 

 

 

FWH

 

PCI Slots

PS/2

 

SIO

 

 

 

 

Serial

16

D15343-003

Introduction

1.2Terminology

Table 1. Terms and Descriptions

Term

Description

 

 

AGTL+

Advanced Gunning Transceiver Logic + (AGTL+) bus

 

 

BLI

Backlight Inverter

 

 

Core

The internal base logic in the Intel® 82854 GMCH

CPU

Central Processing Unit

 

 

CRT

Cathode Ray Tube

 

 

DBI

Dynamic Bus inversion

 

 

DBL

Display Brightness Link

 

 

DDC

Display Data Channel (standard created by VESA)

 

 

DPMS

Display Power Management Signaling (standard created by VESA)

 

 

DVI*

Digital Visual Interface is the interface specified by the DDWG (Digital Display

 

Working Group) DVI Spec. Rev. 1.0 utilizing only the Silicon Image developed

 

TMDS protocol

 

 

DVMT

Dynamic Video Memory Technology

 

 

DVO

Digital Video Out

 

 

EDID

Extended Display Identification Data

 

 

EIST

Enhanced Intel® SpeedStep® Technology

FSB

Front side bus. Connection between Intel® 82854 GMCH and the CPU. Also

 

known as the Host interface

 

 

Full Reset

A full Intel® 82854 GMCH Reset is defined in this document when RSTIN# is

 

asserted

 

 

GMCH

Refers to the GMCH component. Throughout this datasheet, the Intel® 82854

 

Graphics Memory Controller Hub (GMCH) will be referred to as the GMCH.

 

 

HD

High definition, typically MP@HL for MPEG2; Resolution supported are 720p,

 

1080i and 1080p

 

 

Host

This term is used synonymously with processor

 

 

Hub Interface (HI)

The proprietary interconnect between the Intel® 82854 GMCH and the ICH4-M

 

component. In this document, the Hub interface cycles originating from or

 

destined for the ICH4-M are generally referred to as “Hub interface cycles.” Hub

 

cycles originating from or destined for the primary PCI interface on are

 

sometimes referred to as “Hub interface/PCI cycles”

 

 

I2C

Inter-IC (a two wire serial bus created by Philips)

IGD

Integrated Graphics Device

 

 

D15343-003

17

Intel® 82854 Graphics Memory Controller Hub (GMCH)

Intel 82801DBM ICH4-M

The component contains the primary PCI interface, LPC interface, USB 2.0,

 

ATA-100, AC’97, and other I/O functions. It communicates with the Intel® 82854

 

GMCH over a proprietary interconnect called the Hub interface. Throughout this

 

datasheet, the Intel 82801DBM ICH4-M component will be referred to as the

 

ICH4-M

 

 

IPI

Inter Processor Interrupt

 

 

LCD

Liquid Crystal Display

 

 

MSI

Message Signaled Interrupts. MSI allow a device to request interrupt service via

 

a standard memory write transaction instead of through a hardware signal

 

 

Native Graphic Mode

The Intel® 82854 GMCH can support RGB and Dual Independent Display in this

 

mode

 

 

PWM

Pulse Width Modulation

 

 

SD

Standard definition, typically MP@ML for MPEG2

 

 

SSC

Spread Spectrum Clocking

 

 

STB

Set Top Box

 

 

System Bus

Processor-to-Intel® 82854 GMCH interface. The Enhanced mode of the

 

Scalable bus is the P6 Bus plus enhancements, consisting of source

 

synchronous transfers for address and data, and system bus interrupt delivery.

 

The Intel Celeron M processor implements a subset of Enhanced mode.

 

 

UMA

Unified Memory Architecture with graphics memory for the IGD inside system

 

memory

 

 

VDL

Video Data Link

 

 

18

D15343-003

Introduction

1.3Reference Documents

Table 2.

Reference Documents

 

 

 

 

 

Document

Location

 

 

 

 

Intel® Celeron® M Processor Datasheet

http://www.intel.com/design/mobile/datashts/300302.htm

 

 

 

 

Ultra Low Voltage Intel(R) Celeron(R) M

http://developer.intel.com/design/intarch/datashts/

 

Processor at 600 MHz Addendum to the

301753.htm

 

Intel(R) Celeron(R) M Processor Datasheet

 

 

 

 

 

Intel® 854 Chipset Platform Design Guide

Please contact your local Intel representative for this

 

for Use with Ultra Low Voltage Intel®

document.

 

Celeron® M Processor at 600 MHz

 

 

 

 

 

PCI Local Bus Specification 2.2

http://www.pcisig.com

 

 

 

 

Intel® 82801DBM I/O Controller Hub 4

http://developer.intel.com/design/mobile/datashts/

 

Mobile (ICH4-M) Datasheet

252337.htm

 

 

 

 

Advanced Configuration and Power

http://www.acpi.info/

 

Management (ACPI) Specification 1.0b &

 

 

2.0

 

 

 

 

 

IA-32 Intel® Architecture Software

http://developer.intel.com/design/pentium4/manuals/

 

Developer Manual Volume 3: System

245472.htm

 

Programming Guide

 

 

 

 

 

INTEL® DIGITAL VIDEO OUT (DVO) PORT

Please contact your local Intel representative for this

 

HARDWARE EXTERNAL DESIGN

document.

 

SPECIFICATION (EDS) VER – 2.X

 

 

 

 

 

ARIB TR-B15 Operational Guidelines for

http://www.arib.or.jp/english/html/overview/ov/tr_b15.html

 

Digital Satellite Broadcasting (detailed

 

 

Implementation guideline for receiver)

 

 

 

 

 

ATSC Standards

http://www.atsc.org/standards.html

 

 

 

D15343-003

19

Intel® 82854 Graphics Memory Controller Hub (GMCH)

20

D15343-003

Intel® 82854 GMCH Overview

2.0Intel® 82854 GMCH Overview

2.1System Architecture

The Intel® 82854 GMCH includes a processor interface, DDR SDRAM interface, display interface, and Hub interface.

Combined with the ULV Intel® Celeron® M Processor or Genuine Intel® Processor, and an ICH4- M, it provides many of the functions required to deliver the features below:

Overall system software platform

Graphic overlay function for the GUI and 3-D graphics for gaming.

Soft CODEC function

STB middleware execution

New STB embedded applications requiring IA level of high performance.

2.1.1Intel® 82854 GMCH

The Intel® 82854 GMCH is in a 732-pin Micro-FCBGA package that contains the following functionality listed below:

AGTL+ host bus supporting 32-bit host addressing with Enhanced Intel SpeedStep technology support

Supports a single channel of DDR SDRAM memory

System memory supports DDR 266/333 MHz (SSTL_2) DDR SDRAM

Integrated graphics capabilities: Graphic Core frequency at 200, 250 MHz

Supports three display ports: one progressive scan analog monitor and two DVO ports.

Enhanced Power Management Graphics features

D15343-003

21

Intel® 82854 Graphics Memory Controller Hub (GMCH)

2.2Processor Host Interface

The Intel® 82854 GMCH supports the Intel Celeron M Processor, and Genuine Intel Processor.

Key features of the front side bus (FSB) are:

Support for a 400-MHz system bus frequency.

Source synchronous double pumped address (2X)

Source synchronous quad pumped data (4X)

Front side bus interrupt delivery

Low voltage swing Vtt (1.05 ~ 1.55V)

Dynamic Power Down (DPWR#) support

Integrates AGTL+ termination resistors on all of the AGTL+ signals

Supports 32-bit host bus addressing allowing the CPU to access the entire 4 GB of the GMCH memory address space.

An 8-deep, In-Order queue

Support DPWR# signal

Supports one outstanding defer cycle at a time to any particular I/O interface

2.3GMCH System Memory Interface

The GMCH system memory controller directly supports the following:

One channel of PC2100/2700 DIMM DDR SDRAM memory

DDR SDRAM devices with densities of 128-Mb, 256-Mb, and 512-Mb technology

Up to 1 GB (512-Mb technology) with two DDR DIMMs

Up to 2 GB (512-Mb technology) using high density devices with two DDR DIMMs

Table 3. DDR SDRAM Memory Capacity

Technology

Width

System Memory Capacity

System Memory Capacity

with Stacked Memory

 

 

 

 

 

 

 

128 Mb

16

256 MB

-

 

 

 

 

256 Mb

16

512 MB

-

 

 

 

 

512 Mb

16

1 GB

-

 

 

 

 

128 Mb

8

256 MB

512 MB

 

 

 

 

256 Mb

8

512 MB

1 GB

 

 

 

 

512 Mb

8

1 GB

2 GB

 

 

 

 

The GMCH system memory interface supports a thermal throttling scheme to selectively throttle reads and/or writes. Throttling can be triggered either by the on-die thermal sensor, or by preset write bandwidth limits. Read throttle can also be triggered by an external input pin. The memory controller logic supports aggressive Dynamic Row Power Down features to help reduce power and supports Address and Control line tri-stating when DDR SDRAM is in an active power down or in self refresh state.

22

D15343-003

Intel® 82854 GMCH Overview

The GMCH system memory architecture is optimized to maintain open pages (up to 16-KB page size) across multiple rows. As a result, up to 16 pages across four rows is supported. To complement this, the GMCH will tend to keep pages open within rows, or will only close a single bank on a page miss. The GMCH supports only four bank memory technologies.

2.4Graphics Features

The GMCH IGD provides a highly integrated graphics accelerator delivering high performance 2D, 3D, and video capabilities. With its interfaces to UMA using a DVMT configuration, an analog display, and two digital display ports, the GMCH can provide a complete graphics solution.

The GMCH also provides 2D hardware acceleration for block transfers of data (BLTs). The BLT engine provides the ability to copy a source block of data to a destination and perform raster operations (for example, ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination. Performing these common tasks in hardware reduces CPU load, and thus improves performance.

High bandwidth access to data is provided through the system memory interface. The GMCH uses Tiling architecture to increase system memory efficiency and thus maximize effective rendering bandwidth. The Intel® 82854 GMCH improves 3D performance and quality with 3D Zone rendering technology. The Intel® 82854 GMCH also supports Video Mixer rendering, and BiCubic filtering.

2.5Display Features

The Intel® 82854 GMCH has three display ports: one analog and two digital. With these interfaces, the GMCH can provide support for a progressive scan analog monitor and two DVO ports. The native graphic mode is able to deliver up to two streams of data via the two DVO ports.

2.5.1GMCH Analog Display Port

The Intel® 82854 GMCH has an integrated 350-MHz, 24-bit RAMDAC that can directly drive a progressive scan analog monitor pixel resolution up to 1600x1200 at 85-Hz refresh and up to 2048x1536 at 75-Hz refresh. In the native graphic mode, the Analog display port can be driven by Pipe A or Pipe B.

2.5.2GMCH Integrated DVO Ports

The Intel® 82854 GMCH provides a digital display channel that is capable of driving a pixel clock up to 165 MHz.

The GMCH supports three ARIB planes of graphics: Still Picture Plane, Text and Graphic Plane, and Superimpose Text Plane at a frame rate of 10 fps. A minimum of two displays are supported. The ARIB plane resolutions supported can be found in Figure 8.

In native graphics mode, the GMCH supports a single display up to 60 fps real time with maximum resolution of 720 x 480 pixels.

D15343-003

23

Intel® 82854 Graphics Memory Controller Hub (GMCH)

2.6Hub Interface

A proprietary interconnect connects the GMCH to the ICH4-M. All communication between the GMCH and the ICH4-M occurs over the Hub interface 1.5. The Hub interface runs at 66 MHz (266-MB/s).

2.7Address Decode Policies

Host initiated I/O cycles are positively decoded to the GMCH configuration space and subtractively decoded to the Hub interface. Host initiated system memory cycles are positively decoded to DDR SDRAM and are again subtractively decoded to the Hub interface, if less than 4 GB. System memory accesses from the Hub interface to DDR SDRAM will be snooped on the FSB.

24

D15343-003

Intel® 82854 GMCH Overview

2.8GMCH Clocking

The GMCH has the following clock input/output pins:

400-MHz, spread spectrum, low voltage differential BCLK, BCLK# for front side bus (FSB)

66-MHz, 3.3-V GCLKIN for Hub interface buffers

Six pairs of differential output clocks (SCK[5:0], SCK[5:0]#), 200/266 MHz, 2.5 V for system memory interface

48-MHz, non-Spread Spectrum, 3.3-V DREFCLK for the Display Frequency Synthesis

8-MHz or 66-MHz, Spread Spectrum, 3.3-V DREFSSCLK for the Display Frequency Synthesis

Up to 148.5 MHz, 1.5-V DVOBCCLKINT for TV-Out mode

DPMS clock for S1-M

Clock Synthesizer chips are responsible for generating the system host clocks, GMCH display clocks, Hub interface clocks, PCI clocks, SIO clocks, and FWH clocks. The host target speed is 400 MHz. The GMCH does not require any relationship between the BCLK Host clock and the 66-MHz clock generated for the Hub interface; they are asynchronous to each other. The Hub interface runs at a constant 66-MHz base frequency. Table 4 indicates the frequency ratios between the various interfaces that the GMCH supports.

Table 4. Intel® 82854 GMCH Interface Clocks

 

 

CPU System

Samples

Data Rate

Data

Peak

Interface

Clock Speed

Bus Frequency

(Mega-

Width

Bandwidth

Per Clock

 

 

Ratio

samples/s)

(Bytes)

(MB/s)

 

 

 

 

 

 

 

 

 

 

CPU Bus

100 MHz

Reference

4

400

8

3200

 

 

 

 

 

 

 

DDR SDRAM

133 MHz

1:1 Synchronous

2

266

8

2128

 

 

 

 

 

 

 

 

166 MHz

1:1 Synchronous

2

333

8

2664

 

 

 

 

 

 

 

DVO B or DVO C

Up to 165

Asynchronous

2

330

1.5

495

(Native Graphic

MHz

 

 

 

 

 

Mode)

 

 

 

 

 

 

 

 

 

 

 

 

 

DVO B+DVO C

Up to 330

Asynchronous

2

660

3

1980

(Native Graphic

MHz

 

 

 

 

 

Mode)

 

 

 

 

 

 

 

 

 

 

 

 

 

DAC Interface

350 MHz

Asynchronous

1

350

3

1050

 

 

 

 

 

 

 

D15343-003

25

Intel® 82854 Graphics Memory Controller Hub (GMCH)

2.9System Interrupts

The GMCH supports both the legacy Intel 8259 Programmable Interrupt delivery mechanism and the Intel Celeron M processor FSB interrupt delivery mechanism. The serial APIC Interrupt mechanism is not supported.

The Intel 8259 Interrupt delivery mechanism support consists of flushing in bound Hub interface write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the Hub interface.

PCI MSI interrupts are generated as memory writes. The GMCH decodes upstream memory writes to the range 0FEE0_0000h - 0FEEF_FFFFh from the Hub interface as message based interrupts. The GMCH forwards the memory writes along with the associated write data to the system bus as an Interrupt Message transaction. Since this address does not decode as part of main system memory, the write cycle and the write data do not get forwarded to system memory via the write buffer. The GMCH provides the response and HTRDY# for all Interrupt Message cycles including the ones originating from the GMCH. The GMCH also supports interrupt redirection for upstream interrupt memory writes.

For message based interrupts, system write buffer coherency is maintained by relying on strict ordering of memory writes. The GMCH ensures that all memory writes received from a given interface prior to an interrupt message memory write are delivered to the system bus for snooping in the same order that they occur on the given interface.

26

D15343-003

Signal Description

3.0Signal Description

This section describes the Intel® 82854 GMCH signals. These signals are arranged in functional groups according to their associated interface. The following notations are used to describe the signal type.

Notation

Description

 

 

I

Input pin

 

 

O

Output pin

 

 

I/O

Bi-directional Input/Output pin

 

 

The signal description also includes the type of buffer used for the particular signal:

Buffer

Description

 

 

AGTL+

Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O

 

Specification for complete details. The GMCH integrates AGTL+

 

termination resistors, and supports VTTLF of 1.05 V ± 5%. AGTL+

 

signals are "inverted bus" style where a low voltage represents a

 

logical 1.

 

 

DVO

DVO buffers (1.5-V tolerant)

 

 

Hub

Compatible to Hub interface 1.5

 

 

SSTL_2

Stub Series Termination Logic compatible signals (2.5-V tolerant)

 

 

LVTTL

Low Voltage TTL compatible signals (3.3-V tolerant)

 

 

CMOS

CMOS buffers (3.3-V tolerant)

 

 

Analog

Analog signal interface

 

 

Ref

Voltage reference signal

 

 

Note: System Address and Data Bus signals are logically inverted signals. In other words, the actual values are inverted from what appears on the system bus. This must be taken into account and the addresses and data bus signals must be inverted inside the GMCH. All processor control signals follow normal convention: A 0 indicates an active level (low voltage), and a 1 indicates an active level (high voltage).

D15343-003

27

Intel® 854 Graphics Memory Controller Hub (GMCH)

3.1Host Interface Signals

Table 5. Host Interface Signal Descriptions

Signal Name

Type

Description

 

 

 

ADS#

I/O

Address Strobe: The system bus owner asserts ADS# to indicate the

 

AGTL+

first of two cycles of a request phase. The GMCH can assert this signal

 

 

for snoop cycles and interrupt messages.

 

 

 

BNR#

I/O

Block Next Request: Used to block the current request bus owner from

 

AGTL+

issuing a new request. This signal is used to dynamically control the CPU

 

 

bus pipeline depth.

 

 

 

BPRI#

O

Bus Priority Request: The GMCH is the only Priority Agent on the

 

AGTL+

system bus. It asserts this signal to obtain the ownership of the address

 

 

bus. This signal has priority over symmetric bus requests and will cause

 

 

the current symmetric owner to stop issuing new transactions unless the

 

 

HLOCK# signal was asserted.

 

 

 

BREQ0#

I/O

Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal

 

AGTL+

low during CPURST#. The signal is sampled by the processor on the

 

 

active-to-inactive transition of CPURST#. The minimum setup time for

 

 

this signal is 4 BCLKs. The minimum hold time is 2 clocks and the

 

 

maximum hold time is 20 BCLKs. BREQ0# should be tristated after the

 

 

hold time requirement has been satisfied.

 

 

During regular operation, the GMCH will use BREQ0# as an early

 

 

indication for FSB Address and Ctl input buffer and sense amp activation.

 

 

 

CPURST#

O

CPU Reset: The CPURST# pin is an output from the GMCH. The

 

AGTL+

GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M) is

 

 

asserted and for approximately 1 ms after RESET# is deasserted. The

 

 

CPURST# allows the processor to begin execution in a known state.

 

 

Note that the ICH4-M must provide CPU strap set-up and hold-times

 

 

around CPURST#. This requires strict synchronization between GMCH,

 

 

CPURST# deassertion and ICH4-M driving the straps.

 

 

 

DBSY#

I/O

Data Bus Busy: Used by the data bus owner to hold the data bus for

 

AGTL+

transfers requiring more than one cycle.

 

 

 

DEFER#

O

Defer: GMCH will generate a deferred response as defined by the rules

 

AGTL+

of the GMCH’s Dynamic Defer policy. The GMCH will also use the

 

 

DEFER# signal to indicate a CPU retry response.

 

 

 

DINV[3:0]#

I/O

Dynamic Bus Inversion: Driven along with the HD[63:0]# signals.

 

AGTL+

Indicates if the associated signals are inverted or not. DINV[3:0]# are

 

 

asserted such that the number of data bits driven electrically low (low

 

 

voltage) within the corresponding 16-bit group never exceeds 8.

 

 

DINV#

Data Bits

 

 

DINV[3]#

HD[63:48]#

 

 

DINV[2]#

HD[47:32]#

 

 

DINV[1]#

HD[31:16]#

 

 

DINV[0]#

HD[16:0]#

 

 

 

DPSLP#

I

Deep Sleep #: This signal comes from the ICH4-M device, providing an

 

CMOS

indication of C3 and C4 state control to the CPU. Deassertion of this

 

signal is used as an early indication for C3 and C4 wake up (to active

 

 

 

 

HPLL). Note that this is a low-voltage CMOS buffer operating on the FSB

 

 

VTT power plane.

 

 

 

 

28

D15343-003

 

 

 

 

Signal Description

 

 

 

DRDY#

I/O

Data Ready: Asserted for each cycle that data is transferred.

 

AGTL+

 

 

 

 

 

 

HA[31:3]#

I/O

Host Address Bus: HA[31:3]# connects to the CPU address bus. During

 

AGTL+

processor cycles the HA[31:3]# are inputs. The GMCH drives HA[31:3]#

 

 

during snoop cycles on behalf of Hub interface. HA[31:3]# are

 

 

transferred at 2x rate. Note that the address is inverted on the CPU bus.

 

 

 

HADSTB[1:0]#

I/O

Host Address Strobe: HA[31:3]# connects to the CPU address bus.

 

AGTL+

During CPU cycles, the source synchronous strobes are used to transfer

 

 

HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.

 

 

Strobe

Address Bits

 

 

HADSTB[0]#

HA[16:3]#, HREQ[4:0]#

 

 

HADSTB[1]#

HA[31:17]#

 

 

 

HD[63:0]#

I/O

Host Data: These signals are connected to the CPU data bus.

 

AGTL+

HD[63:0]# are transferred at 4x rate. Note that the data signals are

 

 

inverted on the CPU bus.

 

 

 

 

HDSTBP[3:0]#

I/O

Differential Host Data Strobes: The differential source synchronous

HDSTBN[3:0]#

AGTL+

strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4x

 

transfer rate.

 

 

 

 

 

 

 

 

Strobe

 

Data Bits

 

 

HDSTBP[3]#, HDSTBN[3]#

HD[63:48]#, DINV[3]#

 

 

HDSTBP[2]#, HDSTBN[2]#

HD[47:32]#, DINV[2]#

 

 

HDSTBP[1]#, HDSTBN[1]#

HD[31:16]#, DINV[1]#

 

 

HDSTBP[0]#, HDSTBN[0]#

HD[15:0]#, DINV[0]#

 

 

 

HIT#

I/O

Hit: Indicates that a caching agent holds an unmodified version of the

 

AGTL+

requested line. Also, driven in conjunction with HITM# by the target to

 

 

extend the snoop window.

 

 

 

 

HITM#

I/O

Hit Modified: Indicates that a caching agent holds a modified version of

 

AGTL+

the requested line and that this agent assumes responsibility for

 

 

providing the line. Also, driven in conjunction with HIT# to extend the

 

 

snoop window.

 

 

 

 

 

HLOCK#

I/O

Host Lock: All CPU bus cycles sampled with the assertion of HLOCK#

 

AGTL+

and ADS#, until the negation of HLOCK# must be atomic; that is, no Hub

 

 

interface snoopable access to system memory is allowed when HLOCK#

 

 

is asserted by the CPU.

 

 

 

 

HREQ[4:0]#

I/O

Host Request Command: Defines the attributes of the request.

 

AGTL+

HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting agent

 

 

during both halves of the Request Phase. In the first half the signals

 

 

define the transaction type to a level of detail that is sufficient to begin a

 

 

snoop request. In the second half the signals carry additional information

 

 

to define the complete transaction type.

 

 

The transactions supported by the GMCH Host Bridge are defined in the

 

 

Host Interface section of this document.

 

 

 

HTRDY#

O

Host Target Ready: Indicates that the target of the processor

 

AGTL+

transaction is able to enter the data transfer phase.

 

 

 

 

 

D15343-003

29

Intel® 854 Graphics Memory Controller Hub (GMCH)

RS[2:0]#

O

Response Status: Indicates the type of response according to the

 

AGTL+

following the table:

 

 

RS[2:0]#

Response type

 

 

000

Idle state

 

 

001

Retry response

 

 

010

Deferred response

 

 

011

Reserved (not driven by GMCH)

 

 

100

Hard Failure (not driven by GMCH)

 

 

101

No data response

 

 

110

Implicit Write back

 

 

111

Normal data response

 

 

 

 

30

D15343-003

Signal Description

3.2DDR SDRAM Interface

Table 6.

DDR SDRAM Interface Descriptions

 

 

 

 

 

Signal Name

Type

Description

 

 

 

 

 

SCS[3:0]#

O

Chip Select: These pins select the particular DDR SDRAM

 

 

SSTL_2

components during the active state.

 

 

 

NOTE: There is one SCS# per DDR-SDRAM Physical DDR DIMM

 

 

 

device row. These signals can be toggled on every rising System

 

 

 

Memory Clock edge (SCMDCLK).

 

 

 

 

 

SMA[12:0]

O

Multiplexed Memory Address: These signals are used to provide the

 

 

SSTL_2

multiplexed row and column address to the DDR SDRAM.

 

 

 

 

 

SBA[1:0]

O

Bank Select (Memory Bank Address): These signals define which

 

 

SSTL_2

banks are selected within each DDR SDRAM row. The SMA and SBA

 

 

 

signals combine to address every possible location within a DDR

 

 

 

SDRAM device.

 

 

 

 

 

SRAS#

O

DDR Row Address Strobe: SRAS# may be heavily loaded and

 

 

SSTL_2

requires tw0 DDR SDRAM clock cycles for setup time to the DDR

 

 

 

SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define the

 

 

 

system memory commands.

 

 

 

 

 

SCAS#

O

DDR Column Address Strobe: SCAS# may be heavily loaded and

 

 

SSTL_2

requires two clock cycles for setup time to the DDR SDRAMs. Used

 

 

 

with SRAS# and SWE# (along with SCS#) to define the system memory

 

 

 

commands.

 

 

 

 

 

SWE#

O

Write Enable: Used with SCAS# and SRAS# (along with SCS#) to

 

 

SSTL_2

define the DDR SDRAM commands. SWE# is asserted during writes to

 

 

 

DDR SDRAM. SWE# may be heavily loaded and requires two clock

 

 

 

cycles for setup time to the DDR SDRAMs.

 

 

 

 

 

SDQ[63:0]

I/O

Data Lines: These signals are used to interface to the DDR SDRAM

 

 

SSTL_2

data bus.

 

 

 

 

 

 

I/O

Data Strobes: Data strobes are used for capturing data. During writes,

 

SDQS[8:0]

SSTL_2

SDQS is centered on data. During reads, SDQS is edge aligned with

 

 

data. The following list matches the data strobe with the data bytes.

 

 

 

 

 

 

There is an associated data strobe (DQS) for each data signal (DQ) and

 

 

 

check bit (CB) group.

 

 

 

SDQS[7] -> SDQ[63:56]

 

 

 

SDQS[6] -> SDQ[55:48]

 

 

 

SDQS[5] -> SDQ[47:40]

 

 

 

SDQS[4] -> SDQ[39:32]

 

 

 

SDQS[3] -> SDQ[31:24]

 

 

 

SDQS[2] -> SDQ[23:16]

 

 

 

SDQS[1] -> SDQ[15:8]

 

 

 

SDQS[0] -> SDQ[7:0]

 

 

 

 

 

SCKE[3:0]

O

Clock Enable: These pins are used to signal a self-refresh or power

 

 

SSTL_2

down command to the DDR SDRAM array when entering system

 

 

 

suspend. SCKE is also used to dynamically power down inactive DDR

 

 

 

SDRAM rows. There is one SCKE per DDR SDRAM row. These

 

 

 

signals can be toggled on every rising SCK edge.

 

 

 

 

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31

Intel® 854 Graphics Memory Controller Hub (GMCH)

SMAB[5,4,2,1]

O

Memory Address Copies: These signals are identical to SMA[5,4,2,1]

 

SSTL_2

and are used to reduce loading for selective CPC(clock-per-command).

 

These copies are not inverted.

 

 

 

 

 

SDM[8:0]

O

Data Mask: When activated during writes, the corresponding data

 

SSTL_2

groups in the DDR SDRAM are masked. There is one SDM for every

 

eight data lines. SDM can be sampled on both edges of the data

 

 

 

 

strobes.

 

 

 

RCVENOUT#

O

Clock Output: Reserved, NC.

 

SSTL_2

 

 

 

 

RCVENIN#

O

Clock Input: Reserved, NC.

 

SSTL_2

 

 

 

 

3.3Hub Interface Signals

Table 7.

Hub Interface Signals

 

 

 

 

 

 

Signal Name

Type

Description

 

 

 

 

 

HL[10:0]

I/O Hub

Packet Data: Data signals used for HI read and write operations.

 

 

 

 

 

HLSTB

I/O Hub

Packet Strobe: One of two differential strobe signals used to transmit or

 

 

 

receive packet data over HI.

 

 

 

 

 

HLSTB#

I/O Hub

Packet Strobe Complement: One of two differential strobe signals used

 

 

 

to transmit or receive packet data over HI.

 

 

 

 

32

D15343-003

Signal Description

3.4Clocks

Table 8. Clock Signals

Signal Name

Type

Description

 

 

 

Host Processor Clocking

 

 

 

 

BCLK

I

Differential Host Clock In: These pins receive a buffered host clock

BCLK#

CMOS

from the external clock synthesizer. This clock is used by all of the

GMCH logic that are in the Host clock domain (Host, Hub and system

 

 

 

 

memory). The clock is also the reference clock for the graphics core

 

 

PLL. This is a low voltage differential input.

 

 

 

System Memory Clocking

 

 

 

 

SCK[5:0]

O

Differential DDR SDRAM Clock: SCK and SCK# pairs are differential

 

SSTL_2

clock outputs. The crossing of the positive edge of SCK and the

 

negative edge of SCK# is used to sample the address and control

 

 

 

 

signals on the DDR SDRAM. There are 3 pairs to each DDR DIMM.

 

 

 

SCK[5:0]#

O

Complementary Differential DDR SDRAM Clock: These are the

 

SSTL_2

complimentary differential DDR SDRAM clock signals.

 

 

 

 

 

DVO/Hub Input Clocking

 

 

 

 

GCLKIN

I

Input Clock: 66-MHz, 3.3-V input clock from external buffer DVO/Hub

 

CMOS

interface.

 

 

 

 

 

DVO Clocking

 

 

 

 

 

DVOBCLK

O

Differential DVO Clock Output: These pins provide a differential pair

DVOBCLK#

DVO

reference clock that can run up to 165-MHz.

 

 

DVOBCLK corresponds to the primary clock out.

 

 

DVOBCLK# corresponds to the primary complementary clock out.

 

 

DVOBCLK and DVOBCLK# should be left as NC (“Not Connected”) if

 

 

the DVO B port is not implemented.

 

 

 

DVOCCLK

O

Differential DVO Clock Output: These pins provide a differential pair

DVOCCLK#

DVO

reference clock that can run up to 165-MHz.

 

 

DVOCCLK corresponds to the primary clock out.

 

 

DVOCCLK# corresponds to the primary complementary clock out.

 

 

DVOCCLK and DVOCCLK# should be left as NC (“Not Connected”) if

 

 

the DVO C port is not implemented.

 

 

 

DVOBCCLKINT

I

DVOBC Pixel Clock Input/Interrupt: This signal may be selected as

 

DVO

the reference input to either dot clock PLL (DPLL) or may be

 

configured as an interrupt input. A TV-out device can provide the clock

 

 

 

 

reference. The maximum input frequency for this signal is 148.5 -MHz.

 

 

DVOBC Pixel Clock Input: When selected as the dot clock PLL (DPLL)

 

 

reference input, this clock reference input supports SSC clocking for

 

 

DVO LVDS devices.

 

 

DVOBC Interrupt: When configured as an interrupt input, this interrupt

 

 

can support either DVOB or DVOC.

 

 

DVOBCCLKINT needs to be pulled down if the signal is NOT used.

 

 

 

D15343-003

33

Intel® 854 Graphics Memory Controller Hub (GMCH)

DPMS

I

Display Power Management Signaling: This signal is used only in

 

DVO

mobile systems to act as the DREFCLK in certain power management

 

states (i.e., Display Power Down Mode); DPMS Clock is used to

 

 

 

 

refresh video during S1-M. Clock Chip is powered down in S1-M.

 

 

DPMS should come from a clock source that runs during S1-M and

 

 

needs to be 1.5 V. So, an example would be to use a 1.5-V version of

 

 

SUSCLK from ICH4-M.

 

 

 

DAC Clocking

 

 

 

 

 

DREFCLK

I

Display Clock Input: This pin is used to provide a 48-MHz input clock

 

LVTTL

to the Display PLL that is used for 2D/Video and DAC.

 

 

 

 

 

34

D15343-003

Signal Description

3.5Internal Graphics Display Signals

The IGD has support for DVOB/C interfaces, and an Analog CRT port.Digital Video Output B (DVOB) Port.

3.5.1Digital Video Output B (DVOB) Port

Table 9. Digital Video Output B (DVOB) Port Signal Descriptions

Name

Type

Description

 

 

 

DVOBD[11:0]

O

DVOB Data: This data bus is used to drive 12-bit RGB data on each edge

 

DVO

of the differential clock signals, DVOBCLK and DVOBCLK#. This provides

 

24-bits of data per clock period. In dual channel mode, this provides the

 

 

 

 

lower 12-bits of pixel data.

 

 

DVOBD[11:0] should be left as NC (“Not Connected”) if not used.

 

 

 

DVOBHSYNC

O

Horizontal Sync: HSYNC signal for the DVOB interface.

 

DVO

DVOBHSYNC should be left as left as NC (“Not Connected”) if not used.

 

 

 

DVOBVSYNC

O

Vertical Sync: VSYNC signal for the DVOB interface.

 

DVO

DVOBVSYNC should be left as left as NC (“Not Connected”) if the signal

 

 

is NOT used when using internal graphics device.

 

 

 

DVOBBLANK#

O

Flicker Blank or Border Period Indication: DVOBBLANK# is a

 

DVO

programmable output pin driven by the GMCH.

 

When programmed as a blank period indication, this pin indicates active

 

 

 

 

pixels excluding the border. When programmed as a border period

 

 

indication, this pin indicates active pixel including the border pixels.

 

 

DVOBBLANK# should be left as left as NC (“Not Connected”) if not used.

 

 

 

DVOBFLDSTL

I

TV Field and Flat Panel Stall Signal. This input can be programmed to

 

DVO

be either a TV Field input from the TV encoder or Stall input from the flat

 

panel.

 

 

 

 

DVOB TV Field Signal: When used as a Field input, it synchronizes the

 

 

overlay field with the TV encoder field when the overlay is displaying an

 

 

interleaved source.

 

 

DVOB Flat Panel Stall Signal: When used as the Stall input, it indicates

 

 

that the pixel pipeline should stall one horizontal line. The signal changes

 

 

during horizontal blanking. The panel fitting logic, when expanding the

 

 

image vertically, uses this.

 

 

DVOBFLDSTL needs to be pulled down if not used.

 

 

 

D15343-003

35

Intel® 854 Graphics Memory Controller Hub (GMCH)

3.5.2Digital Video Output C (DVOC) Port

Table 10. Digital Video Output C (DVOC) Port Signal Descriptions

Name

Type

Description

 

 

 

DVOCD[11:0]

O

[Native Graphic Mode]

 

DVO

DVOC Data: This data bus is used to drive 12-bit RGB data on each edge

 

 

of the differential clock signals, DVOCCLK and DVOCCLK#. This

 

 

provides 24-bits of data per clock period. In dual channel mode, this

 

 

provides the upper 12-bits of pixel data.

 

 

DVOCD[11:0] should be left as left as NC (“Not Connected”) if not used.

 

 

 

DVOCHSYNC

O

Horizontal Sync: HSYNC signal for the DVOC interface.

 

DVO

DVOCHSYNC should be left as left as NC (“Not Connected”) if not used.

 

 

 

DVOCVSYNC

O

Vertical Sync: VSYNC signal for the DVOC interface.

 

DVO

DVOCVSYNC should be left as left as NC (“Not Connected”) if the signal

 

 

is NOT used when using internal graphics device.

 

 

 

DVOCBLANK#

O

Flicker Blank or Border Period Indication: DVOCBLANK# is a

 

DVO

programmable output pin driven by the GMCH.

 

When programmed as a blank period indication, this pin indicates active

 

 

 

 

pixels excluding the border. When programmed as a border period

 

 

indication, this pin indicates active pixel including the border pixels.

 

 

DVOCBLANK# should be left as left as NC (“Not Connected”) if not used.

 

 

 

DVOCFLDSTL

I

TV Field and Flat Panel Stall Signal. This input can be programmed to

 

DVO

be either a TV Field input from the TV encoder or Stall input from the flat

 

panel.

 

 

 

 

DVOC TV Field Signal: When used as a Field input, it synchronizes the

 

 

overlay field with the TV encoder field when the overlay is displaying an

 

 

interleaved source.

 

 

DVOC Flat Panel Stall Signal: When used as the Stall input, it indicates

 

 

that the pixel pipeline should stall one horizontal line. The signal changes

 

 

during horizontal blanking. The panel fitting logic, when expanding the

 

 

image vertically, uses this.

 

 

DVOCFLDSTL needs to be pulled down if not used.

 

 

 

36

D15343-003

Signal Description

Table 11. DVOB and DVOC Port Common Signal Descriptions

Name

Type

Description

 

 

 

DVOBCINTR#

I

DVOBC Interrupt: This pin is used to signal an interrupt, typically used to

 

DVO

indicate a hot plug or unplug of a digital display.

 

 

 

 

 

ADDID[7:0]

I

ADDID[7:0]: These pins are used to communicate to the Video BIOS

 

DVO

when an external device is interfaced to the DVO port.

 

Note: Bit[7] needs to be strapped low when an on-board DVO device is

 

 

 

 

present. The other pins should be left as NC.

 

 

ADDID[0] = 0, Reserve

 

 

ADDID[0] = 1, the Intel® 82854 GMCH is strapped to operate under

 

 

Native Graphic Mode

 

 

For detail of strapping option, please refer to Table 33.

 

 

 

DVODETECT

I

DVODETECT: This strapping signal indicates to the GMCH whether a

 

DVO

DVO device is present or not. When a DVO device is connected, then

 

DVODETECT = 0.

 

 

 

 

 

3.5.3Analog CRT Display

Table 12. Analog CRT Display Signal Descriptions

Pin Name

Type

Description

 

 

 

VSYNC

O

CRT Vertical Synchronization: This signal is used as the vertical sync signal.

 

CMOS

 

 

 

 

HSYNC

O

CRT Horizontal Synchronization: This signal is used as the horizontal sync

 

CMOS

signal.

 

 

 

 

 

RED

O

Red (Analog Video Output): This signal is a CRT Analog video output from

 

Analog

the internal color palette DAC. The DAC is designed for a 37.5-Ω equivalent

 

load on each pin (that is, a 75-Ω resistor on the board, in parallel with the 75-Ω

 

 

 

 

CRT load).

 

 

 

RED#

O

Red# (Analog Output): Tied to ground.

 

Analog

 

 

 

 

GREEN

O

Green (Analog Video Output): This signal is a CRT analog video output from

 

Analog

the internal color palette DAC. The DAC is designed for a 37.5-Ω equivalent

 

load on each pin (that is, a 75-Ω resistor on the board, in parallel with the 75- Ω

 

 

 

 

CRT load).

 

 

 

GREEN#

O

Green# (Analog Output): Tied to ground.

 

Analog

 

 

 

 

BLUE

O

Blue (Analog Video Output) : This signal is a CRT Analog video output from

 

 

the internal color palette DAC. The DAC is designed for a 37.5-Ω equivalent

 

Analog

load on each pin (that is, a 75-ohm resistor on the board, in parallel with the 75-

 

 

Ω CRT load).

 

 

 

BLUE#

O

Blue# (Analog Output): Tied to ground.

 

Analog

 

 

 

 

D15343-003

37

Intel® 854 Graphics Memory Controller Hub (GMCH)

3.5.4General Purpose Input/Output Signals

Table 13. GPIO Signal Descriptions

GPIO I/F Total

Type

Comments

 

 

 

RSTIN#

I

Reset: Primary Reset, Connected to PCIRST# of ICH4-M.

 

CMOS

 

 

 

 

PWROK

I

Power OK: Indicates that power to GMCH is stable.

 

CMOS

 

 

 

 

EXTTS_0

I

External Thermal Sensor Input: This signal is an active low input to the

 

CMOS

GMCH and is used to monitor the thermal condition around the system memory

 

and is used for triggering a read throttle. The GMCH can be optionally

 

 

 

 

programmed to send a SERR, SCI, or SMI message to the ICH4-M upon the

 

 

triggering of this signal.

 

 

 

LCLKCTLA

O

SSC Chip Clock Control: Can be used to control an external clock chip with

 

CMOS

SSC control.

 

 

 

 

 

LCLKCTLB

O

SSC Chip Data Control: Can be used to control an external clock chip for

 

 

SSC control.

 

CMOS

 

 

 

 

DDCACLK

I/O

CRT DDC Clock: This signal is used as the DDC clock signal between the

 

 

CRT monitor and the GMCH.

 

CMOS

 

 

 

 

DDCADATA

I/O

CRT DDC Data: This signal is used as the DDC data signal between the CRT

 

 

monitor and the GMCH.

 

CMOS

 

 

 

 

MI2CCLK

I/O

DVO I2C Clock: This signal is used as the I2C_CLK for a digital display (i.e.

 

DVO

TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard

 

reset.

 

 

 

 

 

MI2CDATA

I/O

DVO I2C Data: This signal is used as the I2C_DATA for a digital display (i.e.

 

DVO

TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard

 

reset.

 

 

 

 

 

MDVICLK

I/O

DVI DDC Clock: This signal is used as the DDC clock for a digital display

 

DVO

connector (that is, primary digital monitor). This signal is tri-stated during a hard

 

reset.

 

 

 

 

 

MDVIDATA

I/O

DVI DDC Data: The signal is used as the DDC data for a digital display

 

DVO

connector (that is, the primary digital monitor). This signal is tri-stated during a

 

hard reset.

 

 

 

 

 

MDDCDATA

I/O

DVI DDC Clock: The signal is used as the DDC data for a digital display

 

DVO

connector (that is, the secondary digital monitor). This signal is tri-stated during

 

a hard reset.

 

 

 

 

 

MDDCCLK

I/O

DVI DDC Data: The signal is used as the DDC clock for a digital display

 

DVO

connector (that is, the secondary digital monitor). This signal is tri-stated during

 

a hard reset.

 

 

 

 

 

38

D15343-003

Signal Description

3.6Voltage References, PLL Power

Table 14.

Voltage References, PLL Power

 

 

 

 

 

Signal Name

Type

Description

 

 

 

 

 

Host Processor

 

 

 

 

 

 

 

HXRCOMP

Analog

Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers.

 

 

 

 

 

HYRCOMP

Analog

Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers.

 

 

 

 

 

HXSWING

Analog

Host Voltage Swing (RCOMP reference voltage): This signal provides

 

 

 

a reference voltage used by the FSB RCOMP circuit.

 

 

 

 

 

HYSWING

Analog

Host Voltage Swing (RCOMP reference voltage): This signal provides

 

 

 

a reference voltage used by the FSB RCOMP circuit.

 

 

 

 

 

HDVREF[2:0]

Ref

Host Data (input buffer) VREF: Reference voltage input for the data

 

 

Analog

signals of the Host AGTL+ Interface. Input buffer differential amplifier to

 

 

 

determine a high versus low input voltage.

 

 

 

 

 

HAVREF

Ref

Host Address (input buffer) VREF: Reference voltage input for the

 

 

Analog

address signals of the Host AGTL+ Interface. This signal is connected to

 

 

 

the input buffer differential amplifier to determine a high versus low input

 

 

 

voltage.

 

 

 

 

 

HCCVREF

Ref Analog

Host Common Clock (Command input buffer) VREF: Reference

 

 

 

voltage input for the common clock signals of the Host AGTL+ Interface.

 

 

 

This signal is connected to the input buffer differential amplifier to

 

 

 

determine a high versus low input voltage.

 

 

 

 

 

VTTLF

Power

FSB Power Supply: VTTLF is the low frequency connection from the

 

 

 

board. This signal is the primary connection of power for GMCH.

 

 

 

 

 

VTTHF

Power

FSB Power Supply: VTTHF is the high frequency supply. It is for direct

 

 

 

connection from an internal package plane to a capacitor placed

 

 

 

immediately adjacent to the GMCH.

 

 

 

NOTE: Not to be connected to power rail.

 

 

 

 

 

System Memory

 

 

 

 

 

 

 

SMRCOMP

Analog

System Memory RCOMP: This signal is used to calibrate the memory I/

 

 

 

O buffers.

 

 

 

 

 

SMVREF_0

Ref

Memory Reference Voltage(Input buffer VREF):Reference voltage

 

 

Analog

input for Memory Interface.

 

 

 

Input buffer differential amplifier to determine a high versus low input

 

 

 

voltage.

 

 

 

 

 

SMVSWINGH

Ref

RCOMP reference voltage: This is connected to the RCOMP buffer

 

 

Analog

differential amplifier and is used to calibrate the I/O buffers.

 

 

 

 

 

SMVSWINGL

Ref

RCOMP reference voltage: This is connected to the RCOMP buffer

 

 

Analog

differential amplifier and is used to calibrate the I/O buffers.

 

 

 

 

 

VCCSM

Power

Power supply for Memory I/O.

 

 

 

 

 

VCCQSM

Power

Power supply for system memory clock buffers.

 

 

 

 

 

VCCASM

Power

Power supply for system memory logic running at the core voltage

 

 

 

(isolated supply, not connected to the core).

 

 

 

 

D15343-003

39

Intel® 854 Graphics Memory Controller Hub (GMCH)

Hub Interface

 

 

 

 

 

HLRCOMP

Analog

Hub Interface RCOMP: This signal is connected to a reference resistor

 

 

in order to calibrate the buffers.

 

 

 

PSWING

Analog

RCOMP reference voltage: This is connected to the RCOMP buffer

 

 

differential amplifier and is used to calibrate the buffers.

 

 

 

HLVREF

Ref

Input buffer VREF: Input buffer differential amplifier to determine a high

 

Analog

versus low input voltage.

 

 

 

 

 

VCCHL

Power

Power supply for Hub interface buffers

 

 

 

DVO

 

 

 

 

 

DVORCOMP

Analog

Compensation for DVO: This signal is used to calibrate the DVO I/O

 

Analog

buffers.

 

 

 

 

 

GVREF

Ref Analog

Input buffer VREF: Input buffer differential amplifier to determine a high

 

 

versus low input voltage.

 

 

 

VCCDVO

Power

Power supply for DVO.

 

 

 

GPIO

 

 

 

 

 

VCCGPIO

Power

Power supply for GPIO buffers

 

 

 

DAC

 

 

 

 

 

REFSET

Ref

Resistor Set: Set point resistor for the internal color palette DAC.

 

Analog

 

 

 

 

VCCADAC

Power

Power supply for the DAC

 

 

 

VSSADAC

Power

Ground supply for the DAC

 

 

 

IGD

 

 

 

 

 

VCC1_5

Power

Digital power supply.

 

 

 

VCC2_5

Power

Digital power supply

 

 

 

VCCA

Power

Analog power supply.

 

 

 

VSSA

Power

Ground supply

 

 

 

Clocks

 

 

 

 

 

VCCAHPLL

Power

Power supply for the Host PLL.

 

 

 

VCCAGPLL

Power

Power supply for the Hub/DVO PLL.

 

 

 

VCCADPLLA

Power

Power supply for the display PLL A.

 

 

 

VCCADPLLB

Power

Power supply for the display PLL B.

 

 

 

Core

 

 

 

 

 

VCC

Power

Power supply for the core.

 

 

 

VSS

Power

Ground supply for the chip.

 

 

 

40

D15343-003

Register Description

4.0Register Description

4.1Conceptual Overview of the Platform Configuration

Structure

The GMCH and ICH4-M are physically connected by a Hub interface. From a configuration standpoint, the Hub interface is logically PCI bus #0. As a result, all devices internal to the GMCH and ICH4-M appear to be on PCI bus #0. The system's primary PCI expansion bus is physically attached to the ICH4-M and from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and therefore has a programmable PCI Bus number. Note that the primary PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a configuration standpoint. For the GMCH, the graphics subsystem appears to system software to be a real PCI bus behind PCI-to-PCI bridges, resident as devices on PCI bus #0.

The GMCH contains two PCI devices within a single physical component. The configuration registers for the two devices are mapped as devices residing on PCI bus #0.

Device #0: Host-Hub Interface Bridge/DDR SDRAM Controller. Logically this appears as a PCI device residing on PCI bus #0. Physically, Device #0 contains the standard PCI registers, DDR SDRAM registers, the Graphics Aperture Controller registers, HI Control registers and other GMCH specific registers. Device #0 is divided into the following functions:

Function #0: Host Bridge Legacy registers including Graphics Aperture Control registers, HI Configuration registers and Interrupt Control registers

Function #1: DDR SDRAM Interface Registers

Function #3: Intel Configuration Process Registers

Device #2: Integrated Graphics Controller. Logically this appears as a PCI device residing on PCI bus #0. Physically Device #2 contains the Configuration registers for 2D, 3D, and display functions.

Note: The legacy VGA registers are only supported when the Intel® 82854 GMCH is strapped into

 

Native Graphics Mode.

 

 

Table 15 shows the Device # assignment for the various internal GMCH devices.

Table 15.

Device Number Assignment

 

 

 

 

 

GMCH Function

Bus #0, Device#

 

 

 

 

Host-Hub interface, DDR SDRAM I/F, Legacy control

Device #0

 

 

 

 

Integrated Graphics Controller (IGD)

Device #2

 

 

 

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

4.2Nomenclature for Access Attributes

Table 16 provides the nomenclature for the access attributes.

Table 16. Nomenclature for Access Attributes

RO

Read Only. If a register is Read Only, Writes to this register have no effect.

 

 

R/W

Read/Write. A register with this attribute can be Read and Written.

 

 

R/W/L

Read/Write/Lock. A register with this attribute can be Read, Written, and Locked.

 

 

R/WC

Read/Write Clear. A register bit with this attribute can be Read and Written.

 

However, a Write of a 1 clears (sets to 0) the corresponding bit and a Write of a 0

 

has no effect.

 

 

R/WO

Read/Write Once. A register bit with this attribute can be Written to only once

 

after power up. After the first Write, this bit becomes Read Only.

 

 

L

Lock. A register bit with this attribute becomes Read Only after a Lock bit is set.

 

 

Reserved Bits

Some of the GMCH registers described in this section contain Reserved bits.

 

These bits are labeled "Reserved”. Software must deal correctly with fields that are

 

Reserved. On Reads, software must use appropriate masks to extract the defined

 

bits and not rely on Reserved bits being of any particular value. On Writes,

 

software must ensure that the values of Reserved bit positions are preserved. That

 

is, the values of Reserved bit positions must first be Read, Merged with the new

 

values for other bit positions and then Written back. Note the software does not

 

need to perform Read, Merge, and Write operations for the Configuration Address

 

register.

 

 

Reserved Registers

In addition to Reserved bits within a register, the GMCH contains address locations

 

in the configuration space of the Host-Hub Interface Bridge entity that are marked

 

either "Reserved" or “Intel Reserved”. The GMCH responds to accesses to

 

“Reserved” address locations by completing the Host cycle. When a “Reserved”

 

register location is Read, in certain cases, a zero value can be returned

 

(“Reserved” registers can be 8-bit, 16-bit, or 32-bit in size) or a non-zero value can

 

be returned. In certain cases, Writes to “Reserved” registers may have no effect on

 

the GMCH or may cause system failure. Registers that are marked as “Intel

 

Reserved” must not be modified by system software.

 

 

Default Value upon a

Upon Reset, the GMCH sets all of its internal configuration registers to

Reset

predetermined default states. Some register values at Reset are determined by

 

external strapping options. The default state represents the minimum functionality

 

feature set required to successfully bring up the system. Hence, it does not

 

represent the optimal system configuration. It is the responsibility of the system

 

initialization software (usually BIOS) to properly determine the DDR SDRAM

 

configurations, operating parameters and optional system features that are

 

applicable, and to program the GMCH registers accordingly.

 

 

S

SW Semaphore.

 

 

A physical PCI Bus #0 does not exist. The Hub interface and the internal devices in the GMCH and ICH4-M logically constitute PCI Bus #0 to configuration software.

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4.3Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Specification defines two bus cycles to access the PCI Configuration Space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the CPU. Configuration Space is supported by a mapping mechanism implemented within the GMCH. The PCI 2.2 specification defines two mechanisms to access Configuration Space: Mechanism #1 and Mechanism #2. The GMCH supports only Mechanism #1.

The Configuration Access Mechanism makes use of the CONFIG_ADDRESS register (at I/O address 0CF8h though 0CFBh) and CONFIG_DATA register (at I/O address 0CFCh though 0CFFh). To reference a Configuration register a Dword I/O Write cycle is used to place a value into CONFIG_ADDRESS that specifies the PCI Bus, the device on that bus, the function within the device, and a specific Configuration register of the device function being accessed. CONFIG_ADDRESS[31] must be a 1 to enable a Configuration cycle. CONFIG_DATA then becomes a window into the four Bytes of Configuration Space specified by the contents of CONFIG_ADDRESS. Any Read or Write to CONFIG_DATA will result in the GMCH translating the CONFIG_ADDRESS into the appropriate Configuration cycle.

The GMCH is responsible for translating and routing the CPU’s I/O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH Configuration registers and to the Hub interface.

4.4Routing Configuration Accesses

The GMCH supports one bus interface: the Hub interface. PCI Configuration cycles are selectively routed to this interface. The GMCH is responsible for routing PCI Configuration cycles to the proper interface. PCI configuration cycles to the ICH4-M internal devices, and Primary PCI (including downstream devices) are routed to theICH4-M via the Hub interface.

4.4.1PCI Bus #0 Configuration Mechanism

The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, then the Configuration cycle is targeting a PCI Bus #0 device.

The Host-Hub Interface Bridge entity within the GMCH is hardwired as Device #0 on PCI Bus #0.

Configuration cycles to any of the GMCH’s internal devices are confined to the GMCH and not sent over Hub interface. Accesses to disabled GMCH internal devices will be forwarded over the Hub interface as Type 0 Configuration cycles.

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

4.4.2Primary PCI and Downstream Configuration Mechanism

If the Bus Number in the CONFIG_ADDRESS is non-zero, the GMCH will generate a Type 1 Hub interface Configuration Cycle. A[1:0] of the Hub interface request packet for the Type 1 configuration cycle will be “01”. This Hub interface configuration cycle will be sent over Hub interface.

If the cycle is forwarded to the ICH4-M via Hub interface, the ICH4-M compares the non-zero Bus Number with the Secondary bus number and Subordinate bus number registers of its PCI-to-PCI bridges to determine if the configuration cycle is meant for Primary PCI, one of the ICH4-M’s Hub interfaces, or a downstream PCI bus.

4.5Register Definitions

The GMCH contains four sets of software accessible registers accessed via the Host CPU I/O Address Space, and they are as follows:

Control registers: I/O Mapped into the CPU I/O Space, which control access to PCI Configuration Space via Configuration Mechanism #1 in the PCI 2.2 specification.

Internal Configuration registers: residing within the GMCH, they are partitioned into two logical device register sets (“logical” since they reside within the single physical device). The first register set is dedicated to Host-HI Bridge functionality (that is, DDR SDRAM configuration, other chip-set operating parameters and optional features). The second register block is for the integrated graphics functions.

Internal Memory Mapped Configuration registers: reside in the GMCH Device #0.

Internal Memory Mapped Configuration registers, Legacy VGA registers, or blending function registers: reside in the GMCH Device #2 that controls the Integrated Graphics Controller.

The GMCH internal registers (I/O Mapped and Configuration registers) are accessible by the Host CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the exception of CONFIG_ADDRESS, which can only be accessed as a Dword. All multi-byte numeric fields use “Little Endian Byte Ordering” (that is, lower addresses contain the least significant parts of the field).

Reserved Bits

Some of the GMCH registers described in this section contain Reserved bits. These bits are labeled “Reserved”. Software must deal correctly with fields that are Reserved. On Reads, software must use appropriate Masks to extract the defined bits and not rely on Reserved bits being any particular value. On Writes, software must ensure that the values of Reserved bit positions are preserved.

That is, the values of Reserved bit positions must first be Read, Merged with the new values for other bit positions and then Written back.

Note: The software does not need to perform Read, Merge, and Write operations for the Configuration Address register.

Default Value upon Reset

Upon a Full Reset, the GMCH sets all of its Internal Configuration registers to a predetermined default state. Some register values at Reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the

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Register Description

system initialization software (usually BIOS) to properly determine the DDR SDRAM configurations, operating parameters, and optional system features that are applicable and to program the GMCH registers accordingly.

4.6I/O Mapped Registers

The GMCH contains two registers that reside in the CPU I/O Address Space: the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the Configuration Space and determines what portion of Configuration Space is visible through the Configuration Data window.

4.6.1CONFIG_ADDRESS – Configuration Address Register

I/O Address:

0CF8h Accessed as a Dword

Default Value:

00000000h

Access:

Read/Write

Size:

32 bits

CONFIG_ADDRESS is a 32-bit register that can be accessed only as a Dword. A Byte or Word reference will “pass through” the Configuration Address Register and the Hub interface, onto the PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended.

Figure 2. Configuration Address Register

31 30

 

24

23

16

15

11 10

8 7

2

1 0

Bit

0

R

 

 

0

 

0

0

 

0

R

Default

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

Register Number

Function Number

Device Number

Bus Number

Reserved

Enable

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

Bit

Descriptions

 

 

31

Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI Configuration Space

 

are enabled. If this bit is Reset to 0, accesses to PCI Configuration Space are disabled.

 

 

30:24

Reserved

 

 

23:16

Bus Number: When the Bus Number is programmed to 00h, the target of the Configuration

 

Cycle is a Hub interface agent (GMCH, ICH4-M, and so on.).

 

The Configuration Cycle is forwarded to Hub interface if the Bus Number is programmed to 00h

 

and the GMCH is not the target (the device number is >= 2).

 

 

15:11

Device Number: This field selects one agent on the PCI Bus selected by the Bus Number. When

 

the Bus Number field is 00 the GMCH decodes the Device Number field. The GMCH is always

 

Device Number 0 for the Host-Hub interface bridge entity. Therefore, when the Bus Number =0

 

and the Device Number=0-1 the internal GMCH devices are selected.

 

For Bus Numbers resulting in Hub interface Configuration cycles, the GMCH propagates the

 

device number field as A[15:11].

 

 

10:8

Function Number: This field is mapped to A[10:8] during Hub interface Configuration cycles.

 

This allows the configuration registers of a particular function in a multi-function device to be

 

accessed. The GMCH ignores Configuration cycles to its internal Devices if the function number is

 

not equal to 0.

 

 

7:2

Register Number: This field selects one register within a particular Bus, Device, and Function as

 

specified by the other fields in the Configuration Address register. This field is mapped to A[7:2]

 

during Hub interface Configuration cycles.

 

 

1:0

Reserved

 

 

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Register Description

4.6.2CONFIG_DATA – Configuration Data Register

I/O Address:

0CFCh

Default Value:

00000000h

Access:

Read/Write

Size:

32 bits

CONFIG_DATA is a 32-bit Read/Write window into Configuration Space. The portion of Configuration Space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS.

Figure 3. Configuration Data Register

31

0

Bit

0

 

Default

Configuration Data Window

Bit

Descriptions

31:0 Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, then any I/O access to the CONFIG_DATA register will be mapped to Configuration Space using the contents of CONFIG_ADDRESS.

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

4.7VGA I/O Mapped Registers

If Native Graphics mode is strapped, and Device #2 is enabled, and Function #0 within Device #2 is enabled for VGA, and IO_EN is set within Function #0 then GMCH claims a set of I/O registers for legacy VGA function. Table 17 lists direct CPU Access registers and Table 18 lists registers that are Index – Data registers that are used to access Internal VGA registers.

Table 17. VGA I/O Mapped Register List

Name

Function

Read @

Write @

 

 

 

 

ST00

VGA Input Status Register 0

3C2h

 

 

 

 

ST01

VGA Input Status Register 1

3BAh/3Dah

 

 

 

 

FCR

VGA Feature Control Register

3CAh

3BAh/3DAh

 

 

 

 

MSR

VGA Miscellaneous Status/Output Register

3CCh

3C2h

 

 

 

 

Table 18. Index – Data Registers

Name

Function

Index IO

Data IO

 

 

 

 

SRX

Sequencer Registers

3C4

3C5

 

 

 

 

GRX

Graphics Controller Registers

3CE

3CF

 

 

 

 

ARX

Attribute Control Registers

3C0

3C0: Write

 

 

 

3C1: Read

 

 

 

 

DACMASK

Pixel Data Mask Register

--

3C6h

 

 

 

 

DACSTATE

DAC State Register

--

3C7 Read Only

 

 

 

 

DACRX

Palette Read Index Register

3C7 Write Only

--

 

 

 

 

DACWX

Palette Write Index Register

3C8 Write Only

 

 

 

 

 

DACDATA

Palette Data Register

3C9

 

 

 

 

 

CRX

CRT Registers

3B4/3D4

3B5/3D5

 

 

(MDA/CGA)

(MDA/CGA)

 

 

 

 

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4.8Intel 854 GMCH Host-Hub Interface Bridge Device Registers (Device #0, Function #0)

Table 5 summarizes the configuration space for Device #0, Function#0.

Table 19. GMCH Configuration Space - Device #0, Function#0

Register Name

Register

Register

Register

Default Value

Access

Symbol

Start

End

 

 

 

 

 

 

 

 

 

Vendor Identification

VID

00

01

8086h

RO

 

 

 

 

 

 

Device Identification

DID

02

03

358Ch

RO

 

 

 

 

 

 

PCI Command

PCICMD

04

05

0006h

RO,R/W

 

 

 

 

 

 

PCI Status

PCISTS

06

07

0090h

RO,R/WC

 

 

 

 

 

 

Revision Identification

RID

08

08

02h

RO

 

 

 

 

 

 

Sub-Class Code

SUBC

0A

0A

00h

RO

 

 

 

 

 

 

Base Class Code

BCC

0B

0B

06h

RO

 

 

 

 

 

 

Header Type

HDR

0E

0E

80h

RO

 

 

 

 

 

 

Subsystem Vendor

SVID

2C

2D

0000h

R/WO

Identification

 

 

 

 

 

 

 

 

 

 

 

Subsystem Identification

SID

2E

2F

0000h

R/WO

 

 

 

 

 

 

Capabilities Pointer

CAPPTR

34

34

40h

RO

 

 

 

 

 

 

Capability Identification

CAPID

40

44

84_A105_0009h

RO

 

 

 

 

 

 

GMCH Misc. Control

GMC

50

51

0000h

R/W

 

 

 

 

 

 

GMCH Graphics Control

GGC

52

53

0030h

R/W

 

 

 

 

 

 

Device and Function Control

DAFC

54

55

0000h

R/W

 

 

 

 

 

 

Fixed Dram Hole Control

FDHC

58

58

00h

R/W

 

 

 

 

 

 

Programmable Attribute Map

PAM (6:0)

59

5F

00h Each

R/W

 

 

 

 

 

 

System Management RAM

SMRAM

60

60

02h

R/W/L

Control

 

 

 

 

 

 

 

 

 

 

 

Extended System

ESMRAMC

61

61

38h

R/W/L

Management RAM Control

 

 

 

 

 

 

 

 

 

 

 

Error Status

ERRSTS

62

63

0000h

R/WC

 

 

 

 

 

 

Error Command

ERRCMD

64

65

0000h

R/W

 

 

 

 

 

 

SMI Command

SMICMD

66

66

00h

R/W

 

 

 

 

 

 

SCI Command

SCICMD

67

67

00h

R/W

 

 

 

 

 

 

Secondary Host Interface

SHIC

74

77

00006010h

RO, R/W

Control Register

 

 

 

 

 

 

 

 

 

 

 

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Intel® 82854 Graphics Memory Controller Hub (GMCH)

Aperture Translation Table

ATTBASE

B8

BB

00000000h

RO, R/W

Base

 

 

 

 

 

 

 

 

 

 

 

Host Error Control/Status/

HEM

F0

F3

00000000h

RO, R/W

Obs

 

 

 

 

 

 

 

 

 

 

 

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