Desktop Boards D815EFV and D815EPFV may contain design defects or errors known as errata that may cause the product to deviate from published specifications.
The Intel
Current characterized errata are documented in the Intel Desktop Board D815EFV/D815EPFV Specification Update.
Revision History
Revision Revision History Date
-001 First release of the Intel® Desktop Board D815EFV/D815EPFV Technical
Product Specification
-002 Second release of the Intel® Desktop Board D815EFV/D815EPFV
Technical Product Specification
This product specification applies to only standard D815EFV and D815EPFV boards with BIOS
identifier EA81520A.86A.
Changes to this specification will be published in the Intel Desktop Board D815EFV/D815EPFV
Specification Update before being incorporated into a revision of this document.
®
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY
WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE
OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
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which the failure of the Intel product could create a situation where personal injury or death may occur.
Intel may make changes to specifications and product descriptions at any time, without notice.
®
The Intel
as errata that may cause the product to deviate from published specifications. Current characterized errata are available on
request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
Intel, Pentium, LANDesk, and Celeron are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the
United States and other countries
†
Other names and brands may be claimed as the property of others.
Copyright 2001, Intel Corporation. All rights reserved.
Desktop Board D815EFV and the Intel® Desktop Board D815EPFV may contain design defects or errors known
PRODUCTS. EXCEPT AS
February 2001
April 2001
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and the BIOS for these Intel Desktop Boards: D815EFV
and D815EPFV. It describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the D815EFV and
D815EPFV boards and their components to the vendors, system integrators, and other engineers
and technicians who need this level of information. It is specifically not intended for general
audiences.
What This Document Contains
Chapter Description
1 A description of the hardware used on the D815EFV and D815EPFV boards
2 A map of the resources of the board
3 The features supported by the BIOS Setup program
4 The contents of the BIOS Setup program’s menus and submenus
5 A description of the BIOS error messages, beep codes, and POST codes
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions, which if not observed, can cause personal injury.
# Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX) When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the D815EFV and D815EPFV boards, and X is the instance of
the particular part at that general location. For example, J5J1 is a connector, located at 5J. It
is the first connector in the 5J area.
GB Gigabyte (1,073,741,824 bytes)
KB Kilobyte (1024 bytes)
Kbit Kilobit (1024 bits)
kbits/sec 1000 bits per second
MB Megabyte (1,048,576 bytes)
MB/sec Megabytes per second
Mbit Megabit (1,048,576 bits)
Mbit/sec Megabits per second
xxh An address or data value ending with a lowercase h indicates a hexadecimal value.
x.x V Volts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate other names and brands that may be claimed as the property
of others.
The Universal versions of the D815EFV and D815EPFV can be identified by an uppercase “U” on
the silkscreen of the board. Figure 1 shows the location of the Universal board designator.
INTEL DESKTOP BOARD
D815EFV / D815EPFV
U
Figure 1. Location of Universal Board Designator
NOTE
✏
Unless otherwise stated, all information pertaining to standard boards also apply to Universal
boards.
OM12011
12
1.2 Overview
1.2.1 Feature Summary
Table 2 summarizes the D815EFV and D815EPFV boards’ major features.
Table 2. Feature Summary
Form Factor
Processor
Memory
Chipsets
I/O Control
Video
Audio
Peripheral
Interfaces
Expansion
Capabilities
BIOS
microATX (9.6 inches by 8.2 inches)
Support for either an Intel
(FC-PGA) package or an Intel® Celeron™ processor in an FC-PGA package
• Three 168-pin SDRAM Dual Inline Memory Module (DIMM) sockets
• Support for up to 512 MB system memory
• Support for single-sided or double-sided DIMMs
• The D815EFV board includes the Intel 815E Chipset, consisting of:
Intel 82815 Graphics and Memory Controller Hub (GMCH)
Intel
4 Mbit Firmware Hub (FWH) (STM M50FW040 or equivalent)
• The D815EPFV board includes the Intel 815EP Chipset, consisting of:
Intel 82815EP Memory Controller Hub (MCH)
Intel 82801BA I/O Controller Hub (ICH2)
®
82801BA I/O Controller Hub (ICH2)
®
Pentium® III processor in a Flip Chip Pin Grid Array
4 Mbit Firmware Hub (FWH) (STM M50FW040 or equivalent)
SMSC LPC47M132 LPC bus I/O controller
• The D815EFV board includes:
Intel 82815 integrated graphics support
AGP universal connector supporting 1x, 2x, and 4x AGP cards or a
Graphics Performance Accelerator (GPA)
• The D815EPFV board includes an AGP universal connector supporting
1x, 2x, and 4x AGP cards
• Intel 82801BA ICH2 digital controller (AC link output)
• Analog Devices AD1885 Audio Codec
• Four Universal Serial Bus (USB) ports
• Two serial ports
• One parallel port
• Two IDE interfaces with Ultra DMA, ATA-66/100 support
• One diskette drive interface
• PS/2
• Three PCI bus add-in card connectors (SMBus routed to PCI bus connector 2)
• One AGP universal connector
• Intel/AMI BIOS (stored in an STM M50FW040 4 Mbit FWH or equivalent)
• Support for Advanced Power Management (APM), Advanced Configuration and
• Support for PCI Local Bus Specification Revision 2.2
• Suspend to RAM support
• Wake on PS/2 keyboard and USB ports
• Voltage sense to detect out of range values
• Two fan sense inputs used to monitor fan activity
Allows add-in SCSI host bus adapters to use the same LED as the onboard I/O
controller
For information about Refer to
The board’s compliance level with APM, ACPI, Plug and Play, and SMBIOS Table 4, page 19
1.2.2 Manufacturing Options
Table 3 describes the D815EFV and D815EPFV boards’ manufacturing options. Not every
manufacturing option is available in all marketing channels. Please contact your Intel
representative to determine which manufacturing options are available to you.
Table 3. Manufacturing Options
Chassis fan
connector
Chassis Intrusion
Connector
Communication
and Networking
Riser (CNR)
Connector
Diagnostic LEDs
Front Panel Audio
Connector
Front Panel USB
Connector
I/O Control
LAN Subsystem
Video
Wake on LAN†
Technology
Connector
Connector for an additional chassis fan
Detects chassis intrusion
One CNR connector (slot shared with PCI bus connector 3)
Four dual-color LEDs on the back panel
Routes mic in and line out to the front panel
Provides access to two additional USB ports, routed through the optional SMSC
LPC47M142 I/O controller
SMSC LPC47M142 LPC bus I/O controller
Intel
Digital Video Output (DVO) connector
Support for system wake up using an add-in network interface card with remote wake
up capability
®
82562ET 10/100 Mbit/sec Platform LAN Connect (PLC) device
NOTE
✏
Other drivers may be offered by other third party vendors.
14
Product Description
1.2.3 Board Layout
Figure 2 shows the location of the major components on the D815EFV and D815EPFV boards.
BA
C
D
E
F
U
G
T
H
S
I
ONPMQRLJK
Present only on D815EFV boards
OM11469
K Power connector A Communication and Networking Riser (CNR)
connector (optional)
B AD1885 audio codec M Primary IDE connector
C AGP universal connector N Secondary IDE connector
D Back panel connectors O Intel 82801BA I/O Controller Hub (ICH2)
E DVO connector (optional) P SMSC LPC47M132 I/O Controller
• Intel 82815 Graphics and Memory Controller
F
Hub (GMCH) (D815EFV boards)
• Intel 82815EP Memory Controller Hub (MCH)
(D815EPFV boards)
G Processor socket T Front panel USB connector (optional)
H DIMM sockets U PCI bus add-in card connectors
I Battery
J Speaker
L Diskette drive connector
Q Serial port B connector
R Front panel connectors
S 4 Mbit Firmware Hub (FWH) (STM M50FW040
The D815EFV and D815EPFV boards support drivers for all of the onboard hardware and
subsystems under the following operating systems:
†
• Windows
• Windows ME
• Windows NT
• Windows 2000
For information about Refer to
Supported drivers Section 1.3
98/98SE
†
4.0
NOTE
✏
Other drivers may be offered by other third party vendors.
18
Product Description
1.5 Design Specifications
Table 4 lists the specifications applicable to both the D815EFV and D815EPFV boards, except for
the AIMM and GPA entries, which apply only to the D815EFV board.
Table 4. Specifications
Reference
Name
AC ’97 Audio Codec ’97 Revision 2.2,
ACPI Advanced Configuration
AGP Accelerated Graphics Port
AIMM
(for Graphics
Performance
Accelerator
cards)
AMI BIOS American Megatrends
APM Advanced Power
ATA/
ATAPI-5
ATX ATX Specification Version 2.03,
CNR
Specification
Title
and Power Interface
Specification
Interface Specification
AGP Inline Memory Module Revision 1.0,
BIOS Specification
Management BIOS
Interface Specification
Information Technology AT Attachment with Packet
Interface - 5
(ATA/ATAPI-5)
Communication and
Network Riser (CNR)
Specification
Version, Revision Date,
and Ownership
September 2000,
Intel Corporation.
Version 2.0,
July 27, 2000,
Compaq Computer
Corporation,
Intel Corporation,
Microsoft Corporation,
Phoenix Technologies
Limited, and
Toshiba Corporation.
Revision 2.0,
May 4, 1998,
Intel Corporation.
April 2000,
Intel Corporation.
AMIBIOS 99,
1999,
American Megatrends, Inc.
Version 1.2,
February 1996,
Intel Corporation and
Microsoft Corporation.
Revision 3,
February 29, 2000,
Contact: T13 Chair,
Seagate Technology.
December 1998,
Intel Corporation.
Revision 1.1,
October 18, 2000,
Intel Corporation.
Version 2.3.1,
March 16, 1999,
American Megatrends
Incorporated,
Award Software International
Incorporated,
Compaq Computer Corporation,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
and SystemSoft Corporation.
Revision 1.1,
March 1996,
Intel Corporation.
Version 1.1,
September 23, 1998,
Compaq Computer Corporation,
Intel Corporation,
Microsoft Corporation, and
NEC Corporation.
Version 2.0,
December 18, 1998,
Intel Corporation.
Use only the processors listed below. Use of unsupported processors can damage the board, the
processor, and the power supply. See the IntelUpdate for the most up-to-date list of supported processors for the D815EFV and D815EPFV
boards.
The D815EFV and D815EPFV boards both support a single Pentium III or Celeron processor. The
system bus frequency is automatically selected. The D815EFV and D815EPFV boards support the
processors listed in Table 5.
Table 5. Supported Processors
Type Designation System Bus Frequency L2 Cache Size
533EB, 600EB, 667, 733,
an FC-PGA package
FC-PGA package
800B, 866, and 933 MHz
1.0 GHz
500E, 550E, 600E, 650, 700,
750, 800, and 850 MHz
800 and 850 MHz 100 MHz 128 KB Celeron processor in an
533A, 566, 600, 633, 667, 700,
733, and 766 MHz
All supported onboard memory can be cached, up to the cachability limit of the processor. See the
processor’s data sheet for cachability limits.
For information about Refer to
Product information on supported processors Section 1.3, page 18
Processor data sheets Section 1.3, page 18
®
Desktop D815EFV/D815EPFV Specification
133 MHz 256 KB Pentium III processor in
100 MHz 256 KB
66 MHz 128 KB
22
Product Description
1.7 System Memory
CAUTION
Before installing or removing memory, make sure that AC power is disconnected by unplugging
the power cord from the computer. Failure to do so could damage the memory and the board.
NOTE
✏
Remove the AGP video card before installing or upgrading memory to avoid interference with the
memory retention mechanism.
NOTE
✏
To be fully compliant with all applicable Intel® SDRAM memory specifications, the board should
be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. This
allows the BIOS to read the SPD data and program the chipset to accurately configure memory
settings for optimum performance. If non-SPD memory is installed, the BIOS will attempt to
correctly configure the memory settings, but performance and reliability may be impacted or the
DIMMs may not function under the determined frequency
The D815EFV and D815EPFV boards both have three DIMM sockets and support the following
memory features:
• 3.3 V (only) 168-pin SDRAM DIMMs with gold-plated contacts
• Unbuffered single-sided or double-sided DIMMs
• Maximum total system memory: 512 MB; minimum total system memory: 64 MB
• 133 MHz SDRAM or 100 MHz SDRAM
• Serial Presence Detect (SPD) and non-SPD memory
• Non-ECC and ECC DIMMs (ECC DIMMs will operate in non-ECC mode only)
• Suspend to RAM
When installing memory, note the following:
• Non-SPD DIMMs will always revert to a 100 MHz with 3-3-3 timing SDRAM bus.
• Mixing Non-SPD DIMMs with SPD DIMMs will always revert to a 100 MHz with 3-3-3
timing SDRAM bus.
• The BIOS will not initialize installed memory above 512 MB.
• Mixed memory speed configurations (133 and 100 MHz) will default to 100 MHz.
• 133 MHz SDRAM operation requires a 133 MHz system bus frequency processor.
• The board should be populated with no more than four rows of 133 MHz SDRAM (two
double-sided or one double-sided plus two single-sided DIMMs).
• 100 MHz SDRAM may be populated with six rows of SDRAM (three double-sided DIMMs).
✏ NOTE
At boot, the BIOS displays a message indicating that any installed memory above 512 MB has not
been initialized.
If more than four rows of 133 MHz SDRAM are populated, the BIOS will display a message
indicating that it will initialize installed memory up to 512 MB at 100 MHz.
For information about Refer to
Obtaining the PC Serial Presence Detect (SPD) SpecificationTable 4, page 18
Table 6 lists the supported DIMM configurations.
Table 6. Supported Memory Configurations
DIMM
Capacity
32 MB DS 16 Mbit 2 M x 8/2 M x 8 16
32 MB SS 64 Mbit 4 M x 16/empty 4
48 MB DS 64/16 Mbit 4 M x 16/2 M x 8 12
64 MB DS 64 Mbit 4 M x 16/4 M x 16 8
64 MB SS 64 Mbit 8 M x 8/empty 8
64 MB SS 128 Mbit 8 M x 16/empty 4
96 MB DS 64 Mbit 8 M x 8/4 M x 16 12
96 MB DS 128/64 Mbit 8 M x 16/4 M x 16 8
128 MB DS 64 Mbit 8 M x 8/8 M x 8 16
128 MB DS 128 Mbit 8 M x 16/8 M x 16 8
128 MB SS 128 Mbit 16 M x 8/empty 8
128 MB SS 256 Mbit 16 M x 16/empty 4
192 MB DS 128 Mbit 16 M x 8/8 M x 16 12
192 MB DS 128/64 Mbit 16 M x 8/8 M x 8 16
256 MB DS 128 Mbit 16 M x 8/16 M x 8 16
256 MB DS 256 Mbit 16 M x 16/16 M x 16 8
256 MB SS 256 Mbit 32 M x 8/empty 8
512 MB DS 256 Mbit 32 M x 8/32 M x 8 16
Notes:
1. If the number of SDRAM devices is greater than nine, the DIMM will be double sided.
2. Front side population/back side population indicated for SDRAM density and SDRAM organization.
3. In the second column, “DS” refers to double-sided memory modules (containing two rows of SDRAM) and “SS” refers
to single-sided memory modules (containing one row of SDRAM).
Number of
Sides
SDRAM
Density
SDRAM Organization
Front-side/Back-side
Number of
SDRAM devices
(Note 1)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
(Note 1)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
(Notes 1 and 2)
24
Product Description
1.8 Chipsets
This section describes the chipsets used by the D815EFV and D815EPFV boards:
• The D815EFV board uses the Intel 815E Chipset, described below.
• The D815EPFV board uses the Intel 815EP Chipset, described in Section 1.8.2, beginning on
page 30.
1.8.1 Intel® 815E Chipset
The Intel 815E chipset consists of the following devices:
• 82815 Graphics and Memory Controller Hub (GMCH) with Accelerated Hub Architecture
(AHA) bus
• 82801BA I/O Controller Hub (ICH2) with AHA bus
• Firmware Hub (FWH) (STM M50FW040 or equivalent)
The GMCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
AHA bus. The ICH2 is a centralized controller for the board’s I/O paths. The FWH provides the
nonvolatile storage of the BIOS.
The Intel 815E chipset provides the interfaces shown in Figure 5.
System Bus
SDRAM Bus
Memory Controller
Digital Video
Output
82815
Graphics and
Hub (GMCH)
Display
Interface
ATA-66/100
815E Chipset
AHA
Bus
AGP
Bus
82801BA
I/O Controller Hub
(ICH2)
Network
AC LinkPCI BusSMBus
USB
LPC Bus
Firmware Hub
(FWH)
(STM M50FW040
or equivalent)
OM11887
Figure 5. Intel 815E Chipset Block Diagram
For information about Refer to
The Intel 815E chipset http://developer.intel.com/design/chipsets/815e
The resources used by the chipset Chapter 2
The chipset’s compliance with ACPI, APM, and AC ’97 Table 4, page 19
1.8.1.1 Intel® 82815 Graphics and Memory Controller Hub (GMCH)
The GMCH provides the following:
• An integrated Synchronous DRAM memory controller with autodetection of SDRAM
• An interface for a single AGP device or a Graphics Performance Accelerator (GPA) card
• An interface for an optional digital video output (DVO) connector for a flat panel, digital CRT,
or TV-out
• Support for ACPI Rev. 2.0 and APM Rev. 1.2 compliant power management
1.8.1.2 Intel® 82801BA I/O Controller Hub (ICH2)
The ICH2 provides the following:
• 33 MHz PCI bus interface
• Support for up to four PCI master devices
• Low Pin Count (LPC) interface that supports an LPC-compatible I/O controller
• Support for two Master/DMA devices
• Integrated IDE controller that supports Ultra DMA (33 MB/sec) and ATA-66/100 mode
(66 MB/sec, 100 MB/sec)
• Integrated LAN Media Access Controller
• Universal Serial Bus interface with two USB controllers providing four ports in a
UHCI Implementation (additional USB ports provided with the optional SMSC LPC47M142
I/O controller)
• Power management logic for ACPI Rev. 1.0b compliance
• System Management Bus (SMBus clock and data lines also routed to PCI bus connector 2)
• Real-time clock with 256-byte battery-backed CMOS RAM
• AC ’97 digital link for audio codec, including:
AC ’97 2.1 compliance
Logic for PCM in, PCM out, and mic input
PCI functions for audio
Communication and Network Riser (CNR) interface
1.8.1.2.1 IDE Interfaces
The ICH2’s IDE controller has two independent bus-mastering IDE interfaces that can be
independently enabled. The IDE interfaces support the following modes:
• Programmed I/O (PIO): CPU controls data transfer.
• 8237-style DMA: DMA offloads the CPU, supporting transfer rates of up to 16 MB/sec.
• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
• ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
• ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH2 ATA-100
logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to
88 MB/sec.
26
Product Description
✏ NOTE
ATA-66 and ATA-100 are faster timings and require a specialized cable to reduce reflections,
noise, and inductive coupling.
The IDE interfaces also support ATAPI devices (such as CD-ROM drives) and ATA devices using
the transfer modes listed in Table 71 on page 121.
The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The D815EFV board supports Laser Servo (LS-120) diskette technology through its IDE
interfaces. The LS-120 drive can be configured as a boot device by setting the BIOS Setup
program’s Boot menu to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
For information about Refer to
The location of the IDE connectors Figure 15, page 73
The signal names of the IDE connectors Table 43, page 77
BIOS Setup program’s Boot menu Table 79, page 130
1.8.1.2.2 USB
The ICH2 contains two separate USB controllers. The D815EFV board has four USB ports; one
USB peripheral can be connected to each port. For more than four USB devices, an external hub
can be connected to any of the ports. The D815EFV board fully supports the Universal Hub
Controller Interface (UHCI).
In the standard configuration, the D815EFV board’s four USB ports are implemented with stacked
back panel connectors, routed through the ICH2, as shown in Figure 6.
With the optional SMSC LPC47M142 I/O controller, the D815EFV board supports up to seven
USB ports. The SMSC LPC47M142 I/O controller provides four ports: two ports implemented
with stacked back panel connectors and two ports routed to the optional front panel USB connector
at location J8F1. The ICH2 provides three ports: two ports are implemented with stacked back
panel connectors and the other port is accessible through a CNR add-in card, as shown in Figure 6.
USB port accesible through a USB
connector on an optional CNR add-in card
Back panel USB connectors
Front panel USB connector
OM11892
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
For information about Refer to
The location of the USB connectors on the back panel Figure 13, page 64
The signal names of the back panel USB connectors Table 21, page 65
The location of the optional front panel USB connector Figure 16, page 78
The signal names of the optional front panel USB connector Table 45, page 79
The USB specification and UHCI Table 4, page 19
28
Product Description
1.8.1.2.3 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock provides a time-of-day clock and a multicentury calendar with alarm features.
The real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are
reserved for BIOS use.
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
✏ NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded into CMOS
SRAM at power-on.
The Intel 815EP chipset consists of the following devices:
• 82815EP Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA) bus
• 82801BA I/O Controller Hub (ICH2) with AHA bus
• Firmware Hub (FWH) (STM M50FW040 or equivalent)
The MCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
AHA bus. The ICH2 is a centralized controller for the board’s I/O paths. The FWH provides the
nonvolatile storage of the BIOS.
The Intel 815EP chipset provides the interfaces shown in Figure 7.
ATA-66/100
System Bus
SDRAM Bus
Network
USB
815E Chipset
Graphics and
Memory Controller
Hub (GMCH)
Digital Video
Output
82815
Display
Interface
AGP
Bus
AHA
Bus
82801BA
I/O Controller Hub
(ICH2)
LPC Bus
AC LinkPCI BusSMBus
Firmware Hub
(FWH)
(STM M50FW040
or equivalent)
OM11887
Figure 7. Intel 815EP Chipset Block Diagram
For information about Refer to
The Intel 815EP chipset http://developer.intel.com/design/chipsets/815ep
The resources used by the chipset Chapter 2
The chipset’s compliance with ACPI, APM, and AC ’97 Table 4, page 19
30
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