The Intel® Desktop Boards D815EEA2 and D815EPEA2 may contain design defects or errors known as errata that may cause the product to deviate from published
specifications. Current characterized errata are documented in the Intel Desktop Board D815EEA2/D815EPEA2 Specification Update.
May 2001
Order Number A46399-002
Revision History
Revision Revision History Date
-001 First release of the Intel® Desktop Board D815EEA2/D815EPEA2
Technical Product Specification
-002 Second release of the Intel® Desktop Board D815EEA2/D815EPEA2
Technical Product Specification
This product specification applies to only standard D815EEA2 and D815EPEA2 boards with BIOS
identifier EA81520A.86A.
Changes to this specification will be published in the Intel Desktop Board D815EEA2/
D815EPEA2 Specification Update before being incorporated into a revision of this document.
®
Information in this doc um ent is provided in connection wi th Intel
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions
of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating
to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability,
or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical,
life saving, or life sustaining applications.
Intel may make changes t o specifications and produc t descriptions at any tim e, without notice.
The Intel
known as errata that may cause the product to deviate from publ i shed specifications. Current characterized errata are
available on request.
Contact your local Int el sales office or your distributor to obtain the latest specifications before pl acing your product order.
®
Desktop Board D815EEA2 and the Intel® Desktop Board D815EPEA2 may contain design defects or errors
products. No license, express or implied, by est oppel or
February 2001
May 2001
Copies of documents which have an ordering number and are referenced in this docum ent, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
Intel, Pentium, Celeron, and LANDesk are trademarks or regis tered trademarks of Intel Corporat i on or i t s subsidiaries in the
United States and other count ri es.
†
Other names and brands may be claim ed as the property of others.
Copyright 2001, Intel Corporat i on. All rights reserved.
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and the BIOS for these Intel Desktop Boards: D815EEA2
and D815EPEA2. It describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the D815EEA2 and
D815EPEA2 boards and their components to the vendors, system integrators, and other engineers
and technicians who need this level of information. It is specifically not intended for general
audiences.
What This Document Contains
Chapter Description
1 A description of the hardware used on the D815EEA2 and D815EPEA2 boards
2 A map of the resources of the board
3 The features supported by the BIOS Setup program
4 The contents of the BIOS Setup program’s menus and submenus
5 A description of the BIOS error messages, beep codes, and POST codes
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions, which if not observed, can cause personal injury.
# Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX) When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the D815EEA2 and D815EPEA2 boards, and X is the instance of
the particular part at that general location. For example, J5J1 is a connector, located at 5J. It
is the first connector in the 5J area.
GB Gigabyte (1,073,741,824 bytes)
KB Kilobyte (1024 bytes)
Kbit Kilobit (1024 bits)
kbits/sec 1000 bits per second
MB Megabyte (1,048,576 bytes)
MB/sec Megabytes per second
Mbit Megabit (1,048,576 bits)
Mbit/sec Megabits per second
xxh An address or data value ending with a lowercase h indicates a hexadecimal value.
x.x V Volts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
This TPS describes these Intel® Desktop boards: D815EEA2 and D815EPEA2. Table 1
summarizes the differences between these boards.
Table 1. Summary of Board Differences
D815EEA2
D815EPEA2
• Includes the Intel
Memory Controller Hub (GMCH)
• Provides these video features: AGP universal connector and an optional
Digital Video Output (DVO) connector
• Includes the Intel® 815EP Chipset, which includes the Intel® 82815EP Memory
Controller Hub (MCH)
• Provides this video feature: AGP universal connector
®
815E Chipset, which includes the Intel® 82815 Graphics and
12
Product Description
1.1.2 Identifying Universal Boards
The Universal versions of the D815EEA2 and D815EPEA2 can be identified by an uppercase “U”
on the silkscreen of the board. Figure 1 shows the location of the Universal board designator.
INTEL DESKTOP BOARD
D815EEA2 / D815EPEA2
G
XBT1061
U
BATTERY
SIDE UP
OM12012
Figure 1. Location of Universal Board Designator
NOTE
✏
Unless otherwise stated, all information pertaining to standard boards also apply to Universal
boards.
I/O Control SMSC LPC47M132 LPC bus I/O controller
Video • The D815EEA2 board includes:
Audio
Peripheral
Interfaces
Expansion
Capabilities
BIOS • Intel/AMI BIOS (stored in an SST 49LF004A 4 Mbit FWH)
ATX (11.55 inches by 8.20 inches)
(FC-PGA) package or an Intel
• Support for up to 512 MB system memory
• Support for single-sided or double-sided DIMMs
• The D815EEA2 board includes the Intel 815E Chipset, consisting of:
Intel
Intel
SST 49LF004A 4 Mbit Firmware Hub (FWH)
• The D815EPEA2 board includes the Intel 815EP Chipset, consisting of:
Intel 82815EP Memory Controller Hub (MCH)
Intel 82801BA I/O Controller Hub (ICH2)
82815 Graphics and Memory Controller Hub (GMCH)
®
82801BA I/O Controller Hub (ICH2)
®
Celeron™ processor in an FC-PGA package
SST 49LF004A 4 Mbit Firmware Hub (FWH)
Intel 82815 integrated graphics support
AGP universal connector supporting 1x, 2x, and 4x AGP cards or a
Graphics Performance Accelerator (GPA)
• The D815EPEA2 board includes an AGP universal connector supporting
1x, 2x, and 4x AGP cards
• Intel 82801BA ICH2 digital controller (AC link output)
• Analog Devices AD1885 Audio Codec
• Four Universal Serial Bus (USB) ports
• Two serial ports
• One parallel port
• Two IDE interfaces with Ultra DMA, ATA-66/100 support
• One diskette drive interface
• PS/2† keyboard and mouse ports
• Five PCI bus add-in card connectors (SMBus routed to PCI bus connector 2)
• One AGP universal connector
• Support for Advanced Power Management (APM), Advanced Configuration and
Power Interface (ACPI), Plug and Play, and SMBIOS
continued
14
Product Description
Table 2. Feature Summary (continued)
Instantly Available
PC
Hardware Monitor
Subsystem
SCSI LED
Connector
For information about Refer to
The board’s compliance level with APM, ACPI, Plug and Play, and SMBIOS Table 4, page 20
• Support for PCI Local Bus Specification Revision 2.2
• Suspend to RAM support
• Wake on PS/2 keyboard and USB ports
• Voltage sense to detect out of range values
• Two fan sense inputs used to monitor fan activity
Allows add-in SCSI host bus adapters to use the same LED as the onboard I/O
controller
1.2.2 Manufacturing Options
Table 3 describes the D815EEA2 and D815EPEA2 boards’ manufacturing options. Not every
manufacturing option is available in all marketing channels. Please contact your Intel
representative to determine which manufacturing options are available to you.
Table 3. Manufacturing Options
Chassis fan connector Connector for an additional chassis fan
Chassis Intrusion
Connector
Communication and
Networking Riser (CNR)
Connector
Diagnostic LEDs Four dual-color LEDs on the back panel
Front Panel Audio
Connector
Front Panel USB
Connector
I/O Control SMSC LPC47M142 LPC bus I/O controller
LAN Subsystem Intel
Video Digital Video Output (DVO) connector
Wake on LAN†
Technology Connector
Detects chassis intrusion
One CNR connector (slot shared with PCI bus connector 3)
Routes mic in and line out to the front panel
Provides access to two additional USB ports, routed through the optional
SMSC LPC47M142 I/O controller
®
82562ET 10/100 Mbit/sec Platform LAN Connect (PLC) device
Support for system wake up usi ng an add-in network interface card with
remote wake up capability
Figure 2 shows the location of the major components on the D815EEA2 and D815EPEA2 boards.
AC
B
D
E
F
U
G
T
S
R
H
I
J
N
O
Q
Present only on D815EEA2 boards
connector (optional)
B AD1885 audio codec L Power connector
C AGP universal connector M Diskette drive connector
D Back panel connectors N SMSC LPC47M132 I/O Controller
E DVO connector (optional) O Intel 82801BA I/O Controller Hub (ICH2)
Table 4 lists the specifications applicable to the D815EEA2 and D815EPEA2 boards, except for the
AIMM and GPA entries, which apply only to the D815EEA2 board.
Table 4. Specifications
Reference
Name
AC ’97 Audio Codec ’97 Revision 2.2,
ACPI Advanced Configuration
AGP Accelerated Graphics Port
AIMM
(for Graphics
Performance
Accelerator
cards)
AMI BIOS American Megatrends
APM Advanced Power
ATA/
ATAPI-5
ATX ATX Specification Version 2.03,
CNR Communication and
Specification
Title
and Power Interface
Specification
Interface Specification
AGP Inline Memory Module Revision 1.0,
BIOS Specification
Management BIOS
Interface Specification
Information Technology AT Attachment with Packet
Interface - 5 (ATA/ATAPI-5)
Network Riser (CNR)
Specification
Version, Revision Date,
and Ownership
September 2000,
Intel Corporation.
Version 2.0,
July 27, 2000,
Compaq Computer
Corporation,
Intel Corporation,
Microsoft Corporation,
Phoenix Technologies
Limited, and
Toshiba Corporation.
Revision 2.0,
May 4, 1998,
Intel Corporation.
April 2000,
Intel Corporation.
AMIBIOS 99,
1999,
American Megatrends, Inc.
Version 1.2,
February 1996,
Intel Corporation and
Microsoft Corporation.
Revision 3,
February 29, 2000,
Contact: T13 Chair,
Seagate Technology.
December 1998,
Intel Corporation.
Revision 1.1,
October 18, 2000,
Intel Corporation.
Version 2.3.1,
March 16, 1999,
American Megatrends
Incorporated,
Award Software International
Incorporated,
Compaq Computer Corporation,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
and SystemSoft Corporation.
Revision 1.1,
March 1996,
Intel Corporation.
Version 1.1,
September 23, 1998,
Compaq Computer Corporation,
Intel Corporation,
Microsoft Corporation, and
NEC Corporation.
Version 2.0,
December 18, 1998,
Intel Corporation.
The information is
available from…
http://www.intel.com/
technology/memory
http://www.intel.com/
technology/memory
http://www.intel.com/
technology/memory
http://developer.intel.com/
ial/wfm/design/smbios
http://www.usb.org/
developers
http://www.usb.org/
developers
http://developer.intel.com/
ial/WfM/wfmspecs.htm
22
Product Description
1.6 Processor
CAUTION
Use only the processors listed below. Use of unsupported processors can damage the board, the
processor, and the power supply. See the Intel Desktop D815EEA2/D815EPEA2 Specification Update for the most up-to-date list of supported processors for the D815EEA2 and D815EPEA2
boards.
The D815EEA2 and D815EPEA2 boards both support a single Pentium III or Celeron processor.
The system bus frequency is automatically selected. The D815EEA2 and D815EPEA2 boards
support the processors listed in Table 5.
Table 5. Supported Processors
Type Designation System Bus Frequency L2 Cache Size
533EB, 600EB, 667, 733,
an FC-PGA package
FC-PGA package
800B, 866, and 933 MHz
1.0 GHz
500E, 550E, 600E, 650, 700,
750, 800, and 850 MHz
800 and 850 MHz 100 MHz 128 KB Celeron processor in an
533A, 566, 600, 633, 667, 700,
733, and 766 MHz
All supported onboard memory can be cached, up to the cachability limit of the processor. See the
processor’s data sheet for cachability limits.
For information about Refer to
Product information on supported processors Section 1.3, page 19
Processor data sheets Section 1.3, page 19
Before installing or removing memory, make sure that AC power is disconnected by unplugging the
power cord from the computer. Failure to do so could damage the memory and the board.
NOTE
✏
Remove the AGP video card before installing or upgrading memory to avoid interference with the
memory retention mechanism.
NOTE
✏
To be fully compliant with all applicable Intel® SDRAM memory specifications, the board should
be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. This
allows the BIOS to read the SPD data and program the chipset to accurately configure memory
settings for optimum performance. If non-SPD memory is installed, the BIOS will attempt to
correctly configure the memory settings, but performance and reliability may be impacted or the
DIMMs may not function under the determined frequency.
The D815EEA2 and D815EPEA2 boards both have three DIMM sockets and support the following
memory features:
• 3.3 V (only) 168-pin SDRAM DIMMs with gold-plated contacts
• Unbuffered single-sided or double-sided DIMMs
• Maximum total system memory: 512 MB; minimum total system memory: 64 MB
• 133 MHz SDRAM or 100 MHz SDRAM
• Serial Presence Detect (SPD) and non-SPD memory
• Non-ECC and ECC DIMMs (ECC DIMMs will operate in non-ECC mode only)
• Suspend to RAM
When installing memory, note the following:
• Non-SPD DIMMs will always revert to a 100 MHz with 3-3-3 timing SDRAM bus.
• Mixing Non-SPD DIMMs with SPD DIMMs will always revert to a 100 MHz with
3-3-3 timing SDRAM bus.
• The BIOS will not initialize installed memory above 512 MB.
• Mixed memory speed configurations (133 and 100 MHz) will default to 100 MHz.
• 133 MHz SDRAM operation requires a 133 MHz system bus frequency processor.
• The board should be populated with no more than four rows of 133 MHz SDRAM (two double-
sided or one double-sided plus two single-sided DIMMs).
• 100 MHz SDRAM may be populated with six rows of SDRAM (three double-sided DIMMs).
✏ NOTE
At boot, the BIOS displays a message indicating that any installed memory above 512 MB has not
been initialized.
24
Product Description
✏ NOTE
If more than four rows of 133 MHz SDRAM are populated, the BIOS will display a message
indicating that it will initialize installed memory up to 512 MB at 100 MHz.
For information about Refer to
Obtaining the PC Serial Presence Detect (SPD) SpecificationTable 4, page 19
Table 6 lists the supported DIMM configurations.
Table 6. Supported Memory Configurations
DIMM
Capacity
32 MB DS 16 Mbit 2 M x 8/2 M x 8 16
32 MB SS 64 Mbit 4 M x 16/empty 4
48 MB DS 64/16 Mbit 4 M x 16/2 M x 8 12
64 MB DS 64 Mbit 4 M x 16/4 M x 16 8
64 MB SS 64 Mbit 8 M x 8/empty 8
64 MB SS 128 Mbit 8 M x 16/empty 4
96 MB DS 64 Mbit 8 M x 8/4 M x 16 12
96 MB DS 128/64 Mbit 8 M x 16/4 M x 16 8
128 MB DS 64 Mbit 8 M x 8/8 M x 8 16
128 MB DS 128 Mbit 8 M x 16/8 M x 16 8
128 MB SS 128 Mbit 16 M x 8/empty 8
128 MB SS 256 Mbit 16 M x 16/empty 4
192 MB DS 128 Mbit 16 M x 8/8 M x 16 12
192 MB DS 128/64 Mbit 16 M x 8/8 M x 8 16
256 MB DS 128 Mbit 16 M x 8/16 M x 8 16
256 MB DS 256 Mbit 16 M x 16/16 M x 16 8
256 MB SS 256 Mbit 32 M x 8/empty 8
512 MB DS 256 Mbit 32 M x 8/32 M x 8 16
Notes:
1. If the number of SDRAM devices is greater than nine, the DIMM will be double sided.
2. Front side population/back side population indicated for SDRA M density and SDRAM organizati on.
3. In the second column, “DS” ref ers to double-sided memory modules (containing two rows of SDRAM) and “SS” refers
to single-sided memory m odul es (containing one row of SDRAM).
This section describes the chipsets used by the D815EEA2 and D815EPEA2 boards:
• The D815EEA2 board uses the Intel 815E Chipset, described below.
• The D815EPEA2 board uses the Intel 815EP Chipset, described in Section 1.8.2, beginning on
page 31.
1.8.1 Intel® 815E Chipset
The Intel 815E chipset consists of the following devices:
• 82815 Graphics and Memory Controller Hub (GMCH) with Accelerated Hub Architecture
(AHA) bus
• 82801BA I/O Controller Hub (ICH2) with AHA bus
• SST 49LF004A Firmware Hub (FWH)
The GMCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
AHA bus. The ICH2 is a centralized controller for the board’s I/O paths. The FWH provides the
nonvolatile storage of the BIOS.
The Intel 815E chipset provides the interfaces shown in Figure 5.
ATA-66/100
System Bus
SDRAM Bus
Network
USB
815E Chipset
Graphics and
Memory Controller
Hub (GMCH)
Digital Video
Output
82815
Display
Interface
AHA
Bus
AGP
Bus
82801BA
I/O Controller Hub
(ICH2)
SST 49LF004A
Firmware Hub
(FWH)
LPC Bus
AC LinkPCI BusSMBus
OM11891
Figure 5. Intel 815E Chipset Block Diagram
For information about Refer to
The Intel 815E chipset http://developer.intel.com/design/chipsets/815e
The resources used by the chipset Chapter 2
The chipset’s compliance with ACPI, APM, and AC ’97 Table 4, page 19
26
Product Description
1.8.1.1 Intel® 82815 Graphics and Memory Controller Hub (GMCH)
The GMCH provides the following:
• An integrated Synchronous DRAM memory controller with autodetection of SDRAM
• An interface for a single AGP device or a Graphics Performance Accelerator (GPA) card
• An interface for an optional digital video output (DVO) connector for a flat panel, digital CRT,
or TV-out
• Support for ACPI Rev. 2.0 and APM Rev. 1.2 compliant power management
1.8.1.2 Intel® 82801BA I/O Controller Hub (ICH2)
The ICH2 provides the following:
• 33 MHz PCI bus interface
• Support for up to six PCI master devices
• Low Pin Count (LPC) interface that supports an LPC-compatible I/O controller
• Support for two Master/DMA devices
• Integrated IDE controller that supports Ultra DMA (33 MB/sec) and ATA-66/100 mode
(66 MB/sec, 100 MB/sec)
• Integrated LAN Media Access Controller
• Universal Serial Bus interface with two USB controllers providing four ports in a
UHCI Implementation (additional USB ports provided with the optional SMSC
LPC47M142 I/O controller)
• Power management logic for ACPI Rev. 1.0b compliance
• System Management Bus (SMBus clock and data lines also routed to PCI bus connector 2)
• Real-time clock with 256-byte battery-backed CMOS RAM
• AC ’97 digital link for audio codec, including:
AC ’97 2.1 compliance
Logic for PCM in, PCM out, and mic input
PCI functions for audio
Communication and Network Riser (CNR) interface
1.8.1.2.1 IDE Interfaces
The ICH2’s IDE controller has two independent bus-mastering IDE interfaces that can be
independently enabled. The IDE interfaces support the following modes:
• Programmed I/O (PIO): CPU controls data transfer.
• 8237-style DMA: DMA offloads the CPU, supporting transfer rates of up to 16 MB/sec.
• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
• ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
• ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH2 ATA-100
logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 88 MB/sec.
✏ NOTE
ATA-66 and ATA-100 are faster timings and require a specialized cable to reduce reflections,
noise, and inductive coupling.
The IDE interfaces also support ATAPI devices (such as CD-ROM drives) and ATA devices using
the transfer modes listed in Table 71 on page 121.
The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The D815EEA2 board supports Laser Servo (LS-120) diskette technology through its IDE
interfaces. The LS-120 drive can be configured as a boot device by setting the BIOS Setup
program’s Boot menu to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
For information about Refer to
The location of the IDE connectors Figure 15, page 73
The signal names of the IDE connectors Table 43, page 77
BIOS Setup program’s Boot menu Section 4.7, page 130
1.8.1.2.2 USB
The ICH2 contains two separate USB controllers. The D815EEA2 board has four USB ports; one
USB peripheral can be connected to each port. For more than four USB devices, an external hub
can be connected to any of the ports. The D815EEA2 board fully supports the Universal Hub
Controller Interface (UHCI).
In the standard configuration, the D815EEA2 board’s four USB ports are implemented with stacked
back panel connectors, routed through the ICH2, as shown in Figure 6.
With the optional SMSC LPC47M142 I/O controller, the D815EEA2 board supports up to seven
USB ports. The SMSC LPC47M142 I/O controller provides four ports: two ports implemented
with stacked back panel connectors and two ports routed to the optional front panel USB connector
at location J8F1. The ICH2 provides three ports: two ports are implemented with stacked back
panel connectors and the other port is accessible through a CNR add-in card, as shown in Figure 6.
The D815EEA2 board fully supports the Universal Hub Controller Interface (UHCI).
28
Standard Configuration
Product Description
82801BA
I/O Controller Hub
(ICH2)
82801BA
I/O Controller Hub
(ICH2)
USB
SMSC LPC47M142
LPC Bus
I/O Controller
USB ports 0 and 1
USB
USB ports 2 and 3
Optional Configuration
USB ports 0 and 2
USB
CNR connector
USB ports 1 and 3
USB
USB ports 4 and 5
Figure 6. USB Port Configurations
Back panel USB connectors
Back panel USB connectors
Back panel USB connectors
USB port accesi bl e through a USB
connector on an optional CNR add-in card
Back panel USB connectors
Front panel USB connector
OM11892
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
For information about Refer to
The location of the USB connectors on the back panel Figure 13, page 64
The signal names of the back panel USB connectors Table 21, page 65
The location of the optional front panel USB connector Figure 16, page 78
The signal names of the optional front panel USB connector Table 45, page 79
The USB specification and UHCI Table 4, page 20
1.8.1.2.3 Real-Time Clock, CMOS SRAM, and Bat t e ry
The real-time clock provides a time-of-day clock and a multicentury calendar with alarm features.
The real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are
reserved for BIOS use.
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
✏ NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded into CMOS
SRAM at power-on.
1.8.1.3 SST 49LF004A 4 Mbit Firmware Hub (FWH)
The system BIOS is stored in the FWH.
30
Loading...
+ 116 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.