The Intel® Desktop Board D815EEA may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current
characterized errata are documented in the Intel Desktop Board D815E E A Sp ecif icat ion Updat e.
Revision History
RevisionRevision HistoryDate
-P1First review draft of the Intel Desktop Board D815EEA Technical Product
Specification
-P2Second review draft of the Intel Desktop Board D815EEA Technical
Product Specification
-P3Third review draft of the Intel Desktop Board D815EEA Technical Product
Specification
-001First release of the Intel Desktop Board D815EEA Technical Product
Specification
This product specification applies to only standard D815EEA boards with BIOS identifier
EA81510A.86A.
Changes to this specification will be published in the Intel Desktop Board D815EEA Specification
Update before being incorporated into a revision of this document.
March 2000
April 2000
June 2000
June 2000
Information in this doc um ent is provided in connection wi t h Intel® products. No license, express or implied, by est oppel or
otherwise, to any intell ectual property rights is granted by this document. E x cept as provided in Intel’s Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and I nt el dis claims any express or implied
warranty, relating to sale and/or use of I ntel products including liability or warranties relat i ng t o f i t ness for a particular
purpose, merchantability, or infringement of any patent, copyright or other int ellec t ual propert y right. Intel products are not
intended for use in medical, l i f e saving, or life sustai ni ng appl i cations.
Intel may make changes t o specifications and produc t descriptions at any tim e, without notice.
®
The Intel
deviate from published spec i fications. Current charac terized errata are available on request.
Contact your local Int el sales office or your distributor to obtain the latest specifications before pl acing your product order.
Copies of documents whic h hav e an orderi ng number and are referenced in this document, or other Intel literature, may be
obtained from:
†
Copyright 2000, Intel Corporation. All rights reserved.
Desktop Board D815EEA may contain design defect s or errors known as errata that may cause the produc t to
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
Third-party brands and names are the property of their respective owners.
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and the BIOS for the Intel Desktop Board D815EEA. It
describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the D815EEA board and its
components to the vendors, system integrators, and other engineers and technicians who need this
level of information. It is specifically not intended for general audiences.
What This Document Contains
ChapterDescription
1A description of the hardware used on the D815EEA board
2A map of the resources of the board
3The features supported by the BIOS Setup program
4The contents of the BIOS Setup program’s menus and submenus
5A description of the BIOS error messages, beep codes, POST codes, and diagnostic
LEDs
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions, which if not observed, can cause personal injury.
#Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX)When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the D815EEA board, and X is the instance of the particular part
at that general location. For example, J5J1 is a connector, located at 5J. It is the first
connector in the 5J area.
GBGigabyte (1,073,741,824 bytes)
KBKilobyte (1024 bytes)
KbitKilobit (1024 bits)
kbits/sec1000 bits per second
MBMegabyte (1,048,576 bytes)
MB/secMegabytes per second
MbitMegabit (1,048,576 bits)
Mbit/secMegabits per second
xxhAn address or data value ending with a lowercase h indicates a hexadecimal value.
x.x VVolts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
Version 2.3,
August 12, 1998,
Award Software International Inc.,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
American Megatrends Inc.,
and SystemSoft Corporation.
Version 1.1,
March 1996,
Intel Corporation.
Version 1.1,
September 23, 1998,
Compaq Computer Corporation,
Intel Corporation, Microsoft
Corporation, and NEC.
Version 2.0,
December 18, 1998,
Intel Corporation.
The information is
available from…
http://www.intel.com/
design/chipsets/memory
http://www.intel.com/
design/chipsets/memory
http://www.intel.com/
design/pcisets/memory
http://developer.intel.com/
ial/wfm/design/smbios
http://www.usb.org/
developers
http://www.usb.org/
developers
http://developer.intel.com/
ial/WfM/wfmspecs.htm
18
Product Description
1.4 Processor
CAUTION
The D815EEA board supports processors that have an 18.2 A maximum current draw with a 1.65
to 2.0 V core voltage. Using a processor not in compliance with the above guidelines can damage
the processor, the D815EEA board, and the power supply. See the processor’s data sheet for
voltage and current usage requirements.
The D815EEA board supports a single Pentium III or Celeron processor. The system bus speed is
automatically selected. The D815EEA board supports the processors listed in Table 4.
Table 4.Supported Processors
TypeDesignationSystem Bus FrequencyL2 Cache Size
an FC-PGA package
Celeron processor in an
FC-PGA package
Celeron processor in a
PPGA package
533EB, 600EB, 667, 733,
800EB, 866, and 933
500E, 550E, 600E, 650, 700,
750, 800, and 850
533A, 566, and 60066 MHz128 KB
500 and 53366 MHz128 KB
133 MHz256 KBPentium III processor in
100 MHz256 KB
All supported onboard memory can be cached, up to the cachability limit of the processor. See the
The D815EEA board has three DIMM sockets and supports the following memory features:
• 3.3 V (only) 168-pin SDRAM DIMMs with gold-plated contacts
• Unbuffered single- or double-sided DIMMs
• Maximum system memory: 512 MB; minimum system memory: 32 MB
• 133 MHz SDRAM or 100 MHz SDRAM
• Serial Presence Detect (SPD) and non-SPD memory
• Non-ECC and ECC DIMMs (ECC DIMMs will operate in non-ECC mode only)
• Suspend to RAM
Table 5 lists the supported DIMM configurations. In the second column of Table 5:
• “DS” refers to double-sided memory modules (containing two rows of SDRAM)
• “SS” refers to single-sided memory modules (containing one row of SDRAM).
When installing memory, note the following:
• Non-SPD DIMMs will always revert to a 100 MHz with 3-3-3 timing SDRAM bus.
• Mixing Non-SPD DIMMs with SPD DIMMs will always revert to a 100 MHz with 3-3-3
timing SDRAM bus.
• The BIOS will not initialize installed memory above 512 MB. At boot, the BIOS displays a
message indicating that any installed memory above 512 MB has not been initialized.
• Mixed memory speed configurations (133 and 100 MHz) will default to 100 MHz.
• 133 MHz SDRAM operation requires a 133 MHz system bus frequency processor.
• The board should be populated with no more than four rows of 133 MHz SDRAM (two
double-sided or one double-sided plus two single-sided DIMMs)
• 100 MHz SDRAM may be populated with six rows of SDRAM (three double-sided DIMMs).
✏ NOTE
If more than four rows of 133 MHz SDRAM are populated, the BIOS will initialize installed
memory up to 512 MB at 100 MHz.
20
Product Description
Table 5.Supported Memory Configurations
DIMM
Capacity
32 MBDS16 Mbit2 M X 8 / 2 M X 816 (Note 1)
32 MBSS64 Mbit4 M X 16 / empty4
48 MBDS64 / 16 Mbit4 M X 16 / 2 M X 812 (Notes 1 and 2)
64 MBDS64 Mbit4 M X 16 / 4 M X 168
64 MBSS64 Mbit8 M X 8 / empty8
64 MBSS128 Mbit8 M X 16 / empty4
96 MBDS64 Mbit8 M X 8 / 4 M x 1612 (Notes 1 and 2)
96 MBDS128 / 64 Mbit8 M X 16 / 4 M x 168 (Notes 1 and 2)
128 MBDS64 Mbit8 M X 8 / 8 M X 816 (Note 1)
128 MBDS128 Mbit8 M X 16 / 8 M X 168 (Notes 1 and 2)
128 MBSS128 Mbit16 M X 8 / empty8
128 MBSS256 Mbit16 M X 16 / empty4
192 MBDS128 Mbit16 M X 8 / 8 M x 1612 (Notes 1 and 2)
192 MBDS128 / 64 Mbit16 M X 8 / 8 M x 816 (Notes 1 and 2)
256 MBDS128 Mbit16 M X 8 / 16 M X 816 (Notes 1 and 2)
256 MBDS256 Mbit16 M X 16 / 16 M X 168 (Notes 1 and 2)
256 MBSS256 Mbit32 M X 8 / empty8
512 MBDS256 Mbit32 M X 8 / 32 M X 816 (Notes 1 and 2)
Notes
1.If the number of SDRAM devices is greater than nine, the DIMM will be double sided.
2.Front side popul ation / back side population i ndi c ated for SDRAM density and SDRAM organization.
Number of
Sides
SDRAM
Density
SDRAM Organization
Front-side/Back-side
Number of
SDRAM devices
CAUTION
To be fully compliant with all applicable Intel® SDRAM memory specifications, the motherboard
should be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. If
your memory modules do not support SPD, you will see a notification to this effect on the screen at
power up. The BIOS will attempt to configure the memory controller for normal operation.
However, DIMMs may not function under the determined frequency. You can access the PC Serial
Presence Detect Specification at:
The Intel 815E chipset consists of the following devices:
• 82815E Graphics and Memory Controller Hub (GMCH) with Accelerated Hub Architecture
(AHA) bus
• 82801BA I/O Controller Hub (ICH2) with AHA bus
• 82802AB Firmware Hub (FWH).
The GMCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
Accelerated Hub Architecture interface. The ICH2 is a centralized controller for the board’s I/O
paths. The FWH provides the nonvolatile storage of the BIOS as well as hardware-dependent
security features. The chipset provides the interfaces shown in Figure 3.
SDRAM Bus
System Bus
82815E
Graphics and
Memory Controller
Hub (GMCH)
Digital video
output
ATA-33/66/100
Network
USB
815E Chipset
AHA
Bus
AGP
Interface
82801BA
I/O Controller Hub
(ICH2)
LPC Bus
AC LinkPCI BusSMBus
Figure 3. Intel 815E Chipset Block Diagram
82802AB
Firmware Hub
(FWH)
OM10202
22
For information aboutRefer toThe Intel 815E chipsetHttp://developer.intel.comThe resources used by the chipsetChapter 2The chipset’s compliance with ACPI, APM, AC ‘97Section 1.3, page 16
Product Description
1.6.1 Intel® 82815E Graphics and Memory Controller Hub (GMCH)
The GMCH provides the following:
• An integrated Synchronous DRAM memory controller with autodetection of SDRAM
• An interface for a single AGP device or a Graphics Performance Accelerator (GPA) card
• An interface for a digital video output (DVO) connector for a flat panel, digital CRT, or
TV-out
• Support for ACPI Rev 1.0 and APM Rev 1.2 compliant power management
1.6.2 Intel® 82801BA I/O Controller Hub (ICH2)
The ICH2 provides the following:
• 33 MHz PCI bus interface
• Support for up to six PCI master devices
• Low Pin Count (LPC) interface that supports an LPC-compatible I/O controller
• Support for two Master/DMA devices
• Integrated IDE controller that supports Ultra DMA (33 MB/sec) and ATA-66/100 mode
(66 MB/sec, 100 MB/sec)
• Integrated LAN Media Access Controller
• Universal Serial Bus interface with two USB controllers providing four ports in a
UHCI Implementation
• Power management logic for ACPI Rev 1.0b compliance
• System Management Bus (SMBus clock and data lines also routed to PCI bus connector 2)
• Real-Time Clock with 256-byte battery-backed CMOS RAM
• AC’97 digital link for Audio and telephony codecs, including:
AC’97 2.1 compliance
Logic for PCM in, PCM out, Mic input, Modem in, and Modem out
Separate PCI functions for audio and modem
Communications Network Riser (CNR) interface
1.6.2.1 IDE Interfaces
The ICH2’s IDE controller has two independent bus-mastering IDE interfaces that can be
independently enabled. The IDE interfaces support the following modes:
• Programmed I/O (PIO): CPU controls data transfer
• 8237-style DMA: DMA offloads the CPU, supporting transfer rates of up to 16 MB/sec
• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
• Ultra ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer
rates of up to 66 MB/sec. ATA-66 protocol is similar to ATA-33 and is device driver
compatible. ATA-66 uses faster timings and requires a specialized cable to reduce reflections,
noise, and inductive coupling.
• Ultra ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH2 Ultra
ATA-100 logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to
88 MB/sec. The higher quality cable used for ATA-66 DMA support is adequate to reduce
reflections, noise, and inductive coupling for ATA-100 operation.
The IDE interfaces also support ATAPI devices (such as CD-ROM drives) and ATA devices using
the transfer modes listed in Table 70 on page 107.
The BIOS supports logical block addressing (LBA) and extended cylinder head sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The D815EEA board supports laser servo (LS-120) diskette technology through its IDE interfaces.
The LS-120 drive can be configured as a boot device by setting the BIOS Setup program’s Boot
menu to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
For information aboutRefer to
The location of the IDE connectorsFigure 11, page 63
The signal names of the IDE connectorsTable 43, page 68
BIOS Setup program’s Boot menuTable 76, page 114
1.6.2.2 USB
The ICH2 contains two separate USB controllers. The D815EEA board has four USB ports; one
USB peripheral can be connected to each port. For more than four USB devices, an external hub
can be connected to any of the ports. Two of the USB ports are implemented with stacked back
panel connectors; the other two are accessible via the front panel USB connector at location J8C1.
The D815EEA board fully supports UHCI and uses UHCI-compatible software drivers.
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
For information aboutRefer to
The location of the USB connectors on the back panelFigure 9, page 54
The signal names of the back panel USB connectorsTable 20, page 55
The location of the front panel USB connectorFigure 12, page 69
The signal names of the front panel USB connectorTable 44, page 70
The USB specification and UHCISection 1.3, page 16
24
Product Description
1.6.2.3 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock provides a time-of-day clock and a multicentury calendar with alarm features.
The real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are
reserved for BIOS use.
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
✏ NOTE
If the battery and AC power fail, standard defaults, not custom defaults, will be loaded into CMOS
RAM at power-on.
✏ NOTE
The recommended method of accessing the date in systems with D815EEA boards is indirectly
from the Real-Time Clock (RTC) via the BIOS. The BIOS on D815EEA boards contains a century
checking and maintenance feature. This feature checks the two least significant digits of the year
stored in the RTC during each BIOS request (INT 1Ah) to read the date and, if less than 80 (i.e.,
1980 is the first year supported by the PC), updates the century byte to 20. This feature enables
operating systems and applications using the BIOS date/time services to reliably manipulate the
year as a four-digit value.
For information aboutRefer to
Proper date access in systems with D815EEA boardsSection 1.2, page 16
1.6.3 Intel® 82802AB 4 Mbit Firmware Hub (FWH)
The FWH provides the following:
• System BIOS
• System security and manageability logic that enables protection for storing and updating of
The SMSC LPC47M102 I/O Controller provides the following features:
• Low pin count (LPC) interface
• 3.3 V operation
• Two serial ports
• One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support
• Serial IRQ interface compatible with serialized IRQ support for PCI systems
• PS/2-style mouse and keyboard interfaces
• Interface for one 1.2 MB, 1.44 MB, or 2.88 MB diskette drive
• Intelligent power management, including a programmable wake up event interface
• PCI power management support
• IrDA
• Fan control:
†
1.0 compliant
Two fan control outputs
Two fan tachometer inputs
The BIOS Setup program provides configuration options for the I/O controller.
For information aboutRefer to
SMSC LPC47M102 I/O controllerhttp://www.smsc.com
1.7.1 Serial Ports
The D815EEA board has two serial ports. Serial port A is located on the back panel. Serial port B
is accessible using the connector at location J8E1. The serial ports’ NS16C550-compatible
UARTs support data transfers at speeds up to 115.2 kbits/sec with BIOS support. The serial ports
can be assigned as COM1 (3F8h), COM2 (2F8h), COM3 (3E8h), or COM4 (2E8h).
For information aboutRefer to
The location of the Serial port A connectorFigure 9, page 54
The signal names of the Serial port A connectorTable 23, page 56
The location of the Serial port B connectorFigure 12, page 69
The signal names of the Serial port B connectorTable 45, page 70
1.7.2 Infrared Support
The front panel connector includes four pins that support Hewlett-Packard HSDL-1000 compatible
infrared (IR) transmitters and receivers. In the BIOS Setup program, Serial port B can be directed
to a connected IR device. The IR connection can be used to transfer files to or from portable
devices like laptops, PDAs, and printers. The Infrared Data Association (IrDA) specification
supports data transfers of 115.2 kbits/sec at a distance of 1 meter.
26
Product Description
For information aboutRefer to
The location of the front panel connectorFigure 12, page 69
The signal names of the front panel connectorTable 48, page 71
Configuring serial port B for infrared applicationsSection 4.4.3, page 104
The IrDA specificationSection 1.3, page 16
1.7.3 Parallel Port
The connector for the multimode bidirectional parallel port is a 25-pin D-Sub connector located on
the back panel. In the BIOS Setup program, the parallel port can be configured for the following:
†
• Output only (PC AT
• Bi-directional (PS/2 compatible)
• EPP
• ECP
For information aboutRefer to
The location of the parallel port connectorFigure 9, page 54
The signal names of the parallel port connectorTable 22, page 56
-compatible mode)
1.7.4 Diskette Drive Controller
The I/O controller supports one diskette drive that is compatible with the 82077 diskette drive
controller and supports both PC-AT and PS/2 modes.
For information aboutRefer to
The location of the diskette drive connectorFigure 11, page 63
The signal names of the diskette drive connectorTable 42, page 67
The supported diskette drive capacities and sizesTable 71, page 109
1.7.5 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel. The +5 V lines to these
†
connectors are protected with a PolySwitch
connection after an overcurrent condition is removed.
NOTE
✏
The keyboard is supported in the bottom PS/2 connector and the mouse is supported in the top
PS/2 connector. Power to the computer should be turned off before a keyboard or mouse is
connected or disconnected.
The keyboard controller contains the AMI keyboard and mouse controller code, provides the
keyboard and mouse control functions, and supports password protection for power-on/reset. A
power-on/reset password can be specified in the BIOS Setup program.
circuit that, like a self-healing fuse, reestablishes the
The keyboard controller also supports the hot-key sequence <Ctrl><Alt><Del> for a software reset
(operating system dependent). This key sequence resets the computer’s software by jumping to the
beginning of the BIOS code and running the power-on self-test (POST).
The location of the keyboard and mouse connectorsFigure 9, page 54
The signal names of the keyboard and mouse connectorsTable 18, page 55
1.8 Graphics Subsystem
The 815E chipset contains two separate, mutually exclusive graphics options. Either the integrated
graphics controller (contained within the 82815E GMCH) is used, or an add-in AGP adapter can
be used.
The GMCH includes an integrated display cache SDRAM controller that supports a Graphics
Performance Accelerator (GPA) card. The GPA card is a 32-bit 133 MHz 4 MB SDRAM array for
enhanced integrated 2D and 3D graphics performance. This interface is multiplexed between the
display cache interface and the AGP connector. When an AGP card is installed, the integrated
graphics controller is disabled and the display cache interface is not used.
For information aboutRefer to
GPA supportSection 1.8.3.1, page 31
1.8.1 Integrated Graphics Controller
The GMCH features the following:
• Integrated graphics controller
3-D Hyper pipelined architecture
Full 2-D hardware acceleration
Motion video acceleration
• 3-D graphics visual and texturing enhancement
• Display
Integrated 24-bit 230 MHz RAMDAC
Display Data Channel Standard, Version 3.0, Level 2B protocols compliant
• Video
Hardware motion compensation for software MPEG2 decode
Software DVD at 30 fps
• Integrated graphics memory controller
Table 6 lists the refresh frequencies supported by the graphics subsystem.
28
Table 6.Supported Graphics Refresh Frequencies
Available Refresh
ResolutionColor Palette
320 x 200
320 x 240
352 x 480
352 x 576
400 x 300
512 x 384
640 x 400
640 x 480
640 x 48016 M colors60, 70, 72, 75, 85KDO
800 x 600
1024 x 768
256 colors70
64 K colors70D3
16 M colors70D
256 colors70
64 K colors70D3
16 M colors70D
256 colors70
64 K colors70D3
16 M colors70D
256 colors70
64 K colors70D3
16 M colors70D
256 colors70
64 K colors70D3
16 M colors70D
256 colors70
64 K colors70D3
16 M colors70D
256 colors70
64 K colors70D3
16 M colors70D
256 colors60, 70, 72, 75, 85KDO
64 K colors60, 75, 85KD3O
64 K colors70, 72KDO
256 colors60, 70, 72, 75, 85KDO
64 K colors60, 70, 72, 75, 85KD3O
16 M colors60, 70, 72, 75, 85KDO
256 colors60, 70, 75, 85KDO
64 K colors60, 70, 75KD3O
64 K colors85KD3
16 M colors60, 70, 75, 85KD
D = DirectDraw
3 = Direct3D and OpenGL
O = Overlay
F = Digital Display Device only. A mode will be support ed on bot h analog CRTs and digital display devices (the
KD3O flags above apply to both types of displays), unl ess indicated otherwise.
256 colors60, 70, 72, 75KDO
256 colors85KD
64 K colors60, 70KD3O
64 K colors72, 75, 85KD3
16 M colors60KDO
16 M colors75, 85KD
256 colors60 (reduced blanking)KDOF
64 K colors60 (reduced blanking)KD3F
16 M colors60 (reduced blanking)KDF
256 colors60KDO
256 colors70, 72, 75, 85KD
64 K colors60, 70, 72, 75, 85KD3
16 M colors60, 70, 75, 85KD
256 colors
Frequencies (Hz)Notes
60, 70, 72, 75KD
For information aboutRefer to
Obtaining graphics software and utilitiesSection 1.2, page 16
1.8.2 Digital Video Output (DVO) Connector
The board routes the Intel 82815E GMCH DVO port to an onboard 40-pin DVO connector. The
DVO connector can be cabled to a DVI or TV out card to enable digital displays or TV out
functionality. The Digital Visual Interface (DVI) specification provides a high-speed digital
connection for visual data types when using the integrated graphics controller. This interface is
active only when the integrated graphics controller is enabled.
The DVI interface allows interfacing with a discrete Transmission Minimized Differential
Signaling (TMDS) transmitter to enable platform support for DVI compliant digital displays or
with a discrete TV encoder for TV Out functionality.
For information aboutRefer to
The location of the DVO connectorFigure 10, page 59
The signal names of the DVO connectorTable 33, page 61
30
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