The Intel® Desktop Board D810EMO/MO810E may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current
characterized errata are documented in the Intel Desktop Board D810EMO/MO810E Specification Update.
Revision History
RevisionRevision HistoryDate
-001First release of the Intel® Desktop Board D810EMO/MO810E Technical
Product Specification
This product specification applies to only standard D810EMO/MO810E boards with BIOS
identifier MO81010A.86A.
Changes to this specification will be published in the Intel Desktop Board D810EMO/MO810E
Specification Update before being incorporated into a revision of this document.
February 2000
Information in this doc um ent is provided in connecti on wi th Intel® products. No license, express or implied, by es toppel or
otherwise, to any intell ectual property rights is granted by this document. E xcept as provided in Int el ’s Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and I nt el disclaims any express or implied
warranty, relating to sale and/or use of I ntel products including liability or warranties relat i ng t o fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel produc ts are not
intended for use in medical, l i f e saving, or life sustaining applications.
Intel may make changes t o specifications and product descriptions at any time, without noti ce.
The D810EMO/MO810E board may cont ai n des i gn defects or errors known as errat a t hat may cause the product to deviate
from published specifi c ations. Current characteri z ed errata are available on request.
Contact your local Int el sales office or your dis tributor to obtain the lates t specifications before placing your product order.
Copies of documents whic h hav e an orderi ng number and are referenced in this document , or other Intel literature, m ay be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
†
All other brands and names are the property of their respective owners.
Copyright 2000, Intel Corporation. All rights reserved.
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and the BIOS for the D810EMO/MO810E desktop board.
It describes the standard product and available manufacturing options.
The D810EMO desktop board is known in some documentation and sales collateral as the
MO810E. Both names refer to the same product.
Intended Audience
The TPS is intended to provide detailed, technical information about the board and its components
to the vendors, system integrators, and other engineers and technicians who need this level of
information. It is specifically not intended for general audiences.
What This Document Contains
ChapterDescription
1A description of the hardware used on this board
2A map of the resources of the board
3The features supported by the BIOS Setup program
4The contents of the BIOS Setup program’s menus and submenus
5A description of the BIOS error messages, beep codes, and POST codes
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions that, if not observed, can cause personal injury.
#Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX)When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the board, and X is the instance of the particular part at that
general location. For example, J5J1 is a connector, located at 5J. It is the first connector in the
5J area.
KBKilobyte (1024 bytes)
KbitKilobit (1024 bits)
MBMegabyte (1,048,576 bytes)
MbitMegabit (1,048,576 bits)
GBGigabyte (1,073,741,824 bytes)
xxhAn address or data value ending with a lowercase h indicates a hexadecimal value.
x.x VVolts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
Version 1.1, October 17, 1995
Infrared Data Association
Phone: (510) 943-6546
Fax: (510) 943-5600
Version 1.0,
September 29, 1997,
Intel Corporation.
Version 1.0,
December 1997
Intel Corporation
Version 1.1,
February 1998
Intel Corporation
Version 2.2,
December 18, 1998,
PCI Special Interest Group.
Version 1.1,
December 18, 1998,
PCI Special Interest Group.
Version 1.0a,
May 5, 1994,
Compaq Computer Corp.,
Phoenix Technologies Ltd.,
and Intel Corporation.
Revision 1.0,
February 1998,
Intel Corporation.
Revision 1.2A,
December 1997,
Intel Corporation
Version 2.3,
August 12, 1998,
Award Software International Inc.,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
American Megatrends Inc.,
and SystemSoft Corporation.
The board supports processors that draw a maximum of 22 amps. Using a processor that draws
more than 22 amps can damage the processor, the board, and the power supply. See the
processor’s data sheet for current usage requirements.
The board supports the processors listed in Table 3. The host bus frequency is automatically
selected.
Table 3.Processors Supported by the Board
Processor TypeProcessor SpeedHost Bus FrequencyL2 Cache Size
600EB MHz133 MHz256 KBPentium III processor
600E MHz
550E MHz
500E MHz
Celeron processor533 MHz
500 MHz
466 MHz
433 MHz
400 MHz
366 MHz
100 MHz
100 MHz
100 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
256 KB
256 KB
256 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
All supported onboard memory can be cached, up to the cachability limit of the processor.
For information aboutRefer to
Processor support for the D810EMO/MO810E
board
Processor data sheetshttp://www.intel.com/design/litcentr
To be fully compliant with all applicable Intel® SDRAM memory specifications, the board should
be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. If your
memory modules do not support SPD, you will see a notification to this effect on the screen at
power up. The BIOS will attempt to configure the memory controller for normal operation;
however, DIMMs may not function at the determined frequency.
CAUTION
Because the main system memory is also used as video memory, the board requires a 100 MHz
SDRAM DIMM even though the host bus frequency is 66 MHz. It is highly recommended that an
SPD DIMM be used, since this allows the BIOS to read the SPD data and program the chipset to
accurately configure memory settings for optimum performance. If non-SPD memory is installed,
the BIOS will attempt to correctly configure the memory settings, but performance and reliability
may be impacted.
The board has one DIMM socket. The minimum memory size is 32 MB and the maximum
memory size is 256 MB. The BIOS automatically detects memory type, size, and frequency.
The board supports the following memory features:
• 3.3 V, 168-pin DIMM with gold-plated contacts
• 100 MHz SDRAM
• Serial Presence Detect (SPD) or non-SPD memory (BIOS recovery requires an SPD DIMM)
• Non-ECC (64-bit) memory
• Unbuffered single- or double-sided DIMM
The board is designed to support the DIMM configurations listed in Table 4 below.
Table 4.System Memory Configuration
DIMM SizeNon-ECC Configuration
32 MB4 Mbit x 64
64 MB8 Mbit x 64
128 MB16 Mbit x 64
256 MB (Note)32 Mbit x 64
Note:A 256 MB DIMM used with this board must be built with 128 Mbit device technol ogy.
For information aboutRefer to
The
PC Serial Presence Detect Specification
Obtaining copies of PC SDRAM specificationshttp://www.intel.com/design/pcisets/memory
The chipset provides the host, memory, display, and I/O interfaces shown in Figure 3.
66/100/133 MHz
Host Bus
ATA33/66USB
810E Chipset
100 MHz
SDRAM
Bus
Display
Interface
82810E
Graphics Memory
Controller Hub
(GMCH)
AHA
Bus
82801AA I/O Controller Hub
(ICH)
SMBus
PCI Bus
AC Link
Figure 3. Intel 810E Chipset Block Diagram
For information about Refer to
The Intel 810E chipsethttp://developer.intel.comThe resources used by the chipsetChapter 2The chipset’s compliance with ACPI and AC ‘97Table 2, page 13
82802AB
Firmware Hub
(FWH)
LPC Bus
OM09130
18
Product Description
1.6.1 Direct AGP
Direct (integrated) AGP is a high-performance bus (independent of the PCI bus) for
graphics-intensive applications, such as 3-D applications. AGP overcomes certain limitations of
the PCI bus related to handling large amount of graphics data with the following features:
• Pipelined memory read and write operations that hide memory access latency
• Demultiplexing of address and data on the bus for nearly 100 percent bus efficiency
For information aboutRefer to
The location of the VGA port connectorFigure 4, page 39
Obtaining the
Accelerated Graphics Port Interface Specification
Table 2, page 13
1.6.2 USB
The board supports up to four USB ports; one USB peripheral can be connected to each port. For
more than four USB devices, an external hub can be connected to any of the ports. Two USB ports
are implemented with stacked back panel connectors. The other two ports can be routed from the
connector at location J7A1 via a cable to the front panel. The board fully supports UHCI and uses
UHCI-compatible software drivers. USB features include:
• Support for self-identifying peripherals that can be connected or disconnected while the
computer is running
• Automatic mapping of function to driver and configuration
• Support for isochronous and asynchronous transfer types over the same set of wires
• Support for up to 127 physical devices
• Guaranteed bandwidth and low latencies appropriate for telephony, audio, and other
applications
• Error-handling and fault-recovery mechanisms built into the protocol
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
For information aboutRefer to
The location of the USB connectors on the back panelFigure 4, page 39
The signal names of the USB connectorsTable 17, page 40
The location of the USB port connector for the front panelFigure 6, page 46
The signal names for the USB port connector for the front panelTable 30, page 47
The USB and UHCI specificationsTable 2, page 13
The board has two independent bus-mastering IDE interfaces. These interfaces support:
• ATAPI devices (such as CD-ROM drives)
• ATA devices using the transfer modes listed in Table 51 on page 79
The BIOS supports logical block addressing (LBA) and extended cylinder head sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The board supports laser servo (LS-120) diskette technology through its IDE interfaces. The
LS-120 drive can be configured as a boot device by setting the BIOS Setup program’s Boot menu
to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
The board has two IDE interface connectors. The primary IDE connector is a standard 40-pin IDE
interface. The secondary IDE connector is a 50-pin Slimline IDE connector, intended for use with
devices such as 2.5-inch hard disk drives and mobile CD-ROM drives. The Slimline IDE
connector has the standard IDE interface pins but also includes audio and power signals.
For information aboutRefer to
The location of the IDE connectorsFigure 5, page 41
The signal names of the primary IDE connectorTable 24, page 42
The signal names of the Slimline secondary IDE connectorTable 25, page 43
BIOS Setup program’s Boot menuTable 56, page 85
1.6.4 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock is compatible with DS1287 and MC146818 components. The clock provides a
time-of-day clock and a multicentury calendar with alarm features and century rollover. The
real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reserved
for BIOS use.
A coin-cell battery powers the real-time clock and CMOS memory. When the computer is not
plugged into a wall socket, the battery has an estimated life of three years. When the computer is
plugged in, the 3.3 V standby current from the power supply extends the life of the battery. The
clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
NOTE
✏
If the battery and AC power fail, standard defaults, not custom defaults, will be loaded into CMOS
RAM at power on.
20
Product Description
NOTE
✏
The recommended method of accessing the date in systems with Intel desktop boards is indirectly
from the Real-Time Clock (RTC) via the BIOS. The BIOS on Intel desktop boards contains a
century checking and maintenance feature. This feature checks the two least significant digits of
the year stored in the RTC during each BIOS request (INT 1Ah) to read the date and, if less than
80 (i.e., 1980 is the first year supported by the PC), updates the century byte to 20. This feature
enables operating systems and applications using the BIOS date/time services to reliably
manipulate the year as a four-digit value.
For information aboutRefer to
Proper date access in systems with Intel de sktop boardshttp://support.intel.com/support/year2000/
1.7 I/O Controller
The SMSC LPC47M102 I/O controller provides the following features:
• Low pin count (LPC) interface
• One serial port
• Infrared (IrDA) interface
• Intelligent power management, including a programmable wake up event interface
• Fan control:
One pulse width modulation (PWM) fan speed control output
One fan tachometer input
The BIOS Setup program provides configuration options for the I/O controller.
For information aboutRefer to
SMSC LPC47M102 I/O controllerhttp://www.smsc.com
The IrDA interfaceSection 2.8.3, page 46
1.8 Serial Debug Port
The board has one 9-pin serial debug port connector. The serial debug port’s
NS16C550-compatible UART supports data transfers at rates of up to 115.2 kbits/sec with BIOS
support. The serial debug port can be assigned as COM1 (3F8h), COM2 (2F8h), COM3 (3E8h), or
COM4 (2E8h).
For information aboutRefer to
The location of the serial debug port connectorFigure 5, page 41
The signal names of the serial debug port connectorTable 26, page 43
16 colors60, 70, 72, 75, 85
256 colors60, 70, 72, 75, 85
64 K colors60, 70, 72, 75, 85
16 M colors60, 70, 72, 75, 85
256 colors75, 85
64 K colors75, 85
16 M colors75, 85
256 colors60, 75, 85
64 K colors60, 75, 85
16 M colors60, 75, 85
256 colors60, 70, 72, 75, 85
64 K colors60, 70, 72, 75, 85
16 M colors60, 70, 72, 75, 85
256 colors60, 70, 72, 75, 85
64 K colors60, 70, 72, 75, 85
16 M colors60, 70, 72, 75, 85
256 colors60, 70, 72, 75, 85
64 K colors60, 70, 72, 75, 85
16 M colors60, 70, 72, 75, 85
256 colors60, 70, 72, 75, 85
64 K colors60, 70, 72, 75, 85
16 M colors60, 70, 75, 85
22
For information aboutRefer to
Obtaining graphics software and utilitieshttp://support.intel.com/support/motherboards/desktop
Product Description
1.10 Audio Subsystem
The Audio Codec ’97 (AC ’97) compatible audio subsystem includes these features:
• Split digital/analog architecture for improved signal-to-noise ratio (≥ 85 dB) measured at line
out, from any analog input, including line in, and CD-ROM
• ATAPI CD-ROM (connects an internal ATAPI CD-ROM drive to the audio mixer)
For information aboutRefer to
The back panel audio connectorsSection 2.8.1, page 39
The location of the ATAPI CD-ROM connectorFigure 5, page 41
The signal names of the ATAPI CD-ROM connectorTable 29, page 45
1.11 Hardware Monitor Component
The hardware monitor component provides low-cost instrumentation capabilities. The features of
the component include:
• Internal ambient temperature sensing
• Remote thermal diode sensing for direct monitoring of processor temperature
• Power supply monitoring (+12, +5, +3.3, +2.5, V
acceptable values
• SMBus interface
• The hardware monitor component enables the board to be compatible with the Wired for
Management (WfM) specification.
CCP) to detect levels above or below
For information aboutRefer to
The board’s compatibility with the WfM specificationTable 2, page 13
24
Product Description
1.12 LAN Subsystem
The Intel 82559 Fast Ethernet Wired for Management (WfM) PCI LAN subsystem provides both
10Base-T and 100Base-TX connectivity. Features include:
• 32-bit, 33 MHz direct bus mastering on the PCI bus
• 10Base-T and 100Base-TX capability using a single RJ-45 connector with connection and
activity status LEDs
• IEEE 802.3u Auto-Negotiation for the fastest available connection
• Jumperless configuration; the LAN subsystem is completely software-configurable
For information aboutRefer to
The WfM specificationTable 2, page 13
1.12.1 Intel® 82559 PCI LAN Controller
The Intel 82559 PCI LAN controller’s features include:
• CSMA/CD Protocol Engine
• PCI bus interface
• DMA engine for movement of commands, status, and network data across the PCI bus
• Integrated physical layer interface, including:
Complete functionality necessary for the 10Base-T and 100Base-TX network interfaces;
when in 10 Mbit/sec mode, the interface drives the cable directly
A complete set of Media Independent Interface (MII) management registers for control
and status reporting
IEEE 802.3u Auto-Negotiation for automatically establishing the best operating mode
when connected to other 10Base-T or 100Base-TX devices, whether half- or full-duplex
capable
• Integrated power management features, including support for wake on network event (from an ACPI
S3 state using the PCI bus PME# signal)
For information aboutRefer to
The LAN subsystem’s PCI specification complianceTable 2, page 13
The Intel 82559 Fast Ethernet WfM PCI LAN software and drivers are available from Intel’s
World Wide Web site.
For information aboutRefer to
Obtaining LAN software and driversSection 1.2, page 13
1.12.3 RJ-45 LAN Connector LEDs
Two LEDs are built into the RJ-45 LAN connector. Table 6 describes the LED states when the
board is powered up and the LAN subsystem is operating.
Table 6.LAN Connector LED States
LED ColorLED StateCondition
Off10 Mbit/sec data rate is selected.Green
On100 Mbit/sec date rate is selected.
Yellow
OffLAN link is not established.
On (steady state)LAN link is established.
On (brighter and pulsing)The computer is communicating with another computer on
the LAN.
26
Product Description
1.13 Power Management Features
Power management is implemented at several levels, including:
• Advanced Configuration and Power Interface (ACPI)
• Hardware support:
Power connector
Wake on network event
Instantly Available technology
Wake on Ring
Resume on Ring
1.13.1 ACPI
If the board is used with an ACPI-aware operating system, the BIOS can provide ACPI support.
ACPI gives the operating system direct control over the power management and Plug and Play
functions of a computer. The use of ACPI with this board requires the support of an operating
system that provides full ACPI functionality. ACPI features include:
• Plug and Play (including bus and device enumeration)
• Power management control of individual devices, add-in boards (some add-in boards may
require an ACPI-aware driver), video displays, and hard disk drives
• Methods for achieving less than 30-watt system operation in the Power On Suspend sleeping
state, and less than 5-watt system operation in the Suspend to RAM sleeping state
• A Soft-off feature that enables the operating system to power off the computer
• Support for multiple wake up events (see Table 9 on page 29)
• Support for a front panel power and sleep mode switch. Table 7 lists the system states based
on how long the power switch is pressed, depending on how ACPI is configured with an
ACPI-aware operating system.
Table 7.Effects of Pressing the Power Switch
…and the power switch is
If the system is in this state…
Off(ACPI G2/S5 state)Less than four secondsPower on
On(ACPI G0 state)Less than four secondsSoft off/Suspend
On(ACPI G0 state)More than four secondsFail safe power off
Sleep(ACPI G1 state)Less than four secondsWake up
Sleep(ACPI G1 state)More than four secondsPower off
For information aboutRefer to
The board’s compliance level with ACPISection 1.3, page 13
Under ACPI, the operating system directs all system and device power state transitions. The
operating system puts devices in and out of low-power states based on user preferences and
knowledge of how devices are being used by applications. Devices that are not being used can be
turned off. The operating system uses information from applications and user settings to put the
system as a whole into a low-power state.
Table 8 lists the power states supported by the board along with the associated system power
targets. See the ACPI specification for a complete description of the various system and power
states.
Table 8.Power States and Targeted System Power
Global StatesSleeping StatesCPU StatesDevice StatesTargeted System Power*
G0 – working
state
G1 – sleeping
state
G1 – sleeping
state
G2/S5S5 – Soft off.
G3 –
mechanical off.
AC power is
disconnected
from the
computer.
*Total system power is dependent on the system configuration, including add-in boards and peripherals powered by the
system chassis’ power supply.
**Dependent on the standby power consumpt i on of wake up devices used in the system.
S0 – workingC0 – workingD0 – working
state
S1 – CPU stoppedC1 – stop
grant
S3 – Suspend-toRAM. Context
saved to RAM.
Context not saved.
Cold boot is
required.
No power to the
system.
No powerD3 – no power
No powerD3 – no power
No powerD3 – no power for
D1, D2, D3 –
device
specification
specific.
except for wake
up logic.
except for wake
up logic.
wake up logic,
except when
provided by
battery or external
source.
Full power > 30 W
5 W < power < 30 W
Power < 5 W **
Power < 5 W **
No power to t he system so
that service can be
performed.
28
Product Description
1.13.1.2 Wake Up Devices and Events
Table 9 lists the devices or specific events that can wake the computer from specific states.
Table 9.Wake Up Devices and Events
These devices/events can wake up the computer……from this state
Power switchS1, S3, S5
RTC alarmS1, S3, S5
LANS1, S3
ModemS1, S3
USBS1, S3
PCI bus PME#S3
1.13.1.3 Plug and Play
In addition to power management, ACPI provides controls and information so that the operating
system can facilitate Plug and Play device enumeration and configuration. ACPI is used only to
enumerate and configure devices that do not have other hardware standards for enumeration and
configuration. PCI devices on a desktop board, for example, are not enumerated by ACPI.
1.13.2 Hardware Support
CAUTION
If Wake on network event and Instantly Available technology features are used, the power supply
must be capable of providing adequate +5 V standby current. Failure to provide adequate standby
current can damage the power supply. The total amount of standby current required depends on
the wake devices supported and manufacturing options. Refer to Section 2.11.3 on page 54 for
additional information.
The board provides several hardware features that support power management, including:
• Power connector
• Wake on network event
• Instantly Available technology
• Wake on Ring
• Resume on Ring
Wake on network event and Instantly Available technology require power from the +5 V standby
line. The sections discussing these features describe the incremental standby power requirements
for each.
Wake on Ring and Resume on Ring enable telephony devices to access the computer when it is in
a power-managed state. The method used depends on the type of telephony device (external or
internal) and the power management mode being used (ACPI).
NOTE
✏
The use of Wake on Ring and Resume on Ring technologies from an ACPI state require the support
of an operating system that provides full ACPI functionality.
When used with an ATX-compliant power supply that supports remote power on/off, the board can
turn off the system power through software control. To enable soft-off control in software,
advanced power management must be enabled in the BIOS Setup program and in the operating
system. When the system BIOS receives the correct power management command from the
operating system, the BIOS turns off power to the computer.
With soft-off enabled, if power to the computer is interrupted by a power outage or a disconnected
power cord, when power resumes, the computer returns to the power state it was in before power
was interrupted (on or off).
For information aboutRefer to
The location of the power connectorFigure 5, page 41
The signal names of the power connectorTable 27, page 44
The ATX specificationSection 1.3, page 13
1.13.2.2 Fan Connectors
The board has two fan connectors. The functions of these connectors are described in Table 10.
Table 10.Fan Connector Descriptions
ConnectorFunction
Chassis fanProvides +12 V DC for a system o r chassis fan.
Processor fanProvides +12 V DC for a processor fan or active fan heatsink.
For information aboutRefer to
The location of the fan connectorsFigure 5, page 41
The signal names of the chassis fan connectorTable 22, page 42
The signal names of the processor fan connectorTable 23, page 42
1.13.2.3 Wake on Network Event
CAUTION
For Wake on network event, the +5 V standby line for the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
implementing Wake on network event can damage the power supply. Refer to Section 2.11.3 on
page 54 for additional information.
Wake on network event enables remote wakeup of the computer through a network. The LAN
subsystem, whether onboard or as a PCI bus network adapter, monitors network traffic at the
†
Media Independent Interface. Upon detecting a Magic Packet
wakeup signal that powers up the computer. The board supports Wake on network event through
the PCI bus PME# signal.
, the LAN subsystem asserts a
30
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