The Intel® Desktop Board D810EMO/MO810E may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current
characterized errata are documented in the Intel Desktop Board D810EMO/MO810E Specification Update.
Revision History
RevisionRevision HistoryDate
-001First release of the Intel® Desktop Board D810EMO/MO810E Technical
Product Specification
This product specification applies to only standard D810EMO/MO810E boards with BIOS
identifier MO81010A.86A.
Changes to this specification will be published in the Intel Desktop Board D810EMO/MO810E
Specification Update before being incorporated into a revision of this document.
February 2000
Information in this doc um ent is provided in connecti on wi th Intel® products. No license, express or implied, by es toppel or
otherwise, to any intell ectual property rights is granted by this document. E xcept as provided in Int el ’s Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and I nt el disclaims any express or implied
warranty, relating to sale and/or use of I ntel products including liability or warranties relat i ng t o fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel produc ts are not
intended for use in medical, l i f e saving, or life sustaining applications.
Intel may make changes t o specifications and product descriptions at any time, without noti ce.
The D810EMO/MO810E board may cont ai n des i gn defects or errors known as errat a t hat may cause the product to deviate
from published specifi c ations. Current characteri z ed errata are available on request.
Contact your local Int el sales office or your dis tributor to obtain the lates t specifications before placing your product order.
Copies of documents whic h hav e an orderi ng number and are referenced in this document , or other Intel literature, m ay be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
†
All other brands and names are the property of their respective owners.
Copyright 2000, Intel Corporation. All rights reserved.
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and the BIOS for the D810EMO/MO810E desktop board.
It describes the standard product and available manufacturing options.
The D810EMO desktop board is known in some documentation and sales collateral as the
MO810E. Both names refer to the same product.
Intended Audience
The TPS is intended to provide detailed, technical information about the board and its components
to the vendors, system integrators, and other engineers and technicians who need this level of
information. It is specifically not intended for general audiences.
What This Document Contains
ChapterDescription
1A description of the hardware used on this board
2A map of the resources of the board
3The features supported by the BIOS Setup program
4The contents of the BIOS Setup program’s menus and submenus
5A description of the BIOS error messages, beep codes, and POST codes
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions that, if not observed, can cause personal injury.
#Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX)When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the board, and X is the instance of the particular part at that
general location. For example, J5J1 is a connector, located at 5J. It is the first connector in the
5J area.
KBKilobyte (1024 bytes)
KbitKilobit (1024 bits)
MBMegabyte (1,048,576 bytes)
MbitMegabit (1,048,576 bits)
GBGigabyte (1,073,741,824 bytes)
xxhAn address or data value ending with a lowercase h indicates a hexadecimal value.
x.x VVolts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
Version 1.1, October 17, 1995
Infrared Data Association
Phone: (510) 943-6546
Fax: (510) 943-5600
Version 1.0,
September 29, 1997,
Intel Corporation.
Version 1.0,
December 1997
Intel Corporation
Version 1.1,
February 1998
Intel Corporation
Version 2.2,
December 18, 1998,
PCI Special Interest Group.
Version 1.1,
December 18, 1998,
PCI Special Interest Group.
Version 1.0a,
May 5, 1994,
Compaq Computer Corp.,
Phoenix Technologies Ltd.,
and Intel Corporation.
Revision 1.0,
February 1998,
Intel Corporation.
Revision 1.2A,
December 1997,
Intel Corporation
Version 2.3,
August 12, 1998,
Award Software International Inc.,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
American Megatrends Inc.,
and SystemSoft Corporation.
The board supports processors that draw a maximum of 22 amps. Using a processor that draws
more than 22 amps can damage the processor, the board, and the power supply. See the
processor’s data sheet for current usage requirements.
The board supports the processors listed in Table 3. The host bus frequency is automatically
selected.
Table 3.Processors Supported by the Board
Processor TypeProcessor SpeedHost Bus FrequencyL2 Cache Size
600EB MHz133 MHz256 KBPentium III processor
600E MHz
550E MHz
500E MHz
Celeron processor533 MHz
500 MHz
466 MHz
433 MHz
400 MHz
366 MHz
100 MHz
100 MHz
100 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
256 KB
256 KB
256 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
All supported onboard memory can be cached, up to the cachability limit of the processor.
For information aboutRefer to
Processor support for the D810EMO/MO810E
board
Processor data sheetshttp://www.intel.com/design/litcentr
To be fully compliant with all applicable Intel® SDRAM memory specifications, the board should
be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. If your
memory modules do not support SPD, you will see a notification to this effect on the screen at
power up. The BIOS will attempt to configure the memory controller for normal operation;
however, DIMMs may not function at the determined frequency.
CAUTION
Because the main system memory is also used as video memory, the board requires a 100 MHz
SDRAM DIMM even though the host bus frequency is 66 MHz. It is highly recommended that an
SPD DIMM be used, since this allows the BIOS to read the SPD data and program the chipset to
accurately configure memory settings for optimum performance. If non-SPD memory is installed,
the BIOS will attempt to correctly configure the memory settings, but performance and reliability
may be impacted.
The board has one DIMM socket. The minimum memory size is 32 MB and the maximum
memory size is 256 MB. The BIOS automatically detects memory type, size, and frequency.
The board supports the following memory features:
• 3.3 V, 168-pin DIMM with gold-plated contacts
• 100 MHz SDRAM
• Serial Presence Detect (SPD) or non-SPD memory (BIOS recovery requires an SPD DIMM)
• Non-ECC (64-bit) memory
• Unbuffered single- or double-sided DIMM
The board is designed to support the DIMM configurations listed in Table 4 below.
Table 4.System Memory Configuration
DIMM SizeNon-ECC Configuration
32 MB4 Mbit x 64
64 MB8 Mbit x 64
128 MB16 Mbit x 64
256 MB (Note)32 Mbit x 64
Note:A 256 MB DIMM used with this board must be built with 128 Mbit device technol ogy.
For information aboutRefer to
The
PC Serial Presence Detect Specification
Obtaining copies of PC SDRAM specificationshttp://www.intel.com/design/pcisets/memory
The chipset provides the host, memory, display, and I/O interfaces shown in Figure 3.
66/100/133 MHz
Host Bus
ATA33/66USB
810E Chipset
100 MHz
SDRAM
Bus
Display
Interface
82810E
Graphics Memory
Controller Hub
(GMCH)
AHA
Bus
82801AA I/O Controller Hub
(ICH)
SMBus
PCI Bus
AC Link
Figure 3. Intel 810E Chipset Block Diagram
For information about Refer to
The Intel 810E chipsethttp://developer.intel.comThe resources used by the chipsetChapter 2The chipset’s compliance with ACPI and AC ‘97Table 2, page 13
82802AB
Firmware Hub
(FWH)
LPC Bus
OM09130
18
Product Description
1.6.1 Direct AGP
Direct (integrated) AGP is a high-performance bus (independent of the PCI bus) for
graphics-intensive applications, such as 3-D applications. AGP overcomes certain limitations of
the PCI bus related to handling large amount of graphics data with the following features:
• Pipelined memory read and write operations that hide memory access latency
• Demultiplexing of address and data on the bus for nearly 100 percent bus efficiency
For information aboutRefer to
The location of the VGA port connectorFigure 4, page 39
Obtaining the
Accelerated Graphics Port Interface Specification
Table 2, page 13
1.6.2 USB
The board supports up to four USB ports; one USB peripheral can be connected to each port. For
more than four USB devices, an external hub can be connected to any of the ports. Two USB ports
are implemented with stacked back panel connectors. The other two ports can be routed from the
connector at location J7A1 via a cable to the front panel. The board fully supports UHCI and uses
UHCI-compatible software drivers. USB features include:
• Support for self-identifying peripherals that can be connected or disconnected while the
computer is running
• Automatic mapping of function to driver and configuration
• Support for isochronous and asynchronous transfer types over the same set of wires
• Support for up to 127 physical devices
• Guaranteed bandwidth and low latencies appropriate for telephony, audio, and other
applications
• Error-handling and fault-recovery mechanisms built into the protocol
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
For information aboutRefer to
The location of the USB connectors on the back panelFigure 4, page 39
The signal names of the USB connectorsTable 17, page 40
The location of the USB port connector for the front panelFigure 6, page 46
The signal names for the USB port connector for the front panelTable 30, page 47
The USB and UHCI specificationsTable 2, page 13
The board has two independent bus-mastering IDE interfaces. These interfaces support:
• ATAPI devices (such as CD-ROM drives)
• ATA devices using the transfer modes listed in Table 51 on page 79
The BIOS supports logical block addressing (LBA) and extended cylinder head sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The board supports laser servo (LS-120) diskette technology through its IDE interfaces. The
LS-120 drive can be configured as a boot device by setting the BIOS Setup program’s Boot menu
to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
The board has two IDE interface connectors. The primary IDE connector is a standard 40-pin IDE
interface. The secondary IDE connector is a 50-pin Slimline IDE connector, intended for use with
devices such as 2.5-inch hard disk drives and mobile CD-ROM drives. The Slimline IDE
connector has the standard IDE interface pins but also includes audio and power signals.
For information aboutRefer to
The location of the IDE connectorsFigure 5, page 41
The signal names of the primary IDE connectorTable 24, page 42
The signal names of the Slimline secondary IDE connectorTable 25, page 43
BIOS Setup program’s Boot menuTable 56, page 85
1.6.4 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock is compatible with DS1287 and MC146818 components. The clock provides a
time-of-day clock and a multicentury calendar with alarm features and century rollover. The
real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reserved
for BIOS use.
A coin-cell battery powers the real-time clock and CMOS memory. When the computer is not
plugged into a wall socket, the battery has an estimated life of three years. When the computer is
plugged in, the 3.3 V standby current from the power supply extends the life of the battery. The
clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
NOTE
✏
If the battery and AC power fail, standard defaults, not custom defaults, will be loaded into CMOS
RAM at power on.
20
Product Description
NOTE
✏
The recommended method of accessing the date in systems with Intel desktop boards is indirectly
from the Real-Time Clock (RTC) via the BIOS. The BIOS on Intel desktop boards contains a
century checking and maintenance feature. This feature checks the two least significant digits of
the year stored in the RTC during each BIOS request (INT 1Ah) to read the date and, if less than
80 (i.e., 1980 is the first year supported by the PC), updates the century byte to 20. This feature
enables operating systems and applications using the BIOS date/time services to reliably
manipulate the year as a four-digit value.
For information aboutRefer to
Proper date access in systems with Intel de sktop boardshttp://support.intel.com/support/year2000/
1.7 I/O Controller
The SMSC LPC47M102 I/O controller provides the following features:
• Low pin count (LPC) interface
• One serial port
• Infrared (IrDA) interface
• Intelligent power management, including a programmable wake up event interface
• Fan control:
One pulse width modulation (PWM) fan speed control output
One fan tachometer input
The BIOS Setup program provides configuration options for the I/O controller.
For information aboutRefer to
SMSC LPC47M102 I/O controllerhttp://www.smsc.com
The IrDA interfaceSection 2.8.3, page 46
1.8 Serial Debug Port
The board has one 9-pin serial debug port connector. The serial debug port’s
NS16C550-compatible UART supports data transfers at rates of up to 115.2 kbits/sec with BIOS
support. The serial debug port can be assigned as COM1 (3F8h), COM2 (2F8h), COM3 (3E8h), or
COM4 (2E8h).
For information aboutRefer to
The location of the serial debug port connectorFigure 5, page 41
The signal names of the serial debug port connectorTable 26, page 43
16 colors60, 70, 72, 75, 85
256 colors60, 70, 72, 75, 85
64 K colors60, 70, 72, 75, 85
16 M colors60, 70, 72, 75, 85
256 colors75, 85
64 K colors75, 85
16 M colors75, 85
256 colors60, 75, 85
64 K colors60, 75, 85
16 M colors60, 75, 85
256 colors60, 70, 72, 75, 85
64 K colors60, 70, 72, 75, 85
16 M colors60, 70, 72, 75, 85
256 colors60, 70, 72, 75, 85
64 K colors60, 70, 72, 75, 85
16 M colors60, 70, 72, 75, 85
256 colors60, 70, 72, 75, 85
64 K colors60, 70, 72, 75, 85
16 M colors60, 70, 72, 75, 85
256 colors60, 70, 72, 75, 85
64 K colors60, 70, 72, 75, 85
16 M colors60, 70, 75, 85
22
For information aboutRefer to
Obtaining graphics software and utilitieshttp://support.intel.com/support/motherboards/desktop
Product Description
1.10 Audio Subsystem
The Audio Codec ’97 (AC ’97) compatible audio subsystem includes these features:
• Split digital/analog architecture for improved signal-to-noise ratio (≥ 85 dB) measured at line
out, from any analog input, including line in, and CD-ROM
• ATAPI CD-ROM (connects an internal ATAPI CD-ROM drive to the audio mixer)
For information aboutRefer to
The back panel audio connectorsSection 2.8.1, page 39
The location of the ATAPI CD-ROM connectorFigure 5, page 41
The signal names of the ATAPI CD-ROM connectorTable 29, page 45
1.11 Hardware Monitor Component
The hardware monitor component provides low-cost instrumentation capabilities. The features of
the component include:
• Internal ambient temperature sensing
• Remote thermal diode sensing for direct monitoring of processor temperature
• Power supply monitoring (+12, +5, +3.3, +2.5, V
acceptable values
• SMBus interface
• The hardware monitor component enables the board to be compatible with the Wired for
Management (WfM) specification.
CCP) to detect levels above or below
For information aboutRefer to
The board’s compatibility with the WfM specificationTable 2, page 13
24
Product Description
1.12 LAN Subsystem
The Intel 82559 Fast Ethernet Wired for Management (WfM) PCI LAN subsystem provides both
10Base-T and 100Base-TX connectivity. Features include:
• 32-bit, 33 MHz direct bus mastering on the PCI bus
• 10Base-T and 100Base-TX capability using a single RJ-45 connector with connection and
activity status LEDs
• IEEE 802.3u Auto-Negotiation for the fastest available connection
• Jumperless configuration; the LAN subsystem is completely software-configurable
For information aboutRefer to
The WfM specificationTable 2, page 13
1.12.1 Intel® 82559 PCI LAN Controller
The Intel 82559 PCI LAN controller’s features include:
• CSMA/CD Protocol Engine
• PCI bus interface
• DMA engine for movement of commands, status, and network data across the PCI bus
• Integrated physical layer interface, including:
Complete functionality necessary for the 10Base-T and 100Base-TX network interfaces;
when in 10 Mbit/sec mode, the interface drives the cable directly
A complete set of Media Independent Interface (MII) management registers for control
and status reporting
IEEE 802.3u Auto-Negotiation for automatically establishing the best operating mode
when connected to other 10Base-T or 100Base-TX devices, whether half- or full-duplex
capable
• Integrated power management features, including support for wake on network event (from an ACPI
S3 state using the PCI bus PME# signal)
For information aboutRefer to
The LAN subsystem’s PCI specification complianceTable 2, page 13
The Intel 82559 Fast Ethernet WfM PCI LAN software and drivers are available from Intel’s
World Wide Web site.
For information aboutRefer to
Obtaining LAN software and driversSection 1.2, page 13
1.12.3 RJ-45 LAN Connector LEDs
Two LEDs are built into the RJ-45 LAN connector. Table 6 describes the LED states when the
board is powered up and the LAN subsystem is operating.
Table 6.LAN Connector LED States
LED ColorLED StateCondition
Off10 Mbit/sec data rate is selected.Green
On100 Mbit/sec date rate is selected.
Yellow
OffLAN link is not established.
On (steady state)LAN link is established.
On (brighter and pulsing)The computer is communicating with another computer on
the LAN.
26
Product Description
1.13 Power Management Features
Power management is implemented at several levels, including:
• Advanced Configuration and Power Interface (ACPI)
• Hardware support:
Power connector
Wake on network event
Instantly Available technology
Wake on Ring
Resume on Ring
1.13.1 ACPI
If the board is used with an ACPI-aware operating system, the BIOS can provide ACPI support.
ACPI gives the operating system direct control over the power management and Plug and Play
functions of a computer. The use of ACPI with this board requires the support of an operating
system that provides full ACPI functionality. ACPI features include:
• Plug and Play (including bus and device enumeration)
• Power management control of individual devices, add-in boards (some add-in boards may
require an ACPI-aware driver), video displays, and hard disk drives
• Methods for achieving less than 30-watt system operation in the Power On Suspend sleeping
state, and less than 5-watt system operation in the Suspend to RAM sleeping state
• A Soft-off feature that enables the operating system to power off the computer
• Support for multiple wake up events (see Table 9 on page 29)
• Support for a front panel power and sleep mode switch. Table 7 lists the system states based
on how long the power switch is pressed, depending on how ACPI is configured with an
ACPI-aware operating system.
Table 7.Effects of Pressing the Power Switch
…and the power switch is
If the system is in this state…
Off(ACPI G2/S5 state)Less than four secondsPower on
On(ACPI G0 state)Less than four secondsSoft off/Suspend
On(ACPI G0 state)More than four secondsFail safe power off
Sleep(ACPI G1 state)Less than four secondsWake up
Sleep(ACPI G1 state)More than four secondsPower off
For information aboutRefer to
The board’s compliance level with ACPISection 1.3, page 13
Under ACPI, the operating system directs all system and device power state transitions. The
operating system puts devices in and out of low-power states based on user preferences and
knowledge of how devices are being used by applications. Devices that are not being used can be
turned off. The operating system uses information from applications and user settings to put the
system as a whole into a low-power state.
Table 8 lists the power states supported by the board along with the associated system power
targets. See the ACPI specification for a complete description of the various system and power
states.
Table 8.Power States and Targeted System Power
Global StatesSleeping StatesCPU StatesDevice StatesTargeted System Power*
G0 – working
state
G1 – sleeping
state
G1 – sleeping
state
G2/S5S5 – Soft off.
G3 –
mechanical off.
AC power is
disconnected
from the
computer.
*Total system power is dependent on the system configuration, including add-in boards and peripherals powered by the
system chassis’ power supply.
**Dependent on the standby power consumpt i on of wake up devices used in the system.
S0 – workingC0 – workingD0 – working
state
S1 – CPU stoppedC1 – stop
grant
S3 – Suspend-toRAM. Context
saved to RAM.
Context not saved.
Cold boot is
required.
No power to the
system.
No powerD3 – no power
No powerD3 – no power
No powerD3 – no power for
D1, D2, D3 –
device
specification
specific.
except for wake
up logic.
except for wake
up logic.
wake up logic,
except when
provided by
battery or external
source.
Full power > 30 W
5 W < power < 30 W
Power < 5 W **
Power < 5 W **
No power to t he system so
that service can be
performed.
28
Product Description
1.13.1.2 Wake Up Devices and Events
Table 9 lists the devices or specific events that can wake the computer from specific states.
Table 9.Wake Up Devices and Events
These devices/events can wake up the computer……from this state
Power switchS1, S3, S5
RTC alarmS1, S3, S5
LANS1, S3
ModemS1, S3
USBS1, S3
PCI bus PME#S3
1.13.1.3 Plug and Play
In addition to power management, ACPI provides controls and information so that the operating
system can facilitate Plug and Play device enumeration and configuration. ACPI is used only to
enumerate and configure devices that do not have other hardware standards for enumeration and
configuration. PCI devices on a desktop board, for example, are not enumerated by ACPI.
1.13.2 Hardware Support
CAUTION
If Wake on network event and Instantly Available technology features are used, the power supply
must be capable of providing adequate +5 V standby current. Failure to provide adequate standby
current can damage the power supply. The total amount of standby current required depends on
the wake devices supported and manufacturing options. Refer to Section 2.11.3 on page 54 for
additional information.
The board provides several hardware features that support power management, including:
• Power connector
• Wake on network event
• Instantly Available technology
• Wake on Ring
• Resume on Ring
Wake on network event and Instantly Available technology require power from the +5 V standby
line. The sections discussing these features describe the incremental standby power requirements
for each.
Wake on Ring and Resume on Ring enable telephony devices to access the computer when it is in
a power-managed state. The method used depends on the type of telephony device (external or
internal) and the power management mode being used (ACPI).
NOTE
✏
The use of Wake on Ring and Resume on Ring technologies from an ACPI state require the support
of an operating system that provides full ACPI functionality.
When used with an ATX-compliant power supply that supports remote power on/off, the board can
turn off the system power through software control. To enable soft-off control in software,
advanced power management must be enabled in the BIOS Setup program and in the operating
system. When the system BIOS receives the correct power management command from the
operating system, the BIOS turns off power to the computer.
With soft-off enabled, if power to the computer is interrupted by a power outage or a disconnected
power cord, when power resumes, the computer returns to the power state it was in before power
was interrupted (on or off).
For information aboutRefer to
The location of the power connectorFigure 5, page 41
The signal names of the power connectorTable 27, page 44
The ATX specificationSection 1.3, page 13
1.13.2.2 Fan Connectors
The board has two fan connectors. The functions of these connectors are described in Table 10.
Table 10.Fan Connector Descriptions
ConnectorFunction
Chassis fanProvides +12 V DC for a system o r chassis fan.
Processor fanProvides +12 V DC for a processor fan or active fan heatsink.
For information aboutRefer to
The location of the fan connectorsFigure 5, page 41
The signal names of the chassis fan connectorTable 22, page 42
The signal names of the processor fan connectorTable 23, page 42
1.13.2.3 Wake on Network Event
CAUTION
For Wake on network event, the +5 V standby line for the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
implementing Wake on network event can damage the power supply. Refer to Section 2.11.3 on
page 54 for additional information.
Wake on network event enables remote wakeup of the computer through a network. The LAN
subsystem, whether onboard or as a PCI bus network adapter, monitors network traffic at the
†
Media Independent Interface. Upon detecting a Magic Packet
wakeup signal that powers up the computer. The board supports Wake on network event through
the PCI bus PME# signal.
, the LAN subsystem asserts a
30
Product Description
1.13.2.4 Instantly Available Technology
CAUTION
For Instantly Available technology, the +5 V standby line for the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
using this feature can damage the power supply. Refer to Section 2.11.3 on page 54 for additional
information.
Instantly Available technology enables the board to enter the ACPI S3 (Suspend-to-RAM) sleepstate. While in the S3 sleep-state, the computer will appear to be off (the power supply is off, the
fans are off, and the power LED is amber). When signaled by a wake up device or event, the
system quickly returns to its last known wake state. Table 9 on page 29 lists the devices and
events that can wake the computer from the S3 state.
The board supports the PCI Bus Power Management Interface Specification. For information on
the versions of these specifications, see Section 1.3. Add-in boards that also support these
specifications can participate in power management and can be used to wake the computer.
1.13.2.5 Wake on Ring
NOTE
✏
Wake on Ring requires the use of a modem (external USB or internal PCI) that supports the Wake
on Ring feature.
The operation of Wake on Ring can be summarized as follows:
• Wakes up the computer from the ACPI S5 state
• Requires two calls to access the computer:
First call restores the computer
Second call enables access (when the appropriate software is loaded)
• Detects incoming calls differently for external as opposed to internal modems:
For external USB modems, the USB bus is monitored for the RING_DETECT signal
For internal PCI modems, incoming calls are detected through the PCI bus PME# signal
1.13.2.6 Resume on Ring
The operation of Resume on Ring can be summarized as follows:
• Resumes operation from the ACPI S1 state
• Requires only one call to access the computer
• Detects incoming call similarly for external and internal modems
Sections 2.2 – 2.6 contain several standalone tables. Table 11 describes the system memory map,
Table 12 shows the I/O map, Table 13 lists the DMA channels, Table 14 defines the PCI
configuration space map, and Table 15 describes the interrupts. The remaining sections in this
chapter are introduced by text found with their respective section headings.
2.2 Memory Map
Table 11.System Memory Map
Address Range (decimal)Address Range (hex)SizeDescription
1024 K – 262144 K100000 – FFFFFFF255 MBExtended memory
960 K – 1024 KF0000 – FFFFF64 KBRuntime BIOS
896 K – 960 KE0000 – EFFFF64 KBReserved
800 K – 896 KC8000 – DFFFF96 KBAvailable high DOS memory (open
to PCI bus)
640 K – 800 KA0000 – C7FFF160 KBVideo memory and BIOS
639 K – 640 K9FC00 – 9FFFF1 KBExtended BIOS data (movable by
0CF9
0CFC – 0CFF4 bytesPCI configuration data register
FFA0 – FFA78 bytesPrimary bus master IDE registers
FFA8 – FFAF8 bytesSecondary bus master IDE registers
1
8 bytesCOM4/video (8514A)
1
8 bytesCOM2
2
4 bytesPCI configuration address register
1 byteTurbo and reset control register
continued
34
Table 12.I/O Map (continued)
Address (hex)SizeDescription
96 contiguous bytes starting on a
128-byte divisible boundary
64 contiguous bytes starting on a
64-byte divisible boundary
32 contiguous bytes starting on a
32-byte divisible boundary
16 contiguous bytes starting on a
16-byte divisible boundary
4096 contiguous bytes starting on
a 4096-byte divisible boundary
32 contiguous bytes starting on a
32-byte divisible boundary
96 contiguous bytes starting on a
128-byte divisible boundary
64 contiguous bytes starting on a
64-byte divisible boundary
Notes:
1.Default, but can be changed to another address range
2.Dword access only
3. Byte access only
ICH (ACPI + TCO)
Onboard resource
ICH (USB)
ICH (SMBus)
Intel 82810EAA PCI Bridge
Intel 82559 LAN Controller
LPC47M102 PME Status
Creative ES1373D Digital Audio Controller
Technical Reference
✏ NOTE
Some additional I/O addresses are not available due to ICH addresses aliasing. For information
about ICH addressing, refer to Intel web site at:
000000Memory controller of Intel 82810E component
000100Graphics controller of Intel 82810E component
001E00Link to PCI bridge
001F00PCI-to-LPC bridge
001F01IDE controller
001F02USB controller #1
001F03SMBus controller
001F04Reserved
001F05AC ’97 audio controller
001F06AC ’97 modem controller
010100Intel 82559 PCI LAN controller
010700PCI Audio Accelerator ES1373D
010900PCI bus connector
Device
Number (hex)
Function
Number (hex)Description
2.6 Interrupts
Table 15.Interrupts
IRQSystem Resource
NMII/O channel check
0Reserved, interval timer
1Reserved, keyboard buffer full
2Reserved, cascade interrupt from slave PIC
3COM2*
4COM1*
5User available
6User available
7Audio / User available *
8Real-time Clock
9Reserved for ICH system management bus
10User available
11User available
12User available
13Reserved, math coprocessor
14Primary IDE (if present, else user available)
15Secondary IDE (if present, else user available)
*Default, but can be changed to anot her IRQ
36
Technical Reference
2.7 PCI Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected between the
PCI bus connector and onboard PCI devices. The PCI specification specifies how interrupts can be
shared between devices attached to the PCI bus. In most cases, the small amount of latency added
by interrupt sharing does not affect the operation or throughput of the devices. In some special
cases where maximum performance is needed from a device, a PCI device should not share an
interrupt with other PCI devices. Use the following information to avoid sharing an interrupt with
a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
• INTA: By default, all add-in cards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
• INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is
classified as INTB. (This is not an absolute requirement.)
• INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a
fourth interrupt is classified as INTD.
The ICH PCI-to-LPC bridge has four programmable interrupt request (PIRQ) input signals. Any
PCI interrupt source (either onboard or from a PCI add-in card) connects to one of these
PIRQ signals. Because there are only four signals, some PCI interrupt sources are mechanically
tied together on the board and therefore share the same interrupt. Table 16 lists the PIRQ signals
and shows how the signals are connected to the PCI bus connectors and to onboard PCI interrupt
sources.
Table 16.PCI Interrupt Routing Map
ICH PIRQ Signal Name
✏
PCI Interrupt Source
AGP Controller
ICH Audio Controller
ICH USB Controller
Intel 82559 PCI LAN Controller
PCI Bus Connector
NOTE
PIRQAPIRQBPIRQCPIRQD
INTA
INTC
INTC
INTAINTBINTCINTD
The ICH can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 10, 11, 14,
and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt.
However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ
lines to be connected to the same IRQ signal.
Only the back panel I/O connectors of the board have overcurrent protection. The internal board
connectors are not overcurrent protected, and should connect only to devices inside the computer
chassis, such as fans and internal peripherals. Do not use these connectors for powering devices
external to the computer chassis. A fault in the load presented by the external devices could cause
damage to the computer, the interconnecting cable, and the external devices themselves.
This section describes the board’s connectors. The connectors can be divided into the following
groups:
• Back panel I/O connectors (see page 39)
USB (2)
VGA
LAN
Audio line out
Mic in
• Internal I/O connectors (see page 41)
Fans (2)
IDE (2)
Serial debug port
Power
PCI
ATAPI CD-ROM
• External I/O connectors (see page 46)
USB ports
Front panel (Power/Sleep/Message waiting LED, power switch, hard drive activity LED,
reset switch, and infrared port)
38
2.8.1 Back Panel I/O Connectors
Figure 4 shows the location of the back panel I/O connectors.
Technical Reference
CDFEAB
OM08925
ItemDescription
AUSB port 0(see Table 17, page 40)
BUSB port 1(see Table 17, page 40)
CVGA port (see Table 18, page 40)
DLAN(see Table 19, page 40)
EAudio line out (see Table 20, page 40)
FMic in (see Table 21, page 40)
Figure 4. Back Panel I/O Connectors
NOTE
✏
The back panel audio line out connector is designed to power headphones or amplified speakers
only. Poor audio quality may occur if passive (non-amplified) speakers are connected to this
output.
2.8.3.2.1 Power / Sleep / Message Waiting LED Connector
Pins 2 and 4 can be connected to a single- or dual-colored LED. Table 32 lists the possible states
for a single-colored LED. Table 33 shows the possible states for a dual-colored LED.
To use the message waiting function, ACPI must be enabled in the operating system and a
message-capturing application must be invoked.
2.8.3.2.2 Power Switch Connector
Pins 6 and 8 can be connected to a front panel power switch. The switch must pull pin 6 to ground
for at least 50 ms to signal the power supply to switch on or off. (The time requirement is due to
internal debounce circuitry on the board.) At least two seconds must pass before the power supply
will recognize another on/off signal.
2.8.3.2.3 Hard Drive Activity LED Connector
Pins 1 and 3 can be connected to an LED to provide a visual indicator that data is being read from
or written to a hard drive. For the LED to function properly, an IDE drive must be connected to
the onboard IDE interface.
2.8.3.2.4 Reset Switch Connector
Pins 5 and 7 can be connected to a momentary SPST type switch that is normally open. When the
switch is closed, the board resets and runs the POST.
48
Technical Reference
2.9 Jumper Block
CAUTION
Do not move jumpers with the power on. Always turn off the power and unplug the power cord
from the computer before changing a jumper setting. Otherwise, damage to the board could occur.
Figure 7 shows the location of the BIOS Setup jumper block. This 3-pin jumper block determines
the BIOS Setup program’s mode. Table 34 describes the jumper settings for the three modes:
normal, configure, and recovery.
The BIOS uses current configuration information and passwords
1
for booting.
Configure
Recovery
2-3
None
3
3
After the POST runs, Setup runs automatically. The maintenance
1
menu is displayed.
The BIOS attempts to recover the BIOS configuration. Bootable
1
recovery media is required.
For information aboutRefer to
How to access the BIOS Setup programSection 4.1, page 71
The maintenance menu of the BIOS Setup programSection 4.2, page 72
BIOS recoverySection 3.6, page 66
50
Technical Reference
2.10 Mechanical Considerations
2.10.1 FlexATX Form Factor
The board is designed to fit into a FlexATX form-factor chassis. The board can also be installed in
a microATX-form-factor chassis. Figure 8 illustrates the mechanical form factor for the board.
Dimensions are given in inches [millimeters]. The outer dimensions are 9.0 inches by 7.5 inches
(228.6 millimeters by 190.5 millimeters). Location of the I/O connectors and mounting holes are
in compliance with the FlexATX addendum of the microATX specification (see Section 1.3).
The back panel I/O shield for the board must meet specific dimension and material requirements.
Systems based on this board need the back panel I/O shield to pass certification testing. Figure 9
shows the critical dimensions of the I/O shield. Dimensions are given in inches [millimeters]. For
dimensions given to two decimal places, the tolerance is ±0.02 inches (±5.08 millimeters). The
figure indicates the position of each cutout. Additional design considerations for I/O shields
relative to chassis requirements are described in the ATX specification. See Section 1.3 for
information about the ATX specification.
0.00
0.47[12.03]
0.68
[17.32]
0.00
0.80
[20.57]
1.64
[41.89]
4.37
[111.14]
5.32
[135.15]
5.82
[147.90]
0.33 Dia(2)
[8.50]
0.46[11.80]
0.66[16.86]
OM08930
52
Figure 9. I/O Shield Dimensions
Technical Reference
2.11 Electrical Considerations
2.11.1 Add-in Board Considerations
The board is designed to provide 2 A (average) of +5 V current for an add-in board in the PCI slot.
2.11.2 Power Consumption
Table 35 lists voltage and current specifications for a computer that contains the board and the
following:
• 550E MHz Intel Pentium III processor with a 256 KB cache
• 256 MB SDRAM
• 6.2 GB IDE hard disk drive
• Toshiba Mobile CD-ROM drive
This information is provided only as a guide for calculating approximate power usage with
additional resources added.
Values for the Windows
†
98 desktop mode are measured at 640 x 480 x 256 colors and 60 Hz
refresh rate. AC watts are measured with a typical 145 W power supply, nominal input voltage
and frequency, with true RMS wattmeter at the line input.
Table 35.Power Usage
DC Amps at:
ModeAC Watts+3.3 V+5 V+12 V-12 V+5 VSB
Windows 98 ACPI S046 W1.90 A2.23 A0.2 A-0.02 A0.17 A
Windows 98 ACPI S122 W1.37 A0.38 A0.2 A-0.02 A0.143 A
Windows 98 ACPI S31 W0.0 A0.0 A0.0 A0.0 A0.13 A
Windows 98 ACPI S51 W0.0 A0.0 A0.0 A0.0 A0.11 A
System integrators should refer to the power usage values listed in Table 35 when selecting a
power supply for use with this board. The power supply must comply with the following
recommendations found in the indicated sections of the ATX form factor specification
(see Table 2 on page 13).
• The potential relation between +3.3 VDC and +5 VDC power rails (Section 4.2)
• The current capability of the +5 VSB line (Section 4.2.1.2)
• All timing parameters (Section 4.2.1.3)
• All voltage tolerances (Section 4.2.2)
2.11.4 Fan Power Requirements
Table 36 lists the maximum DC voltage and current requirements for the chassis fan when the
board is in sleep mode or normal operating mode. Power consumption is independent of the
operating system used and other variables.
Table 36.Chassis Fan (J3A2) DC Power Requirements
ModeVoltageMaximum Current (Amps)
Normal (S0)+ 12 VDC250 mA
Sleep (S1)+ 12 VDC250 mA
Sleep (S3)+ 0 VDC0 mA
For information aboutRefer to
The location of the chassis fan connectorFigure 5, page 41
The signal names of the chassis fan connectorTable 23, page 42
54
Technical Reference
2.12 Thermal Considerations
CAUTION
An ambient temperature that exceeds the board’s maximum operating temperature by 5 oC to 10 oC
could cause components to exceed their maximum case temperature and malfunction. For
information about the maximum operating temperature, see the environmental specifications in
Section 2.14.
Figure 10 shows the localized high-temperature zones.
C DEA B
ACreative ES1373D
BIntel 82801AA ICH
CIntel 82810E DC-133 GMCH
DProcessor
EProcessor voltage regulator area
Table 37 provides maximum component case temperatures for board components that could be
sensitive to thermal changes. Case temperatures could be affected by the operating temperature,
current load, or operating frequency. Maximum case temperatures are important when considering
proper airflow to cool the board.
Table 37.Thermal Considerations for Components
ComponentMaximum Case Temperature
Intel Celeron Processor
366 MHz85 °C
400 MHz85 °C
433 MHz85 °C
466 MHz70 °C
500 MHz70 °C
533 MHz70 °C
Intel Pentium III Processor
500E MHz85 °C
550E MHz85 °C
600E MHz85 °C
600EB MHz85 °C
Intel 82810E DC-133 GMCH70 °C
Intel 82801AA ICH100 °C
Creative ES1373D70 °C
CAUTION
The voltage regulator area can reach a temperature of up to 85 oC in an open chassis. Ensure that
there is proper airflow to this area of the board. Failure to do so may result in damage to the
voltage regulator circuit. System integrators should ensure that proper airflow is maintained in
the voltage regulator circuit (item E in Figure 10). Components in this area could be damaged
without adequate airflow.
2.13 Reliability
The mean time between failures (MTBF) prediction is calculated using component and
subassembly random failure rates. The calculation is based on the Bellcore Reliability Prediction
Procedure, TR-NWT-000332, Issue 4, September 1991. The MTBF prediction is used to estimate
repair rates and spare parts requirements.
The Mean Time Between Failures (MTBF) data is calculated from predicted data at 55 ºC.
Board MTBF: 330,526 hours
56
2.14 Environmental
Table 38 lists the environmental specifications for the board.
Table 38.Board Environmental Specifications
ParameterSpecification
Temperature
Non-Operating-40 °C to +70 °C
Operating0 °C to +55 °C
The board uses an Intel/AMI BIOS, which is stored in flash memory and can be upgraded using a
disk-based program. In addition to the BIOS, the flash memory contains the BIOS Setup program,
POST, the PCI auto-configuration utility, and Plug and Play support.
This board supports system BIOS shadowing, allowing the BIOS to execute from 64-bit onboard
write-protected DRAM.
The BIOS displays a message during POST identifying the type of BIOS and a revision code. The
initial production BIOS is identified as MO81010A.86A.
For information aboutRefer to
The board’s compliance level with Plug and PlayTable 2, page 13
The Intel 82802AB Firmware Hub (FWH) includes a 4 Mbit (512 KB) symmetrical flash memory
device. Internally, the device is grouped into eight 64-KB blocks that are individually erasable,
lockable, and unlockable. Figure 11 shows the organization of the flash memory.
The last two 8 KB blocks of the fault tolerance area are the parameter blocks. These blocks
contain data such as BIOS updates, vital product data (VPD), logo, System Management BIOS
(SMBIOS) interface, and extended system configuration data (ESCD) information. The backup
block contains a copy of the fault tolerance block.
The BIOS can automatically configure PCI devices. PCI devices may be onboard or add-in cards.
Autoconfiguration lets a user insert or remove PCI cards without having to configure the system.
When a user turns on the system after adding a PCI card, the BIOS automatically configures
interrupts, the I/O space, and other system resources.
PCI devices can share an interrupt. Autoconfiguration information is stored in ESCD format.
For information aboutRefer to
The board’s compliance level with Plug and PlayTable 2, page 13
OM08376
62
Overview of BIOS Features
3.3.2 PCI IDE Support
If you select Auto in the BIOS Setup program, the BIOS automatically sets up the two
PCI IDE connectors with independent I/O channel support. The primary IDE interface supports
hard drives up to ATA/66 and recognizes any ATAPI devices, including CD-ROM drives, tape
drives, and Ultra DMA drives. The secondary IDE interface supports to ATA/33. The BIOS
determines the capabilities of each drive and configures them to optimize capacity and
performance. To take advantage of the high capacities typically available today, hard drives are
automatically configured for Logical Block Addressing (LBA) and to PIO Mode 3 or 4, depending
on the capability of the drive. You can override the auto-configuration options by specifying
manual configuration in the BIOS Setup program.
To use ATA-66 features the following items are required:
• An ATA-66 peripheral device
• An ATA-66 compatible cable
• ATA-66 operating system device drivers
For information aboutRefer to
The supported version of ATAPITable 2, page 13
NOTE
✏
Do not connect an ATA device as a slave on the same IDE cable as an ATAPI master device. For
example, do not connect an ATA hard drive as a slave to an ATAPI CD-ROM drive.
SMBIOS is a Desktop Management Interface (DMI) compliant method for managing computers in
a managed network.
The main component of SMBIOS is the management information format (MIF) database, which
contains information about the computing system and its components. Using SMBIOS, a system
administrator can obtain the system types, capabilities, operational status, and installation dates for
system components. The MIF database defines the data and provides the method for accessing this
®
information. The BIOS enables applications such as Intel
SMBIOS. The BIOS stores and reports the following SMBIOS information:
• BIOS data, such as the BIOS revision level
• Fixed-system data, such as peripherals, serial numbers, and asset tags
• Resource data, such as memory size, cache size, and processor speed
• Dynamic data, such as event detection and error logging
Non-Plug and Play operating systems, such as Windows NT
obtaining the SMBIOS information. The BIOS supports an SMBIOS table interface for such
operating systems. Using this support, an SMBIOS service-level application running on a nonPlug and Play operating system can obtain the SMBIOS information.
LANDesk® Client Manager to use
†
, require an additional interface for
For information aboutRefer to
The board’s compliance level with SMBIOSSection 1.3, page 13
64
Overview of BIOS Features
3.5 BIOS Upgrades
The BIOS can be upgraded using the Intel® Flash Memory Update utility that is available from
Intel. This utility supports the following BIOS maintenance functions:
• Upgrading the flash BIOS from bootable recovery media
• Changing the language section of the BIOS
• Verifying that the upgrade BIOS matches the target system to prevent accidentally installing
an incompatible BIOS
• Updating the BIOS boot block
BIOS upgrades and the Intel Flash Memory Update utility are available from Intel through the
Intel World Wide Web site.
NOTE
✏
Please review the instructions distributed with the upgrade utility before attempting a BIOS
upgrade.
For information aboutRefer to
The Intel World Wide Web siteSection 1.2, page 13
3.5.1 Language Support
The BIOS Setup program and help messages are supported in five languages: US English,
German, Italian, French, and Spanish. The default language is US English, which is present unless
another language is selected in the BIOS Setup program.
3.5.2 Custom Splash Screen
During POST, an Intel splash screen is displayed by default. This splash screen can be replaced
with a custom splash screen. A utility is available from Intel to assist with creating a custom
splash screen. The custom splash screen can be programmed into the flash memory using the
BIOS upgrade utility. Information about this capability is available on the Intel Support World
Wide Web site.
Some types of failure can destroy the BIOS. For example, the data can be lost if a power outage
occurs while the BIOS is being upgraded in flash memory. The BIOS can be recovered from
either a 1.44 MB diskette (for recovery from an LS-120 diskette drive configured as an ATAPI
removable IDE device) or from a CD-ROM (for use in an ATAPI CD-ROM drive) using the BIOS
recovery mode. When recovering the BIOS, be aware of the following:
• Recovery requires the use of bootable media in a bootable device.
• Because of the small amount of code available in the nonerasable boot block area, there is no
video support. You can only monitor this procedure by listening to the speaker or looking at
the recovery drive LED.
• Two beeps indicate the beginning of the BIOS recovery process.
• Two beeps and the end of activity in the recovery drive indicate successful BIOS recovery.
• A series of continuous beeps indicates a failed BIOS recovery.
BIOS recovery media can be either a 1.44 MB diskette or a CD-ROM. The recovery media must
be bootable and it must contain the BIOS update files copied to it. BIOS upgrades and the Intel
Flash Memory Upgrade utility are available from Intel Customer Support through the Intel World
Wide Web site.
NOTE
✏
BIOS recovery cannot be accomplished using non-SPD DIMMs. SPD data structure is required
for the recovery process.
NOTE
✏
If the computer is configured to boot from an LS-120 diskette (in the Boot menu), the BIOS
recovery diskette must be a standard 1.44 MB diskette not a 120 MB diskette.
For information aboutRefer to
The BIOS recovery modeSection 2.9, page 49
The Boot menu in the BIOS Setup programSection 4.7, page 85
Contacting Intel customer supportSection 1.2, page 13
66
Overview of BIOS Features
3.7 Boot Options
In the BIOS Setup program, the user can choose to boot from an ATAPI removable media device,
hard drives, CD-ROM, or the network. Boot devices are defined in priority order. The default
setting is for the CD-ROM drive to be the primary boot device and the hard drive to be the
secondary boot device.
3.7.1 CD-ROM and Network Boot
Booting from CD-ROM is supported in compliance to the El Torito bootable CD-ROM format
specification. The network can also be selected as a boot device. This selection allows booting
from a network add-in card with a remote boot ROM installed.
For information aboutRefer to
The El Torito specificationSection 1.3, page 13
3.7.2 Booting Without Attached Devices
For use in embedded applications, the BIOS has been designed so that after passing the POST, the
operating system loader is invoked even if the keyboard and mouse are not connected.
USB legacy support enables USB devices such as keyboards, mice, and hubs to be used even when
no operating system USB drivers are in place. By default, USB legacy support is set to Auto.
USB legacy support is used in accessing the BIOS Setup program and installing an operating
system that supports USB.
This sequence describes how USB legacy support operates in the default (auto) mode.
1. When you power up the computer, USB legacy support is disabled.
2. POST begins.
3. USB legacy support is temporarily enabled by the BIOS. This allows you to use a
USB keyboard to enter the BIOS Setup program or the maintenance mode.
4. POST completes and disables USB legacy support (unless it was set to Enabled while in the
BIOS Setup program. Or if set to Auto while in the BIOS Setup program and a USB keyboard
or mouse is connected, then USB Legacy support will be enabled).
5. The operating system loads. While the operating system is loading, USB keyboards and mice
are not recognized (unless USB legacy support was set to Enabled while in the BIOS Setup
program, or if USB legacy support was set to Auto while in the BIOS Setup program and a
USB keyboard or mouse is connected). After the operating system loads the USB drivers, the
USB devices are recognized by the operating system.
To install an operating system that supports USB, enable USB Legacy support or set it to Auto in
the BIOS Setup program and follow the operating system’s installation instructions. Once the
operating system is installed and the USB drivers have been configured, USB legacy support is no
longer used. USB Legacy support can be left enabled or set to auto in the BIOS Setup program if
needed.
Notes on using USB legacy support:
• Do not use USB devices with an operating system that does not support USB. USB legacy is
not intended to support the use of USB devices in a non-USB aware operating system.
• USB legacy support is for keyboards, mice, and hubs only. Other USB devices are not
supported.
68
Overview of BIOS Features
3.9 BIOS Security Features
The BIOS includes security features that restrict access to the BIOS Setup program and who can
boot the computer. A supervisor password and a user password can be set for the BIOS Setup
program and for booting the computer, with the following restrictions:
• The supervisor password gives unrestricted access to view and change all the Setup options in
the BIOS Setup program. This is supervisor mode.
• The user password gives restricted access to view and change Setup options in the BIOS Setup
program. This is user mode.
• If only the supervisor password is set, pressing the <Enter> key at the password prompt of the
BIOS Setup program allows the user restricted access to Setup.
• If both the supervisor and user passwords are set, users can enter either the supervisor
password or the user password to access Setup. Users have access to Setup respective to
which password is entered.
• Setting the user password restricts who can boot the computer. The password prompt will be
displayed before the computer is booted. If only the supervisor password is set, the computer
boots without asking for a password. If both passwords are set, the user can enter either
password to boot the computer.
Table 41 shows the effects of setting the supervisor password and user password. This table is for
reference only and is not displayed on the screen.
Table 41.Supervisor and User Password Functions
Supervisor
Password Set
NeitherCan change all
Supervisor
only
User onlyN/ACan change all
Supervisor
and user set
*If no password is set, any user can change all Setup opt i ons .
For information aboutRefer to
Setting user and supervisor passwordsSection 4.4.5, page 82
The BIOS Setup program can be used to view and change the BIOS settings for the computer. The
BIOS Setup program is accessed by pressing the <F2> key after the Power-On Self-Test (POST)
memory test begins and before the operating system boot begins. The menu bar is shown below.
Maintenance MainAdvancedSecurityPowerBootExit
Table 42 lists the BIOS Setup program menu functions.
Table 42.BIOS Setup Program Menu Functions
MaintenanceMainAdvancedSecurityPowerBootExit
Selects boot
options and
power supply
controls
✏
Clears
passwords and
BIS credentials,
enables
extended
configuration
modes
NOTE
Allocates
resources for
hardware
components
Configures
advanced
features
available
through the
chipset
Sets
passwords
and security
features
Configures
power
management
features
The Setup screens described in this chapter apply to boards with BIOS identifier MO81010A.86A.
Boards with other BIOS identifiers might have differences in some of the Setup screens.
NOTE
✏
In this chapter, all examples of the BIOS Setup Program menu bar include the maintenance menu;
however, the maintenance menu is displayed only when the board is in configuration mode.
Section 2.9 on page 49 tells how to put the board in configuration mode.
Saves or
discards
changes to
Setup
program
options
Table 43 lists the function keys available for menu screens.
Table 43.BIOS Setup Program Function Keys
BIOS Setup Program Function KeyDescription
<←> or <→>Selects a different menu screen
<↑> or <↓>Selects an item
<Tab>Selects a field
<Enter>Executes command or selects a submenu
<F9>Load the default configuration values for the current menu
<F10>Save the current values and exits the BIOS Setup program
<Esc>Exits the menu
4.2 Maintenance Menu
To access this menu, select Maintenance on the menu bar at the top of the screen.
Maintenance
MainAdvancedSecurityPowerBootExit
Extended Configuration
The menu shown in Table 44 is for clearing the Setup passwords and the Wired for Management
Boot Integrity Service credentials, and for changing extended configuration memory settings.
Setup only displays this menu in configuration mode. See Section 2.9 on page 49 for configuration
mode setting information.
Table 44.Maintenance Menu
FeatureOptionsDescription
4Clear All PasswordsConfirm: Yes/NoSelecting
passwords.
4Clear BIS Credentials
(Note)
4Extended Configuration (See Extended
CPU Information:
CPU Microcode Update
Revision
CPU Stepping SignatureNo optionsDisplays CPU’s Stepping Signature.
Note: For information about the B IS, refer to the Intel web s i te at:
http://developer.i nt el .com/design/sec uri t y/index1.htm
Confirm: Yes/NoSelecting
Service) credentials.
Selecting
Configuration Submenu)
No optionsDisplays CPU’s Microcode Update Revision.
control and video memory cache modes.
Yes
clears the user and supervisor
Yes
clears the WfM BIS (Boot Integrity
User-Defined
allows setting system
72
4.2.1 Extended Configuration Submenu
To access this submenu, select Maintenance on the menu bar,
Extended Configuration.
then
BIOS Setup Program
Maintenance
MainAdvancedSecurityPowerBootExit
Extended Configuration
The submenu represented by Table 45 is for setting system control and video memory cache mode.
This submenu becomes available when User-Defined is selected under Extended Configuration.
Table 45.Extended Configuration Submenu
FeatureOptionsDescription
Extended Configuration
Memory Control:
SDRAM Auto
Configuration
CAS# Latency• 3
SDRAM RAS# to
CAS# delay
SDRAM RAS#
Precharge
• Default
(default)
• User-Defined
• Auto (default)
• User-Defined
• 2
• Auto (default)
• 3
• 2
• Auto (default)
• 3
• 2
• Auto (default)
Selecting user-defined allows you to select
User-Defined
configure the items listed under Memory Control below.
Note: If
in the Advanced Menu as: “Extended Configuration: Used.”
Sets extended memory configuration options to auto or
user-defined.
Selects the number of clock cycles required to address a
column in memory.
Selects the number of clock cycles between addressing a
row and addressing a column.
Selects the length of time required before accessing a new
row.
To access this menu, select Main on the menu bar at the top of the screen.
Maintenance
Main
AdvancedSecurityPowerBootExit
Table 46 describes the Main menu. This menu reports processor and memory information and is
for configuring the system date and system time.
Table 46.Main Menu
FeatureOptionsDescription
BIOS VersionNo optionsDisplays the version of the BIOS.
Processor TypeNo optionsDisplays processor type.
Processor SpeedNo optionsDisplays processor speed.
System Bus
Frequency
Cache RAMNo optionsDisplays the size of second-level cache.
Total MemoryNo optionsDisplays the total amount of RAM on the board.
Memory Bank 0No optionsDisplays type of DIMM installed.
LanguageEnglishDisplays the current language.
Processor Serial
Number
System TimeHour, minute, and
System DateDay of the week,
No optionsDisplays the host bus frequency.
• Disabled (default)
• Enabled
second
month, day, and year
When enabled, displays the processor’s serial number.
(Not supported by all processor types and speeds.)
Specifies the current time.
Specifies the current date.
74
4.4 Advanced Menu
To access this menu, select Advanced on the menu bar at the top of the screen.
BIOS Setup Program
MaintenanceMain
Advanced
SecurityPowerBootExit
Boot Configuration
Peripheral Configuration
IDE Configuration
Event Log Configuration
Video Configuration
Table 47 describes the Advanced menu. This menu is used for setting advanced features that are
available through the chipset.
Table 47.Advanced Menu
FeatureOptionsDescription
Extended ConfigurationNo optionsIndicates the setting of the Extended Configuration submenu
(from the Maintenance Menu)
Used
indicates that the Extended Configuration submenu is
being used.
Not Used
Configuration submenu is not being used.
4Boot ConfigurationNo optionsConfigures Plug and Play and the Numlock key, and resets
configuration data. When selected, displays the Boot
Settings Configuration submenu.
4Peripheral Configuration No optionsConfigures peripheral ports and devices. When selected,
displays the Peripheral Configuration submenu.
4IDE ConfigurationNo optionsSpecifies type of connected IDE device.
4Event Log ConfigurationNo optionsConfigures Event Logging. When selected, displays the
Event Log Configuration submenu.
4Video ConfigurationNo optionsSpecifies the primary video adapter.
Primary IDE Master
Primary IDE Slave
Secondary IDE Master
Secondary IDE Slave
Diskette Configuration
Event Log Configuration
Video Configuration
There are four IDE submenus: primary master, primary slave, secondary master, and secondary
slave. Table 51 shows the format of the IDE submenus. For brevity, only one example is shown.
Table 51.Primary/Secondary IDE Master/Slave Submenus
FeatureOptionsDescription
Type• None
• User
• Auto (default)
• CD-ROM
• ATAPI Removable
• Other ATAPI
• IDE Removable
LBA Mode Control• Disabled
• Enabled (default)
Multi-Sector Transfers• Disabled
• 2 Sectors
• 4 Sectors
• 8 Sectors
• 16 Sectors (default)
Specifies the IDE configuration mode for IDE devices.
User
allows the user to change the other features in this
table.
Auto
automatically sets the other features in this table.
None
or
Auto
Any setting other than
set features.
Enables or disables the LBA mode control.
Specifies number of sectors per block for transfers from
the hard disk drive to memory.
Check the hard disk drive’s specifications for optimum
setting.
Table 51.Primary/Secondary IDE Master/Slave Submenus (continued)
FeatureOptionsDescription
PIO Mode
Ultra DMA
Use ARMD Drive As• Auto
• Auto (default)
• 0
• 1
• 2
• 3
• 4
• Disabled (default)
• Mode 0
• Mode 1
• Mode 2
• Mode 3
• Mode 4
• Floppy (default)
• Hard Disk
Configures the PIO mode.
Auto sets the PIO mode to the fastest speed supported.
Specifies the Ultra DMA mode for the drive.
Specifies the type of ARMD drive.
This option appears only if an ARMD drive is attached to
an IDE interface.
80
BIOS Setup Program
4.4.4 Event Log Configuration
To access this menu, select Advanced on the menu bar, then Event Log Configuration.
MaintenanceMain
Advanced
SecurityPowerBootExit
Boot Configuration
Peripheral Configuration
IDE Configuration
Event Log Configuration
Video Configuration
The submenu represented by Table 52 is used to configure the event logging features.
Table 52.Event Log Configuration Submenu
FeatureOptionsDescription
Event logNo optionsIndicates if there is space available in the event log.
Event log validityNo optionsIndicates if the contents of the event log are valid.
View event log[Enter]Displays the event log.
Clear all event logs
Event Logging• Disabled
Mark events as read[Enter]Marks all events as read.
To access this menu, select Advanced on the menu bar, then Video Configuration.
MaintenanceMain
Advanced
SecurityPowerBootExit
Boot Configuration
Peripheral Configuration
IDE Configuration
Event Log Configuration
Video Configuration
The submenu represented by Table 52 is used to select the video adapter.
Table 53.Video Configuration Submenu
FeatureOptionsDescription
Primary Video Adapter
• AGP (default)
• PCI
Selects the Direct AGP or PCI video controller as the
display device that will be active when the systems
boots.
82
4.5 Security Menu
To access this menu, select Security from the menu bar at the top of the screen.
BIOS Setup Program
MaintenanceMainAdvanced
Security
PowerBootExit
The menu represented by Table 54 is for setting passwords and security features.
Table 54.Security Menu
FeatureOptionsDescription
Supervisor Password IsNo options.Reports if there is a supervisor password set.
User Password IsNo options.Reports if there is a user password set.
Set Supervisor PasswordPassword can be up to seven
alphanumeric characters.
Set User PasswordPassword can be up to seven
alphanumeric characters.
Clear User Password
(Note 1)
User Access Level
(Note 2)
Unattended Start
(Note 1)
Notes:
1. This feature appears only i f a user password has been set.
2. This feature appears only i f both a user password and a supervis or password have been set.
• Yes (default)
• No
• Limited
• No Access
• View Only
• Full (default)
• Disabled (default)
• Enabled
Specifies the supervisor password.
Specifies the user password.
Clears the user password.
Sets BIOS Setup Utility access rights for user
level.
Enables or disables Wake on network event
capability. The keyboard remains locked until
a password is entered.
Specifies the boot sequence according to the device
type. The computer will attempt to boot from up to
four devices as specified here. Only one of the
devices can be an IDE hard disk drive.
To specify the boot sequence:
1. Select the boot device with <↑> or <↓>.
2. Press <Enter> to set the selection as the intended
boot device.
The default settings for the first through fourth boot
devices are, respectively:
• ATAPI CDROM
• IDE-HDD
• Intel UNDI, PXE 2.0 (build 071)
• Disabled
NOTE: To configure the computer to boot from an
IDE hard disk drive, set a boot device in this Setup
feature to
IDE-HDD
master or slave mode of the drive. Then, in the next
Setup feature,
channel and mode to
1st IDE
specifies the IDE hard disk drive to boot from.
nd
The
2
through
note above for more information.
To specify the drive to boot from:
1. Use <↑> or <↓> to select the channel, and master
or slave mode of the drive to boot from.
2. Press <Enter>.
3. Use <↑> or <↓> to select 1
4. Press <Enter> to set the selection.
. Determine the IDE channel, and
IDE Drive Configuration
1st IDE
.
4th IDE
settings are ignored. See the
st
IDE.
, set that
86
4.8 Exit Menu
To access this menu, select Exit from the menu bar at the top of the screen.
BIOS Setup Program
MaintenanceMainAdvancedSecurityPowerBoot
Exit
The menu represented in Table 57 is for exiting the BIOS Setup program, saving changes, and
loading and saving defaults.
Table 57.Exit Menu
FeatureDescription
Exit Saving ChangesExits and saves the changes in CMOS SRAM.
Exit Discarding Changes Exits without saving any changes made in the BIOS Setup program.
Load Setup DefaultsLoads the factory default values for all the Setup options.
Load Custom DefaultsLoads the custom defaults for Setup options.
Save Custom DefaultsSaves the current values as custom defaults. Normally, the BIOS reads the
Setup values from flash memory. If this memory is corrupted, the BIOS reads the
custom defaults. If no custom defaults are set, the BIOS reads the factory
defaults.
Discard ChangesDiscards changes without exiting Setup. The option values present when the
Cache Memory BadAn error occurred when testing L2 cache. Cache memory may be
CMOS Battery LowThe battery may be losing power. Replace the battery soon.
CMOS Display Type WrongThe display type is different than what has been stored in CMOS.
CMOS Checksum BadThe CMOS checksum is incorrect. CMOS memory may have
CMOS Settings WrongCMOS values are not the same as the last boot. These values
CMOS Date/Time Not SetThe time and/or date values stored in CMOS are invalid. Run
DMA ErrorError during read/write test of DMA controller.
HDC FailureError occurred trying to access hard disk controller.
Could not read sector from corresponding drive.
Corresponding drive is not an ATAPI device. Run Setup to make
sure device is selected correctly.
bad.
Check Setup to make sure type is correct.
been corrupted. Run Setup to reset values.
have either been corrupted or the battery has failed.
Checking NVRAM.....NVRAM is being checked to see if it is valid.
Update OK!NVRAM was invalid and has been updated.
Updated FailedNVRAM was invalid but was unable to be updated.
Keyboard ErrorError in the keyboard connection. Make sure keyboard is
connected properly.
Memory Size DecreasedMemory size has decreased since the last boot. If no memory
was removed then memory may be bad.
Memory Size IncreasedMemory size has increased since the last boot. If no memory was
added there may be a problem with the system.
Memory Size ChangedMemory size has changed since the last boot. If no memory was
added or removed then memory may be bad.
No Boot Device AvailableSystem did not find a device to boot.
Off Board Parity ErrorA parity error occurred on an offboard card. This error is followed
by an address.
On Board Parity ErrorA parity error occurred in onboard memory. This error is followed
by an address.
Parity ErrorA parity error occurred in onboard memory at an unknown
address.
NVRAM / CMOS / PASSWORD cleared
by Jumper
<CTRL_N> PressedCMOS is ignored and NVRAM is cleared. User must enter Setup.
NVRAM, CMOS, and passwords have been cleared. The system
should be powered down and the jumper removed.
90
Error Messages and Beep Codes
5.2 Port 80h POST Codes
During the POST, the BIOS generates diagnostic progress codes (POST-codes) to I/O port 80h. If
the POST fails, execution stops and the last POST code generated is left at port 80h. This code is
useful for determining the point where an error occurred.
Displaying the POST-codes requires an add-in card (often called a POST card). The POST card
can decode the port and display the contents on a medium such as a seven-segment display.
The tables below offer descriptions of the POST codes generated by the BIOS. Table 59 defines
the Uncompressed INIT Code Checkpoints, Table 60 describes the Boot Block Recovery Code
Checkpoints, and Table 61 lists the Runtime Code Uncompressed in F000 Shadow RAM. Some
codes are repeated in the tables because that code applies to more than one operation.
starting.
D1Keyboard controller BAT test, CPU ID saved, and going to 4 GB flat mode.
D3Do necessary chipset initialization, start memory refresh, do memory sizing.
D4Verify base memory.
D5Init code to be copied to segment 0 and control to be transferred to segment 0.
D6Control is in segment 0. To check recovery mode and verify main BIOS checksum. If the B IOS is
in recovery mode or the main BIOS checksum is bad, go to check point E0 for recovery else go to
check point D7 for giving control to main BIOS.
D7Find main BIOS module in ROM image.
D8Uncompress the main BIOS module.
D9Copy main BIOS image to F000 shadow RAM and give control to main BIOS in F000 shadow
RAM.
Table 60.Boot Block Recovery Code Checkpoints
CodeDescription of POST Operation
E0Onboard floppy controller (if any) is initialized. Compressed recovery code is uncompressed in
F000:0000 in shadow RAM and give control to recovery code in F000 Shadow RAM. Initialize
interrupt vector tables, initialize system ti mer, initialize DMA cont roller, interrupt co ntroller.
E8Initialize extra (Intel Recovery) Module.
E9Initialize floppy drive.
EATry to boot from floppy. If reading of boot sector is successful, give control to boot sector code.
EBBooting from floppy failed, look for ATAPI (LS-120, Zip†) devices.
ECTry to boot from ATAPI. If reading of boot sector is successful, give control to boot sector code.
EFBooting from floppy and ATAPI device failed. Give two beeps. Retry the booting procedure again
Table 61.Runtime Code Uncompressed in F000 Shadow RAM
CodeDescription of POST Operation
03NMI is Disabled. To check soft reset/power-on.
05BIOS stack set. Going to disable cache if any.
06POST code to be uncompressed.
07CPU init and CPU data area init to be done.
08CMOS checksum calculation to be done next.
0BAny initialization before keyboard BAT to be done next.
0CKB controller I/B free. To issue the BAT command to keyboard controller.
0EAny initialization after KB controller BAT to be done next.
0FKeyboard command byte to be written.
10Going to issue Pin-23, 24 blocking/unblocking command.
11Going to check pressing of <INS>, <END> key during power-on.
12To init CMOS if "Init CMOS in every boot" is set or <END> key is pressed. Going to disable DMA
and Interrupt controllers.
13Video display is disabled and port-B is initialized. Chipset init about to begin.
148254 timer test about to start.
19About to start memory refresh test.
1AMemory Refresh line is toggling. Going to check 15 µs ON/OFF time.
23To read 8042 input port and disable Megakey GreenPC feature. Make BIOS code segment
writeable.
24To do any setup before Int vector init.
25Interrupt vector initialization to begin. To clear password if necessary.
27Any initialization before setting video mode to be done.
28Going for monochrome mode and color mode setting.
2ADifferent buses init (system, static, ou tput devices) to start if present. (See Section 5.3 for details
of different buses.)
2BTo give control for any setup required before optional video ROM check.
2CTo look for optional video ROM and give control.
2DTo give control to do any processing after video ROM returns control.
2EIf EGA/VGA not found then do display memory R/W test.
2FEGA/VGA not found. Display memory R/W test about to begin.
30Display memory R/W test passed. About to look for the retrace checking.
31Display memory R/W test or retrace checking failed. To do alternate display memory R/W test.
32Alternate display memory R/W test passed. To look for the alternate display retrace checking.
34Video display checking over. Display mode to be set next.
37Display mode set. Going to display the power on message.
38Different buses init (input, IPL, general devices) to start if present. (See Section 5.3 for details of
different buses.)
39Display different buses initialization error messages. (See Section 5.3 for details of different
buses.)
3ANew cursor position read and saved. To display the Hit <DEL> message.
continued
92
Error Messages and Beep Codes
Table 61.Runtime Code Uncompressed in F000 Shadow RAM (continued)
CodeDescription of POST Operation
40To prepare the descriptor tables.
42To enter in virtual mode for memory test.
43To enable interrupts for diagnostics mode.
44To initialize data to check memory wrap around at 0:0.
45Data initialized. Going to check for memory wrap around at 0:0 and finding the total system
memory size.
46Memory wrap around test done. Memory size calculation over. About to go for writing patterns to
test memory.
47Pattern to be tested written in extended memory. Going to write patterns in base 640 K memory.
48Patterns written in base memory. Going to find out amount of memory below 1 M memory.
49Amount of memory below 1 M found and verified. Going to find out amount of memory above 1 M
memory.
4BAmount of memory above 1 M found and verified. Check for soft reset and going to clear memory
below 1 M for soft reset. (If power on, go to check point # 4Eh).
4CMemory below 1 M cleared. (SOFT RESET) Going to clear memory above 1 M.
4DMemory above 1 M cleared. (SOFT RESET) Going to save the memory size. (Go to check
point # 52h).
4EMemory test started. (NOT SOFT RESET) About to display the first 64 K memory size.
4FMemory size display started. This will be updated during memory test. Going for sequential and
random memory test.
50Memory testing/initialization below 1 M complete. Going to adjust displayed memory size for
relocation/ shadow.
51Memory size display adjusted due to relocation/shadow. Memory test above 1 M to follow.
52Memory testing/initialization above 1 M complete. Going to save memory size information.
53Memory size information is saved. CPU registers are saved. Going to enter in real mode.
54Shutdown successful, CPU in real mode. Going to disable gate A20 line and disable parity/NMI.
57A20 address line, parity/NMI disable successful. Going to adjust memory size depending on
relocation/shadow.
58Memory size adjusted for relocation/shadow. Going to clear Hit <DEL> message.
59Hit <DEL> message cleared. <WAIT...> message displayed. About to start DMA and interrupt
controller test.
60DMA page register test passed. To do DMA#1 base register test.
62DMA#1 base register test passed. To do DMA#2 base register test.
65DMA#2 base register test passed. To program DMA unit 1 and 2.
66DMA unit 1 and 2 programming over. To initialize 8259 interrupt controller.
7FExtended NMI sources enabling is in progress.
80Keyboard test started. Clearing output buffer, checking for stuck key, to issue keyboard reset
command.
81Keyboard reset error/stuck key found. To issue keyboard controller interface test command.
82Keyboard controller interface test over. To write command byte and init circular buffer.
83Command byte written, global data init done. To check for lock-key.
Table 61.Runtime Code Uncompressed in F000 Shadow RAM (continued)
CodeDescription of POST Operation
84Lock-key checking over. To check for memory size mismatch with CMOS.
85Memory size check done. To display soft error and check for password or bypass setup.
86Password checked. About to do programming before setup.
87Programming before setup complete. To uncompress SETUP code and execute CMOS setup.
88Returned from CMOS setup program and screen is cleared. About to do programming after
setup.
89Programming after setup complete. Going to display power on screen message.
8BFirst screen message displayed. <WAIT...> message displayed. PS/2 Mouse check and
extended BIOS data area allocation to be done.
8CSetup options programming after CMOS setup about to start.
8DGoing for hard disk controller reset.
8FHard disk controller reset done. Floppy setup to be done next.
91Floppy setup complete. Hard disk setup to be done next.
95Init of different buses optional ROMs from C800 to start. (See Section 5.3 for details of different
buses.)
96Going to do any init before C800 optional ROM control.
97Any init before C800 optional ROM control is over. Optional ROM check and control will be done
next.
98Optional ROM control is done. About to give control to do any required processing after optional
ROM returns control and enable external cache.
99Any initialization required after optional ROM test over. Going to setup timer data area and printer
base address.
9AReturn after setting timer and printer base address. Going to set the RS-232 base address.
9BReturned after RS-232 base address. Going to do any initialization before coprocessor test.
9CRequired initialization before coprocessor is over. Going to initialize the coprocessor next.
9DCoprocessor initialized. Going to do any initialization after coprocessor test.
9EInitialization after coprocessor test is complete. Going to check extended keyboard, keyboard ID,
and Num Lock.
A2Going to display any soft errors.
A3Soft error display complete. Going to set keyboard typematic rate.
A4Keyboard typematic rate set. To program memory wait states.
A5Going to enable parity/NMI.
A7NMI and parity enabled. Going to do any initialization required before giving control to optional
ROM at E000.
A8Initialization before E000 ROM control over. E000 ROM to get control next.
A9Returned from E000 ROM control. Going to do any initialization required after E000 optional
ROM control.
AAInitialization after E000 optional ROM control is over. Going to display the system configuration.
ABPut INT13 module runtime image to shadow.
ACGenerate MP for multiprocessor support (if present).
ADPut CGA INT10 module (if present) in shadow.
continued
94
Error Messages and Beep Codes
Table 61.Runtime Code Uncompressed in F000 Shadow RAM (continued)
CodeDescription of POST Operation
AEUncompress SMBIOS module and init SMBIOS code and form the runtime SMBIOS image in
shadow.
B1Going to copy any code to specific area.
00Copying of code to specific area done. Going to give control to INT19 boot loader.
5.3 Bus Initialization Checkpoints
The system BIOS gives control to the different buses at several checkpoints to do various tasks.
Table 62 describes the bus initialization checkpoints.
Table 62.Bus Initialization Checkpoints
CheckpointDescription
2ADifferent buses init (syst em, static, and output devices) to start if present.
38Different buses init (input, IPL, and general devices) to start if present.
39Display different buses initialization error messages.
95Init of different buses optional ROMs from C800 to start.
While control is inside the different bus routines, additional checkpoints are output to port 80h as a
WORD to identify the routines under execution. In these WORD checkpoints, the low byte of the
checkpoint is the system BIOS checkpoint from which the control is passed to the different bus
routines. The high byte of the checkpoint is the indication of which routine is being executed in
the different buses. Table 63 describes the upper nibble of the high byte and indicates the function
that is being executed.
Table 63.Upper Nibble High Byte Functions
ValueDescription
0func#0, disable all devices on the bus concerned
1func#1, static devices init on the bus concerned
2func#2, output device init on the bus concerned
3func#3, input device init on the bus concerned
4func#4, IPL device init on the bus concerned
5func#5, general device init on the bus concerned
6func#6, error reporting for the bus concerned
7func#7, add-on ROM init for all buses
Table 64 describes the lower nibble of the high byte and indicates the bus on which the routines are
being executed.
Table 64.Lower Nibble High Byte Functions
ValueDescription
0Generic DIM (Device Initialization Manager)
1Onboard system devices
2ISA devices
3EISA devices
4ISA PnP devices
5PCI devices
5.4 Speaker
A 47 Ω inductive speaker is mounted on the board. The speaker provides audible error code (beep
code) information during the power-on self-test (POST).
For information aboutRefer to
The location of the onboard speakerFigure 1, page 11
96
Error Messages and Beep Codes
5.5 BIOS Beep Codes
Whenever a recoverable error occurs during power-on self-test (POST), the BIOS displays an error
message describing the problem (see Table 65). The BIOS also issues a beep code (one long tone
followed by two short tones) during POST if the video configuration fails (a faulty video card or
no card installed) or if an external ROM module does not properly checksum to zero.
An external ROM module (for example, a video BIOS) can also issue audible errors, usually
consisting of one long tone followed by a series of short tones. For more information on the beep
codes issued, check the documentation for that external device.
There are several POST routines that issue a POST terminal error and shut down the system if they
fail. Before shutting down the system, the terminal-error handler issues a beep code signifying the
test point error, writes the error to I/O port 80h, attempts to initialize the video and writes the error
in the upper left corner of the screen (using both monochrome and color adapters).
If POST completes normally, the BIOS issues one short beep before passing control to the
operating system.
Table 65.Beep Codes
BeepDescription
1Refresh failure
2Parity cannot be reset
3First 64 KB memory failure
4Timer not operational
5Not used
68042 GateA20 cannot be toggled
7Exception interrupt error
8Display memory R/W error
9Not used
10CMOS Shutdown register test error
11Invalid BIOS (e.g. POST module not found, etc.)