The Intel®Desktop Board D810E2CB may contain design defects or errors knowna serratathat may cause the product to deviate from published specifications. Current characterized
errata are documented in the Intel Desktop Board D810E2CB Specification Update.
Revision History
RevisionRevision HistoryDate
001First release of the Intel®Desktop Board D810E2CB Technical Product
Specification.
This product specification applies to only standard D810E2CB boards with BIOS identifier
CB81010A.86A.
®
Changes to this specification will be published in the Intel
Desktop Board D810E2CB Specification
Update before being incorporated into a revision of this documen t.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL®PRODUCTS. EXCEPT AS
PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY
W HATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE
OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL
PROPERTY RIGHT.
January 2001
Intel Corporation mayhave patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that
relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any
license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property
rights.
Intel products are not intended for use in medical, lifesaving, or life sustaining applications or for anyother application in which
the failure of the Intel product could create a situation where personal injury or death may occur.
Intel may make changes to specifications and product descriptions at any time, without notice.
The D810E2CB board may contain design defects or errors known as errata that may causethe product to deviate from
published specifications. Current characterized errata are availableon request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
or call in North America1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany44-0-1793-421-333, other Countries 708-296-9333.
†
Third-party brands and names are the property of their respective owners.
Copyright 2001, Intel Corporation. All rights reserved.
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and theBIOS for the D810E2CB desktop board. It
describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the D810E2CB board and its
components to the vendors, system integrators, and other engineers and technicians who need this
level of information. It is specifically not intended for general audiences.
What This Document Contains
ChapterDescription
1A description of the hardware used on this board
2A map of theresources of the board
3The features supported by the BIOS Setup program
4The contents of the BIOS Setup program’s menus and submenus
5A description of the BIOS error messages, beep codes, and POST codes
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions which, if not observed, can cause personal injury.
#Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX)When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the D810E2CB board, and X is the instance of the particular part
at that general location. For example, J5J1 is a connector, located at 5J. It is the first
connector in the 5J area.
KBKilobyte (1024 bytes)
KbitKilobit (1024 bits)
MBMegabyte (1,048,576 bytes)
MbitMegabit (1,048,576 bits)
GBGigabyte (1,073,741,824 bytes)
xxhAn address or data value ending with a lowercase h indicates a hexadecimal value.
x.xVVolts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
Table 1 summarizes the D810E2CB board’s major features.
Table 1.Feature Summary
Form Factor
Processor
Memory
Chipset
Direct AGP Video
Audio
I/O Control
Peripheral Interfaces
Expansion
Capabilities
BIOS
Instantly Available PC
FlexATX (9.00 inches by 7.50 inches)
Support for either an:
®
• Intel
• Intel
• Two 168-pin dual inline memory module (DIMM) sockets
• Supports up to 512 MB of 100 MHz non-ECC synchronous DRAM (SDRAM)
• Support for serial presence detect (SPD) and non-SPD DIMMs
Intel
• Intel
• Intel
• SST 49LF004A 4 Mbit Firmware Hub (FWH)
• Intel 82810E GMCH
• VGA port connector on back panel
Audio Codec ’97 (AC’97) compatible audio subsystem, consisting of the
following:
• Intel 82801BA ICH2 (AC link output)
• CS4201 analog codec
LPC47M102 Low Pin Count (LPC) I/O controller
• Four universal serial bus (USB) ports (two back panel, two front panel)
• Two IDE interfaces with Ultra DMA, ATA-66/100 support
• One diskettedrive interface
• One serial port
• One parallel port
• PS/2
Two PCI-bus add-in card connectors
• Intel/AMI BIOS stored in an SST 49LF004A 4 Mbit firmware hub (FWH)
• Support for Advanced Configuration and Power Interface (ACPI), Advanced
• Support for
• Suspend-to-RAM support
• Wake from USB ports
Pentium®III processor with 256 KB L2 cache (in an FCPGA package)
®
Celeron™processor with 128 KB L2 cache (in a PGA package)
®
810E chipset, consisting of:
®
82810E Graphics/Memory Controller Hub (GMCH)
®
82801BA I/O Controller Hub (ICH2)
†
keyboard and mouse ports
Power Management (APM), Plug and Play, and SMBIOS
PCI Local Bus Specifi cation
, Revision 2.2
NOTE
✏
The D810E2CB board is designed to support only USB-aware operating systems.
12
Product Description
For information aboutRefer to
The board’s compliance level with ACPI, APM, Plug and Play, and SMBIOSTable 3, page 16
1.1.2Manufacturing Options
Table 2 describes the D810E2CB board’s manufacturing options. Not every manufacturing option
is available in all marketing channels. Please contact your Intel representative to determine which
manufacturing options are available to you.
Table 2.Manufacturing Options
LANIntel®82562ET 10/100 Mbit/sec Platform LAN Connect (PLC) device
Hardware monitor
component
Hardware monitor component features include:
• Voltage sense to detect out of range power supply voltages
• Thermal sense to detect out of range thermal values
Version 2.3.1,
August 12, 1998,
Award Software International Inc.,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
American Megatrends Inc.,
SystemSoft Corporation, and
Compaq Computer Corporation.
Version 1.1,
March 1996,
Intel Corporation.
Version 1.1,
September 23, 1998,
Compaq Computer Corporation,
Intel Corporation,
Microsoft Corporation, and
NEC.
Version 2.0,
December 18, 1998,
Intel Corporation.
The D810E2CB board supports processors that draw a maximum of 22 A. Using a processor that
draws more than 22 A can damage the processor, the board, and the power supply. See the
processor’s data sheet for current usage requirements.
CAUTION
Before installing or removing the processor, make sure that AC power has been removed by
unplugging the power cord from the computer. Failure to do so could damage the processor and
the board.
The D810E2CB board supports either an Intel PentiumIII processor (FCPGA package), or an Intel
Celeron processor (PGA package) as shown in Table 4. The system bus frequency is automatically
selected.
Table 4.Supported Processors
Processor TypeProcessor DesignationSystem Bus FrequencyL2 Cache Size
To be compliant with applicable Intel®SDRAM memory specifications, the D810E2CB board
should be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. If
your memory modules do not support SPD, the BIOS will attempt to configure the memory
controller for normal operation; however, the DIMMs may not function at their optimum speed.
CAUTION
Before installing or removing memory, make sure that AC power has been removed by unplugging
the power cord from the computer. Failure to do so could damage the memory and the board.
CAUTION
Because the main system memory is also used as video memory, the board r equires 100 MHz
SDRAM DIMMs even though the processor’s system bus speed is 66 MHz. It is highly
recommended that SPD DIMMs be used, since this allows the BIOS to read the SPD data and
program the chipset to accurately configure memory settings for optimum performance. If nonSPD memory is installed, the BIOS will attempt to correctly configure the memory settings, but
performance and reliability may be impacted.
The D810E2CB board has two DIMM sockets. The minimum memory size is 64 MB and the
maximum memory size is 512 MB. The BIOS automatically detects memory type, size, and speed.
Memory can be installed in one or both sockets. Memory size can vary between sockets.
The D810E2CB board supports the following memory features:
• 3.3 V, 168-pin DIMMs with gold-plated contacts
• 100 MHz SDRAM
• Serial Presence Detect (SPD) or non-SPD memory (BIOS recovery requires SPD DIMMs)
• Non-ECC (64-bit) memory
• Unbuffered single- or double-sided DIMMs
The board is designed to support DIMMs in the configurations listed in Table 5 below.
Table 5.System Memory Configuration
DIMM SizeNon-ECC Configuration
16 MB2 Mbit x 64
32 MB4 Mbit x 64
64 MB8 Mbit x 64
128 MB16 Mbit x 64
256 MB32 Mbit x 64
20
For information aboutRefer to
PC Serial Presence Detect Specification
The
Obtaining copies of PC SDRAM specificationshttp://www.intel.com/design/pcisets/memory
Table 3, page 16
Product Description
1.6Intel®810E Chipset
The Intel 810E chipset consists of the following devices:
The GMCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
Accelerated Hub Architecture interface. The ICH2 is a centralized controller for the board’s I/O
paths. The FWH provides the nonvolatile storage of the BIOS. The component combination
provides the chipset interfaces as shown in Figure 3.
ATA-66/100
66/100/133 MHz
SystemBus
Network
USB
810E Chipset
100 MHz
SDRAM Bus
82810E
Graphics Memory
Controller Hub
(GMCH)
DisplayInterface
AHA
Bus
82801BA
I/O Controller Hub
(ICH2)
LPC Bus
AC LinkPCI BusSMBus
Figure 3. Intel 810E Chipset Block Diagram
For information aboutRefer to
The Intel 810E chipsethttp://www.developer.intel.com
The resources used by the chipsetChapter 2
The chipset’s compliance with ACPI and AC ‘97Table 3, page 16
Direct (integrated) AGP is a high-performance bus (independent of the PCI bus) for graphicsintensive applications, such as 3D applications. AGP overcomes certain limitations of the PCI bus
related to handling large amount of graphics data with the following features:
• Pipelined memory read and write operations that hide memory access latency
• Demultiplexing of address and data on the bus for nearly 100 percent bus efficiency
For information aboutRefer to
The location of the VGA port connectorFigure 5, page 46
Obtainingthe
Accelerated Graphics Port Interface Specification
Table 3, page 16
1.6.2USB
The ICH2 contains two separate USB controllers supporting four USB ports. One USB peripheral
can be connected to each port. For more than four USB devices, an external hub can be connected to
any of the ports. Two of the USB ports are implemented with stacked back panel connectors. The
other two are accessible via the front panel USB connector at location J8B1. The D810E2CB board
fully supports Universal Hub Controller Interface (UHCI) and uses UHCI-compatible software
drivers.
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device is attached to the cable. Use shielded cable that meets the
requirements for full-speed devices.
For information aboutRefer to
The location of the USB connectors on the back panelFigure 5, page 46
The signal names of the USB connectors on the back panelTable 21, page 47
The location of the USB connectors on the front panelFigure 8, page 58
The signal names of the USB connectors on the front panelTable 41, page 60
The USB and UHCI specificationsTable 3, page 16
22
Product Description
1.6.3IDE Support
The ICH2’s IDE controller has two independent bus-mastering IDE interfaces that can be
independently enabled. The IDE interfaces support the following modes:
• Programmed I/O (PIO): processor controls data transfer.
• 8237-style DMA: DMA offloads the processor, supporting transfer rat es of up to 16 MB/sec.
• Ultra DMA: DMA protocol on IDE bus supportinghost and target throttling a nd transfer rates
of up to 33 MB/sec.
• Ultra ATA-66: DMA protocolon IDE bus supporting host and target throttling and transfer
rates of up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver
compatible.
• Ultra ATA-100: DMA protocolon IDE bus allows host and target throttling. The ICH2 Ultra
ATA-100 logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to
88 MB/sec.
✏ NOTE
ATA-100 and ATA-66 use faster timings and require a specialized cable to reduce reflections,
noise, and inductive coupling.
The IDE interfaces also support ATAPI devices (such as CD-ROM drives) and ATA devices using
the transfer modes listed in Section 4.4.4.1 on page 91.
The BIOS supports logical block addressing (LBA) and extended cylinder head sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The D810E2CB board supports laser servo (LS-120) diskette technology through its IDE interfaces.
An LS-120 drive can be configured as a boot device by setting the BIOS Setup program’s Boot
menu to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
For information aboutRefer to
The location of the IDE connectorsFigure 7, page 54
The signal names of the IDE connectorsTable 36, page 56
BIOS Setup program’s Boot menuTable 66, page 98
The real-time clock is compatiblewith DS1287 and MC146818 components. The clockprovides a
time-of-day clock and a multicentury calendar with alarm features and century rollover. The realtimeclock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reservedfor
BIOS use.
A coin-cell battery powers the real-time clock and CMOS memory. When the computer is not
plugged into a wall socket, the battery has an estimated life of three years. When the computer is
plugged in, the 3.3 V standby current from the power supply extends the life of the battery. The
clock is accurate to ± 13 minutes/year at 25 ºC with 3. 3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
NOTE
✏
If the battery and AC power fail, the last saved defaults, custom or standard, will be loaded into
CMOS SRAM at power on.
NOTE
✏
The recommended method of accessing the date in systems with Intel®desktop boards is indirectly
from the Real-Time Clock (RTC) via the BIOS. The BIOS on Intel desktop boards contains a
century checking and maintenance feature. This feature checks the two least significant digits of
the year stored in the RTC during each BIOS request (INT 1Ah) to read the date and, if less than
80 (i.e., 1980 is the first year supported by the PC), updates the century byte to 20. This feature
enables operating systems and applications using the BIOS date/time services to reliably
manipulate the year as a four-digit value.
For information aboutRefer to
Proper date access in systems with Intel desktop boardshttp://support.intel.com/support/year2000/
1.6.5SST 49LF004A 4 Mbit Firmware Hub (FWH)
The FWH provides the following:
• System BIOS program
• System security and manageability logic that enables protection for storing and updating of
platform information
24
1.7I/O Controller
The SMSC LPC47M102 I/O controller provides the following features:
• 3.3 V operation
• One serial port
• One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support
• Serial IRQ interface compatiblewith serialized IRQ support for PCI systems
• PS/2-style mouse and keyboard interfaces
• Interface for one 1.2 MB or 1.44 MB diskette drive
• Intelligent power management, including a programm able wake up event interface
• PCI power management support
The BIOS Setup program provides configuration options for the I/O controller.
For information aboutRefer to
SMSC LPC47M102 I/O controllerhttp://www.smsc.com
Product Description
1.7.1Serial Port
The D810E2CB board has one serial port connector on the back panel. The serial port’s
NS16C550-compatible UART supports data transfers at speeds up to 115.2 kbits/sec with BIOS
support. The serial port can be assigned as COM1 (3F8h), COM2 (2F8h), COM3 (3E8h), or
COM4 (2E8h).
For information aboutRefer to
The location of the serial port connectorFigure 5, page 46
The signal names of the serial port connectorTable 24, page 48
1.7.2Parallel Port
The connector for the multimode bidirectional parallel port is a 25-pin D-Sub connector located on
the back panel. In the BIOS Setup program, the parallel port can be configured for the following:
• Output only (PC AT
• Bi-directional (PS/2 compatible)
• EPP
• ECP
For information aboutRefer to
The location of the parallel port connectorFigure 5, page 46
The signal names of the parallel port connectorTable 22, page 47
The I/O controller supports one diskettedrive that is compatible with the 82077 diskette drive
controller and supports both PC-AT and PS/2 modes.
For information aboutRefer to
The location of the diskette drive connectorFigure 7, page 54
The signal names of the diskette drive connectorTable 37, page 57
The supported diskette drive capacities and sizesTable 61, page 93
1.7.4Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel. The +5 V lines to these
†
connectors are protected with a PolySwitch
connection after an overcurrent condition is removed.
NOTE
✏
The keyboard is supported in the bottom PS/2 connector and the mouse is supported in the top
PS/2 connector. Power to the computer should be turned off before a keyboard or mouse is
connected or disconnected.
circuit that, like a self-healing fuse, reestablishes the
The keyboard controller contains the AMI keyboard and mouse controller code, provides the
keyboard and mousecontrol functions, and supports password protectionfor power-on/reset. A
power-on/reset password can be specified in the BIOS Setup program.
For information aboutRefer to
The location of the keyboard and mouse connectorsFigure 5, page 46
The signal names of the keyboard and mouse connectorsTable 20, page 47
26
1.8Graphics Subsystem
The Intel 82810E GMCH graphics memory controller hub component provides the following
graphics support features:
• Integrated 2-D and 3-D graphics engines
• Integrated hardware motion compression engine
• Integrated230 MHz DAC
Table 6 lists the refresh r ates supported by the graphics subsystem.
Table 6.Supported Graphics Refresh Rates
ResolutionAvailable Refresh Rates (Hz)
640 x 200 x 16 colors70
640 x 350 x 16 colors70
640 x 400 x 256 colors60, 70, 75, 85
640 x 400 x 64 K colors60, 70, 75, 85
640 x 400 x 16 M colors70
640 x 480 x 16 colors60, 72, 75, 85
640 x 480 x 256 colors60, 70, 72, 75, 85
640 x 480 x 32 K colors60, 75, 85
640 x 480 x 64 K colors60, 70, 72, 75, 85
640 x 480 x 16 M colors60, 70, 72, 75, 85
800 x 600 x 256 colors60, 75, 85
800 x 600 x 32 K colors60, 70, 72, 75, 85
800 x 600 x 64 K colors60, 70, 72, 75, 85
800 x 600 x 16 M colors60, 70, 72, 75, 85
1024 x 768 x 256 colors60, 70, 75, 85
1024 x 768 x 32 K colors60, 75, 85
1024 x 768 x 64 K colors60, 70, 72, 75, 85
1024 x 768 x 16 M colors60, 70, 72, 75, 85
1056 x 800 x 16 colors70
1280 x 1024 x 256 colors60, 70, 72, 75, 85
1280 x 1024 x 32 K colors60, 75, 85
1280 x 1024 x 64 K colors60, 70, 72, 75
1280 x 1024 x 16 M colors60, 70, 72, 75, 85
Product Description
For information aboutRefer to
Obtaining graphics software and utilitieshttp://support.intel.com/support/motherboards/desktop
The D810E2CB board includes an Audio Codec ’97 (AC ’97) compatible audio subsystem
consisting of these devices:
• Intel 82801BA ICH2 (AC link output)
• CS4201 analog codec
Figure 4 is a block diagram of the audio subsystem.
CD-ROM
82801BA
I/O ControllerHub
(ICH2)
Figure 4. Block Diagram of Audio Subsystem with CS4201 Codec
AC '97
Link
CS4201
Analog Codec
Line In
Line Out
MicIn
Modem Audio
OM11128
Features of the audio subsystem include:
• Independent channels for PCM in, PCM out, and Mic in
• 16-bit stereo I/O up to 48 kHz
• Multiple sample rates
For information aboutRefer to
Obtaining audio software and utilitiesSection1.2, page 16
1.9.1CS4201 Analog Codec
The CS4201 is a fully AC ’97 compliant codec. T he codec's features include:
• 16-bit stereo full-duplex operation
• High quality CD-ROM input with ground sense
• Stereo line level output
• Power management support
• Full duplex variable sampling rate (7 kHz to 48 kHz) with 1 Hz resolution
†
• Phat
Stereo 3-D stereo enhancement
1.9.2Audio Connectors
The audio connectors include the following:
• ATAPI CD-ROM (connects an internal ATAPI CD-ROM drive to the audio mixer)
• Telephony
• Line out (back panel)
• Line in (back panel)
• Mic in
28
Product Description
For information aboutRefer to
The location of the ATAPI CD-ROM and telephony connectorsFigure 6, page 51
The signal names of the ATAPI CD-ROM connectorTable 29, page 52
The signal names of the telephony connectorTable 30, page 52
The back panel audio connectorsSection 2.8.1, page 46
1.10 Hardware Management Subsystem
The hardware manageme nt features enable the board to be compatible with the Wired for
Management (WfM) specification. The board has several hardware management features, including
the following:
• Fan control and monitoring
• Thermal and voltage monitoring
For information aboutRefer to
The WfM specificationTable 3, page 16
1.10.1Hardware Monitor Component (Optional)
The hardware monitor component provides low-cost instrumentation capabilities. The features of the
component include:
• Internal ambient temperaturesensing
• Remote thermal diode sensing for direct monitoring of processor temperature
• Power supply monitoring (+12 V, +5 V, +3.3 V, +2.5 V, 3.3 VSB, Vccp) to detect levels above
or below acceptable values
• SMBus interface
The hardware monitor component enables the board to be compatible with the Wired for
Management (WfM) specification.
For information aboutRefer to
The board’s compatibility with the WfM specificationTable3, page 16
1.10.2Fan Control and Monitoring
The SMSC LPC47M102 I/O controller provides two fan sense inputs and two fan control outputs.
Monitoring and control can be impleme nted using third-party software.
For information aboutRefer to
The functions of the fan connectorsSection 1.12.3.2, page 35
The locations of the fan connectorsFigure 6, page 51
The signal names of the fan connectorsSection 2.8.2.1, page 51
The Network Interface Controller subsystemconsists of the ICH2 (with integrated LAN Media
Access Controller) and a physical layer interface device. Features of the LAN subsystem include:
• PCI Bus Master interface
• CSMA/CD Protocol Engine
• Serial CSMA/CD unit interface that supports the 82562ET (10/100 Mbit/sec Ethernet) physical
Supports Wake up from suspend state (Wake on LAN
For information aboutRefer to
Obtaining LAN software and driversSection 1.2, page 16
1.11.1Intel®82562ET Platform LAN Connect Device
technology)
The Intel 82562ET component provides a n interface to the back panel RJ-45 connector with
integrated LEDs. This physical interface may alternately be provided via the CNR connector.
The Intel 82562ET provides the following functions:
• Basic 10/100 Ethernet LAN connectivity
• Supports RJ-45 connector with status indicator LEDs on the back panel
• Full device driver compatibility
• Advanced Power Management and ACPI support
• Programmable transit threshold
• Configuration EEPROM that contains the MAC address
• Remote monitoring (alerting)
1.11.2RJ-45 LAN Connector with Integrated LEDs
Two LEDs are built into the RJ-45 LAN connector. Table 7 describes the LED states when the
board is powered up and the LAN subsystem is operating.
Table 7.LAN Connector LED States
LED ColorLED StateCondition
Off10 Mbit/sec data rate is selected.Green
On100 Mbit/sec data rate is selected.
Yellow
OffLAN link is not established.
On (steady state)LAN link is established.
On (brighter and pulsing)The computer is communicating with another computer on
the LAN.
30
1.12 Power Management Features
Power management is implemented at several levels, including:
• Advanced Configuration and Power Interface (ACPI)
• Advanced Power Management (APM)
• Hardware support:
Power connector
Fan connectors
Wake on LAN technology
†
Instantly Available
Wake on Ring
Resume on Ring
Wake from USB
PME# wakeup support
1.12.1ACPI
technology
Product Description
If the board is used with an ACPI-aware operating system, the BIOS can provide ACPI support.
ACPI gives the operating system direct control over the power management and Plug and Play
functions of a computer. The use of ACPI with this board requires the support of a n operating
system that provides full ACPI functionality. ACPI features include:
• Plug and Play (including bus and device enumeration)
• Power management control of individual devices, video displays, and hard disk drives
• Methods for achieving less than 30-watt system operation in the Power On Suspend sleeping
state, and less than 5-watt system operationin the Suspend to RAM sleepingstate
• A Soft-off feature that enables the operating system to power off the computer
• Support for multiple wake up events (see Table 10 on page 33)
• Support for a front panel power and sleep mode switch.
Table 8 lists the system states based on how long the power switch is pressed, depending on how
ACPI is configured with an ACPI-aware operating system.
Table 8.Effects of Pressing the Power Switch
…and the power switch is
If the system is in this state…
Off(ACPI G2/S5 state)Less than four secondsPower on
On(ACPI G0 state)Less than four secondsSoft off/Suspend
On(ACPI G0 state)More than four secondsFail safe power off
Sleep(ACPI G1 state)Less than four secondsWake up
Sleep(ACPI G1 state)More than four secondsPower off
pressed for…the system enters this state
For information aboutRefer to
The board’s compliance level with ACPITable 3, page 16
Under ACPI, the operating system directs all system and device power state transitions. The
operating system puts devices in and out of low-power states based on user preferences and
knowledge of how devices are being used by applications. Devices that are not being used can be
turned off. The operating system uses information from applications and user settings to put the
system as a whole into a low-power state.
Table 9 lists the power sta t es supported by the board along with the associated system power targets.
See the ACPI specification for a complete description of the various system and power states.
Table 9.Power States and Targeted System Power
Global StatesSleeping StatesCPU StatesDevice StatesTargeted System
Power*
G0 - working stateS0 - workingC0 - workingD0 - working
In addition to power management, ACPI provides controls and information so that the operating
system can facilitate Plug and Play device enumeration and configuration. ACPI is used only to
enumerate and configure devices that do not have other hardware standards for enumeration and
configuration. PCI devices on a desktop board, for example, are not enumerated by ACPI.
1.12.2APM
APM makes it possible for the computer to enter an energy saving standby mode. The standby mode
can be initiated in the following ways:
• Time-out period specified in the BIOS Setup program
• Suspend/Resume switch connected to the front panel sleep connector
• From the operating system, such as the Suspend menu item in Windows 98 SE
In standby mode, the board can reduce power consumption by spinning down hard drives, and
†
reducing power to or turning off VESA
be enabled or disabled in the BIOS Setup program.
While in standby mode, the system retains the ability to respond to external interrupts and service
requests, such as incoming faxes or network messages. Any keyboard or mouse activity brings the
system out of standby mode and immediately restores power to the monitor.
The BIOS enables APM by default, but the operating system must support an APM driver for the
power-management features to work. For example, Windows 98 SE supports the powermanagement features upon detecting that APM is enabled in the BIOS.
Table 11 lists the devices or specific events that can wake the computer from specific states.
DPMS-compliant monitors. Power-manageme nt mode can
*Unattended WakeMode – display will be video BIOS string only
For information aboutRefer to
Enabling or disabling power management in the BIOS Setup programSection 4.6, page 97
The board’s compliance level with APMTable 3, page 16
1.12.3Hardware Support
CAUTION
If Wake on LAN and Instantly Available technology features are used, the power supply must be
capable of providing adequate +5 V standby current. Failure to provide adequate standby current
can damage the power supply. The total amount of standby current required depends on the wake
devices supported and manufacturing options. Refer to Section 2.11.2 on page 66 for additional
information.
The board provides several hardware features that support power management, including:
• Power connector
• Fan connectors
• Wake on LAN technology
• Instantly Available technology
• Wake on Ring
• Resume on Ring
• Wake from USB
• PME# wakeup support
Wake on LAN technology and Instantly Available technology require power from the +5 V standby
line. The sections discussing these features describe the incremental standby power requirements for
each.
Wake on Ring and Resume on Ring enable telephony devices to access the computer when it is in a
power-managed state. The method used depends on the type of telephony device (external or
internal) and the ACPI or APM state beingused.
NOTE
✏
The use of Wake on Ring, Resume on Ring, and Wake from USB technologies from an ACPI state
require the support of an operating system that provides full ACPI functionality.
34
Product Description
1.12.3.1Power Connector
When used with an ATX-compliant power supply that supports remotepower on/off, the D810E2CB
board can turn off the system power through software control.
With soft-off enabled, if power to the computer is interrupted by a power outage or a disconnected
power cord, when power resumes, the computer returns to the power state it was in before power
was interrupted (on or off).
For information aboutRefer to
The location of the power connectorFigure 6, page 51
The signal names of the power connectorTable 32, page 53
The ATX specificationTable 3, page 16
The MicroATX specification and the SFX Power Supply Design GuideTable 3, page 16
1.12.3.2Fan Connectors
Table 12 describes the functions of the fan connectors.
Table 12.Fan Connector Descriptions
ConnectorFunction
Processor fan (fan 1)Provides +12 V DC for a processor fan or active fan heatsink.
Chassis fan (fan 2)Provides +12 V DC for a system or chassis fan.
For information aboutRefer to
The location of the fan connectorsFigure 6, page 51
The signal names of the processor fan connectorTable 31, page 52
The signal names of the chassis fan connectorTable 34, page 53
1.12.3.3Wake on LAN T echnology
CAUTION
For Wake on LAN technology, the 5-V standby line for the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
implementing Wake on LAN technology can damage the power supply. Refer to Section 2.11.2 on
page 66 for additional information.
Wake on LAN technology enables remote wakeup of the computer through a network. The LAN
subsystem monitors network traffic at the Media Independent Interface. Upon detecting a Magic
†
Packet
D810E2CB board supports Wake on LAN technology through the PCI bus PME# signal.
frame, the LAN subsystem asserts a wakeup signal that powers up the computer. The
For Instantly Available technology, the 5-V standby line for the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
using this feature can damage the power supply. Refer to Section 2.11.2 on page 66 for additional
information.
Instantly Available technology enables the board to enter the ACPI S3 (Suspend-to-RAM) sleepstate. While in the S3 sleep-state, the computer will appear to be off. The power supply appears to
be off, the fans are off, and the front panel power LED will be yellow (unless a single color LED is
installed, in which case, it will be off.) When signaled by a wake-up device or event, the system
quickly returns to its last known wake state. Table 10 on page 33 lists the devices and events that
can wake the computer from the S3 state.
The D810E2CB board supports the PCI Bus Power Management Interface Specification.For
information on the versions of this specification, see Section 1.3. Add-in boards that also support
this specification can participate in power management and can be used to wake the computer.
The use of Instantly Available technology requires operating system support and PCI 2.2 compliant
add-in cards and drivers.
1.12.3.5Wake on Ring
NOTE
✏
Wake on Ring requires the use of a modem (external USB, or modem connected to serial port A)
that supports the Wake on Ring feature.
The operation of Wake on Ring can be summarized as follows:
• Powers up the computer from the ACPI S5 state or from APM soft-off mode
• Requires two calls to access the computer:
First call restores the computer from an ACPI S5 state or powers up the computer from
APM soft-off mode.
Second call enables access (when the appropriate software is loaded).
• Detects incoming calls for external USB modems. The USB bus is monitored for the
RING_DETECT signal.
Table 13 outlines wake on ring support for modems.
Table 13.Wake on Ring Support for Modems
StateUSB ModemSerial Port ModemPCI Bus Modem (via PME#)
S1Refer to Section 1.12.3.6Refer to Section 1.12.3.6Supported
S3SupportedSupportedSupported
S5Not supportedSupportedNot supported
Soft-offNot supportedSupportedSupported
SuspendRefer to Section 1.12.3.6Refer to Section 1.12.3.6Supported
36
Product Description
1.12.3.6Resume on Ring
The operation of Resume on Ring can be summarized as follows:
• Resumes operation from the ACPI S1 state or APM suspend mode
• Requires only one call to access the computer
• Detects incoming call similarly for external and internal modems
1.12.3.7Wake from USB
USB bus activity wakes the computer from an ACPI S1 or S3 state or APM suspend mode.
NOTE
✏
Wake from USB requires the use of a USB peripheral that supports Wake from USB. Wake from
USB is not supported in APM soft-off mode.
1.12.3.8PME# Wakeup Support
When the PME# signal on the PCI bus is asserted, the computer wakes from an ACPI S1 or S3
state.
Sections 2.2 – 2.6 contain several standalone tables. Table 14 describes the system memory map,
Table 15 shows the I/O map, Table 16 lists the DMA channels, Table 17 defines the PCI
configuration space map, and Table 18 describes the interrupts. The remaining sections in this
chapter are introduced by text found with their respective section headings.
2.2Memory Map
Table 14.System Memory Map
Address Range (decimal)Address Range (hex)SizeDescription
1024 K - 524288 K100000 - 1FFFFFFF511 MBExtended memory
960 K - 1024 KF0000 - FFFFF64 KBRuntime BIOS
896 K - 960 KE0000 - EFFFF64 KBReserved
800 K - 896 KC8000 - DFFFF96 KBAvailable high DOS memory (open
to PCI bus)
640 K - 800 KA0000 - C7FFF160 KBVideo memory and BIOS
639 K - 640 K9FC00 - 9FFFF1 KBExtended BIOS data (movable by
08- or 16-bitsOpen
18- or 16-bitsOpen
28- or 16-bitsOpen
38- or 16-bitsOpen / ECP
4Reserved - cascade channel
516-bitsOpen
616-bitsOpen
716-bitsOpen
2.5PCI Configuration Space Map
Table 17.PCI Configuration Space Map
Bus
Number (hex)
000000Memory controller of Intel 82810E component
000100Graphics controller of Intel 82810E component
001E00Link to PCI bridge
001F00PCI-to-LPC bridge
001F01IDE controller
001F02USB controller #1
001F03SMBus controller
001F04USB controller #2
001F05AC ’97 audio controller
001F06AC ’97 modem controller
010800ICH2 LAN controller (optional)
010900PCI bus connector 1 (J3B1)
010A00PCI bus connector 2 (J3A2)
Device
Number (hex)
Function
Number (hex)Description
42
2.6Interrupts
Table 18.Interrupts
IRQSystem Resource
NMII/O channel check
0Reserved, interval timer
1Reserved, keyboard buffer full
2Reserved, cascade interrupt from slave PIC
3COM2*
4COM1*
5LAN / User available
6User available
7LPT1 (Parallel port if present, or else, user available) / ECP
8Real-time clock
9Reserved for ICH2 system management bus / Audio
10User available
11User available
12Onboard mouse port (if present, or else, user available)
13Reserved, math coprocessor
14Primary IDE (if present, or else, user available)
15Secondary IDE (if present, or else, user available)
This section describes interrupt sharing and how the interrupt signals are connected between the
onboard PCI devices. The PCI specification shows how interrupts can be shared between devices
attached to the PCI bus. In most cases, the small amount of latency added by interrupt sharing does
not affect the operation or throughput of the devices.
The ICH2 PCI-to-LPC bridge has eight programm able interrupt request (PIRQ) input signals. All
PCI interrupt sources connect to one of these PIRQ signals. Because there are only eight signals,
some PCI interrupt sources are mechanically tied together on the D810E2CB board and therefore
share the same interrupt.
Table 19 lists the PIRQ signals and shows how the signals are connected to the onboard PCI
interrupt sources.
For example, using as a reference, assume an add-in card using INTA is plugged into PCI bus
connector 2. In PCI bus connector 2, INTA is connected to PIRQF, which is already connected to
the SMBus. The add-in card in PCI bus connector 2 now shares interrupts with these onboard
interrupt sources.
Table 19.PCI Interrupt Routing Map
ICH2 PIRQ Signal Name
PCI Interrupt Source
ICH2 USB controllerINTD to PIRQD
SMBus controllerINTB
ICH2 USB controllerINTC to PIRQH
ICH2 AudioINTB
ICH2 LANINTA to PIRQE
PCI Bus Connector 1 (J3B1)INTAINTBINTCINTD
PCI Bus Connector 2 (J3A2)INTDINTAINTBINTC
NOTE
✏
The ICH2 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 10, 11, 14,
and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt.
However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ
lines to be connected to the same IRQ signal.
PIRQCPIRQFPIRQGPIRQBOther
44
Technical Reference
2.8Connectors
CAUTION
Only the back panel connectors of the board and the front panel USB connectors have overcurrent
protection. The other internal board connectors are not overcurrent protected and should connect
only to devices inside the computer chassis such as fans and internal peripherals. Do not use these
connectors for powering devices external to the computer chassis. A fault in the load presented by
an external device may result in a high output current that could damage the D810E2CB board,
the interconnecting cable, and the external device itself.
This section describes the D810E2CB board’s connectors. The connectors can be divided into the
following three groups:
• Back panel I/O connectors (see page 46)
PS/2 keyboard and mouse
USB (two)
Parallel port
VGA
Serial port
LAN
Audio (Line out, Line in, and Mic in)
• Internal I/O connectors (see page 50)
Audio (ATAPI CD-ROM and telephony)
Fans (2)
Power
Chassis intrusion
Add-in boards (two PCI bus connectors)
IDE (two)
Diskette drive
• External I/O connectors (see page 58)
Front panel (power/sleep/message-waiting LED, power switch, hard drive activity LED,
The back panel audio line out connector is designed to power headphones or amplified speakers
only. Poor audio quality may occur if passive (non-amplified) speakers are connected to this
output.
Figure 7. Add-in Board and Peripheral Interface Connectors
54
Technical Reference
Table 35.PCI Bus Connectors (J3A2 and J3B1)
PinSignal NamePinSignal NamePinSignal NamePinSignal Name
A1Ground (TRST#)* B1-12 VA32AD16B32AD17
A2+12 VB2Ground (TCK)*A33+3.3 VB33C/BE2#
A3+5 V (TMS)*B3GroundA34FRAME#B34Ground
A4+5 V (TDI)*B4no connect (TDO)*A35GroundB35IRDY#
A5+5 VB5+5 VA36TRDY#B36+3.3 V
A6INTA#B6+5 VA37GroundB37DEVSEL#
A7INTC#B7INTB#A38STOP#B38Ground
A8+5 VB8INTD#A39+3.3 VB39LOCK#
A9Reserve dB9no connect (PRSNT1#)* A40Reserved **B40PERR#
A10+5 V (I/O)B10ReservedA41Reserved ***B41+3.3 V
A11ReservedB11no connect (PRSNT 2#)* A42GroundB42SERR#
A12GroundB12GroundA43PARB43+3.3 V
A13GroundB13GroundA44AD15B44C/BE1#
A14+3.3 V auxB14Rese rvedA45+3.3 VB45AD14
A15RST#B15GroundA46AD13B46Ground
A16+5 V (I/O)B16CLKA47AD11B47AD12
A17GNT#B17GroundA48GroundB48AD10
A18GroundB18REQ#A49AD09B49Ground
A19PME#B19+5 V (I/O)A50KeyB50Key
A20AD30B20AD31A51KeyB51Key
A21+3.3 VB21AD29A52C/BE0#B52AD08
A22AD28B22GroundA53+3.3 VB53AD07
A23AD26B23AD27A54AD06B54+3.3 V
A24GroundB24AD25A55AD04B55AD05
A25AD24B25+3.3 VA56GroundB56AD03
A26IDSELB26C/BE3#A57AD02B57Ground
A27+3.3 VB27AD23A58AD00B58AD01
A28AD22B28GroundA59+5 V (I/O)B59+5 V (I/O)
A29AD20B29AD21A60REQ64C#B60ACK64C#
A30GroundB30AD19A61+5 VB61+5 V
A31AD18B31+3.3 VA62+5 VB62+5 V
*These signals (in parentheses) are optional in the PCI specification and are not currently implemented.
**On PCI bus conne ctor2 (J3A2), this pin is connected to the SMBus clock line.
*** On PCI bus connector 2 (J3A2), this pin is connected to the SMBus data line.
Pins 1 and 3 can be connected to an LED to provide a visual indicator that data is being read from or
written to a hard drive. For the LED to function properly, an IDE drive must be connected to the
onboard IDE interface.
2.8.3.1.2Power/Sleep/Message Waiting LED Connector
Pins 2 and 4 can be connected to a single- or dual-colored LED. Table 39 shows the possible states
for a single-colored LED. Table 40 shows the possible states for a dual-colored LED.
To use the message waiting function, ACPI must be enabled in the operating system and a
message-capturing application must be invoked.
2.8.3.1.3Reset Switch Connector
Pins 5 and 7 can be connected to a momentary SPST type switchthat is normally open. When the
switch is closed, the board resets and runs the POST.
2.8.3.1.4Power Switch Connector
Pins 6 and 8 can be connected to a front panel momentary-contact power switch. The switch must
pull the SW_ON# pin to ground for at least 50 ms to signal the power supply to switch on or off.
(The time requirement is due to internal debounce circuitry on the board.) At least two seconds must
pass before the power supply will recognize another on/off signal.
2.8.3.2Front Panel USB Connector
Table lists the signal names of the front panel USB connector.
Table 41.Front Panel USB Connector (J8B1)
PinSignal NamePinSignal Name
1VREG_FP_USB_PWR2VREG_FP_USB_PWR
3ICH_U_P2#4ICH_U_P3#
5ICH_U_P26ICH_U_P3
7Ground8Ground
9Ke y (no pin)10ICU_U_OC1_2#
60
Technical Reference
2.9Jumper Block
CAUTION
Do not move any jumpers with the power on. Always turn off the power and unplug the power cord
from the computer before changing a jumper setting. Otherwise, damage to the D810E2CB board
could occur.
Figure 9 shows the location of the BIOS Setup jumper block. This 3-pin jumper block determines
the BIOS Setup program’s mode. Table 42 describes the jumper settings for the three modes:
normal, configure, and recovery.
The BIOS uses current configuration information and passwords
for booting.
Configure
Recovery
2-3
None
1
3
1
3
After the POST runs, Setup runs automatically. The
maintenance menu is displayed.
The BIOS attempts to recover the BIOS configuration. A
recovery diskette (1.44 MB) or CD–ROM is required.
For information aboutRefer to
How to access the BIOS Setup programSection 4.1, page 81
The maintenance menu of the BIOS Setup programSection 4.2, page 82
BIOS recoverySection 3.7, page 77
62
Technical Reference
2.10 Mechanical Considerations
2.10.1FlexATX Form Factor
The D810E2CB board is designed to fit into an ATX- or microATX-form-factor chassis. Figure 10
illustrates the mechanical form factor for the board. Dimensions are given in inches (millimeters).
The outer dimensions are 9.00 inches by 7.50 inches (228.60 millimeters by 190.50 millime ters).
Location of the I/O connectors and mounting holes are in compliance with the FlexATX addendum to
the microATX specification (see Section 1.3).
The back panel I/O shield for the D810E2CB board must meet specific dimensional requirements.
Systems based on this board need the back panel I/O shield to pass emissions (EMI) certification
testing. Figure 11 shows the critical dimensions of the I/O shield. Dimensions are given in inches
and millimeters, to a tolerance of ±0.02 inches (±5.09 millimeters). The figure indicates the position
of each cutout. Additional design considerations for I/O shields relative to chassis requirements are
described in the ATX specification. See Section 1.3 for information about the ATX specification.
6.39 Ref[162.30]
0.78 ± .01 Typ.[20.0 ±0.25]
0.061 Ref[1.55]6.26[159.20]
0.94 Ref
[23.87]
0.88
[22.45]
0.039 Dia
[1.0]
0.00[0]
0.46[11.81]
0.47[12.0]
0.57[14.43]
8x R .02 Min
[0.50]
0.28
[7.01]
0.00[0]
0.45[11.34]
1.19[30.19]
2.08[52.74]
1.80[45.77]
3.22[81.65]
3x Dia 0.33[8.53]
4.53[115.25]
Pictorial
View
0.52
[13.19]
0.46
[11.81]
0.718
[18.24]
5.77[146.63]
1.89 Ref
[48.00]
OM11070
0.27
[0.69]
64
Figure 11. I/O Shield Dimensions
Technical Reference
2.11 Electrical Considerations
2.11.1Power Consumption
Table 43 lists voltage and current specifications for a computer that contains the D810E2CB board
and the following:
• 1 GHz Intel PentiumIII processor with a 256 KB cache
• 512 MB SDRAM
• 8 GB IDE hard disk drive
• 6X IDE CD-ROM drive
This information is provided only as a guide for calculating approximate power usage with additional
resources added.
†
Values for the Windows
refresh rate. AC watts are measured with a typical 235 W power supply, nominal input voltageand
frequency, with true RMS wattmeter at the line input.
Table 43.Power Usage
98 desktop mode are measured at 640 x 480 x 256 colors and 60 Hz
DC Current at:
ModeAC Power+3.3 V+5 V+12 V-12 V+5 VSB
Windows 98 ACPI S090 W2.5 A5.5 A0.29 A0.08 A0.25 A
Windows 98 ACPI S133 W1.72 A0.6 A0.2 A0.01 A0.245 A
Windows 98 ACPI S34 W0 A0 A0 A0 A0.31 A
Windows 98 ACPI S53 W0 A0 A0 A0 A0.25 A
Windows 98 SE APM On92 W2.4 A5.3 A0.29 A0.08 A0.25 A
Windows 98 SE APM
Systemintegrators should refer to the power usage values listed in when selecting a power supply for
use with this motherboard. The power s upply must comply with the following recommendations
found in the indicated sections of the ATX form factor specification
(see Section 1.3).
• The potential relation between 3.3 VDC and +5 VDC power rails (Section 4.2)
• The current capability of the +5 VSB line (Section 4.2.1.2)
• All timing parame ters (Section 4.2.1.3)
• All voltage tolerances (Section 4.2.2)
2.11.3Standby Current Requirements
The +5 V standby current consumed by the D810E2CB desktop board is TBD. This does not
include external peripherals.
NOTE
✏
These standby current requirements are system configuration dependent.
2.11.4Fan Power Requirements
Table 44 lists the maximum DC voltage and current requirements for the fans when the board is in
sleep mode or normal operating mode. Power consumption is independent of the operating system
used and other variables.
Table 44.Fan DC Power Requirements
Fan TypeModeVoltageMaximum Current (Amps)
Sleep0 VDC0 mA (current limited)Chassis (J7A1)
Normal+ 12 VDC0.17 mA (current limited)
Sleep0 VDC0 mA (current limited)Processor (J2J1)
Normal+ 12 VDC0.17 mA (current limited)
For information aboutRefer to
The location of the fan connectorsFigure 6, page 51
The signal names of the processor fan connectorTable 31, page 52
The signal names of the chassis fan connectorTable 34, page 53
66
Technical Reference
2.12 Thermal Considerations
CAUTION
An ambient temperature that exceeds the board’s maximum operating temperature by 5 ºC to 10 ºC
could cause components to exceed their maximum case temperature and malfunction. For
information about the maximum operating temperature, see the environmental specifications in
Section 2.14.
Figure 12 shows the localized high-temperature zones.
AB
DC
ItemDescription
AIntel 82810E GMCH
BProcessor
CProcessor voltage regulator area
DIntel 82801BA ICH2
Table 45 provides maximum component case temperatures for D810E2CB board components that
couldbe sensitive to thermal changes. Case temperatures could be affected by the operating
temperature, current load, or operatingfrequency. Maximum case temperatures are important when
considering proper airflow to cool the D810E2CB board.
For processor case temperature, see processor
datasheets and processor specification updates
CAUTION
The voltage regulator area can reach a temperature of up to 85 ºC in an open chassis. Ensure that
there is proper airflow to this area of the board. Failure to do so may result in damage to the
voltage regulator circuit. System integrators should ensure that proper airflow is maintained in
the voltage regulator circuit (item C in Figure 12). Components i n this area could be damaged
without adequate airflow.
2.13 Reliability
The mean time between failures (MTBF) prediction is calculated using component and subassembly
random failure rates. The calculation is based on the Bellcore Reliability Prediction Procedure, TRNWT-000332, Issue 4, September 1991. The MTBF prediction is used to estimate repair rates and
spare parts requirements.
The Mean Time Between Failures (MTBF) data is calculated from predicted data at 55 ºC.
D810E2CB board MTBF: 180193.17 hours
68
2.14 Environmental
Table 46 lists the environmental specifications for the D810E2CB board.
Table 46.Environmental Specifications
ParameterSpecification
Temperature
Non-Operating
Operating
Shock
Unpackaged30 g trapezoidal waveform
PackagedHalf sine 2 millisecond
Vibration
Unpackaged5 Hz to 20 Hz: 0.01 g² Hz sloping up to 0.02 g² Hz
This section describes the D810E2CB board’s compliance with U.S. and international safety and
electromagnetic compatibility (EMC) regulations.
2.15.1Safety Regulations
Table 47 lists the safety regulations the D810E2CB board complies with when correctly installed in
a compatible host system.
Table 47.Safety Regulations
RegulationTitle
rd
UL 1950/CSA C22.2 No. 950, 3
edition
EN 60950, 2ndEdition, 1992
(with Amendments 1, 2, 3, and
4)
IEC 60950, 2ndEdition, 1991
(with Amendments 1, 2, 3, and
4)
EMKO-TSE (74-SEC) 207/94Summary of Nordic deviations to EN 60950. (Norway, Sweden,
Bi-National Standard for Safety of Information Technology Equipment
including Electrical Business Equipment. (USA and Canada)
The Standard for Safety of Information Technology Equipment
including Electrical Business Equipment. (European Union)
The Standard for Safety of Information Technology Equipment
including Electrical Business Equipment. (International)
Denmark, and Finland)
2.15.2EMC Regulations
Table 48 lists the EMC regulations the D810E2CB board complies with when correctly installed in a
compatible host system.
Table 48.EMC Regulations
RegulationTitle
FCC (Class B)Title 47 of the Code of Federal Regulations, Parts 2 and 15, Subpart B,
Radiofrequency Devices. (USA)
ICES-003 (Class B)Interference-Causing Equipment Standard, Digital Apparatus (Canada)
EN55022: 1994 (Class B)Limits and methods of measurement of Radio Interference
Characteristics of Information Technology Equipment. (European
3.10 BIOS Security Features .............................................................................................80
3.1Introduction
The D810E2CB board uses an Intel/AMI BIOS, which is stored in flash memory and can be
upgraded. In addition to the BIOS, the flash memory contains the BIOS Setup program, POST, the
PCI auto-configuration utility, and Plug and Play support.
This D810E2CB board supports system BIOS shadowing, allowing the BIOS t o execute from 64-bit
onboard write-protected DRAM.
The BIOS displays a message during POST identifying the type of BIOS and a revision code. The
initial production BIOS is identified as CB81010A.86A.
For information aboutRefer to
The board’s compliance level with Plug and PlayTable 3, page 16
3.2BIOS Flash Memory Organization
The SST 49LF004A Firmware Hub (FWH) includes a 4 Mbit (512 KB) symmetrical flash memory
device. Internally, the device is grouped into eight 64-KB blocks that are individually erasable,
lockable, and unlockable.
The BIOS can automatically configure PCI devices. PCI devices may be onboard or add-in cards.
Autoconfiguration lets a user insert or remove PCI cards without having to configure the system.
When a user turns on the system after adding a PCI card, the BIOS automatically configures
interrupts, the I/O space, and other systemresources. Any interrupts set to Available in Setup are
considered to be available for use by the add-in card. Autoconfiguration information is stored in
ESCD format.
For information a bout the versions of PCI and Plug and Play supported by the BIOS, see
Section 1.3.
3.3.2PCI IDE Support
If you select Auto in the BIOS Setup program, the BIOS automatically sets up the two
PCI IDE connectors with independent I/O channel support. The IDE interface supports hard drives
up to Ultra ATA-100 and recognizes any ATAPI compliant devices, including CD-ROM drives, tape
drives, and Ultra DMA drives (see Section 1.3 for the supported version of ATAPI). The BIOS
determines the capabilities of each drive and configures them to optimize capacity and performance.
To take advantage of the high capacities typically available today, hard drives are automatically
configured for Logical Block Addressing (LBA) and to PIO Mode 3 or 4, depending on the
capability of the drive. You can override the auto-configuration options by specifying manual
configuration in the BIOS Setup program.
To use Ultra ATA-66/100 features the following items are required:
• An Ultra ATA-66/100 peripheral device
• An Ultra ATA-66/100 compatible cable
• Ultra ATA-66/100 operatingsystemdevice drivers
NOTE
✏
Ultra ATA-66/100 compatible cables are backward compatible with drives using slower IDE
transfer protocols. If an Ultra ATA-66/100 disk drive and a disk drive using any other IDE
transfer protocol are attached to the same cable, the maximum transfer rate between the drives is
reduced to that of the slowest device.
NOTE
✏
Do not connect an ATA device as a slave on the same IDE cable as an ATAPI master device. For
example, do not connect an ATA hard drive as a slave to an ATAPI CD-ROM drive.
74
Overview of BIOS Features
3.4System Management BIOS (SMBIOS)
SMBIOS is a Desktop Management Interface (DMI) compliant method for managing computers in a
managed network.
The main component of SMBIOS is the management information format (MIF) database, which
contains information about the computing system and its components. Using SMBIOS, a system
administrator can obtain the system types, capabilities, operational status, and installation dates for
system components. The MIF database defines the data and provides the method for accessing this
®
information. The BIOS enables applications such as Intel
SMBIOS. The BIOS stores and reports the following SMBIOS information:
• BIOS data, such as the BIOS revision level
• Fixed-system data, such as peripherals, serial numbers, and asset tags
• Resource data, such as memory size, cache size, and processor speed
• Dynamic data, such as event detection and error logging
Non-Plug and Play operating systems, such as Windows NT
obtaining the SMBIOS information. The BIOS supports an SMBIOS table interface for such
operating systems. Usingthis support, an SMBIOS service-level application running on a nonPlugandPlayoperatingsystemcanobtaintheSMBIOSinformation.
For information about
The board’s compliance level with SMBIOSTable 3, page 16
LANDesk®Client Manager to use
†
4.0, require an additional interface for
Refer to
3.5USB Legacy Support
USB legacy support enables USB devices such as keyboards, mice, and hubs to be used even when
the operating system’s USB drivers are not yet available. USB legacysupport is used to access the
BIOS Setup program, and to install an operating system that supports USB. By default, USB legacy
support is set t o Enabled.
USB legacy support operates as follows:
1. When you apply power to the computer, legacy support is disabled.
2. POST begins.
3. USB legacy support is enabled by the BIOS allowing you to use a USB keyboard to enter and
configure the BIOS Setup program and the maintenance menu.
4. POST completes.
5.The operating system loads. While the operating system is loading, USB keyboards and mice are
recognized and may be used to configure the operating system. (Keyboards and mice are not
recognized during this period if USB legacy support was set to Disabled in the BIOS Setup
program.)
6.After the operating system loads the USB drivers, all legacy and non-legacy USB devices are
recognized by the operating system, and USB legacy support fr om the BIOS is no longer used.
To install an operating system that supports USB, verify that USB Legacy support in the BIOS
Setup program is set to Enabled and follow the operating system’s installation instructions.
NOTE
✏
USB legacy support is for keyboards, mice, and hubs only. Other USB devices are not supported
in legacy mode.
The BIOS can be updated using either of the following utilities, which are available on the Intel
World Wide Web site:
• Intel
• Intel
Both utilities support the following BIOS maintenance functions:
• Verifying that the updated BIOS matches the target system to prevent accidentally installing an
• Updating both the BIOS boot block and the main BIOS. This process is fault tolerant to prevent
• Updating the BIOS boot block separately.
• Changing the language section of the BIOS.
• Updating replaceable BIOS modules, such as the video BIOS module.
• Insertinga customsplash screen.
®
Express BIOS Update utility, which enables automated updating while in the Windows
environment. Using this utility, the BIOS can be updated from a file on a hard disk, a 1.44 MB
diskette, or a CD-ROM, or from the file location on the Web.
®
Flash Memory Update Utility, which requires creation of a boot diskette and manual
rebooting of the system. Using this utility, the BIOS can be updated from a file on a 1.44 MB
diskette (from a legacy diskette drive or an LS-120 diskette drive) or a CD-ROM.
incompatible BIOS.
boot block corruption.
NOTE
✏
Review the instructions distributed with the upgrade utility before attempting a BIOS update.
For information aboutRefer to
The Intel World Wide Web siteSection 1.2, page 16
3.6.1Language Support
The BIOS Setup program and help messages are supported in five languages: US English, German,
Italian, French, and Spanish. The default language is US English, which is present unless another
language is selected in the BIOS Setup program.
3.6.2Custom Splash Screen
During POST, an Intel splash screen is displayed by default. This splash screen can be replaced
with a custom splash screen. A utility is available from Intel to assist with creating a custom splash
screen. The custom splash screen can be programmed into the flash memory using the BIOS
upgrade utility. Information about this capability is available on the Intel Support World Wide Web
site.
For information aboutRefer to
The Intel World Wide Web siteSection 1.2, page 16
76
Overview of BIOS Features
3.7Recovering BIOS Data
Some types of failure can destroy the BIOS. For example, the data can be lost if a power outage
occurs while the BIOS is being updated in flash memory. The BIOS can be recovered from either a
1.44 MB diskette (for recovery from an LS-120 diskette drive configured as an ATAPI removable
IDE device), or from a CD-ROM using the BIOS recovery mode. When recovering the BIOS be
aware of the following:
• Because of the small amount of code available in the nonerasable boot block area, there is no
video support. You can monitor this procedure by listening to the speaker or looking at the
recovery drive LED.
• Two beeps and the end of activity in the recovery drive indicate successful BIOS recovery.
• A series of continuous beeps indicates a failed BIOS recovery. In case of a BIOS recovery
failure, verify that SPD memory is installed and retry the BIOS recovery procedure. If non-SPD
memory is installed, replace with SPD memory and try the procedure again.
NOTE
✏
BIOS recovery cannot be accomplished if non-SPD DIMMs are installed. The SPD data structure
is required for the recovery process.
To create a BIOS recovery diskette or CD-ROM, a bootable LS-120 diskette or CD-ROM must be
created and the BIOS update files copied to it. BIOS upgrades and the Intel Flash Memory Upgrade
Utility are available from Intel Customer Support through the Intel World WideWeb site.
NOTE
✏
If the computer is configured to boot from an LS-120 diskette (in the Removable Devices submenu),
the BIOS recovery diskette must be a standard 1.44 MB diskette not a 120 MB diskette.
For information aboutRefer to
The BIOS recovery modeSection 2.9, page 61
The Boot menu in the BIOS Setup programSection 4.7, page 98
Contacting Intel customer supportSection 1.2, page 16
In the BIOS Setup program, the user can choose to boot from a diskette drive, hard drives,
CD-ROM, or the network. The default setting is for the diskette drive to be the first boot device, the
hard drive second, and the ATAPI CD-ROM third. The fourth device is disabled.
3.8.1CD-ROM and Network Boot
Booting from CD-ROM is supported in compliance to the El Torito bootable CD-ROM format
specification. Under the Boot menu in the BIOS Setup program, ATAPI CD-ROM is listed as a
boot device. Boot devices are defined in priority order. Accordingly, if there is not a bootable CD in
the CD-ROM drive, the system will attempt to boot to the next defined drive.
The network can be selected as a boot device. This selection allows booting from the onboard LAN
or a network add-in card with a remote boot ROM installed.
For information aboutRefer to
The El Torito specificationSection 1.3, page 16
3.8.2Booting Without Attached Devices
For use in embedded applications, the BIOS has been designed so that after passing the POST, the
operating system loader is invoked even if the following devices are not present:
• Video adapter
• Keyboard
• Mouse
3.9Fast Booting Systems with Intel®Rapid BIOS Boot
Three factors affect system boot speed:
• Selecting and configuring peripherals properly
• Using an optimized BIOS, such as the Intel
• Selecting a compatible operating system
3.9.1Peripheral Selection and Configuration
The following techniques help improve system boot speed:
• Choose a hard drive with parameters such as “power-up to data ready” less than eight seconds,
that minimize hard drive startup delays.
• Select a CD-ROM drive with a fast initialization rate. This rate can influence POST execution
time.
• Eliminate unnecessary add-in adapter features, such as logo displays, screen repaints, or mode
changes in POST. These features may add time to the boot process.
• Try different monitors. Some monitors initialize and communicate with the BIOS more quickly,
which enables the system to boot more quickly.
®
Rapid BIOS
78
Overview of BIOS Features
3.9.2Intel Rapid BIOS Boot
Use of the following BIOS Setup program settings reduces the POST execution time.
In the Boot Menu:
• Set the hard disk drive as the first boot device. As a result, the POST does not first seek a
diskette drive, which saves about one second from the POST execution time.
• Disable Quiet Boot, which eliminates display of the logo splash screen. This could save several
seconds of painting complex graphic images and changing video modes.
• Enabled Intel Rapid BIOS Boot. This feature bypasses memory count and the search for a
diskette drive
In the Peripheral Configuration submenu, disable the LAN device if it will not be used. This can
reduce up to four seconds of option ROM boot time.
NOTE
✏
It is possible to optimize the boot process to the point where the system boots so quickly that the
Intel logo screen (or a custom logo splash screen) will not be seen. Monitors and hard disk drives
with minimum initialization times can also contribute to a boot time that might be so fast that
necessary logo screens and POST messages cannot be seen.
This boot time may be so fast that some drives might be not be initialized at all. If this condition
should occur, it is possible to introduce a programmable delay ranging from 3 to 30 seconds
(using the Hard Disk Pre-Delay feature of the Advanced Menu in the IDE Configuration Submenu
of the BIOS Setup Program).
For information aboutRefer to
IDE Configuration Submenu in the BIOS Setup ProgramSection 4.4.4, page 90
3.9.3Operating System
The Microsoft Windows Millennium Edition (Windows Me) operating system has built-in
capabilities for making PCs boot more quickly. To speed operating system availability at boot time,
limit the number of applications that load into the system tray or the task bar.
The BIOS includes security features that restrict access to the BIOS Setup program and who can
boot the computer. A supervisor password and a user password can be set for the BIOS Setup
program and for booting the computer, with the following restrictions:
• The supervisor password gives unrestricted access to view and change all the Setup options in
the BIOS Setup program. This is supervisor mode.
• The user password gives restricted access to view and change Setup options in the BIOS Setup
program. This is user mode.
• If only the supervisor password is set, pressing the <Enter> key at the password prompt of the
BIOS Setup program allows the user restricted access to Setup.
• If both the supervisor and user passwords are set, users can enter either the supervisor password
or the user password to access Setup. Users have access to Setup respective to which password
is entered.
• Setting the user password restricts who can boot the computer. The password prompt will be
displayed before the computer is booted. If only the supervisor password is set, the computer
boots without asking for a password. If both passwords are set, the user can enter either
password to boot the computer.
Table 49 shows the effects of setting the supervisor password and user password. This table is for
reference only and is not displayed on the screen.
Table 49.Supervisor and User Password Functions
Supervisor
Password Set
NeitherCan change all
Supervisor
only
User onlyN/ACan change all
Supervisor
and user set
*If no password is set, any user can change all Setup options.
For information aboutRefer to
Setting user and supervisor passwordsSection 4.5, page 96
The BIOS Setup program can be used to view and change the BIOS settings for the computer. The
BIOS Setup programis accessed by pressing the <F2> key after the Power-On Self-Test (POST)
memory test begins and before the operating system boot begins. The menu bar is shown below.
MaintenanceMainAdvancedSecurityPowerBootExit
Table 50 lists the BIOS Setup program menu functions.
Table 50.BIOS Setup Program Menu Functions
MaintenanceMainAdvancedSecurityPowerBootExit
✏
Clears
passwords and
allowsmemory
settings
NOTE
Allocates
resources for
hardware
components
Configures
advanced
features
available
through the
chipset
Sets
passwords
and security
features
Configures
power
management
features
Selects boot
options and
power supply
controls
In this chapter, all examples of the BIOS Setup Program menu bar include the maintenance menu;
however, the maintenance menu is displayed only when the board is in configuration mode. Section
2.9 on page 61 tells how to put the board in configuration mode.
Saves or
discards
changes to
Setup
program
options
Table 51 lists the function keys available for menu screens.
Table 51.BIOS Setup Program Function Keys
BIOS Setup Program Function KeyDescription
<←>or<→>
<↑>or<↓>
<Tab>Selects a field
<Enter>Executes command or selects a submenu
<F9>Load the default configuration values for the current menu
<F10>Save the current values and exits the BIOS Setup program
<Esc>Exits the menu
Selects a different menu screen
Selects an item
4.2Maintenance Menu
To access this menu, select Maintenance on the menu bar at the top of the screen.
MaintenanceMainAdvancedSecurityPowerBootExit
Extended Configuration
The menu shown in Table 52 is for clearing Setup passwords and enabling extended configuration
mode. Setup only displays this menu in configuration mode. See Section 2.9 on page 61 for
configuration mode setting information.
Table 52.Maintenance Menu
FeatureOptionsDescription
Clear All Passwords
Clear BIS Credentials
Extended Configuration
CPU Information:
CPU Microcode Update
Revision
CPU Stepping SignatureNo optionsDisplays CPU’s Stepping Signature.
• Yes (default)
• No
• Yes (default)
• No
• Default (default)
• User-Defined
No optionsDisplays CPU’s Microcode Update Revision.
Selecting
Selecting
Service) credentials.
Selecting
configuration.
Yes
clears all passwords.
Yes
clears the WfM BIS (Boot Integrity
User-Defined
allowssetting memory
82
BIOS Setup Program
4.2.1Extended Configuration Submenu
To access this menu, select Maintenance on the menu bar, then Extended Configuration.
MaintenanceMainAdvancedSecurityPowerBootExit
Extended Configuration
The submenu shown in Table 53 is for setting system memory configuration. This submenu
becomes available when User-Defined is selected under Extended Configuration.
CAUTION
Choosing the wrong settings could cause system problems. Do not change these settings unless
you have all the necessary information about the installed memory.
Table 53.Extended Configuration Submenu
FeatureOptionsDescription
Extended ConfigurationDefault (default)
User-Defined
Memory Control:
SDRAM Auto
Configuration
CAS# Latency
SDRAM RAS# to CAS#
delay
SDRAM RAS#
Precharge
• Auto (default)
• User-Defined
• 3
• 2
• Auto (default)
• 3
• 2
• Auto (default)
• 3
• 2
• Auto (default)
Selecting user-defined allows you to select
Defined
items listed under Memory Control below.
Note: If
in the Advanced Menu as: “Extended Menu: Used.”
Sets extended memory configuration options to auto or
user-defined.
Selects the number of clock cycles required to address a
column in memory.
Selects the number of clock cycles between addressing a
row and addressing a column.
Selects the length of time required before accessing a
new row.
To access this menu, select Main on the menu bar at the top of the screen.
MaintenanceMainAdvancedSecurityPowerBootExit
Table54 describes the Main Menu. This menu reports processor and memory information and is for
configuring the system date and system time.
Table 54.Main Menu
FeatureOptionsDescription
BIOS VersionNo optionsDisplays the version of the BIOS
Processor TypeNo optionsDisplays processor type
Processor SpeedNo optionsDisplays processor speed
Front Side Bus
Speed
Cache RAMNo optionsDisplays the size of second-level cache
Total MemoryNo optionsDisplays the total installed SDRAM memory
Memory Bank 0
Memory Bank 1
Language
System TimeHour, minute, and
System DateMonth, day, and yearSpecifies the current date
No optionsDisplays the system bus speed
No options
No options
• English (default)
• Français
• Portugues
•
second
Displays
or absence of memory in Memory Banks 0 and 1
Selects the current default language used by the BIOS
Specifies the current time
SDRAMorNot Installed
indicating the presence
84
BIOS Setup Program
4.4A dvanced Menu
To access this menu, select Advanced on the menu bar at the top of the screen.
MaintenanceMainAdvancedSecurityPowerBootExit
PCI Configuration
Boot Configuration
Peripheral Configuration
IDE Configuration
Diskette Configuration
Event Log Configuration
Video Configuration
Table 55 describes the Advanced Menu. This menu is used for setting advanced features that are
available through the chipset.
Table 55.Advanced Menu
FeatureOptionsDescription
Extended ConfigurationNo optionsIf
PCI ConfigurationSelect to display
submenu
Boot ConfigurationSelect to display
submenu
Peripheral ConfigurationSelect to display
submenu
IDE ConfigurationSelect to display
submenu
Diskette ConfigurationSelect to display
submenu
Event Log ConfigurationSelect to display
submenu
Video ConfigurationSelect to display
submenu
Used
is displayed,
Extended Configuration under the Maintenance Menu.
Configures individual PCI slot’s IRQ priority. When
selected, displays the PCI Configuration submenu.
Configures Plug and Play and the Numlock key, and
resets configuration data. When selected, displays the
Boot Configuration submenu.
Configures peripheral ports and devices. When selected,
displays the Peripheral Configuration submenu.
Specifies type of connected IDE devices.
When selected, displays the Diskette Configuration
submenu.
Configures Event Logging. When selected, displays the
Event Log Configuration submenu.
Configures video features. When selected, displays the
Video Configuration submenu.
Primary IDE Master
Primary IDE Slave
Secondary IDE Master
Secondary IDE Slave
Diskette Configuration
Event Log Configuration
Video Configuration
There are four IDE submenus: primary master, primary slave, secondary master, and secondary
slave. Table 60 shows the format of the IDE submenus. For brevity, only one example is shown.
Table 60.Primary/Secondary IDE Master/Slave Submenus
FeatureOptionsDescription
DriveInstalledNo optionsDisplays the type of drive installed
Type
Maximum CapacityNo optionsDisplays the capacity of the drive.
LBA Mode Control
Multi-Sector Transfers
• None
• User
• Auto (default)
• CD-ROM
• ATAPI Removable
• Other ATAPI
• IDE Removable
• Disabled
• Enabled (default)
• Disabled (default)
• 2Sectors
• 4Sectors
• 8Sectors
• 16 Sectors
Specifies the IDE configuration mode for IDE devices.
User
allows capabilities to be changed.
Auto
fills-in capabilities from ATA/ATAPI device.
Enables or disables LBA mode control.
Specifies number of sectors per block for transfers
from the hard disk drive to memory.
Check the hard disk drive’s specifications for optimum
setting.
To access this menu, select Advanced on the menu bar, then Event Log Configuration.
MaintenanceMainAdvancedSecurityPowerBootExit
PCI Configuration
Boot Configuration
Peripheral Configuration
IDE Configuration
Diskette Configuration
Event Log Configuration
Video Configuration
The submenu represented by Table 62 is used to configure the event logging features.
Table 62.Event Log Configuration Submenu
FeatureOptionsDescription
Event logNo optionsIndicates if there is space available in the event log.
Event log validityNo optionsIndicates if the contents of the event log are valid.
View event log[Enter]Displays the event log.
Clear all event logs
Event Logging
Mark events as read[Enter]Marks all events as read.
• No (default)
• Yes
• Disabled
• Enabled (default)
Clears the event log after rebooting.
Enables logging of events.
94
4.4.7Video Configuration Submenu
To access this menu, select Advanced on the menu bar, then Video Configuration.
To access this menu, select Security from the menu bar at the top of the screen.
MaintenanceMainAdvancedSecurityPowerBootExit
The menu represented by Table 64 is for setting passwords and security features.
Table 64.Security Menu
FeatureOptionsDescription
Supervisor Password IsNo optionsReports if there is a supervisor password set.
User Password IsNo optionsReports if there is a user password set.
Set Supervisor PasswordPassword can be up to seven
alphanumeric characters.
Set User PasswordPassword can be up to seven
alphanumeric characters.
Clear User Password
(Note 1)
User Access Level
(Note 2)
Unattended Start
(Note 1)
Notes:
1.This feature appears only if a user password has been set.
2.This feature appears only if a supervisor password has been set.
• Yes (default)
• No
• Limited
• No Access
• View Only
• Full (default)
• Disabled (default)
• Enabled
Specifies the supervisor password.
Specifies the user password.
Clears the user password.
Sets BIOS Setup Utility access rights for user
level.
Enabled allows system to complete the boot
process without a password. The keyboard
remains locked until a password is entered.
A password is required to boot from a
diskette.
96
4.6Power Menu
To access this menu, select Power from the menu bar at the top of the screen.
MaintenanceMainAdvancedSecurityPowerBootExit
The menu represented in Table 65 is for setting the power management features.
Table 65.Power Menu
FeatureOptionsDescription
Power Management
(Note)
Inactivity Timer
(Note)
Hard Drive
(Note)
ACPI Suspend State
Power Button Mode
Note:Power Management, Inactivity Timer, and Hard Drive features apply only for APM operating systems.
• Disabled
• Enabled (default)
• Off
• 1 Minute
• 5 Minutes
• 10 Minutes
• 20 Minutes
(default)
• 30 Minutes
• 60 Minutes
• 120 Minutes
• Disabled (default)
• Enabled
• S1 State (default)
• S3 State
• On/Off (default)
• Suspend
Enable or disable the BIOS power management feature.
Specifies the amount of time before the computer
enters standby mode, when APM power management is
active.
Enables or disables power management for hard disks
during standby and suspend modes, when APM power
management is active.
To access this menu, select Boot from the menu bar at the top of the screen.
MaintenanceMainAdvancedSecurityPowerBootExit
IDE Drive Configuration
The menu represented in Table 66 is used to set the boot features and the boot sequence.
Table 66.Boot Menu
FeatureOptionsDescription
Silent Boot
Intel Rapid BIOS
Boot
Scan User Flash
Area
After Power
Failure
Wake on Modem
Ring
Wake on LAN
Wake on PME
• Disabled
• Enabled (default)
• Disabled
• Enabled (default)
• Disabled (default)
• Enabled
• Stays Off
• Last State (default)
• Power On
• Stay Off (default)
• Power On
• Stay Off (default)
• Power On
• Stay Off (default)
• Power On
Disabled
Enabled
Enables the computer to boot without running certain POST
tests.
Enables the BIOS to scan the flash memory for user binary
files that are executed at boot time.
Specifies the mode of operation if an AC power loss occurs.
Stay Off
pressed.
Last State
loss occurred.
Power On
In APM mode only, specifies how the computer responds to
an incoming call on an installed modem when the power is
off.
In APM mode only, determines how the system responds to a
LAN wake up event.
In APM mode only, determines how the system responds to a
PCI power management event.
displays normal POST messages.
displays OEM graphic instead of POST messages.
keeps the power off until the power button is
restores the previous power state before power
restores power to the computer.
continued
98
Table 66.Boot Menu (continued)
FeatureOptionsDescription
1stBoot Device
nd
Boot Device
2
rd
Boot Device
3
th
Boot Device
4
• Floppy
• ARMD-FDD
(Note 1)
• ARMD-HDD
(Note 2)
• IDE-HDD
(Note 3)
• ATAPI CDROM
• Intel UNDI,
PXE 2.0
(Note 4)
• Disabled
IDE Drive Configuration
Primary Master IDE
Primary Slave IDE
Secondary Master IDE
• 1
• 2
• 3
• 4
st
nd
rd
th
IDE (default)
IDE
IDE
IDE
Secondary Slave IDE
Notes:
1ARMD-FDD = ATAPI removabledevice - floppydisk drive
2ARMD-HDD = ATAPI removable device - hard disk drive
3HDD = Hard Disk Drive
4This boot device is availableonly when the onboard LAN subsystem is present.
Specifies the boot sequence according to the device
type. The computer will attempt to boot from up to four
devices as specified here. Only one of the devices can
be an IDE hard disk drive. To specify boot sequence:
1.Select the boot device with <↑>or<↓>.
2.Press <Enter> to set the selection as the intended
boot device.
The default settings for the first through fourth boot
devices are, respectively:
• Floppy
• IDE-HDD
• ATAPI CDROM
• Disabled
NOTE: To configure the computer to boot from an IDE
hard disk drive, set a boot device in the Setup feature to
IDE-HDD
. Determine the IDE channel, and master or
slave mode of the drive. Then, in the next Setup
feature,
mode to
1stIDE
The
IDE Drive Configuration
1stIDE
.
specifies the IDE hard disk drive to boot from.
nd
2
through
4thIDE
note above for more information.
To specify the drive to boot from:
The menu represented in Table 67 is for exiting the BIOS Setup program, saving changes, and
loading and saving defaults.
Table 67.Exit Menu
FeatureDescription
Exit Saving ChangesExits and saves the changes in CMOS SRAM.
Exit Discarding Changes Exits without saving any changes made in the BIOS Setup program.
Load Setup DefaultsLoads the factory default values for all the Setup options.
Load Custom DefaultsLoads the custom defaults for Setup options.
Save Custom DefaultsSaves the current values as custom defaults. Normally, the BIOS reads the
Setup values from flash memory. If this memory is corrupted, the BIOS reads
the custom defaults. If no custom defaults are set, the BIOS reads the factory
defaults.
Discard ChangesDiscards changes without exiting Setup. The option values present when the
computer was turned on are used.
100
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.