— One Instruction/Clock Execution
— Core Clock Rate is 2x the Bus Clock
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
■ Two-Way Set Associative Instruction Cache
— 80960JD - 4 Kbyte
— Programmable Cache Locking
Mechanism
■ Direct Mapped Data Cache
— 80960JD - 2 Kbyte
— Write Through Operation
■ On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
2.2 Burst Bus ............................................................................................................................................2
2.3 Timer Unit ...........................................................................................................................................3
2.5 Instruction Set Summary ....................................................................................................................3
2.6 Faults and Debugging .........................................................................................................................3
2.7 Low Power Operation .........................................................................................................................4
2.8 Test Features ......................................................................................................................................4
2.9 Memory-Mapped Control Registers ....................................................................................................4
2.10 Data Types and Memory Addressing Modes ....................................................................................4
3.0 PACKAGE INFORMATION ........................................................................................................................6
Figure 12.Output Delay Waveform for T
Figure 13.Output Float Waveform for T
Figure 14.Input Setup and Hold Waveform for T
Figure 15.Input Setup and Hold Waveform for T
Figure 16.Input Setup and Hold Waveform for T
Figure 17.Input Setup and Hold Waveform for T
Figure 18.Relative Timings Waveform for T
Figure 19.DT/R
and DEN Timings Waveform .......................................................................................... 38
Figure 21.Input Setup and Hold Waveforms for T
Figure 22.Output Delay and Output Float Waveform for T
Figure 23.Output Delay and Output Float Waveform for T
Figure 24.Input Setup and Hold Waveform for T
Figure 25.Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ...............................42
Figure 26.Burst Read and Write Transactions Without Wait States, 32-Bit Bus ......................................43
Figure 27.Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ................................................44
Figure 28.Burst Read and Write Transactions Without Wait States, 8-Bit Bus ........................................ 45
Figure 29.Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus ...................................................................................46
Figure 30.Bus Transactions Generated by Double Word Read Bus Request,
Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian ........................... 47
Figure 31.HOLD/HOLDA Waveform For Bus Arbitration .......................................................................... 48
This document contains advance information for the
80960JD microprocessor, including electrical
characteristics and package pinout information.
Detailed functional descriptions — other than
parametric performance — are published in the
®
Jx Microprocessor User’s Guide (272483).
i960
Throughout this data sheet, references to “80960Jx”
indicate features which apply to all of the following:
• 80960JD — 5V, 4 Kbyte instruction cache, 2 Kbyte
data cache and clock doubling
• 80L960JA — 3.3 V version of the 80960JA
• 80L960JF — 3.3 V version of the 80960JF
2.080960JD OVERVIEW
The 80960JD offers high performance to costsensitive 32-bit embedded applications. The
80960JD is object code compatible with the 80960
Core Architecture and is capable of sustained
execution at the rate of one instruction per clock.
This processor’s features include generous
instruction cache, data cache and data RAM. It also
boasts a fast interrupt mechanism, dual programmable timer units and new instructions.
The 80960JD’s clock doubler operates the processor
core at twice the bus clock rate to improve execution
performance without increasing the complexity of
board designs.
Memory subsystems for cost-sensitive embedded
applications often impose substantial wait state
penalties. The 80960JD integrates considerable
storage resources on-chip to decouple CPU
execution from the external bus.
The 80960JD rapidly allocates and deallocates local
register sets during context switches. The processor
needs to flush a register set to the stack only when it
saves more than seven sets to its local register
cache.
A 32-bit multiplexed burst bus provides a high-speed
interface to system memory and I/O. A full
complement of control signals simplifies the
connection of the 80960JD to external components.
The user programs physical and logical memory
attributes through memory-mapped control registers
(MMRs) — an extension not found on the i960 Kx,
Sx or Cx processors. Physical and logical configuration registers enable the processor to operate with
all combinations of bus width and data object
alignment. The processor supports a homogeneous
byte ordering model.
This processor integrates two important peripherals:
a timer unit and an interrupt controller. These and
other hardware resources are programmed through
memory-mapped control registers, an extension to
the familiar 80960 architecture.
The timer unit (TU) offers two independent 32-bit
timers for use as real-time system clocks and
general-purpose system timing. These operate in
either single-shot or auto-reload mode and can
generate interrupts.
The interrupt controller unit (ICU) provides a flexible
means for requesting interrupts. The ICU provides
full programmability of up to 240 interrupt sources
into 31 priority levels. The ICU takes advantage of a
cached priority table and optional routine caching to
minimize interrupt latency. Clock doubling reduces
interrupt latency by 40% compared to the
80960JA/JF. Local registers may be dedicated to
high-priority interrupts to further reduce latency.
Acting independently from the core, the ICU
compares the priorities of posted interrupts with the
current process priority, off-loading this task from the
core. The ICU also supports the integrated timer
interrupts.
The 80960JD features a Halt mode designed to
support applications where low power consumption
is critical. The halt instruction shuts down instruction
execution, resulting in a power savings of up to 90
percent.
The 80960JD’s testability features, including ONCE
(On-Circuit Emulation) mode and Boundary Scan
(JTAG), provide a powerful environment for design
debug and fault diagnosis.
The Solutions960® program features a wide variety
of development tools which support the i960
processor family. Many of these tools are developed
by partner companies; some are developed by Intel,
such as profile-driven optimizing compilers. For more
information on these products, contact your local
Intel representative.
PRELIMINARY
1
80960JDA
SRC1
SRC2
DEST
SRC1
SRC2
DEST
SRC1
DEST
CLKIN
TAP
Local Register Cache
PLL, Clocks,
Power Mgmt
Boundary Scan
5
8-Set
128
Global / Local
Register File
SRC2 DESTSRC1
Controller
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
4 KByte Instruction Cache
Two-Way Set Associative
Constants
and
Address
Unit
effective
address
Control
Multiply
Divide
Unit
Instruction Sequencer
Execution
Generation
Figure 2. 80960JD Block Diagram
Memory
Interface
Unit
32-bit Address
32-bit Data
32-bit buses
address / data
Physical Region
Configuration
Bus
Control Unit
Bus Request
Queues
Two 32-Bit
Timers
Programmable
Interrupt Controller
Memory-Mapped
Register Interface
1 K byte
Data RAM
2 Kbyte Direct
Mapped Data
Cache
Control
21
Address/
Data Bus
32
Interrupt
Port
9
2.180960 Processor Core
The 80960Jx family is a scalar implementation of the
80960 Core Architecture. Intel designed this
processor core as a very high performance device
that is also cost-effective. Factors that contribute to
the core’s performance include:
• Core operates at twice the bus speed (80960JD
only)
• Register and resource scoreboarding allow
overlapped instruction execution
2
• 128-bit register bus speeds local register caching
• 4 Kbyte two-way set associative, integrated
instruction cache
• 2 Kbyte direct-mapped, integrated data cache
• 1 Kbyte integrated data RAM delivers zero wait
state program data
2.2Burst Bus
A 32-bit high-performance bus controller interfaces
the 80960JD to external memory and peripherals.
The BCU fetches instructions and transfers data at
the rate of up to four 32-bit words per six clock
cycles. The external address/data bus is multiplexed.
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A80960JD
Users may configure the 80960JD’s bus controller to
match an application’s fundamental memory organization. Physical bus width is register-programmed for
up to eight regions. Byte ordering and data caching
are programmed through a group of logical memory
templates and a defaults register.
The BCU’s features include:
• Multiplexed external bus to minimize pin count
• 32-, 16- and 8-bit bus widths to simplify I/O
interfaces
• External ready control for address-to-data, data-todata and data-to-next-address wait state types
• Support for big or little endian byte ordering to
facilitate the porting of existing program code
• Unaligned bus accesses performed transparently
• Three-deep load/store queue to decouple the bus
from the core
Upon reset, the 80960JD conducts an internal self
test. Then, before executing its first instruction, it
performs an external bus confidence test by
performing a checksum on the first words of the
initialization boot record (IBR).
The user may examine the contents of the caches at
any time by executing special cache control instructions.
2.3Timer Unit
The timer unit (TU) contains two independent 32-bit
timers which are capable of counting at several clock
rates and generating interrupts. Each is programmed
by use of the TU registers. These memory-mapped
registers are addressable on 32-bit boundaries. The
timers have a single-shot mode and auto-reload
capabilities for continuous operation. Each timer has
an independent interrupt request to the 80960JD’s
interrupt controller. The TU can generate a fault
when unauthorized writes from user mode are
detected. Clock prescaling is supported.
2.4Priority Interrupt Controller
A programmable interrupt controller manages up to
240 external sources through an 8-bit external
interrupt port. Alternatively, the interrupt inputs may
be configured for individual edge- or level-triggered
inputs. The interrupt unit (IU) also accepts interrupts
from the two on-chip timer channels and a single
Non-Maskable Interrupt (NMI
serviced according to their priority levels relative to
the current process priority.
Low interrupt latency is critical to many embedded
applications. As part of its highly flexible interrupt
mechanism, the 80960JD exploits several
techniques to minimize latency:
• Interrupt vectors and interrupt handler routines can
be reserved on-chip
• Register frames for high-priority interrupt handlers
can be cached on-chip
• The interrupt stack can be placed in cacheable
memory space
• Interrupt microcode executes at twice the bus
frequency
) pin. Interrupts are
2.5Instruction Set Summary
The 80960Jx adds several new instructions to the
i960 core architecture. The new instructions are:
• Conditional Move
• Conditional Add
• Conditional Subtract
• Byte Swap
• Halt
• Cache Control
• Interrupt Control
Table 1 identifies the instructions that the 80960Jx
supports. Refer to i960Guide (272483) for a detailed description of each
instruction.
®
Jx Microprocessor User’s
2.6Faults and Debugging
The 80960Jx employs a comprehensive fault model.
The processor responds to faults by making implicit
calls to a fault handling routine. Specific information
collected for each fault allows the fault handler to
diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities. In
software, the 80960Jx may be configured to detect
as many as seven different trace event types. Alter-
PRELIMINARY
3
80960JDA
natively, mark and fmark instructions can generate
trace events explicitly in the instruction stream.
Hardware breakpoint registers are also available to
trap on execution and data addresses.
2.7Low Power Operation
Intel fabricates the 80960Jx using an advanced submicron manufacturing process. The processor’s submicron topology provides the circuit density for
optimal cache size and high operating speeds while
dissipating modest power. The processor also uses
dynamic power management to turn off clocks to
unused circuits.
Users may program the 80960Jx to enter Halt mode
for maximum power savings. In Halt mode, the
processor core stops completely while the integrated
peripherals continue to function, reducing overall
power requirements up to 90 percent. Processor
execution resumes from internally or externally
generated interrupts.
2.8Test Features
The 80960Jx incorporates numerous features which
enhance the user’s ability to test both the processor
and the system to which it is attached. These
features include ONCE (On-Circuit Emulation) mode
and Boundary Scan (JTAG).
The 80960Jx provides testability features compatible
with IEEE Standard Test Access Port and Boundary
Scan Architecture (IEEE Std. 1149.1).
One of the boundary scan instructions, HIGHZ,
forces the processor to float all its output pins
(ONCE mode). ONCE mode can also be initiated at
reset without using the boundary scan mechanism.
ONCE mode is useful for board-level testing. This
feature allows a mounted 80960JD to electrically
“remove” itself from a circuit board. This allows for
system-level testing where a remote tester — such
as an in-circuit emulator — can exercise the
processor system.
The provided test logic does not interfere with
component or circuit board behavior and ensures
that components function correctly, connections
between various components are correct, and
various components interact correctly on the printed
circuit board.
The JTAG Boundary Scan feature is an attractive
alternative to conventional “bed-of-nails” testing. It
can examine connections which might otherwise be
inaccessible to a test system.
2.9Memory-Mapped Control
Registers
The 80960JD, though compliant with i960 series
processor core, has the added advantage of
memory-mapped, internal control registers not found
on the i960 Kx, Sx or Cx processors. These give
software the interface to easily read and modify
internal control registers.
Each of these registers is accessed as a memorymapped, 32-bit register. Access is accomplished
through regular memory-format instructions. The
processor ensures that these accesses do not
generate external bus cycles.
2.10 Data Types and Memory
Addressing Modes
As with all i960 family processors, the 80960Jx
instruction set supports several data types and
formats:
will be specified for operation at V
over a case temperature range of 0° to 100°C:
= 5.0 V ± 5%
cc
• NG80960JD-40 (40 MHz core, 20 MHz bus)
• NG80960JD-33 (33.33 MHz core, 16.67 MHz bus)
For complete package specifications and infor-
mation, refer to Intel’s Packaging Handbook
(240800).
3.1Pin Descriptions
This section describes the pins for the 80960JD in
the 132-pin ceramic Pin Grid Array (PGA) package
and 132-lead Plastic Quad Flatpack Package
(PQFP).
Section 3.1.1, Functional Pin Definitions
describes pin function; Section 3.1.2, 80960Jx 132Lead PGA Pinout and Section 3.1.3, 80960Jx
PQFP Pinout define the signal and pin locations for
the supported package types.
3.1.1 Functional Pin Definitions
Table 2 presents the legend for interpreting the pin
descriptions which follow. Pins associated with the
bus interface are described in Table 3. Pins
associated with basic control and test functions are
described in Table 4. Pins associated with the
Interrupt Unit are described in Table 5.
Table 2. Pin Description Nomenclature
SymbolDescription
IInput pin only.
OOutput pin only.
I/OPin can be either an input or output.
–Pin must be connected as described.
SSynchronous. Inputs must meet setup
and hold times relative to CLKIN for
proper operation.
R(1) is driven to V
R(0) is driven to V
R(Q) is a valid output
CC
SS
R(X) is driven to unknown state
R(H) is pulled up to V
CC
H (...)While the processor is in the hold state,
the pin:
H(1) is driven to V
H(0) is driven to V
H(Q) Maintains previous state or
CC
SS
continues to be a valid output
H(Z) Floats
P (...)While the processor is halted, the pin:
P(1) is driven to V
P(0) is driven to V
P(Q) Maintains previous state or
CC
SS
continues to be a valid output
6
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A80960JD
Table 3. Pin Description — External Bus Signals (Sheet 1 of 4)
NAMETYPEDESCRIPTION
AD31:0I/O
S(L)
R(X)
H(Z)
P(Q)
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data
T
to and from memory. During an address (
address (bits 0-1 indicate SIZE; see below). During a data (T
) cycle, bits 31:2 contain a physical word
a
data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,
AD15:8 and AD7:0. During write operations, unused pins are driven to determinate
values.
SIZE, which comprises bits 0-1 of the AD lines during a
number of data transfers during the bus transaction.
When the processor enters Halt mode, if the previous bus operation was a:
• write — AD31:2 are driven with the last data value on the AD bus.
• read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are
driven with the value of A3:2 from the last data cycle.
Typically, AD1:0 reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
ALEO
R(0)
H(Z)
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
T
asserted during a
active HIGH and floats to a high impedance state during a hold cycle (T
cycle and deasserted before the beginning of the Td state. It is
a
P(0)
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE
ALE
O
R(1)
H(Z)
inverted version of ALE. This signal gives the 80960JD a high degree of compatibility
with existing 80960Kx systems.
P(1)
ADDRESS STROBE indicates a valid address and the start of a new bus access.
ADS
O
R(1)
H(Z)
The processor asserts ADS
samples ADS
at the end of the cycle.
for the entire Ta cycle. External bus control logic typically
P(1)
A3:2O
R(X)
H(Z)
P(Q)
ADDRESS3:2 comprise a partial demultiplexed address bus.
32-bit memory accesses: the processor asserts address bits A3:2 during
partial word address increments with each assertion of RDYRCV
16-bit memory accesses: the processor asserts address bits A3:1 during
driven on the
of RDYRCV
BE1 pin. The partial short word address increments with each assertion
during a burst.
8-bit memory accesses: the processor asserts address bits A3:0 during
driven on BE1:0
RDYRCV
. The partial byte address increments with each assertion of
during a burst.
) cycle, read or write
d
T
cycle, specifies the
a
h
during a burst.
T
).
is the
T
. The
a
T
with A1
a
, with A1:0
a
PRELIMINARY
7
80960JDA
Table 3. Pin Description — External Bus Signals (Sheet 2 of 4)
NAMETYPEDESCRIPTION
BE3:0O
R(1)
H(Z)
P(1)
WIDTH/
HLTD1:0
R(0)
H(Z)
P(1)
D/C
R(X)
H(Z)
P(Q)
W/R
R(0)
H(Z)
P(Q)
BYTE ENABLES select which of up to four data bytes on the bus participate in the
current bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:
32-bit bus:
enables data on AD31:24
BE3
enables data on AD23:16
BE2
enables data on AD15:8
BE1
enables data on AD7:0
BE0
16-bit bus:
becomes Byte High Enable (enables data on AD15:8)
BE3
is not used (state is high)
BE2
becomes Address Bit 1 (A1)
BE1
becomes Byte Low Enable (enables data on AD7:0)
BE0
8-bit bus:
is not used (state is high)
BE3
is not used (state is high)
BE2
becomes Address Bit 1 (A1)
BE1
becomes Address Bit 0 (A0)
BE0
The processor asserts byte enables, byte high enable and byte low enable during
Since unaligned bus requests are split into separate bus transactions, these signals
do not toggle during a burst. They remain active through the last T
cycle.
d
For accesses to 8- and 16-bit memory, the processor asserts the address bits in
conjunction with A3:2 described above.
WIDTH/HALTED signals denote the physical memory attributes for a bus transaction:
The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in
response to a HOLD request, regardless of prior operating state.
DATA/CODE indicates that a bus access is a data access (1) or an instruction access
O
has the same timing as W/R.
(0). D/C
0 = instruction access
1 = data access
WRITE/READ specifies, during a
O
(0). It is latched on-chip and remains valid during T
T
cycle, whether the operation is a write (1) or read
a
cycles.
d
0 = read
1 = write
T
.
a
8
PRELIMINARY
A80960JD
Table 3. Pin Description — External Bus Signals (Sheet 3 of 4)
NAMETYPEDESCRIPTION
DT/RO
DEN
BLAST
RDYRCV
/
LOCK
ONCE
R(0)
H(Z)
P(Q)
R(1)
H(Z)
P(1)
R(1)
H(Z)
P(1)
S(L)
S(L)
R(H)
H(Z)
P(1)
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the
address/data bus. It is low during T
/Td cycles for a write. DT/R never changes state when DEN is asserted.
and T
w
0 = receive
1 = transmit
DATA ENABLE indicates data transfer cycles during a bus access. DEN
O
at the start of the first data cycle in a bus access and deasserted at the end of the last
data cycle. DEN
to the data bus.
0 = data cycle
1 = not data cycle
BURST LAST indicates the last transfer in a bus access. BLAST
O
last data transfer of burst and non-burst accesses. BLAST
wait states are inserted via the RDYRCV
data transfer in a bus cycle.
0 = last data transfer
1 = not last data transfer
I
READY/RECOVER indicates that data on AD lines can be sampled or removed. If
RDYRCV
by inserting a wait state (T
0 = sample data
1 = don’t sample data
The RDYRCV
continues to insert additional recovery states until it samples the pin HIGH. This
function gives slow external devices more time to float their buffers before the
processor begins to drive address again.
0 = insert wait states
1 = recovery complete
BUS LOCK indicates that an atomic read-modify-write operation is in progress. The
I/O
output is asserted in the first clock of an atomic operation and deasserted in
LOCK
the last data transfer of the sequence. The processor does not grant HOLDA while it
is asserting LOCK
semaphore operations.
0 = Atomic read-modify-write in progress
1 = Atomic read-modify-write not in progress
ONCE MODE: The processor samples the ONCE
LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the
processor stops all clocks and floats all output pins. The pin has a weak internal
pullup which is active during reset to ensure normal operation when the pin is left
unconnected.
0 = ONCE mode enabled
1 = ONCE mode not enabled
is used with DT/R to provide control for data transceivers connected
is not asserted during a Td cycle, the Td cycle is extended to the next cycle
w
pin has another function during the recovery (Tr) state. The processor
. This prevents external agents from accessing memory involved in
and Tw/Td cycles for a read; it is high during Ta
a
is asserted in the
pin. BLAST becomes inactive after the final
).
remains active as long as
input during reset. If it is asserted
is asserted
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9
80960JDA
Table 3. Pin Description — External Bus Signals (Sheet 4 of 4)
NAMETYPEDESCRIPTION
HOLDI
S(L)
HOLDAO
R(Q)
H(1)
P(Q)
BSTATO
R(0)
H(Q)
P(0)
Table 4. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 1 of 2)
NAMETYPEDESCRIPTION
CLKINICLOCK INPUT provides the processor’s fundamental time base; both the processor
RESET
A(L)
STESTI
S(L)
HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the T
HOLD is deasserted, the processor deasserts HOLDA and enters either the T
state. When
h
state, resuming control of the address/data and control lines.
0 = no hold request
1 = hold request
HOLD ACKNOWLEDGE indicates to an external bus master that the processor has
relinquished control of the bus. The processor can grant HOLD requests and enter
state during reset and while halted as well as during regular operation.
the T
h
0 = hold not acknowledged
1 = hold acknowledged
BUS STATUS indicates that the processor may soon stall unless it has sufficient
access to the bus; see i960
logic can examine this signal to determine when an external bus master should
acquire/relinquish the bus.
0 = no potential stall
1 = potential stall
core and the external bus run at the CLKIN rate. All input and output timings are
specified relative to a rising CLKIN edge.
I
RESET initializes the processor and clears its internal logic. During reset, the
processor places the address/data bus and control output pins in their idle (inactive)
states.
During reset, the input pins are ignored with the exception of LOCK
/ONCE, STEST
and HOLD.
The RESET
ization during power up, RESET
cycles with V
a minimum of 15 cycles.
pin has an internal synchronizer. To ensure predictable processor initial-
must be asserted a minimum of 10,000 CLKIN
and CLKIN stable. On a warm reset, RESET should be asserted for
CC
SELF TEST enables or disables the processor’s internal self-test feature at initialization. STEST is examined at the end of reset. When STEST is asserted, the
processor performs its internal self-test and the external bus confidence test. When
STEST is deasserted, the processor performs only the external bus confidence test.
0 = self test disabled
1 = self test enabled
or Ta
i
10
PRELIMINARY
A80960JD
Table 4. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 2 of 2)
NAMETYPEDESCRIPTION
FAILO
TCKITEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1
TDII
TDOO
TRST
TMSI
V
CC
V
CCPLL
V
SS
NC–NO CONNECT pins. Do not make any system connections to these pins.
R(0)
H(Q)
P(1)
S(L)
R(Q)
HQ)
P(Q)
A(L)
S(L)
FAIL indicates a failure of the processor’s built-in self-test performed during initialization. FAIL
indicate the status of individual tests:
• When self-test passes, the processor deasserts FAIL
user code.
• When self-test fails, the processor asserts FAIL
0 = self test failed
1 = self test passed
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.
TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising edge
of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.
TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling
edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At
other times, TDO floats. TDO does not float during ONCE mode.
I
TEST RESET asynchronously resets the Test Access Port (TAP) controller function
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
feature, connect a pulldown resistor between this pin and V
pin must be connected to V
Connection Recommendations (pg. 24).
TEST MODE SELECT is sampled at the rising edge of TCK to select the operation
of the test logic for IEEE 1149.1 Boundary Scan testing.
–POWER pins intended for external connection to a VCC board plane.
–PLL POWER is a separate VCC supply pin for the phase lock loop clock generator. It
is intended for external connection to the V
add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on
timing relationships.
–GROUND pins intended for external connection to a VSS board plane.
is asserted immediately upon reset and toggles during self-test to
and begins operation from
and then stops executing.
. If TAP is not used, this
; however, no resistor is required. See Section 4.3,
SS
board plane. In noisy environments,
CC
SS
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11
80960JDA
Table 5. Pin Description — Interrupt Unit Signals
NAMETYPEDESCRIPTION
I
XINT7:0
A(E/L)
NMI
A(E)
EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT7:0
pins can be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs
can be programmed to be level (low) or edge (falling) sensitive.
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins
are level sensitive in this mode.
Mixed Mode: The XINT7:5
pins act as dedicated sources and the XINT4:0 pins
act as the five most significant bits of a vectored source. The least
significant bits of the vectored source are set to 010
Unused external interrupt pins should be connected to V
I
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
is the highest priority interrupt source and is falling edge-triggered. If NMI is
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
34BLAST67NC100AD8
68AD26101AD7
69AD25102AD6
70AD24103AD5
38VSS (Core)71V
39V
40V
41V
(Core)72V
CC
(I/O)73V
SS
(I/O)74V
CC
(I/O)104AD4
SS
(I/O)105V
CC
(Core)106V
SS
(Core)107AD3
CC
CC
SS
(I/O)
(I/O)
44HOLDA77AD21110AD0
45ALE78AD20111V
46V
47V
48V
56V
57V
(Core)79V
SS
(Core)80V
CC
(I/O)81AD19114V
SS
(I/O)82AD18115V
CC
85V
86V
(I/O)89AD13122NC
SS
(I/O)90AD12123V
CC
(Core)91V
SS
(Core)92V
CC
(I/O)97V
SS
(I/O)98V
CC
(I/O)112V
SS
(I/O)113V
CC
(I/O)118V
SS
(I/O)119V
CC
(Core)124VSS (Core)
SS
(Core)125RESET
CC
(I/O)126NC
SS
(I/O)127NC
CC
(I/O)130TDI
SS
(I/O)131V
CC
(I/O)
CC
(I/O)
SS
(Core)
CC
(Core)
SS
(Core)
CC
(Core)
SS
(CLK)
SS
CCPLL
CC (CLK)
(Core)
CC
(I/O)
CC
(I/O)
SS
PRELIMINARY
19
80960JDA
T
3.2Package Thermal Specifications
The 80960JD is specified for operation when T
(case temperature) is within the range of 0°C to 85°C
for the (PGA) 80960JD-50, or 0°C to 100°C for the
(PQFP and PGA) 80960JD-40 and 80960JD-33.
Case temperature may be measured in any
environment to determine whether the 80960JD is
within specified operating range. The case temperature should be measured at the center of the top
surface, opposite the pins.
θCA is the thermal resistance from case to ambient.
Use the following equation to calculate T
maximum ambient temperature to conform to a
particular case temperature:
= TC - P (θCA)
T
A
Junction temperature (T
reliability calculations. T
(thermal resistance from junction to case) using the
. Values for θJC and θCA are given in Table 10 for
V
CC
the PGA package and Table 11 for the PQFP
is known, the corresponding case
A
) can be calculated as follows:
C
from Table 14 and
CC
package. For high speed operation, the processor’s
θJA may be significantly reduced by adding a
heatsink and/or by increasing airflow.
Figure 6 shows the maximum ambient temperature
) permitted without exceeding TC for the
(T
A
80960JD-50 in a PGA package. Figure 7 illustrates
this for the 80960JD-40 in PGA and PQFP
packages. The curves are based on minimum I
(hot) and maximum VCC of +5.25 V, with a T
+85°C for the 80960JD-50, or a T
the 80960JD-40.
CASE
Airflow — ft./min (m/sec)
0
(0)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
333333
181512111111
θ
CA
θ
JC
θ
J-CAP
CASE
of +100°C for
1000
(5.08)
CC
of
20
NOTES:
1. This table applies to a PGA device plugged into a socket or soldered directly into a board.
1. This table applies to a PQFP device soldered directly into board.
θJA = θJC + θ
2.
3. θJL = 18°C/W (approx.)
θJB = 18°C/W (approx.)
4.
CA
65
60
55
50
45
40
35
30
0100200300400500600700800
PGA with no heatsinkPGA with omnidirectional heatsink
AIRFLOW (ft/min)
PGA with unidirectional heatsink
Figure 6. 50 MHz Maximum Allowable Ambient Temperature
PRELIMINARY
21
80960JDA
TEMPERATURE (oC)
85
80
75
70
65
60
55
50
45
40
050100200300400
PQFP
PGA with no heatsinkPGA with omnidirectional heatsink
AIRFLOW (ft/min)
500600700
PGA with unidirectional heatsink
800
Figure 7. 40 MHz Maximum Allowable Ambient Temperature
3.3Thermal Management
Accessories
The following is a list of suggested sources for
80960JD thermal solutions. This is neither an
endorsement or a warranty of the performance of
any of the listed products and/or companies.
3. Aavid Thermal Technologies, Inc.
One Kool Path
Laconia, NH 03247-0400
(603) 528-3400
Heatsinks
1. Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75234-8993
(214) 243-4321 FAX: (214) 241-4656
22
PRELIMINARY
A80960JD
4.0ELECTRICAL SPECIFICATIONS
4.1Absolute Maximum Ratings
ParameterMaximum Rating
Storage Temperature..............................–65° C to +150° C
Case Temperature Under Bias ...............–65° C to +110° C
Supply Voltage wrt. V
Voltage on Other Pins wrt. V
..............................–0.5V to + 4.6V
SS
........... –0.5V to VCC + 0.5V
SS
NOTICE: This data sheet contains preliminary information
on new products in production. The specifications are
subject to change without notice.
WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only. Operation
beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
For clean on-chip power distribution, VCC and V
pins separately feed the device’s functional units.
Power and ground connections must be made to all
80960JD power and ground pins. On the circuit
board, every V
plane and every V
plane. Place liberal decoupling capacitance near the
80960JD, since the processor can cause transient
power surges.
pin should connect to a power
CC
pin should connect to a ground
SS
Pay special attention to the Test Reset (TRST
is essential that the JTAG Boundary Scan Test
Access Port (TAP) controller initializes to a known
SS
state whether it will be used or not. If the JTAG
Boundary Scan function will be used, connect a
pulldown resistor between the TRST
the JTAG Boundary Scan function will not be used
(even for board-level testing), connect the TRST
. Also, do not connect the TDI, TDO, and TCK
to V
SS
pins if the TAP Controller will not be used.
Pins identified as NC must not be connected in
pin and VSS. If
the system.
4.4DC Specifications
Table 13. 80960JD DC Characteristics
SymbolParameterMinTypMaxUnitsNotes
V
IL
V
IH
V
OL
V
OH
V
OLP
C
IN
C
OUT
C
CLK
NOTES:
1. Typical is measured with VCC = 5.0V and temperature = 25 °C.
2. Not tested.
Input Low Voltage -0.30.8V
Input High Voltage2.0VCC + 0.3V
Output Low Voltage0.45VIOL = 5 mA
Output High Voltage2.4
V
CC
- 0.5
VI
= -1 mA
OH
= -200 µA
I
OH
Output Ground Bounce< 0.8V(1,2)
Input Capacitance
PGA
PQFP
I/O or Output Capacitance
PGA
PQFP
12
10
12
10
pF
pF
f
CLKIN
f
CLKIN
CLKIN Capacitance
PGA
PQFP
12
10
pFf
CLKIN
= f
= f
= f
) pin. It
MIN
MIN
MIN
pin
(2)
(2)
(2)
24
PRELIMINARY
A80960JD
Table 14. 80960JD ICC Characteristics
SymbolParameterTypMaxUnitsNotes
I
LI1
I
LI2
I
LO
I
Active
CC
(Power Supply)
Active
I
CC
(Thermal)
Test
I
CC
(Power modes)
Input Leakage Current for
each pin except TCK, TDI,
and TMS
TRST
Input Leakage Current for
TCK, TDI, TRST
and TMS
-140-250
Output Leakage Current± 1µA0.4 ≤ V
80960JD-50
80960JD-40
80960JD-33
80960JD-50
80960JD-40
80960JD-33
525
430
365
Reset mode
80960JD-50
80960JD-40
80960JD-33
± 1
640
530
450
510
430
370
µA0 ≤ VIN ≤ V
CC
µAVIN = 0.45V (1)
≤ V
OUT
mA(2,3)
(2,3)
(2,3)
mA(2,4)
(2,4)
(2,4)
(5)
mA
(5)
(5)
CC
Halt mode
80960JD-50
80960JD-40
80960JD-33
ONCE mode
48
41
36
10
(5)
(5)
(5)
(5)
NOTES:
1. These pins have internal pullup devices. Typical leakage current is not tested.
2. Measured with device operating and outputs loaded to the test condition in Figure 8, AC Test Load (pg.
33).
Active (Power Supply) value is provided for selecting your system’s power supply. It is measured
3. I
CC
using one of the worst case instruction mixes with V
tested.
Active (Thermal) value is provided for your system’s thermal management. Typical ICC is measured
4. I
CC
with V
5. I
Halt mode or ONCE mode with V
= 5.0V and temperature = 25° C. This parameter is characterized but not tested.
CC
Test (Power modes) refers to the ICC values that are tested when the 80960JD is in Reset mode,
CC
= 5.25V.
CC
= 5.25V. This parameter is characterized but not
CC
PRELIMINARY
25
80960JDA
4.5AC Specifications
The 80960JD AC timings are based upon device characterization.
Table 15. 80960JD AC Characteristics (50 MHz) (Sheet 1 of 2)
SymbolParameterMinMaxUnitsNotes
INPUT CLOCK TIMINGS
T
F
T
C
T
CS
T
CH
T
CL
T
CR
T
CF
T
OV1
CLKIN Frequency825MHz
CLKIN Period40125ns
CLKIN Period Stability± 250ps(1, 2)
CLKIN High Time16nsMeasured at 1.5 V (1)
CLKIN Low Time16nsMeasured at 1.5 V (1)
CLKIN Rise Time25ns0.8 V to 2.0 V (1)
CLKIN Fall Time5ns2.0 V to 0.8 V (1)
NOTE:See Table 16 on page 28 for note definitions for this table .
Input Setup to CLKIN —
AD31:0, NMI
, XINT7:0
Input Hold from CLKIN —
AD31:0, NMI
, XINT7:0
Input Setup to CLKIN —
RDYRCV
and HOLD
Input Hold from CLKIN —
RDYRCV
and HOLD
Input Setup to CLKIN —
RESET
Input Hold from CLKIN —
RESET
Input Setup to RESET —
, STEST
ONCE
Input Hold from RESET —
, STEST
ONCE
8ns(5)
2ns(5)
9ns(6)
1ns(6)
8ns(7)
2ns(7)
8ns(8)
2ns(8)
26
PRELIMINARY
A80960JD
Table 15. 80960JD AC Characteristics (50 MHz) (Sheet 2 of 2)
SymbolParameterMinMaxUnitsNotes
RELATIVE OUTPUT TIMINGS
T
T
T
LXL
LXA
DXD
ALE/ALE Width
Address Hold from ALE/ALE
Inactive
- 7.5ns
0.5T
C
DT/R Valid to DEN ActiveEqual Loading (9)
BOUNDARY SCAN TEST SIGNAL TIMINGS
T
BSF
T
BSCH
T
BSCL
T
BSCR
T
BSCF
T
BSIS1
T
BSIH1
T
BSOV1
T
BSOF1
T
BSOV2
T
BSOF2
T
BSIS2
T
BSIH2
NOTE:See Table 16 on page 28 for note definitions for this table .
TCK Frequency0.5TF MHz
TCK High Time15nsMeasured at 1.5 V (1)
TCK Low Time15nsMeasured at 1.5 V (1)
TCK Rise Time5ns0.8 V to 2.0 V (1)
TCK Fall Time5ns2.0 V to 0.8 V (1)
Input Setup to TCK — TDI, TMS4ns
Input Hold from TCK — TDI,
Table 16. Note Definitions for Table 15, 80960JD AC Characteristics (50 MHz) (pg. 26)
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than I
designed to be no longer than the valid delay.
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. For asynchronous operation, NMI
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV
and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET
may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE
and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
10. Relative to falling edge of TCK.
refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
. Float delay is not tested, but is
LO
and XINT7:0 must be asserted for a
Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 1 of 3)
SymbolParameterMinMaxUnitsNotes
INPUT CLOCK TIMINGS
T
F
T
C
T
CS
T
CH
T
CL
T
CR
T
CF
CLKIN Frequency820MHz
CLKIN Period50125ns
CLKIN Period Stability±250ps(1, 2)
CLKIN High Time20nsMeasured at
1.5 V (1)
CLKIN Low Time20nsMeasured at
1.5 V (1)
CLKIN Rise Time7ns0.8 V to 2.0
V (1)
CLKIN Fall Time7ns2.0 V to 0.8
V (1)
SYNCHRONOUS OUTPUT TIMINGS
28
T
OV1
Output Valid Delay, Except ALE/ALE
Inactive and DT/R
3.518ns(3)
PRELIMINARY
A80960JD
Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 2 of 3)
HOLD
Input Setup to CLKIN — RESET8ns(7)
Input Hold from CLKIN — RESET2ns(7)
Input Setup to RESET — ONCE, STEST8ns(8 )
Input Hold from RESET — ONCE,
2ns(8)
STEST
RELATIVE OUTPUT TIMINGS
ALE/ALE Width
Address Hold from ALE/ALE InactiveEqual
- 7.5ns
0.5T
C
(9)
Loading (9)
DT/R Valid to DEN ActiveEqual
Loading (9)
BOUNDARY SCAN TEST SIGNAL TIMINGS
TCK Frequency0.5TF MHz
TCK High Time15nsMeasured at
1.5 V (1)
TCK Low Time15nsMeasured at
1.5 V (1)
TCK Rise Time5ns0.8 V to 2.0
V (1)
TCK Fall Time5ns2.0 V to 0.8
V (1)
Input Setup to TCK — TDI, TMS4ns
Input Hold from TCK — TDI, TMS6ns
TDO Valid Delay330ns(1, 10)
TDO Float Delay330ns(1, 10)
PRELIMINARY
29
80960JDA
Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 3 of 3)
SymbolParameterMinMaxUnitsNotes
T
BSOV2
T
BSOF2
T
BSIS2
T
BSIH2
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
3. Inactive ALE/ALE
4. A float condition occurs when the output current becomes less than I
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
6. RDYRCV
7. RESET
8. ONCE
9. Guaranteed by design. May not be 100% tested.
10. Relative to falling edge of TCK.
All Outputs (Non-Test) Valid Delay330ns(1, 10)
All Outputs (Non-Test) Float Delay330ns(1, 10)
Input Setup to TCK — All Inputs (Non-
4ns
Test)
Input Hold from TCK — All Inputs (Non-
6ns
Test)
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
. Float delay is not tested, but is
designed to be no longer than the valid delay.
LO
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. For asynchronous operation, NMI
and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
and STEST must be stable at the rising edge of RESET for proper operation.
30
PRELIMINARY
A80960JD
Table 18. 80960JD AC Characteristics (33 MHz) (Sheet 1 of 2)
SymbolParameterMinMaxUnitsNotes
INPUT CLOCK TIMINGS
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
F
C
CS
CH
CL
CR
CF
OV1
OV2
OF
IS1
IH1
IS2
IH2
IS3
IH3
IS4
IH4
LXL
LXA
DXD
CLKIN Frequency816.67MHz
CLKIN Period60125ns
CLKIN Period Stability± 250ps(1, 2)
CLKIN High Time24nsMeasured at 1.5 V (1)
CLKIN Low Time24nsMeasured at 1.5 V (1)
CLKIN Rise Time8ns0.8 V to 2.0 V (1)
CLKIN Fall Time8ns2.0 V to 0.8 V (1)
SYNCHRONOUS OUTPUT TIMINGS
Output Valid Delay, Except
ALE/ALE
Inactive and DT/R
Output Valid Delay, DT/R0.5TC +
3.519ns(3)
0.5TC + 19ns
3.5
Output Float Delay3.518ns(4)
SYNCHRONOUS INPUT TIMINGS
Input Setup to CLKIN — AD31:0,
, XINT7:0
NMI
Input Hold from CLKIN — AD31:0,
, XINT7:0
NMI
Input Setup to CLKIN — RDYRCV
8ns(5)
2ns(5)
9ns(6)
and HOLD
Input Hold from CLKIN —
RDYRCV
and HOLD
1ns(6)
Input Setup to CLKIN — RESET8ns(7)
Input Hold from CLKIN — RESET2ns(7)
Input Setup to RESET — ONCE,
8ns(8)
STEST
Input Hold from RESET — ONCE,
2ns(8)
STEST
RELATIVE OUTPUT TIMINGS
ALE/ALE Width
Address Hold from ALE/ALE Inac-
tive
- 8ns
0.5T
C
(9)
Equal Loading (9)
DT/R Valid to DEN ActiveEqual Loading (9)
PRELIMINARY
31
80960JDA
Table 18. 80960JD AC Characteristics (33 MHz) (Sheet 2 of 2)
SymbolParameterMinMaxUnitsNotes
BOUNDARY SCAN TEST SIGNAL TIMINGS
T
BSF
T
BSCH
T
BSCL
T
BSCR
T
BSCF
T
BSIS1
T
BSIH1
T
BSOV1
T
BSOF1
T
BSOV2
T
BSOF2
T
BSIS2
T
BSIH2
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
3. Inactive ALE/ALE
4. A float condition occurs when the output current becomes less than I
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
6. RDYRCV
7. RESET
8. ONCE
9. Guaranteed by design. May not be 100% tested.
10. Relative to falling edge of TCK.
TCK Frequency0.5TF MHz
TCK High Time15nsMeasured at 1.5 V (1)
TCK Low Time15nsMeasured at 1.5 V (1)
TCK Rise Time5ns0.8 V to 2.0 V (1)
TCK Fall Time5ns2.0 V to 0.8 V (1)
Input Setup to TCK — TDI, TMS4ns
Input Hold from TCK — TDI, TMS6ns
TDO Valid Delay330ns(1, 10)
TDO Float Delay330ns(1, 10)
All Outputs (Non-Test) Valid Delay330ns(1, 10)
All Outputs (Non-Test) Float Delay330ns(1, 10)
Input Setup to TCK — All Inputs
4ns
(Non-Test)
Input Hold from TCK — All Inputs
6ns
(Non-Test)
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
. Float delay is not tested, but is
designed to be no longer than the valid delay.
LO
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. For asynchronous operation, NMI
and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at
a particular clock edge.
and STEST must be stable at the rising edge of RESET for proper operation.
32
PRELIMINARY
A80960JD
Output Valid Delay (ns) @ 1.5V
4.5.1 AC Test Conditions and Derating Curves
The AC Specifications in Section 4.5, AC Specifications are tested with the 50 pF load indicated in Figure 8.
Figure 9 shows how timings vary with load capacitance; Figure 10 shows how output rise and fall times vary
with load capacitance.
Output Pin
C
= 50 pF for all signals
L
AC Derating Curves
nom +6
nom +4
C
L
Figure 8. AC Test Load
nom +2
nom
nom -2
50100150
CL (pF)
High-to-Low Transitions
Low-to-High Transitions
Figure 9. Output Delay or Hold vs. Load Capacitance
PRELIMINARY
33
80960JDA
Time (ns)
10
2.0V to 0.8V Transitions
8
6
4
2
Figure 10. Rise and Fall Time Derating
4.5.2AC Timing Waveforms
0.8V to 2.0V Transitions
50100150
C
(pF)
L
T
CR
T
CH
T
CF
2.0V
1.5V
0.8V
T
CL
T
C
Figure 11. CLKIN Waveform
34
PRELIMINARY
A80960JD
HOLDA, BSTAT,
CLKIN
AD31:0,
ALE (active),
ALE
(active),
ADS
, A3:2,
WIDTH/HLTD1:0,
DEN
BE3:0,
D/C
, W/R, DEN,
BLAST
, LOCK,
AD31:0,
ALE, ALE
ADS, A3:2,
WIDTH/HLTD1:0,
BE3:0,
D/C
, W/R, DT/R,
, BLAST, LOCK
1.5V
T
OV1
1.5V
FAIL
Figure 12. Output Delay Waveform for T
CLKIN
T
OF
1.5V
OV1
1.5V1.5V
PRELIMINARY
Figure 13. Output Float Waveform for T
OF
35
80960JDA
CLKIN
T
IS1
AD31:0
NMI
XINT7:0
1.5V
Figure 14. Input Setup and Hold Waveform for T
CLKIN
T
IS2
HOLD,
RDYRCV
1.5V
Valid
Valid
T
IH2
1.5V1.5V1.5V
T
IH1
1.5V
IS1
and T
IH1
1.5V1.5V1.5V
36
Figure 15. Input Setup and Hold Waveform for T
IS2
and T
IH2
PRELIMINARY
A80960JD
CLKIN
T
IH3
RESET
Figure 16. Input Setup and Hold Waveform for T
RESET
T
IS4
1.5V1.5V
T
IS3
and T
IS3
T
IH4
IH3
ONCE,
STEST
Figure 17. Input Setup and Hold Waveform for T
PRELIMINARY
Valid
IS4
and T
IH4
37
80960JDA
T
a
CLKIN
T
LXL
ALE
ALE
AD31:0
1.5V
1.5V
Valid
Valid
Figure 18. Relative Timings Waveform for T
T
a
CLKIN
1.5V
Tw/T
d
1.5V1.5V1.5V
1.5V
T
LXA
1.5V
Tw/T
LXL
d
and T
LXA
1.5V1.5V
38
DT/R
DEN
T
OV2
Figure 19. DT/R
Valid
T
DXD
T
OV1
and DEN Timings Waveform
PRELIMINARY
A80960JD
TCK
TMS
TDI
T
BSCR
T
BSCF
T
BSCH
T
BSCL
Figure 20. TCK Waveform
T
BSIS1TBSIH1
1.5V
Valid
2.0V
1.5V
0.8V
1.5V1.5V1.5V
1.5V
Figure 21. Input Setup and Hold Waveforms for T
PRELIMINARY
BSIS1
and T
BSIH1
39
80960JDA
TCK
TDO
1.5V
T
BSOV1
Valid
T
BSOF1
Figure 22. Output Delay and Output Float Waveform for T
TCK
Non-Test
Outputs
1.5V
1.5V
T
BSOV2
1.5V
Valid
T
BSOF2
1.5V1.5V1.5V
BSOV1
AND T
1.5V
BSOF1
40
Figure 23. Output Delay and Output Float Waveform for T
and T
BSOV2
BSOF2
PRELIMINARY
A80960JD
TCK
T
T
BSIS2
Non-Test
Inputs
Figure 24. Input Setup and Hold Waveform for T
1.5V
Valid
BSIH2
1.5V
BSIS2
1.5V1.5V1.5V
and T
BSIH2
PRELIMINARY
41
80960JDA
F_JF030A
5.0BUS FUNCTIONAL WAVEFORMS
Figures 25 through 30 illustrate typical 80960JD bus transactions. Figure 31 depicts the bus arbitration
sequence. Figure 32 illustrates the processor reset sequence from the time power is applied to the device.
Figure 33 illustrates the processor reset sequence when the processor is in operation. Figure 34 illustrates the
processor ONCE sequence from the time power is applied to the device. Figures 35 and 36 also show
accesses on 32-bit buses. Tables 19 through 22 summarize all possible combinations of bus accesses across
8-, 16-, and 32-bit buses according to data alignment.
CLKIN
AD31:0
ALE
ADS
A3:2
BE3:0
WIDTH1:0
D/C
W/R
BLAST
T
aTdTr
D
ADDR
In
1010
TiTiTaTdTrTiT
Invalid
ADDR
i
DATA Out
42
DT/R
DEN
RDYRCV
Figure 25. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
PRELIMINARY
A80960JD
CLKIN
AD31:0
ALE
ADS
A3:2
BE3:0
WIDTH1:0
D/C
W/R
TaTdTdTrTaTdTdTdT
DD
ADDR
InInOutOutOutOut
00 or 1001 or 1100011011
1 0
DATA DATA DATADATA
ADDR
d
1 0
T
r
BLAST
DT/R
DEN
RDYRCV
Figure 26. Burst Read and Write Transactions Without Wait States, 32-Bit Bus
PRELIMINARY
43
80960JDA
CLKIN
AD31:0
ALE
ADS
A3:2
BE3:0
WIDTH1:0
D/C
W/R
TaTwTwTdTwTdTwTdTwTdT
ADDR
DATA
OutOut
0 0
DATADATADATA
0 11 01 1
1 0
Out
Out
r
44
BLAST
DT/R
DEN
RDYRCV
F_JF032A
Figure 27. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus
PRELIMINARY
A80960JD
CLKIN
AD31:0
ALE
ADS
A3:2
BE1
/A1
BE0/A0
WIDTH1:0
D/C
W/R
TaTdTdTrTaTdTdTdT
D
ADDR
D
InInOutOut
00,01,10 or 1100,01,10 or 11
00
01 or
11
00 or 10
ADDR
DATA DATA
DATA
Out
00011011
00
T
d
r
DATA
Out
BLAST
DT/R
DEN
RDYRCV
Figure 28. Burst Read and Write Transactions Without Wait States, 8-Bit Bus
PRELIMINARY
F_JF033A
45
80960JDA
CLKIN
AD31:0
ALE
ADS
A3:2
BE1/A1
BE3
/BHE
BE0/BLE
WIDTH1:0
D/C
TwTdTdTrTrTaTwTdT
T
a
D
ADDR
00,01,10, or 1100,01,10, or 11
0
D
In
1
0101
ADDR
DATADATA
OutOutIn
01
T
d
r
46
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF034A
Figure 29. Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus
PRELIMINARY
A80960JD
CLKIN
AD31:0
ALE
ADS
A3:2
BE3:0
WIDTH1:0
D/C
W/R
TaTdTrTaTdTrTaT
D
AAA
In
00000110
11 0 100 1 1
D
A
In
0 0 0 0
1 0
Valid
TrTaTdT
d
D
In
1 1 1 0
r
D
In
BLAST
DT/R
DEN
RDYRCV
Figure 30. Bus Transactions Generated by Double Word Read Bus Request,
Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian
PRELIMINARY
47
80960JDA
the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.
Ti or T
∼
Valid
∼
∼
∼
∼
∼
∼
∼
(Note)
∼
∼
CLKIN
Outputs:
AD31:0,
ALE, ALE
ADS
WIDTH/HLTD1:0,
DT/R,
BLAST
NOTE: HOLD is sampled on the rising edge of CLKIN. The processor asserts HOLDA to grant the bus on the
same edge in which it recognizes HOLD if the last state was T
D/C
, LOCK
HOLDA
, A3:2,
BE3:0,
, W/R,
DEN,
HOLD
,
Figure 31. HOLD/HOLDA Waveform For Bus Arbitration
T
r
h
T
h
∼
∼
∼
∼
∼
∼
∼
∼
or the last Tr of a bus transaction. Similarly,
i
Ti or T
a
Valid
48
PRELIMINARY
A80960JD
CLKIN
ALE, ADS,
ALE,W/R,
RESET
LOCK/
STEST
V
CC
DT/R
FAIL
First
Bus
Activity
Valid
(Output)
ONCE
AD31:0, A3:2,D/C
WIDTH/HLTD1:0
(Note 1)
Idle (Note 2)
HOLD
Valid Input (Note 3)
BE3:0, DEN,
BLAST
Valid Output (Note 3)
HOLDA
V
10,000 CLKIN periods, for PLL stabilization.
CC
and CLKIN stable to RESET High, minimum
Built-in self-test, approximately
207,000 CLKIN periods
(if selected)
(Input)
1. The processor asserts FAIL during built-in self-test. If self- test passes, the FAIL pin is deasserted.The processor also asserts FAIL
during the bus confidence test. If the bus confidence test passes, FAIL is deasserted and the processor begins user program execution.
Notes:
2. If the processor fails built-in self-test, it initiates one dummy load bus access. The load address indicates the point of self-test failure.
3. Since the bus is idle, hold requests are honored during reset and built-in self-test.
∼
∼
∼
∼∼∼
∼
∼
∼
∼∼∼
∼
∼
∼
∼∼∼
∼
∼
∼∼∼
∼
∼
∼
∼
∼∼∼
∼
∼
∼∼∼
∼
∼
∼
∼∼∼∼∼∼∼
∼
∼∼∼
∼
∼
∼∼∼
∼
∼
∼
∼
∼∼∼
∼∼∼
∼∼∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼∼∼
∼∼∼
∼∼∼
∼∼∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
Figure 32. Cold Reset Waveform
∼
∼
∼
PRELIMINARY
∼
∼
∼
∼
∼
∼
∼
49
80960JDA
Maximum RESET Low to Reset State
4 CLKIN Cycles
CLKIN
AD31:0, A3:2, D/C
STEST
RESET
RESET High to First Bus
Minimum RESET Low Time
15 CLKIN Cycles
HOLDA
Valid
ALE, ADS, BE3:0,
DEN, BLAST
ALE, W/R,DT/R, BSTAT,
WIDTH/HLTD1:0
FAIL
HOLD
LOCK/ONCE
Activity, 46 CLKIN Cycles
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼∼∼
∼
∼∼∼
∼∼∼
∼
∼
∼∼∼
∼
∼
∼
∼
∼
∼∼∼
∼
∼
∼
∼
∼∼∼
∼
∼
∼
∼
∼∼∼
∼
∼
∼
∼∼∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
Figure 33. Warm Reset Waveform
50
PRELIMINARY
A80960JD
CLKIN
ALE, ADS,
ALE,W/R,
RESET
LOCK/
V
CC
DT/R, WIDTH/HLTD1:0
FAIL
ONCE
AD31:0, A3:2,
D/C
HOLD
BE3:0, DEN, BLAST
HOLDA
(Input)
minimum 10,000 CLKIN periods, for PLL
V
CC
and CLKIN stable to RESET High,
(Note 1)
1. ONCE mode may be entered prior to the rising edge of RESET: ONCE input is not latched until the rising edge of RESET.
NOTES:
CLKIN may not be allowed to float.
STEST
2. The ONCE input may be removed after the processor enters ONCE Mode.
stabilization.
It must be driven high or low or continue to run.
∼
∼
∼∼∼
∼
∼
∼
∼
∼
∼
∼∼∼
∼∼∼
∼
∼
∼
∼
∼∼∼
∼
∼∼∼
∼
∼
∼
∼
∼
∼
∼∼∼
∼∼∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼∼∼
∼
∼
∼
∼
∼∼∼
∼
∼
∼
∼∼∼
∼
∼
∼
∼
∼
∼
∼∼∼
∼
∼∼∼
∼
∼
∼∼∼
∼
∼
∼
∼
∼
∼∼∼∼∼
∼∼∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
Figure 34. Entering the ONCE State
PRELIMINARY
51
80960JDA
Table 19. Natural Boundaries for Load and Store Accesses
• n burst(s) of 4 bytes• n burst(s) of 2 short words• n word access(es )
Accesses on 16 Bit Bus
(WIDTH1:0=01)
burst of 2 short words
• case n=2:
burst of 4 short words
• case n=3:
burst of 4 short words
burst of 2 short words
• case n=4:
2 bursts of 4 short words
• byte access
• short-word access
• n-1 burst(s) of 2 short words
• byte access
• short-word access
• n-1 burst(s) of 2 short words
• short-word access
• byte access
• n-1 burst(s) of 2 short words
• short-word access
• byte access
Accesses on 32 Bit
Bus (WIDTH1:0=10)
• burst of n word(s)
• byte access
• short-word access
• n-1 word access(es)
• byte access
• short-word access
• n-1 word access(es)
• short-word access
• byte access
• n-1 word access(es)
• short-word access
• byte access
PRELIMINARY
53
80960JDA
Byte Offset
Word Offset
Short-Word
Load/Store
Word
Load/Store
04812162024
0123456
Short Access (Aligned)
Byte, Byte Accesses
Short Access (Aligned)
Byte, Byte Accesses
Word Access (Aligned)
Byte, Short, Byte, Accesses
Short, Short Accesses
Byte, Short, Byte Accesses
One Double-Word Burst (Aligned)
Byte, Short, Word, Byte Accesses
54
Double-Word
Load/Store
Short, Word, Short Accesses
Byte, Word, Short, Byte Accesses
Word, Word Accesses
One Double-Word
Burst (Aligned)
Figure 35. Summary of Aligned and Unaligned Accesses (32-Bit Bus)
PRELIMINARY
A80960JD
Byte Offset
Word Offset
Triple-Word
Load/Store
Quad-Word
Load/Store
04812162024
0123456
One Three-Word
Burst (Aligned)
Byte, Short, Word,
Word, Byte Accesses
Short, Word, Word,
Short Accesses
Byte, Word, Word,
Short, Byte Accesses
Word, Word,
Word Accesses
Word, Word,
Word Accesses
One Four-Word
Burst (Aligned)
Byte, Short, Word, Word,
Word, Byte Accesses
Short, Word, Word, Word,
Short Accesses
Byte, Word, Word, Word,
Short, Byte Accesses
Word,
Word,
Word
Accesses
Figure 36. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)
PRELIMINARY
Word, Word, Word,
Word Accesses
Word,
Word,
Word,
Word,
Accesses
55
80960JDA
6.0DEVICE IDENTIFICATION
80960JD processors may be identified electrically according to device type and stepping (see Table 23). The
32-bit identifier is accessible in three ways:
• Upon reset, the identifier is placed into the g0 register.
• The identifier may be accessed from supervisor mode at any time by reading the DEVICEID register at
address FF008710H.
• The IEEE Standard 1149.1 Test Access Port may select the DEVICE ID register through the IDCODE
instruction.
The device and stepping letter is also printed on the top side of the product package.
Table 23. 80960JD Die and Stepping Reference
Device and
Stepping
Version
Number
Part NumberManufacturerX
Complete ID
(Hex)
80960JD A, A200001000 1000 0010 00000000 0001 001108820013
NOTE: This data sheet applies to the 80960JD A and 80960JD A2 steppings.
7.0REVISION HISTORY
This data sheet supersedes revision 272596-001. Table 24 indicates significant changes since the previous
revision.
Table 24. Data Sheet Version -001 to -002 Revision History (Sheet 1 of 2)
Table 13, 80960JD DC Characteristics (pg. 24) Removed Icc characteristics. Added V
ground bounce) specification
Table 14, 80960JD ICC Characteristics (pg.
25)
New table for comprehensible Icc characteristics.
Added Icc’s for reset mode. Halt Icc for: 80960JD-50
OLP
(output
(max) improved from 56 mA to 48 mA, 80960JD-40
(max) improved from 44 mA to 41mA. ONCE Icc
Improved from 30 mA to 10 mA.
Section 4.5, AC Specifications (pg. 26)Grouped AC Specifications tables by frequency. Added