Intel 80960HT, 80960HD, 80960HA User Manual

80960HA/HD/HT 32-Bit High-Performance
Superscalar Pr ocessor

Datasheet

Product Features

■ 32-Bit Parallel Architecture

—Load/Store Architecture
—Sixteen 32-Bit Global Registers
—Sixteen 32-Bit Local Registers
—1.28 Gbyte Internal Bandwidth

(80 MHz)

—On-Chip Register Cache

■ Processor Core Clock

—80960HA is 1x Bus Clock
—80960HD is 2x Bus Clock
—80960HT is 3x Bus Clock

■ Binary Compatible with Other 80960

Processors

■ Issue Up To 150 Million Instructions per

Second

■ High-Performance On-Chip Storage

—16 Kbyte Four-Way Set-Associative

Instruction Cache

—8 Kbyte Four-Way Set-Associative Data

Cache

—2 Kbyte General Purpose RAM

■ Separate 128-Bit Internal Paths For

Instructions/Data

■ 3.3 V Supply Voltage

—5 V Tolerant Inputs
—TTL Compatible Outputs

■ Guarded Memory Unit

—Provides Memory Protection
—User/Supervisor Read/Write/Execute

■ 32-Bit Demultiplexed Burst Bus

—Per-Byte Parity Generation/Checking
—Address Pipel ining Option
—Fully Programmable W ait S tate Generator
—Supports 8-, 16- or 32-Bit Bus Widths
—160 Mbyte/s External Bandwidth

(40 MHz)

■ High-Speed Interrupt Controller

—Up to 240 External Interrupts
—31 Fully Programmable Priori t ie s
—Separate, Non-maskable Interrupt Pin

■ Dual On-Chip 32-Bit Timers

—Auto Reload Capability and One-Shot
—CLKIN Prescaling, divided by 1, 2, 4 or 8
—JTAG Support - IEEE 1149.1 Compliant

Order Number: 272495-008

September 2002

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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor may contain design defects or errors known as errata which may cause the

product to deviate from published specifications. Current characterized errata are available on request.
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2 Datasheet

Contents

Contents

1.0 About This Document ...................................................................................................................9

2.0 Intel 80960Hx Processor...............................................................................................................9

2.1 The i960

®

Processor Family...............................................................................................10

2.2 Key 80960Hx Features.......................................................................................................10

2.2.1 Execution Architecture...........................................................................................10

2.2.2 Pipelined, Burst Bus ..............................................................................................10

2.2.3 On-Chip Caches and Data RAM.............................................. ....... ...... ....... ...... ....11

2.2.4 Priority Interrupt Controller.....................................................................................11

2.2.5 Guarded Memory Unit ...........................................................................................11

2.2.6 Dual Programmable Timers...................................................................................12

2.2.7 Processor Self Test ...............................................................................................12

2.3 Instruction Set Summary ....................................................................................................13

3.0 Package Information ...................................................................................................................14

3.1 Pin Descriptions..................................................................................................................15

3.2 80960Hx Mechanical Data..................................................................................................20

3.2.1 80960Hx PGA Pinout.............................................................................................20

3.2.2 80960Hx PQ4 Pinout.............................................................................................26

3.3 Package Thermal Specifications ........................................................................................31

3.4 Heat Sink Adhesives...........................................................................................................34

3.5 PowerQuad4 Plastic Package ............................................................................................34

3.6 Stepping Register Information............................................................................................34

3.7 Sources for Accessories .....................................................................................................36

4.0 Electrical Specifications.............................................................................................................37

4.1 Absolute Maximum Ratings................................................................................................37

4.2 Operating Conditions..........................................................................................................37

4.3 Recommended Connections ..............................................................................................38

4.4 VCC5 Pin Requirements (V

DIFF

) ........................................................................................38

4.5 VCCPLL Pin Requirements ................................................................................................39

4.6 DC Specifications ...............................................................................................................40

4.7 AC Specifications ..... .......................................................... ...... ....... ...... ....... ...... ....... ...... ....4 2

4.7.1 AC Test Conditions................................................................................................45

4.8 AC Timing Waveforms....................... ...... ....... ...... ...... ....... ...... ....... ...... ..............................46

5.0 Bus Waveforms ...........................................................................................................................54

5.1 80960Hx Boundary Scan Chain .........................................................................................84

5.2 Boundary Scan Description Language Example ................................................................88

Figures

1 80960Hx Block Diagram...............................................................................................................9

2 80960Hx 168-Pin PGA Pinout—View from Top (Pins Facing Down)........... ....... ...... ....... ...... ....20

3 80960Hx 168-Pin PGA Pinout—View from Bottom (Pins Facing Up) ........................................21

4 80960Hx 208-Pin PQ4 Pinout.....................................................................................................26

5 Measuring 80960Hx PGA Case Temperature............................................................................31

6 80960Hx Device Identification Register......................................................................................34

Datasheet 3

Contents

7 VCC5 Current-Limiting Resistor.................................................................................................38

8 AC Test Load............... ....... ...... ....... ...... ....... ...... ....... .......................................................... ...... .45

9 CLKIN Waveform........................................................................................................................46

10 Output Delay Waveform .............................................................................................................46

11 Output Delay Waveform .............................................................................................................46

12 Output Float Waveform ..............................................................................................................47

13 Input Setup and Hold Waveform ................................................................................................47

14 NMI, XINT7:0 Input Setup and Hold Waveform..........................................................................47

15 Hold Acknowledge Timings........................................................................................................48

16 Bus Backoff (BOFF) Timings......................................................................................................48

17 TCK Waveform...................................... ....... ...... ....... ...... ...... ....... ...... ....... ...... ...........................49

18 Input Setup and Hold Waveforms for T

BSIS1

and TBSIH1..........................................................49

19 Output Delay and Output Float for TBSOV1 and TBSOF1 ........................................................50

20 Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 .......................................50

21 Input Setup and Hold Waveform for TBSIS2 and TBSIH2 .........................................................50

22 Rise and Fall Time Derating at 85 °C and Minimum VCC..........................................................51

23 I

CC

Active (Power Supply) vs. Frequency...................................................................................51

24 ICC Active (Thermal) vs. Frequency............................................................................................52

25 Output Delay or Hold vs. Load Capacitance ..............................................................................52

26 Output Delay vs. Temperature ................................................................................................... 53

27 Output Hold Times vs. Temperature ..........................................................................................53

28 Output Delay vs. VCC ................................................................................................................53

29 Cold Reset Waveform ................................................................................................................54

30 Warm Reset Waveform ..............................................................................................................55

31 Entering ONCE Mode.................................................................................................................56

32 Non-Burst, Non-Pipelined Requests without Wait States...........................................................57

33 Non-Burst, Non-Pipelined Read Request with Wait States ........................................................58

34 Non-Burst, Non-Pipelined Write Request with Wait States ........................................................59

35 Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus........................................60

36 Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus.............................................61

37 Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus ........................................62

38 Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus .............................................63

39 Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus.............................................64

40 Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus...............................................65

41 Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus ........................................66

42 Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus .............................................67

43 Burst, Pipelined Read Request without Wait States, 32-Bit Bus................................................68

44 Burst, Pipelined Read Request with Wait States, 32-Bit Bus.....................................................69

45 Burst, Pipelined Read Request with Wait States, 8-Bit Bus .......................................................70

46 Burst, Pipelined Read Request with Wait States, 16-Bit Bus.....................................................71

47 Using External READY...............................................................................................................72

48 Terminating a Burst with BTERM...............................................................................................73

49 BREQ and BSTALL Operation...................................................................................................74

50 BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle.........................75

51 HOLD Functional Timing ............................................................................................................76

52 LOCK Delays HOLDA Timing.....................................................................................................77

53 FAIL Functional Timing...............................................................................................................77

54 A Summary of Aligned and Unaligned Transfers for 32-Bit Regions..........................................78

55 A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued)......................79

56 A Summary of Aligned and Unaligned Transfers for 16-Bit Bus.................................................80

4 Datasheet

Contents

57 A Summary of Aligned and Unaligned Transfers for 8-Bit Bus...................................................81

58 Idle Bus Operation......................................................................................................................82

59 Bus States ..................................................................................................................................83

Tables

1 80960Hx Product Description.......................................................................................................9

2 Fail Codes For BIST (bit 7 = 1)...................................................................................................12

3 Remaining Fail Codes (bit 7 = 0)................................................................................................12

4 80960Hx Instruction Set .............................................................................................................13

5 80960HA/HD/HT Package Types and Speeds...........................................................................14

6 Pin Description Nomenclature....................................................................................................15

7 80960Hx Processor Family Pin Descriptions..............................................................................16

8 80960Hx 168-Pin PGA Pinout—Signal Name Order..................................................................22

9 80960Hx 168-Pin PGA Pinout—Pin Number Order ...................................................................24

10 80960Hx PQ4 Pinout—Signal Name Order................................................................................27

11 80960Hx PQ4 Pinout—Pin Number Order.................................................................................29

13 80960Hx 168-Pin PGA Package Thermal Characteristics .........................................................32

12 Maximum T

A

at Various Airflows in °C (PGA Package Only).....................................................32

15 80960Hx 208-Pin PQ4 Package Thermal Characteristics..........................................................33

14 Maximum T

A

at Various Airflows in °C (PQ4 Package Only)......................................................33

17 80960Hx Device ID Model Types...............................................................................................35

18 Device ID Version Numbers for Different Steppings...................................................................35

16 Fields of 80960Hx Device ID......................................................................................................35

19 Absolute Maximum Ratings........................................................................................................37

20 Operating Conditions..................................................................................................................37

21 V

DIFF

Specification for Dual Power Supply Requirements (3.3 V, 5 V) ......................................39

22 80960Hx DC Characteristics......................................................................................................40

23 80960Hx AC Characteristics.......................................................................................................42

25 80960Hx Boundary Scan Test Signal Timings ...........................................................................44

24 AC Characteristics Notes............................................................................................................44

26 80960Hx Boundary Scan Chain ............................. ...... ...... ....... .................................................84

Datasheet 5

Contents

Revision History

Date Revision History

September 2002 008

Formatted the datasheet in a new template.
In “32-Bit Parallel Architecture” on page 1:

• Removed operating frequency of 16/32 (bus/core) from 80960HD.

• Removed operating frequency of 20/60 (bus/core) from 80960HT.

In

Table 5 “80960HA/HD/HT Package Types and Speeds” on page14:

• Removed core speed of 32 MHz and bus speed of 16 MHz, and order
number A80960HD32-S-L2GG from the 168L PGA package, 80960HD
device.

• Removed core speed of 60 MHz and bus speed of 20 MHz, and order
number A80960HT60 from the 168L PGA package, 80960HT device.

• Removed core speed of 32 MHz and bus speed of 16 MHz, and order
number FC80960HD32-S-L2GL from the 208L PQFP package,
80960HD device.

• Removed core speed of 60 MHz and bus speed of 20 MHz, and order
number FC80960HT60-S-L2G2 from the 208L PQFP package,
80960HT device.

July 1998 007

In

“32-Bit Parallel Architecture” on page 1:

• Revised 1.2 Gbyte Internal Bandwidth (75 MHz) to 1.28 Gbyte Internal
Bandwidth (80 MHz).

In

Section 3.0, “Package Information” on page 14:

• Added paragraph two and

Table 5 “80960HA/HD/HT Package Types

and Speeds” on page 14.

In

Table 7 “80960Hx Processor Family Pin Descriptions” on page 16:

• Corrected minor typeset and spacing errors.

• BREQ; Revised description.

• ONCE

; last sentence, changed ‘low’ to ‘high’.

• TDI and TMS; removed last sentence stating, “Pull this pin low when
not in use.”

In

Figure 2 “80960Hx 168-Pin PGA Pinout—View from Top (Pins Facing

Down)” on page 20:

• Added insert package marking diagram.

In

Figure 4 “80960Hx 208-Pin PQ4 Pinout” on page 26:

• Added insert package marking diagram.

In

Table 10 “80960Hx PQ4 Pinout—Signal Name Order” on page 27:

• Corrected TDO (‘O’ was zero) and revised alphabetical ordering.

In

Table 11 “80960Hx PQ4 Pinout—Pin Number Order” on page 29:

• Corrected TDO (‘O’ was zero) and revised alphabetical ordering.

In

Section 4.1, “Absolute Maximum Ratings” on page 37:

• Revised V

CC

to VCC5 for Voltage on Other Pins with respect to VSS.

In

Section 4.5, “VCCPLL Pin Requirements” on page 39:

• Added section.

In

Table 22 “80960Hx DC Characteristics” on page 40:

• Added footnote (1) to I

LO

notes column for TDO pin.

• Added footnote (10) to CIN, C

OUT

and C

I/O

pin.

6 Datasheet

July 1998

(continued)

007

(continued)

In

Table 23 “80960Hx AC Characteristics” on page 42:

• Added overbars where required.

• Modified T

DVNH

to list separate specifications for 3.3 V and 5 V.

• Modified T

OV2

, T

OH2

and T

TVEL

to reflect specific 80960HA, 80960HD

and 80960HT values.

In

Figure 23 “ICC Active (Power Supply) vs. Frequency” on page 51:

• Changed ‘5’ to ‘0’ on the CLKIN Frequency axis.

In

Figure 49 “BREQ and BSTALL Operation” on page 74:

• Added figure and following text.

August 1997 006 Fixed several font and format issues.

Date Revision History

Contents

Datasheet 7

Contents

This page intentionally left blank.

8 Datasheet

Datasheet 9

1.0 About This Document

This document describes the parametric performance of Intel’s 80960Hx embedded superscalar
microprocessors. Detailed descriptions for functional topics, other than parametric performance,
are published in the i960

®

Hx Microprocessor User’s Guide (272484).

In this document, ‘80960Hx’ and ‘i960 Hx proce ssor’ refer to the products described in

Table 1.

Throughout this document, information that is specific to each is clearly indicated.

2.0 Intel 80960Hx Processor

The Intel 80960Hx processor provides new performance levels while maintaining backward
compatibility (pin1 and software) with the i960 CA/CF processor. This newest member of the
family of i960 32-bit, RISC-style, embedded processors allows customers to create scalable
designs that meet multiple price and performance points. This is accomplished by pro vidin g
processors that may run at the bus speed or faster using Intel’s clock multiplying technology
(see

Table 1). The 80960Hx core is capable of issuing 150 million instructions per seco nd, using a

sophisticated instruction scheduler that allows the processor to sustain a throughput of two
instructions every core clock, with a peak performance of three instructions per clock. The
80960Hx-series comprises three processo rs, which dif fer in the ratio of core clock s peed to external
bus speed.

Figure 1. 80960Hx Block Diagram

Execution Unit

Programmable

Bus Controll er

Bus Request Queues

Six-Port Register File

32-bit Base Bus

Instruction Cache

128-Bit Cache Bus

Instruction Prefetch Queue

Interrupt Controller

Control

Address

Data

Memory-Side
Machine Bus

Register-Side

Machine Bus

Memory Region Configuration

Multiply/Divide Unit

Interrupt

Port

Address Generation Unit

Data Cache

16 Kbyte, Four-Way Set-Associative

8 Kbyte, Four-Way Set-Associativ e

Guarded Memory Unit

Timers

JTAG Port

Parallel Instruction Scheduler

Data RAM - 2 Kbyte

Register Cache - 5 to 15 sets

64-bit SRC1 Bus
64-bit SRC2 Bus

64-bit DST Bus

128-bit Load Bus

128-bit Store Bus

1. The 80960Hx is not “drop-in” compatible in an 80960Cx-based system. Customers may design systems that accept either 80960Hx or Cx
processors.

Table 1. 80960Hx Product Description

Product Core Voltage Operating Frequency (bus/core)

80960HA 1x 3.3 V

†

25/25, 33/33, 40/40

80960HD 2x 3.3 V

†

25/50, 33/66, 40/80

80960HT 3x 3.3 V

†

25/75

† Processor inputs are 5 V tolerant.

80960HA/HD/HT

80960HA/HD/HT

10 Datasheet

In addition to expanded clock frequency op tions, the 8096 0Hx provi des essential en hancements for
an emerging class of high-performance embedded applications. Features include a larger
instruction cache, data cache, and data RAM than any other 80960 processor to date. It also boasts
a 32-bit demultiplexed and pipelined burst bus, fast interrupt mechanism, guarded memory unit,
wait state generator, dual programmable timers , ONCE and IEEE 1149.1-compliant boundary scan
test and debug support, and new instructions.

2.1 The i960® Processor Family

The i960® processor family is a 32-bit RISC architecture created by Intel to serve the needs of
embedded applications. The embedded market includes applications as diverse as industrial
automation, avionics, image processing, graphics and communications.

Because all members of the i960 processor family share a common core architecture, i960
applications are code-compatible. Each new processor in the family adds its own special set of
functions to the core to satisfy the needs of a specific application or range of applications in the
embedded market.

2.2 Key 80960Hx Features

2.2.1 Execution Architecture

Independent instruction paths inside the processor allow the execution of multiple, out-of-sequence
instructions per clock. Register and resource scoreboarding interlocks maintain the logical integrity
of sequential instructions that are being executed in parallel. To sustain execution of multiple
instructions in each clock cycle, the processor decodes multiple instructions in parallel and
simultaneously issues these instructions to parallel processing units. The various processing units
are then able to independently access instruction operands in parallel from a common register set.

Local Register Cache integrated on-chip provides automatic register management on call /return
instructions. Upon a call instruction, the processor allocates a set of local registers for the called
procedure, then stores the registers for the previous procedure in the on-chip register cache. As
additional procedures are called, the cache stores the associated registers such that the most recently
called procedure is the first available by the next return (ret) instruction. The processor may store up
to fifteen register sets, after which the oldest sets are stored (spilled) into external memory.

The 80960Hx supports the 80960 architecturally-defined branch prediction mechanism. This
allows many branches to execute with no pipeline break. With the 80960Hx’s efficient pipeline, a
branch may take as few as zero clocks to execute. The maximu m penalty for an inco rrect prediction
is two core clocks.

2.2.2 Pipelined, Burst Bus

A 32-bit high performance bus controller interfaces the 80960Hx core to the external memory and
peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at a
40 MHz external bus clock frequency). A key advantage of this design is its versatility. The user
may independently program the physical and logical attributes of system memory. Physical
attributes include wait state profile, bus width, and parity. Logical attributes include cacheability
and Big or Little Endian byte order. Internally programmable wait states and 16 separately
configurable physical memory regions allow the processor to interface with a variety of memory

Datasheet 11

subsystems with minimum system complexity . To reduce the effect of wait states, the bus design is
decoupled from the core. This lets the processor execute instructions while the bus performs
memory accesses independently.

The Bus Controller’s key features include:

• Demultiplexed, Burst Bus to support most efficient DRAM access modes

• Address Pipelining to reduce memory cost while m a intaining performance

• 32-, 16- and 8-bit modes to facilitate I/O interfacing

• Full internal wait state generation to reduce sys tem cost

• Little and Big Endian support

• Unaligned Access support implemented in hardware

• Three-deep request queue to decouple the bus from the core

• Independent physical and logical address space characteristics

2.2.3 On-Chip Caches and Data RAM

As shown in Figure 1, the 80960Hx provides generous on-chip cache and storage features to
decouple CPU execution from the external bus. The processor includes a 16 Kbyte instruction
cache, an 8 Kbyte data cache and 2 Kbytes of Data RAM. The caches are organized as 4-way set
associative. Stores that hit the data cache are written through to memory. The data cache performs
write allocation on cache misses. A fifteen-set stack frame cache allows the processor to rapidly
allocate and deallocate local registers. All of the on-chip RAM sustains a 4-word (128-bit) access
every clock cycle.

2.2.4 Priority Interrupt Controller

The interrupt unit provides the mechanism for the low latency and high throughput interrupt
service essential for embedded applications. A priority interrupt controller provides full
programmability of 240 interrupt sources with a typical interrupt task switch (latency) time of 17
core clocks. The controller supports 31 priority levels. I nterrupts are prior itized and signaled within
10 core clocks of the request. When the interrupt has a higher priority than the processor priority,
the context switch to the interrupt routine would typically complete in another seven bus clocks.

External agents post interrupts through the 8-bit external interrupt port. The Interrupt unit also
handles the two internal sources from the Timers. Interrupts may be level- or edge-triggered.

2.2.5 Guarded Memory Unit

The Guarded Memory Unit (GMU) provides memory protection without the address transl ation
found in Memory Management Units. The GMU contains two memory protection schemes: o ne
prevents illegal memory accesses, the other detects memory access violations. Both signal a fault
to the processor. The programmable protection modes are: user read, write or execute; and
supervisor read, write or execute.

80960HA/HD/HT

80960HA/HD/HT

12 Datasheet

2.2.6 Dual Programmable Timers

The processor provides two independent 32-bit timers, with four programmable clock rates. The
user configures the timers through the Timer Unit registers. These registers are memory-mapped
within the 80960Hx, addressable on 32-bit boundaries. The timers have a single-shot mode and
auto-reload capabilities for continuous operation. Each timer has an independent inte rrupt req ues t
to the processor’s interrupt controller.

2.2.7 Processor Self Test

When a system error is detected, the FAIL pin is asserted, a fail code message is driven onto the
address bus, and the processor stops execution at the point of failure. The only way to resume
normal operation is to perform a RESET operation. Because System Error generation may occur
sometime after the bus confidence test and even after initialization during normal processor
operation, the FAIL

pin is HIGH (logic “1”) before the detection of a System Error.

The processor uses only one read bus-transactio n to signal the fail code mes sage; the addr ess of the
bus transaction is the fail code itself. The fail code is of the form: 0xfeffffnn; bits 6 to 0 contain a
mask recording the possible failures. Bit 7, when set to 1, indicates that the mask contains failures
from the internal Built-In Self-Test (BIST); when 0, the mask indicates other failures.

Ignore reserved bits 0 and 1. Also ignore bits 5 and 6 when bit 7 is clear (=0).
The mask is show n in

Table 2 and Table 3.

Table 2. Fail Codes For BIST (bit 7 = 1)

Bit When Set

6 On-chip Data-RAM failure detected by BIST.
5 Internal Microcode ROM failure detected by BIST.
4 Instruction cache failure detected by BIST.
3 Data cache failure detected by BIST.
2 Local-register cache or processor core failure detected by BIST.
1 Reserved. Always zero.
0 Reserved. Always zero.

Table 3. Remaining Fail Codes (bit 7 = 0)

Bit When Set

6 Reserved. Always one.
5 Reserved. Always one.
4 A data structure within the IMI is not aligned to a word boundary.
3 A System Error during normal operation has occurred.
2 The Bus Confidence test has failed.
1 Reserved. Always zero.
0 Reserved. Always zero.

Datasheet 13

2.3 Instruction Set Summary

Table 4 summarizes the 80960Hx instruction set by logical groupings.

Table 4. 80960Hx Instruction Set

Data Movement Arithmetic Logical Bit / Bit Field / Byte

Load
Store
Move
Load Address
Conditional Select

2

Add
Subtract
Multiply
Divide
Remainder
Modulo
Shift
Extended Shift
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
Rotate
Conditional Add

2

Conditional Subtract

2

And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Nor
Exclusive Nor
Not
Nand

Set Bit
Clear Bit
Not Bit
Alter Bit
Scan For Bit
Span Ove r Bit
Extract
Modify
Scan Byte for Equal
Byte Swap

2

Comparison Branch Call/Return Fault

Compare
Conditional Compare
Compare and Increment
Compare and Decrement
Compare Byte

2

Compare Short

2

Test Condition Code
Check Bit

Unconditional Branch
Conditional Branch
Compare and Branch

Call
Call Extended
Call System
Return
Branch and Link

Conditional Fault
Synchronize Faults

Debug Processor Mgmt Atomic Cache Control

Modify Trace Controls
Mark
Force Mark

Flush Local Registers
Modify Arithmetic Controls
Modify Process Controls
Interrupt Enable/ Disable

1, 2

System Control

1

Atomic Add
Atomic Modify

Instruction Cache
Control

1, 2

Data Cache Control

1, 2

NOTES:

1. 80960Hx extensions to the 80960 core instruction set.

2. 80960Hx extensions to the 80960Cx instruction set.

80960HA/HD/HT

80960HA/HD/HT

14 Datasheet

3.0 Package Information

This section describes the pins, pinouts and ther mal characteri s tics for the 80 960 H x in the 168- pi n
ceramic Pin Grid Array (PGA) package, 208-pin PowerQuad2* (PQ4). For complete package
specifications and information, see the Intel Packaging Handbook (Order# 24080 0).

The 80960HA/HD/HT is offered with eight speeds and two package types (

Table 5). Both the

168-pin ceramic Pin Grid A rr ay (PGA) and the 208-pin Pow er Qu ad2 * (P Q4) dev i ces are specified
for operation at V

CC

= 3.3 V ± 0.15 V over a case temperature range of 0 °C to 85 °C.

Table 5. 80960HA/HD/HT Package Types and Speeds

Package/Name Device

Core Speed

(MHz)

Bus Speed

(MHz)

Order #

168L PGA

80960HA

25 A80960HA25 S L2GX
33 A80960HA33 S L2GY
40 A80960HA40 S L2GZ

80960HD

50 25 A80960HD50 S L2GH
66 33 A80960HD66 S L2GJ
80 40 A80960HD80 S L2GK

80960HT 75 25 A80960HT75 S L2GP

208L PQFP

(also known as PQ4)

80960HA

25 FC80960HA25 S L2GU
33 FC80960HA33 S L2GV
40 FC80960HA40 S L2GW

80960HD

50 25 FC80960HD50 S L2GM
66 33 FC80960HD66 S L2GN
80 40 FC80960HD80 S L2LZ

80960HT 75 25 FC80960HT75 S L2GT

Datasheet 15

3.1 Pin Descriptions

This section defines the 80960Hx pins. Table 6 presents the legend for interpreting the pin
descriptions in

Table 7. All pins float while the processor is in the ONCE mode, except TDO,

which may be driven active according to normal JTAG specifications.

Table 6. Pin Description Nomenclature

Symbol Description

I Input only pin.

O Output only pin.

I/O Pin may be input or output.

- Pin must be connected as indicated for proper device functionality.

S(E)

Synchronous edge sensitive input. This input must meet the setup and hold times relative to
CLKIN to ensure proper operation of the processor.

S(L)

Synchronous level sensitive input. This input must meet the setup and hold times relative to
CLKIN to ensure proper operation of the processor.

A(E) Asynchronous edge-sensitive input.
A(L) Asynchronous level-sensitive input.

H(...)

While the processor bus is in the HOLD state (HOLDA asserted), the pin:

H(1) is driven to V

CC

H(0) is driven to V

SS

H(Z) floats
H(Q) continues to be a valid output

B(...)

While the processor is in the bus backoff state (BOFF

asserted), the pin:

B(1) is driven to V

CC

B(0) is driven to V

SS

B(Z) floats
B(Q) continues to be a valid output

R(...)

While the processor’s RESET

pin is asserted, the pin:

R(1) is driven to V

CC

R(0) is driven to V

SS

R(Z) floats
R(Q) continues to be a valid output

80960HA/HD/HT

80960HA/HD/HT

16 Datasheet

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 1 of 4)

Name Type Description

A31:2

O

H(Z)

B(Z)

R(Z)

ADDRESS BUS carries the upper 30 bits of the physical address. A31 is the most
significant address bit and A2 is the least significant. During a bus access, A31:2
identify all external addresses to word (4-byte) boundaries. The byte enable
signals indicate the selected byte in each word. During burst accesses, A3 and
A2 increment to indicate successive addresses.

D31:0

I/O

S(L)

H(Z)

B(Z)

R(Z)

DATA BUS carries 32, 16, or 8-bit data quantities depending on bus width
configuration. The least significant bit of the data is carried on D0 and the most
significant on D31. The lower eight data lines (D7:0) are used when the bus is
configured for 8-bit data. When configured for 16-bit data, D15:0 are used.

DP3:0

I/O

S(L)

H(Z)

B(Z)

R(Z)

DATA PARITY carries parity information for the data bus. Each parity bit is
assigned a group of eight data bus pins as follows:

DP3 generates/checks parity for D31:24
DP2 generates/checks parity for D23:16
DP1 generates/checks parity for D15:8
DP0 generates/checks parity for D7:0

Parity information is generated for a processor write cycle and is checked for a
processor read cycle. Parity checking and polarity are programmable. Parity
generation/checking is only performed for the size of the data accessed.

PCHK

O

H(Q)
B(Q)

R(1)

PARITY CHECK indicates the result of a parity check operation. An asserted
PCHK

indicates that the previous bus read access resulted in a parity check error.

BE3:0

O

H(Z)

B(Z)
R(1)

BYTE ENABLES select which of the four bytes addressed by A31:2 are active
during a bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:

32-bit bus:

BE3

enables D31:24
BE2 enables D23:16
BE1 enables D15:8
BE0 enables D7:0

16-bit bus:

BE3

becomes Byte High Enable (enables D15:8)
BE2 is not used (state is undefined)
BE1 becomes Address Bit 1 (A1)
BE0 becomes Byte Low Enable (enables D7:0)

8-bit bus:

BE3

is not used (state is undefined)
BE2 is not used (state is undefined)
BE1

Address Bit 1 (A1)
BE0 Address Bit 0 (A0)

W/R

O

H(Z)

B(Z)
R(0)

WRITE/READ is low for read accesses and high for write accesses.
W/R

becomes valid during the address phase of a bus cycle and remains valid
until the end of the cycle for non-pipelined accesses. For pipelined accesses, W/
R

changes state when the next address is presented.

0= Read
1= Write

D/C

O

H(Z)

B(Z)
R(0)

DATA/CODE indicates that a bus access is a data access or an instruction
access. D/C

has the same timing as W/R.

0 = Code
1 = Data

Datasheet 17

SUP

O

H(Z)
B(Z)
R(1)

SUPERVISOR ACCESS indicates whether the current bus access originates
from a request issued while in supervisor mode or user mode. SUP

may be used
by the memory subsystem to isolate supervisor code and data structures from
non-supervisor access.

0 = Supervisor Mode
1 = User Mode

ADS

O

H(Z)
B(Z)
R(1)

ADDRESS STROBE indicates a valid address and the start of a new bus access.
ADS

is asserted for the first clock of a bus access.

READY

I

S(L)

READY

, when enabled for a memory region, is asserted by the memory

subsystem to indicate the completion of a data transfer. READY

is used to
indicate that read data on the bus is valid, or that a write transfer has completed.
READY

works in conjunction with the internal wait state generator to
accommodate various memory speeds. READY is sampled after any
programmed wait states:

During each data cycle of a burst access
During the data cycle of a non-burst access

BTERM

I

S(L)

BURST TERMINATE, when enabled for a memory region, is asserted by the
memory subsystem to terminate a burst access in progress. When BTERM

is
asserted, the current burst access is terminated and another address cycle
occurs.

WAIT

O

H(Z)
B(Z)
R(1)

WAIT

indicates the status of the internal wait-state generator. WAIT is asserted

when the internal wait state generator generates N

WAD

, N

RAD

, N

WDD

and N

RDD

wait states. WAIT may be used to derive a write data strobe.

BLAST

O

H(Z)
B(Z)
R(1)

BURST LAST indicates the last transfer in a bus access. BLAST is asserted in
the last data transfer of burst and non-burst accesses after the internal wait-state
generator reaches zero. BLAST remains active as long as wait states are inserted
through the READY

pin. BLAST becomes inactive after the final data transfer in a

bus cycle.

DT/R

O

H(Z)
B(Z)
R(0)

DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R

is
used with DEN to provide control for data transceivers connected to the data bus.
DT/R is driven low to indicate the processor expects data (a read cycle). DT/R is
driven high when the processor is “transmitting” data (a store cycle). DT/R only
changes state when DEN

is high.

0 = Data Receive
1 = Data Transmit

DEN

O

H(Z)
B(Z)
R(1)

DATA ENABLE indicates data transfer cycles during a bus access. DEN

is
asserted at the start of the first data cycle in a bus access and de-asserted at the
end of the last data cycle. DEN

remains asserted for an entire bus request, even
when that request spans several bus accesses. For example, a ldq instruction
starting at an unaligned quad word boundary is one bus request spanning at least
two bus accesses. DEN

remains asserted throughout all the accesses (including

ADS

states) and de-asserts when the Iqd instruction request is satisfied. DEN is
used with DT/R to provide control for data transceivers connected to the data bus.
DEN

remains asserted for sequential reads from pipelined memory regions.

LOCK

O

H(Z)
B(Z)
R(1)

BUS LOCK indicates that an atomic read-modify-write operation is in progress.
LOCK

may be used by the memory subsystem to prevent external agents from
accessing memory that is currently involved in an atomic operation (e.g., a
semaphore). LOCK

is asserted in the first clock of an atomic operation and de-

asserted when BLAST is deasserted in the last bus cycle.

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 2 of 4)

Name Type Description

80960HA/HD/HT

80960HA/HD/HT

18 Datasheet

HOLD

I

S(L)

HOLD REQUEST signals that an external agent requests access to the
processor’s address, data, and control buses. When HOLD is asserted, the
processor:

Completes the current bus request.
Asserts HOLDA and floats the address, data, and control buses.
When HOLD is deasserted, the HOLDA pin is deasserted and the processor

reassumes control of the address, data, and control pins.

HOLDA

O

H(1)
B(0)

R(Q)

HOLD ACKNOWLEDGE indicates to an external master that the processor has
relinquished control of the bus. The processor grants HOLD requests and enters
the HOLDA state while the RESET

pin is asserted.

HOLDA is never granted while LOCK

is asserted.

BOFF

I

S(L)

BUS BACKOFF forces the processor to immediately relinquish control of the bus
on the next clock cycle. When READY

/BTERM is enabled and:

When BOFF

is asserted, the address, data, and control buses are floated on the

next clock cycle and the current access is aborted.
When BOFF

is deasserted, the processor resumes by regenerating the aborted

bus access.
See

Figure 16 on page 48 fo r BOFF

timing requirements.

BREQ

O

H(Q)
B(Q)

R(0)

BUS REQUEST indicates that a bus request is pending in the bus controller.
BREQ does not indicate whether or not the processor is stalled. See BSTALL for
processor stall status. BREQ may be used with BSTALL to indicate to an external
bus arbiter the processor’s bus ownership requirements.

BSTALL

O

H(Q)
B(Q)

R(0)

BUS STALL indicates that the processor has stalled pending the result of a
request in the bus controller. When BSTALL is asserted, the processor must
regain bus ownership to continue processing (i.e., it may no longer execute
strictly out of on-chip cache memory).

CT3:0

O

H(Z)

B(Z)

R(Z)

CYCLE TYPE indicates the type of bus cycle currently being started or processor
state. CT3:0 encoding follows:

Cycle Type ADSCT3:0

Program-initiated access using 8-bit bus 00000
Program-initiated access using 16-bit bus 00001
Program-initiated access using 32-bit bus 00010
Event-initiated access using 8-bit bus 00100
Event-initiated access using 16-bit bus 00101
Event-initiated access using 32-bit bus 00110
Reserved 00X11
Reserved for future products 01XXX
Reserved 1XXXX

XINT7:0

I

A(E)

A(L)

EXTERNAL INTERRUPT pins are used to request interrupt service. These pins
may be configured in three modes:

Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated
inputs may be programmed to be level (low or high) or edge (rising or falling)
sensitive.

Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt
pins are level sensitive in this mode.

Mixed Mode: The XINT7:5

pins act as dedicated sources and the XINT4:0 pins
act as the five most significant bits of a vectored source. The least significant bits
of the vectored source are set to “010” internally.

NMI

I

A(E)

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI

is the highest priority interrupt source. NMI is falling edge triggered.

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 3 of 4)

Name Type Description

Datasheet 19

CLKIN I

CLOCK INPUT provides the time base for the 80960Hx. All internal circuitry is

synchronized to CLKIN. All input and output timings are specified relative to
CLKIN.

For the 80960HD, the 2x internal clock is derived by multiplying the CLKIN
frequency by two. For the 80960HT, the 3x internal clock is derived by multiplying
the CLKIN frequency by three.

RESET

I

A(L)

RESET

forces the device into reset. RESET causes all external and internal
signals to return to their reset state (when defined). The rising edge of RESET
starts the processor boot sequence.

STEST

I

S(L)

SELF TEST, when asserted during the rising edge of RESET, causes the
processor to execute its built in self-test.

FAIL

O

H(Q)

B(Q)
R(0)

FAIL

indicates a failure of the processor’s built-in self-test performed during

initialization. F AIL

is asserted immediately out of reset and toggles during self-test

to indicate the status of individual tests. When self-test passes, FAIL

is de­asserted and the processor branches to the user’s initialization code. When self­test fails, the FAIL pin asserts and the processor ceases execution.

ONCE

I

ON-CIRCUIT EMULA TION control: the processor samples this pin during reset.

When it is asserted low at the end of reset, the processor enters ONCE mode. In
ONCE mode, the processor stops all clocks and floats all output pins except the
TDO pin. ONCE

uses an internal pull-up resistor; see RPU definition in Table 22,

“80960Hx DC Characteristics” on page 40. Pull this pin high when not in use.

TCK I

TEST CLOCK provides the clocking function for IEEE 1149.1 Boundary Scan

testing.

TDI I

TEST DAT A INPUT is the serial input pin for IEEE 1 149. 1 Boundary Scan testing.

TDI uses an internal pull-up resistor; see R

PU

definition in

Table 22, “80960Hx DC

Characteristics” on page 40.

TDO O

TEST DATA OUTPUT is the serial output pin for IEEE 1149.1 Boundary Scan

testing. ONCE does not disable this pin.

TRST

I

TEST RESET asynchronously resets the T est Access Port (TAP) controller. TRST

must be held low at least 10,000 clock cycles after power-up. One method is to
provide TRST

with a separate power-on-reset circuit. TRST includes an internal
pull-up resistor; see RPU definition in Table 22, “80960Hx DC Characteristics” on

page 40. Pull this pin low when not in use.

TMS I

TEST MODE SELECT is sampled at the rising edge of TCK. TCK controls the

sequence of TAP controller state changes for IEEE 1149.1 Boundary Scan
testing. TMS uses an internal pull-up resistor; see R

PU

definition in

Table 22,

“80960Hx DC Characteristics” on page 40.

VCC5 I

5 V REFERENCE VOLTAGE input is t he reference voltage for the 5V-tolerant I/O

buffers. Connect this signal to +5 V for use with inputs which exceed 3.3 V. When
all inputs are from 3.3 V components, connect this signal to 3.3 V.

VCCPLL I PLL VOLTAGE is the +3.3 VDC analog input for the PLL.

VOLDET O

VOLTAGE DETECT signal allows external system logic to distinguish between a

5 V 80960Cx processor and the 3.3 V 80960Hx processor. This signal is active
low for a 3.3 V 80960Hx (it is high impedance for 5 V 80960Cx). This pin is
available only on the PGA version.

0 = 80960Hx
1 = 80960Cx

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 4 of 4)

Name Type Description

80960HA/HD/HT

80960HA/HD/HT

20 Datasheet

3.2 80960Hx Mechanical Data

3.2.1 80960Hx PGA Pinout

Figure 2

depicts the complete 80960Hx PGA pinout as viewed from the top side of the compon ent

(i.e., pins facing down).

Figure 3 shows the complete 80960Hx PGA pinout as viewed from the

pin-side of the package (i.e., pins facing up).

Table 9 lists the 80960Hx pin names with package

location. See

Section 4.3, “R ecommended Connections” on page 38 for specifications and

recommended connections.

Figure 2. 80960Hx 168-Pin PGA Pinout—View from Top (Pins Facing Down)

D5D7D8D9D11D12D13D15D16D17D19D21D24D25

D2D4D6V

CC

D10V

CC

V

CC

D14V

CC

D18D20D23D27D29

NCD0V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

CC

D22D31READY D26

D28BTERM

HOLDA

D30HOLD

BE3

V

CC

ADSBE2

V

SS

V

CC

BE1

V

SS

V

CC

BLAST

V

SS

BE0

DEN

V

SS

V

CC

W/R

V

SS

V

CC

DT/R

A29LOCK

SUPWAIT BSTALL

A28

A30BREQD/C

D3

D1

ONCE

V

SS

VCC5

V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

CLKIN

V

CC

V

SS

BOFF

STEST

DP1

DP3

TCK

TMS

V

CC

PCHK

VCC

VCCPLL

V

CC

NC

NC

V

CC

V

SS

FAIL

DP0

DP2

VOLDET

TRST

TDI

TDO

NC

NC

CTO

CT2

CT3

CT1

V

SS

A2

V

CC

A22A25

A20 V

SS

A3A5

NMIV

CC

V

SS

V

SS

V

SS

VSSV

SS

A24A31 A26

A4V

CC

A6A8A9A10A11A12A14A15A17A18

V

CC

V

CC

V

CC

A13V

CC

A16A19A21A23A27 A7

XINT6

XINT7

XINT4

XINT3

XINT5

XINT0

RESET

XINT2

XINT1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

ABCDEFGHJKLMNPQRS

ABCDEFGHJKLMNPQRS

i

© 19xx

A80960Hx

XXXXXXXX SS

M

Datasheet 21

Figure 3. 80960Hx 168-Pin PGA Pinout—View from Bottom (Pins Facing Up)

D5 D7 D8 D9 D11 D12 D13 D15 D16 D17 D19 D21 D24 D25

D2 D4 D6 V

CC

D10 VCCVCCD14 VCCD18 D20 D23 D27 D29

NC D0 VCCVSSVSSVSSVSSVSSVSSVCCD22 D31 READY

D26

D28 BTERM

HOLDA

D30 HOLD BE3

VCCADS BE2

VSSVCCBE1

VSSVCCBLAST

V

SS

BE0

DEN

VSSVCCW/R

VSSVCCDT/R

A29 LOCK

SUP WAITBSTALL

A28

A30 BREQ D/C

D3

D1

ONCE

V

SS

VCC5

V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

CLKIN

V

CC

V

SS

BOFF

STEST

DP1

DP3

TCK

TMS

V

CC

PCHK

VCC

VCCPLL

V

CC

NC

NC

V

CC

V

SS

FAIL

DP0

DP2

VOLDET

TRST

TDI

TDO

NC

NC

CT0

CT2

CT3

CT1

V

SS

A2

V

CC

A22 A25

A20V

SS

A3 A5

NMI

VCCV

SS

VSSV

SS

V

SS

V

SS

A24 A31A26

A4 V

CC

A6 A8 A9 A10 A11 A12 A14 A15 A17 A18

V

CCVCCVCC

A13 VCCA16 A19 A21

A23

A27A7

XINT6

XINT7

XINT4

XINT3

XINT5

XINT0

RESET

XINT2

XINT1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

ABCDEFGHJKLMNPQRS

ABCDEFGHJKLMNPQRS

Package Lid

80960HA/HD/HT

80960HA/HD/HT

22 Datasheet

Table 8. 80960Hx 168-Pin PGA Pinout—Signal Name Order (Sheet 1 of 2)

Signal Name

PGA

Pin

Signal Name

PGA

Pin

Signal Name

PGA

Pin

Signal Name

PGA

Pin

A2 D16 ADS

R6 D14 L2 LOCK S14

A3 D17 BE0

R9 D15 L1 NC A9

A4 E16 BE1

S7 D16 M1 NC A10

A5 E17 BE2

S6 D17 N1 NC B13

A6 F17 BE3

S5 D18 N2 NC B14

A7 G16 BLAST

S8 D19 P1 NC D3

A8 G17 BOFF

B1 D20 P2 NMI D15

A9 H17 BREQ R13 D21 Q1 ONCE

C3

A10 J17 BSTALL R12 D22 P3 PCHK

B8

A11 K17 BTERM

R4 D23 Q2 READY S3

A12 L17 CLKIN C13 D24 R1 RESET

A16

A13 L16 CT0 A11 D25 S1 STEST B2
A14 M17 CT1 A12 D26 Q3 SUP

Q12

A15 N17 CT2 A13 D27 R2 TCK B5
A16 N16 CT3 A14 D28 Q4 TDI A7
A17 P17 D/C

S13 D29 S2 TDO A8
A18 Q17 D0 E3 D30 Q5 TMS B6
A19 P16 D1 C2 D31 R3 TRST

A6

A20 P15 D2 D2 DEN

S9 V

CC

B7

A21 Q16 D3 C1 DP0 A3 V

CC

B9

A22 R17 D4 E2 DP1 B3 V

CC

B11

A23 R16 D5 D1 DP2 A4 V

CC

B12

A24 Q15 D6 F2 DP3 B4 V

CC

C6

A25 S17 D7 E1 DT/R

S11 V

CC

C14

A26 R15 D8 F1 FAIL

A2 V

CC

E15

A27 S16 D9 G1 ——V

CC

F3

A28 Q14 D10 H2 ——V

CC

F16

A29 R14 D11 H1 ——V

CC

G2

A30 Q13 D12 J1 HOLD R5 V

CC

H16

A31 S15 D13 K1 HOLDA S4 V

CC

J2

Datasheet 23

V

CC

J16 VCCPLL B10 V

SS

H3 V

SS

Q10

V

CC

K2 VOLDET A5 V

SS

H15 V

SS

Q11

V

CC

K16 V

SS

A1 V

SS

J3 W/R

S10

V

CC

M2 V

SS

C4 V

SS

J15 WAIT

S12

V

CC

M16 V

SS

C7 V

SS

K3 XINT0

B15

V

CC

N3 V

SS

C8 V

SS

K15 XINT1

A15

V

CC

N15 V

SS

C9 V

SS

L3 XINT2

A17

V

CC

Q6 V

SS

C10 V

SS

L15 XINT3

B16

V

CC

R7 V

SS

C11 V

SS

M3 XINT4

C15

V

CC

R8 V

SS

C12 V

SS

M15 XINT5

B17

V

CC

R10 V

SS

F15 V

SS

Q7 XINT6

C16

V

CC

R11 V

SS

G3 V

SS

Q8 XINT7

C17

VCC5 C5 V

SS

G15 V

SS

Q9 ——

Table 8. 80960Hx 168-Pin PGA Pinout—Signal Name Order (Sheet 2 of 2)

Signal Name

PGA

Pin

Signal Name

PGA

Pin

Signal Name

PGA

Pin

Signal Name

PGA

Pin

80960HA/HD/HT

80960HA/HD/HT

24 Datasheet

Table 9. 80960Hx 168-Pin PGA Pinout—Pin Number Order (Sheet 1 of 2)

PGA

Pin

Signal Name

PGA

Pin

Signal Name

PGA

Pin

Signal Name

PGA

Pin

Signal Name

A1 V

SS

B14 NC E15 V

CC

K15 V

SS

A2 FAIL

B15 XINT0 E16 A4 K16 V

CC

A3 DP0 B16 XINT3

E17 A5 K17 A11

A4 DP2 B17 XINT5

F1 D8 L1 D15
A5 VOLDET C1 D3 F2 D6 L2 D14
A6 TRST

C2 D1 F3 V

CC

L3 V

SS

A7 TDI C3 ONCE

F15 V

SS

L15 V

SS

A8 TDO C4 V

SS

F16 V

CC

L16 A13

A9 NC C5 VCC5 F17 A6 L17 A12

A10 NC C6 V

CC

G1 D9 M1 D16

A11 CT0 C7 V

SS

G2 V

CC

M2 V

CC

A12 CT1 C8 V

SS

G3 V

SS

M3 V

SS

A13 CT2 C9 V

SS

G15 V

SS

M15 V

SS

A14 CT3 C10 V

SS

G16 A7 M16 V

CC

A15 XINT1

C11 V

SS

G17 A8 M17 A14

A16 RESET

C12 V

SS

H1 D11 N1 D17

A17 XINT2

C13 CLKIN H2 D10 N2 D18

B1 BOFF

C14 V

CC

H3 V

SS

N3 V

CC

B2 STEST C15 XINT4

H15 V

SS

N15 V

CC

B3 DP1 C16 XINT6

H16 V

CC

N16 A16

B4 DP3 C17 XINT7

H17 A9 N17 A15
B5 TCK D1 D5 J1 D12 P1 D19
B6 TMS D2 D2 J2 V

CC

P2 D20

B7 V

CC

D3 NC J3 V

SS

P3 D22

B8 PCHK

D15 NMI J15 V

SS

P15 A20

B9 V

CC

D16 A2 J16 V

CC

P16 A19
B10 VCCPLL D17 A3 J17 A10 P17 A17
B11 V

CC

E1 D7 K1 D13 Q1 D21

B12 V

CC

E2 D4 K2 V

CC

Q2 D23

B13 NC E3 D0 K3 V

SS

Q3 D26

Datasheet 25

Q4 D28 Q16 A21 R11 V

CC

S6 BE2
Q5 D30 Q17 A18 R12 BSTALL S7 BE1
Q6 V

CC

R1 D24 R13 BREQ S8 BLAST

Q7 V

SS

R2 D27 R14 A29 S9 DEN

Q8 V

SS

R3 D31 R15 A26 S10 W/R

Q9 V

SS

R4 BTERM R16 A23 S11 DT/R

Q10 V

SS

R5 HOLD R17 A22 S12 WAIT

Q11 V

SS

R6 ADS S1 D25 S13 D/C

Q12 SUP R7 V

CC

S2 D29 S14 LOCK

Q13 A30 R8 V

CC

S3 READY S15 A31

Q14 A28 R9 BE0

S4 HOLDA S16 A27

Q15 A24 R10 V

CC

S5 BE3

S17 A25

Table 9. 80960Hx 168-Pin PGA Pinout—Pin Number Order (Sheet 2 of 2)

PGA

Pin

Signal Name

PGA

Pin

Signal Name

PGA

Pin

Signal Name

PGA

Pin

Signal Name

80960HA/HD/HT

80960HA/HD/HT

26 Datasheet

3.2.2 80960Hx PQ4 Pinout

Figure 4. 80960Hx 208-Pin PQ4 Pinout

PIN 1

PIN 208

PIN 52

PIN 53

PIN 104

PIN 157

PIN 156

V

CC

VSSV

SS

V

CC

FAIL

ONCE

V

SS

V

CC

BOFF

V

CC

D0D1D2

D3

V

SS

V

CC

V

SS

V

CC

D4D5D6

D7

V

SS

V

CC

D8

D9

D10

V

CC

V

SS

VCCD12

D13

D14

D15

VCCD16

D17

D18

D19

V

SS

VCCD21

D22

D23

PIN 105

V

SS

D24

D25

D26

D27

V

SS

V

CC

V

CC

D28

D29

D30

D31

V

SS

V

CC

BTERM

READY

HOLD

HOLDA

V

SS

V

CC

V

SS

V

CC

V

SS

V

CC

ADS

BE3

BE2

V

SS

V

CC

BE1

BE0

BLAST

DEN

V

SS

V

CC

W/R

DT/R

WAIT

BSTALL

V

CC

V

SS

V

SS

V

CC

D/C

SUP

V

SS

LOCK

BREQ

V

CC

V

CC

V

SS

VSSVSSVCCVCCVSSA2A3VCCVSSA4A5A6A7VCCVSSA8A9A10

A11

VCCVSSA12

A13

A14

A15

VCCVSSVSSVCCA16

A17

A18

A19

VCCVSSA20

A21

A22

A23

VCCVSSVCCVSSA24

A25

A26

A27

VCCVSSA28

A29

A30

V

SS

V

CC

NMI
XINT7
XINT6
XINT5
XINT4

V

SS

V

CC

XINT3
XINT2
XINT1
XINT0

V

SS

V

CC

V

SS

V

CC

RESET

CLKIN

VCCPLL

V

SS

V

CC

CT3

CT2

CT1

CT0

V

SS

V

CC

V

SS

V

CC

TDO

PCHK

V

SS

TDI

TMS

TRST

TCK

V

SS

V

CC

VCC5

V

CC

V

SS

V

CC

DP3
DP2

V

CC

V

SS

DP0
DP1

STEST

D11

V

SS

A31

V

SS

V

CC

D20

V

CC

V

SS

V

SS

i

XXXXXXXX SS

M

© 19xx

i960

®

FC80960Hx

V

CC

V

SS

Datasheet 27

Table 10. 80960Hx PQ4 Pinout—Signal Name Order (Sheet 1 of 2)

Signal Name

PQ4

Pin

Signal Name

PQ4

Pin

Signal Name

PQ4

Pin

Signal Name

PQ4

Pin

A2 151 BE0

83 D16 39 PCHK 189

A3 150 BE1

82 D17 40 READY 68

A4 147 BE2

79 D18 41 RESET 174

A5 146 BE3

78 D19 42 STEST 208

A6 145 BLAST

84 D20 45 SUP 97

A7 144 BOFF

10 D21 50 TCK 194
A8 141 BREQ 100 D22 51 TDI 191
A9 140 BSTALL 91 D23 52 TDO 188

A10 139 BTERM

67 D24 54 TMS 192

A11 138 CLKIN 175 D25 55 TRST

193

A12 135 CT0 183 D26 56 V

CC

1

A13 134 CT1 182 D27 57 V

CC

4

A14 133 CT2 181 D28 61 V

CC

9

A15 132 CT3 180 D29 62 V

CC

11

A16 127 D/C

96 D30 63 V

CC

17

A17 126 D0 12 D31 64 V

CC

19

A18 125 D1 13 DEN

85 V

CC

25

A19 124 D2 14 DP0 206 V

CC

31

A20 121 D3 15 DP1 207 V

CC

33

A21 120 D4 20 DP2 203 V

CC

38

A22 119 D5 21 DP3 202 V

CC

44

A23 118 D6 22 DT/R

89 V

CC

46

A24 113 D7 23 FAIL

5 V

CC

49

A25 112 D8 26 ——V

CC

59

A26 111 D9 27 ——V

CC

60

A27 110 D10 28 ——V

CC

66

A28 107 D11 29 HOLD 69 V

CC

71

A29 106 D12 34 HOLDA 72 V

CC

74

A30 105 D13 35 LOCK

99 V

CC

76

A31 104 D14 36 NMI

159 V

CC

81

ADS

77 D15 37 ONCE 6 V

CC

87

80960HA/HD/HT

80960HA/HD/HT

28 Datasheet

V

CC

92 V

CC

187 V

SS

70 V

SS

164

V

CC

95 V

CC

196 V

SS

73 V

SS

170

V

CC

101 V

CC

199 V

SS

75 V

SS

172

V

CC

102 V

CC

201 V

SS

80 V

SS

178

V

CC

109 V

CC

204 V

SS

86 V

SS

184

V

CC

115 VCC5 197 V

SS

93 V

SS

186

V

CC

117 VCCPLL 177 V

SS

94 V

SS

190

V

CC

123 V

SS

2 V

SS

98 V

SS

195

V

CC

128 V

SS

3 V

SS

103 V

SS

198

V

CC

131 V

SS

7VSS108 V

SS

200

V

CC

137 V

SS

8 V

SS

114 V

SS

205

V

CC

143 V

SS

16 V

SS

116 W/R

88

V

CC

149 V

SS

18 V

SS

122 WAIT

90

V

CC

153 V

SS

24 V

SS

129 XINT0

169

V

CC

154 V

SS

30 V

SS

130 XINT1

168

V

CC

158 V

SS

32 V

SS

136 XINT2

167

V

CC

165 V

SS

43 V

SS

142 XINT3

166

V

CC

171 V

SS

47 V

SS

148 XINT4

163

V

CC

173 V

SS

48 V

SS

152 XINT5

162

V

CC

176 V

SS

53 V

SS

155 XINT6

161

V

CC

179 V

SS

58 V

SS

156 XINT7

160

V

CC

185 V

SS

65 V

SS

157 ——

Table 10. 80960Hx PQ4 Pinout—Signal Name Order (Sheet 2 of 2)

Signal Name

PQ4

Pin

Signal Name

PQ4

Pin

Signal Name

PQ4

Pin

Signal Name

PQ4

Pin

Datasheet 29

Table 11. 80960Hx PQ4 Pinout—Pin Number Order (Sheet 1 of 2)

PQ4

Pin

Signal Name

PQ4

Pin

Signal Name

PQ4

Pin

Signal Name

PQ4

Pin

Signal Name

1 V

CC

31 V

CC

61 D28 91 BSTALL

2 V

SS

32 V

SS

62 D29 92 V

CC

3 V

SS

33 V

CC

63 D30 93 V

SS

4 V

CC

34 D12 64 D31 94 V

SS

5 FAIL

35 D13 65 V

SS

95 V

CC

6 ONCE

36 D14 66 V

CC

96 D/C

7 V

SS

37 D15 67 BTERM 97 SUP

8 V

SS

38 V

CC

68 READY 98 V

SS

9 V

CC

39 D16 69 HOLD 99 LOCK

10 BOFF 40 D17 70 V

SS

100 BREQ

11 V

CC

41 D18 71 V

CC

101 V

CC

12 D0 42 D19 72 HOLDA 102 V

CC

13 D1 43 V

SS

73 V

SS

103 V

SS

14 D2 44 V

CC

74 V

CC

104 A31

15 D3 45 D20 75 V

SS

105 A30

16 V

SS

46 V

CC

76 V

CC

106 A29

17 V

CC

47 V

SS

77 ADS

107 A28

18 V

SS

48 V

SS

78 BE3

108 V

SS

19 V

CC

49 V

CC

79 BE2

109 V

CC

20 D4 50 D21 80 V

SS

110 A27

21 D5 51 D22 81 V

CC

111 A26

22 D6 52 D23 82 BE1

112 A25

23 D7 53 V

SS

83 BE0

113 A24

24 V

SS

54 D24 84 BLAST

114 V

SS

25 V

CC

55 D25 85 DEN

115 V

CC

26 D8 56 D26 86 V

SS

116 V

SS

27 D9 57 D27 87 V

CC

117 V

CC

28 D10 58 V

SS

88 W/R

118 A23

29 D11 59 V

CC

89 DT/R

119 A22

30 V

SS

60 V

CC

90 WAIT

120 A21

80960HA/HD/HT

80960HA/HD/HT

30 Datasheet

121 A20 143 V

CC

165 V

CC

187 V

CC

122 V

SS

144 A7 166 XINT3

188 TDO

123 V

CC

145 A6 167 XINT2

189 PCHK

124 A19 146 A5 168 XINT1 190 V

SS

125 A18 147 A4 169 XINT0

191 TDI

126 A17 148 V

SS

170 V

SS

192 TMS

127 A16 149 V

CC

171 V

CC

193 TRST

128 V

CC

150 A3 172 V

SS

194 TCK

129 V

SS

151 A2 173 V

CC

195 V

SS

130 V

SS

152 V

SS

174 RESET

196 V

CC

131 V

CC

153 V

CC

175 CLKIN 197 VCC5

132 A15 154 V

CC

176 V

CC

198 V

SS

133 A14 155 V

SS

177 VCCPLL 199 V

CC

134 A13 156 V

SS

178 V

SS

200 V

SS

135 A12 157 V

SS

179 V

CC

201 V

CC

136 V

SS

158 V

CC

180 CT3 202 DP3

137 V

CC

159 NMI

181 CT2 203 DP2

138 A11 160 XINT7

182 CT1 204 V

CC

139 A10 161 XINT6

183 CT0 205 V

SS

140 A9 162 XINT5

184 V

SS

206 DP0

141 A8 163 XINT4

185 V

CC

207 DP1

142 V

SS

164 V

SS

186 V

SS

208 STEST

Table 11. 80960Hx PQ4 Pinout—Pin Number Order (Sheet 2 of 2)

PQ4

Pin

Signal Name

PQ4

Pin

Signal Name

PQ4

Pin

Signal Name

PQ4

Pin

Signal Name