Intel 80960HT, 80960HD, 80960HA User Manual

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80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

Datasheet

Product Features

32-Bit Parallel Architecture

Load/Store Architecture

Sixteen 32-Bit Global Registers

Sixteen 32-Bit Local Registers

1.28 Gbyte Internal Bandwidth

(80 MHz)

On-Chip Register Cache

Processor Core Clock

80960HA is 1x Bus Clock

80960HD is 2x Bus Clock

80960HT is 3x Bus Clock

Binary Compatible with Other 80960 Processors

Issue Up To 150 Million Instructions per Second

High-Performance On-Chip Storage

16 Kbyte Four-Way Set-Associative Instruction Cache

8 Kbyte Four-Way Set-Associative Data Cache

2 Kbyte General Purpose RAM

Separate 128-Bit Internal Paths For Instructions/Data

3.3 V Supply Voltage

5 V Tolerant Inputs

TTL Compatible Outputs

Guarded Memory Unit

Provides Memory Protection

User/Supervisor Read/Write/Execute

32-Bit Demultiplexed Burst Bus

Per-Byte Parity Generation/Checking

Address Pipelining Option

Fully Programmable Wait State Generator

Supports 8-, 16or 32-Bit Bus Widths

160 Mbyte/s External Bandwidth

(40 MHz)

High-Speed Interrupt Controller

Up to 240 External Interrupts

31 Fully Programmable Priorities

Separate, Non-maskable Interrupt Pin

Dual On-Chip 32-Bit Timers

Auto Reload Capability and One-Shot

CLKIN Prescaling, divided by 1, 2, 4 or 8

JTAG Support - IEEE 1149.1 Compliant

Order Number: 272495-008

September 2002

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.

Copyright © Intel Corporation, 2002

AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet

 

 

 

 

Contents

Contents

 

 

 

 

1.0

About This Document ...................................................................................................................

9

2.0

Intel 80960Hx Processor ...............................................................................................................

9

 

2.1

The i960® Processor Family ...............................................................................................

10

 

2.2

Key 80960Hx Features .......................................................................................................

10

 

 

2.2.1

Execution Architecture...........................................................................................

10

 

 

2.2.2

Pipelined, Burst Bus ..............................................................................................

10

 

 

2.2.3 On-Chip Caches and Data RAM............................................................................

11

 

 

2.2.4

Priority Interrupt Controller.....................................................................................

11

 

 

2.2.5

Guarded Memory Unit ...........................................................................................

11

 

 

2.2.6

Dual Programmable Timers ...................................................................................

12

 

 

2.2.7

Processor Self Test ...............................................................................................

12

 

2.3

Instruction Set Summary ....................................................................................................

13

3.0

Package Information ...................................................................................................................

14

 

3.1

Pin Descriptions..................................................................................................................

15

 

3.2

80960Hx Mechanical Data..................................................................................................

20

 

 

3.2.1

80960Hx PGA Pinout.............................................................................................

20

 

 

3.2.2

80960Hx PQ4 Pinout .............................................................................................

26

 

3.3

Package Thermal Specifications ........................................................................................

31

 

3.4

Heat Sink Adhesives...........................................................................................................

34

 

3.5

PowerQuad4 Plastic Package ............................................................................................

34

 

3.6

Stepping Register Information ............................................................................................

34

 

3.7

Sources for Accessories .....................................................................................................

36

4.0

Electrical Specifications .............................................................................................................

37

 

4.1

Absolute Maximum Ratings ................................................................................................

37

 

4.2

Operating Conditions ..........................................................................................................

37

 

4.3

Recommended Connections ..............................................................................................

38

 

4.4

VCC5 Pin Requirements (VDIFF) ........................................................................................

38

 

4.5

VCCPLL Pin Requirements ................................................................................................

39

 

4.6

DC Specifications ...............................................................................................................

40

 

4.7

AC Specifications................................................................................................................

42

 

 

4.7.1

AC Test Conditions................................................................................................

45

 

4.8

AC Timing Waveforms........................................................................................................

46

5.0

Bus Waveforms ...........................................................................................................................

54

 

5.1

80960Hx Boundary Scan Chain .........................................................................................

84

 

5.2

Boundary Scan Description Language Example ................................................................

88

Figures

 

 

 

1

80960Hx Block Diagram ...............................................................................................................

9

2

80960Hx 168-Pin PGA Pinout— View from Top (Pins Facing Down) .........................................

20

3

80960Hx 168-Pin PGA Pinout— View from Bottom (Pins Facing Up) ........................................

21

4 80960Hx 208-Pin PQ4 Pinout.....................................................................................................

26

5 Measuring 80960Hx PGA Case Temperature ............................................................................

31

6 80960Hx Device Identification Register......................................................................................

34

Datasheet

3

Contents

 

7

VCC5 Current-Limiting Resistor .................................................................................................

38

8

AC Test Load..............................................................................................................................

45

9

CLKIN Waveform........................................................................................................................

46

10

Output Delay Waveform .............................................................................................................

46

11

Output Delay Waveform .............................................................................................................

46

12

Output Float Waveform ..............................................................................................................

47

13

Input Setup and Hold Waveform ................................................................................................

47

14

NMI, XINT7:0 Input Setup and Hold Waveform..........................................................................

47

15

Hold Acknowledge Timings ........................................................................................................

48

16

Bus Backoff (BOFF) Timings......................................................................................................

48

17

TCK Waveform ...........................................................................................................................

49

18

Input Setup and Hold Waveforms for TBSIS1 and TBSIH1..........................................................

49

19

Output Delay and Output Float for TBSOV1 and TBSOF1 ........................................................

50

20

Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 .......................................

50

21

Input Setup and Hold Waveform for TBSIS2 and TBSIH2 .........................................................

50

22

Rise and Fall Time Derating at 85 ° C and Minimum VCC..........................................................

51

23

ICC Active (Power Supply) vs. Frequency...................................................................................

51

24

ICC Active (Thermal) vs. Frequency............................................................................................

52

25

Output Delay or Hold vs. Load Capacitance ..............................................................................

52

26

Output Delay vs. Temperature ...................................................................................................

53

27

Output Hold Times vs. Temperature ..........................................................................................

53

28

Output Delay vs. VCC ................................................................................................................

53

29

Cold Reset Waveform ................................................................................................................

54

30

Warm Reset Waveform ..............................................................................................................

55

31

Entering ONCE Mode.................................................................................................................

56

32

Non-Burst, Non-Pipelined Requests without Wait States ...........................................................

57

33

Non-Burst, Non-Pipelined Read Request with Wait States ........................................................

58

34

Non-Burst, Non-Pipelined Write Request with Wait States ........................................................

59

35

Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus ........................................

60

36

Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus .............................................

61

37

Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus ........................................

62

38

Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus .............................................

63

39

Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus .............................................

64

40

Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus ...............................................

65

41

Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus ........................................

66

42

Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus .............................................

67

43

Burst, Pipelined Read Request without Wait States, 32-Bit Bus ................................................

68

44

Burst, Pipelined Read Request with Wait States, 32-Bit Bus .....................................................

69

45

Burst, Pipelined Read Request with Wait States, 8-Bit Bus .......................................................

70

46

Burst, Pipelined Read Request with Wait States, 16-Bit Bus .....................................................

71

47

Using External READY...............................................................................................................

72

48

Terminating a Burst with BTERM ...............................................................................................

73

49

BREQ and BSTALL Operation ...................................................................................................

74

50

BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle.........................

75

51

HOLD Functional Timing ............................................................................................................

76

52

LOCK Delays HOLDA Timing.....................................................................................................

77

53

FAIL Functional Timing...............................................................................................................

77

54

A Summary of Aligned and Unaligned Transfers for 32-Bit Regions..........................................

78

55

A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued)......................

79

56

A Summary of Aligned and Unaligned Transfers for 16-Bit Bus.................................................

80

4

Datasheet

 

 

Contents

57

A Summary of Aligned and Unaligned Transfers for 8-Bit Bus...................................................

81

58

Idle Bus Operation ......................................................................................................................

82

59

Bus States ..................................................................................................................................

83

Tables

 

1

80960Hx Product Description .......................................................................................................

9

2

Fail Codes For BIST (bit 7 = 1)...................................................................................................

12

3

Remaining Fail Codes (bit 7 = 0) ................................................................................................

12

4

80960Hx Instruction Set .............................................................................................................

13

5

80960HA/HD/HT Package Types and Speeds...........................................................................

14

6

Pin Description Nomenclature ....................................................................................................

15

7

80960Hx Processor Family Pin Descriptions..............................................................................

16

8

80960Hx 168-Pin PGA Pinout— Signal Name Order..................................................................

22

9

80960Hx 168-Pin PGA Pinout— Pin Number Order ...................................................................

24

10

80960Hx PQ4 Pinout— Signal Name Order................................................................................

27

11

80960Hx PQ4 Pinout— Pin Number Order .................................................................................

29

13

80960Hx 168-Pin PGA Package Thermal Characteristics .........................................................

32

12

Maximum TA at Various Airflows in °C (PGA Package Only) .....................................................

32

15

80960Hx 208-Pin PQ4 Package Thermal Characteristics..........................................................

33

14

Maximum TA at Various Airflows in °C (PQ4 Package Only)......................................................

33

17

80960Hx Device ID Model Types ...............................................................................................

35

18

Device ID Version Numbers for Different Steppings...................................................................

35

16

Fields of 80960Hx Device ID ......................................................................................................

35

19

Absolute Maximum Ratings ........................................................................................................

37

20

Operating Conditions ..................................................................................................................

37

21

VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V) ......................................

39

22

80960Hx DC Characteristics ......................................................................................................

40

23

80960Hx AC Characteristics.......................................................................................................

42

25

80960Hx Boundary Scan Test Signal Timings ...........................................................................

44

24

AC Characteristics Notes............................................................................................................

44

26

80960Hx Boundary Scan Chain .................................................................................................

84

Datasheet

5

Contents

Revision History

Date

Revision

 

 

History

 

 

 

 

 

Formatted the datasheet in a new template.

 

 

In “32-Bit Parallel Architecture” on page 1:

 

 

• Removed operating frequency of 16/32 (bus/core) from 80960HD.

 

 

• Removed operating frequency of 20/60 (bus/core) from 80960HT.

 

 

In Table 5 “80960HA/HD/HT Package Types and Speeds” on page 14:

 

 

• Removed core speed of 32 MHz and bus speed of 16 MHz, and order

 

 

 

number A80960HD32-S-L2GG from the 168L PGA package, 80960HD

September 2002

008

 

device.

 

 

• Removed core speed of 60 MHz and bus speed of 20 MHz, and order

 

 

 

number A80960HT60 from the 168L PGA package, 80960HT device.

 

 

• Removed core speed of 32 MHz and bus speed of 16 MHz, and order

 

 

 

number FC80960HD32-S-L2GL from the 208L PQFP package,

 

 

 

80960HD device.

 

 

• Removed core speed of 60 MHz and bus speed of 20 MHz, and order

 

 

 

number FC80960HT60-S-L2G2 from the 208L PQFP package,

 

 

 

80960HT device.

 

 

 

 

 

In “32-Bit Parallel Architecture” on page 1:

 

 

• Revised 1.2 Gbyte Internal Bandwidth (75 MHz) to 1.28 Gbyte Internal

 

 

 

Bandwidth (80 MHz).

 

 

In Section 3.0, “Package Information” on page 14:

 

 

• Added paragraph two and Table 5 “80960HA/HD/HT Package Types

 

 

 

and Speeds” on page 14.

 

 

In Table 7 “80960Hx Processor Family Pin Descriptions” on page 16:

 

 

• Corrected minor typeset and spacing errors.

 

 

BREQ; Revised description.

 

 

 

 

 

ONCE;

last sentence, changed ‘low’ to ‘high’.

 

 

• TDI and TMS; removed last sentence stating, “Pull this pin low when

 

 

 

not in use.”

 

 

In Figure 2 “80960Hx 168-Pin PGA Pinout— View from Top (Pins Facing

 

 

Down)” on page 20:

July 1998

007

Added insert package marking diagram.

 

 

In Figure 4 “80960Hx 208-Pin PQ4 Pinout” on page 26:

 

 

• Added insert package marking diagram.

 

 

In Table 10 “80960Hx PQ4 Pinout— Signal Name Order” on page 27:

Corrected TDO (‘O’ was zero) and revised alphabetical ordering. In Table 11 “80960Hx PQ4 Pinout— Pin Number Order” on page 29:

Corrected TDO (‘O’ was zero) and revised alphabetical ordering. In Section 4.1, “Absolute Maximum Ratings” on page 37:

Revised VCC to VCC5 for Voltage on Other Pins with respect to VSS. In Section 4.5, “VCCPLL Pin Requirements” on page 39:

Added section.

In Table 22 “80960Hx DC Characteristics” on page 40:

Added footnote (1) to ILO notes column for TDO pin.

Added footnote (10) to CIN, COUT and CI/O pin.

6

Datasheet

Contents

Date

Revision

History

 

 

 

 

 

In Table 23 “80960Hx AC Characteristics” on page 42:

 

 

• Added overbars where required.

 

 

• Modified TDVNH to list separate specifications for 3.3 V and 5 V.

 

 

• Modified TOV2, TOH2 and TTVEL to reflect specific 80960HA, 80960HD

July 1998

007

and 80960HT values.

 

(continued)

(continued)

In Figure 23 “ICC Active (Power Supply) vs. Frequency” on page 51:

 

 

• Changed ‘5’ to ‘0’ on the CLKIN Frequency axis.

 

 

In Figure 49 “BREQ and BSTALL Operation” on page 74:

 

 

• Added figure and following text.

 

 

 

August 1997

006

Fixed several font and format issues.

 

 

 

Datasheet

7

Contents

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8

Datasheet

80960HA/HD/HT

1.0About This Document

This document describes the parametric performance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics, other than parametric performance, are published in the i960® Hx Microprocessor User’s Guide (272484).

In this document, ‘80960Hx’ and ‘i960 Hx processor’ refer to the products described in Table 1. Throughout this document, information that is specific to each is clearly indicated.

Figure 1. 80960Hx Block Diagram

 

 

Instruction Prefetch Queue

Guarded Memory Unit

Control

 

 

 

 

 

 

JTAG Port

Instruction Cache

Memory Region Configuration

 

 

 

16 Kbyte, Four-Way Set-Associative

Address

 

 

Bus Controller

 

Timers

 

 

 

128-Bit Cache Bus

 

 

 

 

 

 

Bus Request Queues

Data

Interrupt

Programmable

 

 

Parallel Instruction Scheduler

 

 

Port

Interrupt Controller

Data Cache

 

 

 

 

8 Kbyte, Four-Way Set-Associative

 

 

 

 

 

 

 

Multiply/Divide Unit

 

 

Data RAM - 2 Kbyte

 

 

 

Register-Side

Memory-Side

 

 

Execution Unit

 

 

 

Machine Bus

Machine Bus

Register Cache - 5 to 15 sets

 

 

 

 

 

 

Six-Port Register File

Address Generation Unit

 

 

 

64-bit SRC1 Bus

32-bit Base Bus

 

 

 

 

 

 

 

64-bit SRC2 Bus

128-bit Load Bus

 

 

 

 

64-bit DST Bus

128-bit Store Bus

 

 

2.0Intel 80960Hx Processor

The Intel 80960Hx processor provides new performance levels while maintaining backward compatibility (pin1 and software) with the i960 CA/CF processor. This newest member of the family of i960 32-bit, RISC-style, embedded processors allows customers to create scalable designs that meet multiple price and performance points. This is accomplished by providing processors that may run at the bus speed or faster using Intel’s clock multiplying technology

(see Table 1). The 80960Hx core is capable of issuing 150 million instructions per second, using a sophisticated instruction scheduler that allows the processor to sustain a throughput of two instructions every core clock, with a peak performance of three instructions per clock. The 80960Hx-series comprises three processors, which differ in the ratio of core clock speed to external bus speed.

Table 1. 80960Hx Product Description

Product

Core

Voltage

Operating Frequency (bus/core)

 

 

 

 

80960HA

1x

3.3 V

25/25, 33/33, 40/40

80960HD

2x

3.3 V

25/50, 33/66, 40/80

80960HT

3x

3.3 V

25/75

Processor inputs are 5 V tolerant.

1.The 80960Hx is not “ drop-in” compatible in an 80960Cx-based system. Customers may design systems that accept either 80960Hx or Cx processors.

Datasheet

9

80960HA/HD/HT

In addition to expanded clock frequency options, the 80960Hx provides essential enhancements for an emerging class of high-performance embedded applications. Features include a larger instruction cache, data cache, and data RAM than any other 80960 processor to date. It also boasts a 32-bit demultiplexed and pipelined burst bus, fast interrupt mechanism, guarded memory unit, wait state generator, dual programmable timers, ONCE and IEEE 1149.1-compliant boundary scan test and debug support, and new instructions.

2.1The i960® Processor Family

The i960® processor family is a 32-bit RISC architecture created by Intel to serve the needs of embedded applications. The embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and communications.

Because all members of the i960 processor family share a common core architecture, i960 applications are code-compatible. Each new processor in the family adds its own special set of functions to the core to satisfy the needs of a specific application or range of applications in the embedded market.

2.2Key 80960Hx Features

2.2.1Execution Architecture

Independent instruction paths inside the processor allow the execution of multiple, out-of-sequence instructions per clock. Register and resource scoreboarding interlocks maintain the logical integrity of sequential instructions that are being executed in parallel. To sustain execution of multiple instructions in each clock cycle, the processor decodes multiple instructions in parallel and simultaneously issues these instructions to parallel processing units. The various processing units are then able to independently access instruction operands in parallel from a common register set.

Local Register Cache integrated on-chip provides automatic register management on call/return instructions. Upon a call instruction, the processor allocates a set of local registers for the called procedure, then stores the registers for the previous procedure in the on-chip register cache. As additional procedures are called, the cache stores the associated registers such that the most recently called procedure is the first available by the next return (ret) instruction. The processor may store up to fifteen register sets, after which the oldest sets are stored (spilled) into external memory.

The 80960Hx supports the 80960 architecturally-defined branch prediction mechanism. This allows many branches to execute with no pipeline break. With the 80960Hx’s efficient pipeline, a branch may take as few as zero clocks to execute. The maximum penalty for an incorrect prediction is two core clocks.

2.2.2Pipelined, Burst Bus

A 32-bit high performance bus controller interfaces the 80960Hx core to the external memory and peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at a 40 MHz external bus clock frequency). A key advantage of this design is its versatility. The user may independently program the physical and logical attributes of system memory. Physical attributes include wait state profile, bus width, and parity. Logical attributes include cacheability and Big or Little Endian byte order. Internally programmable wait states and 16 separately configurable physical memory regions allow the processor to interface with a variety of memory

10

Datasheet

80960HA/HD/HT

subsystems with minimum system complexity. To reduce the effect of wait states, the bus design is decoupled from the core. This lets the processor execute instructions while the bus performs memory accesses independently.

The Bus Controller’s key features include:

Demultiplexed, Burst Bus to support most efficient DRAM access modes

Address Pipelining to reduce memory cost while maintaining performance

32-, 16and 8-bit modes to facilitate I/O interfacing

Full internal wait state generation to reduce system cost

Little and Big Endian support

Unaligned Access support implemented in hardware

Three-deep request queue to decouple the bus from the core

Independent physical and logical address space characteristics

2.2.3On-Chip Caches and Data RAM

As shown in Figure 1, the 80960Hx provides generous on-chip cache and storage features to decouple CPU execution from the external bus. The processor includes a 16 Kbyte instruction cache, an 8 Kbyte data cache and 2 Kbytes of Data RAM. The caches are organized as 4-way set associative. Stores that hit the data cache are written through to memory. The data cache performs write allocation on cache misses. A fifteen-set stack frame cache allows the processor to rapidly allocate and deallocate local registers. All of the on-chip RAM sustains a 4-word (128-bit) access every clock cycle.

2.2.4Priority Interrupt Controller

The interrupt unit provides the mechanism for the low latency and high throughput interrupt service essential for embedded applications. A priority interrupt controller provides full programmability of 240 interrupt sources with a typical interrupt task switch (latency) time of 17 core clocks. The controller supports 31 priority levels. Interrupts are prioritized and signaled within 10 core clocks of the request. When the interrupt has a higher priority than the processor priority, the context switch to the interrupt routine would typically complete in another seven bus clocks.

External agents post interrupts through the 8-bit external interrupt port. The Interrupt unit also handles the two internal sources from the Timers. Interrupts may be levelor edge-triggered.

2.2.5Guarded Memory Unit

The Guarded Memory Unit (GMU) provides memory protection without the address translation found in Memory Management Units. The GMU contains two memory protection schemes: one prevents illegal memory accesses, the other detects memory access violations. Both signal a fault to the processor. The programmable protection modes are: user read, write or execute; and supervisor read, write or execute.

Datasheet

11

80960HA/HD/HT

2.2.6Dual Programmable Timers

The processor provides two independent 32-bit timers, with four programmable clock rates. The user configures the timers through the Timer Unit registers. These registers are memory-mapped within the 80960Hx, addressable on 32-bit boundaries. The timers have a single-shot mode and auto-reload capabilities for continuous operation. Each timer has an independent interrupt request to the processor’s interrupt controller.

2.2.7Processor Self Test

When a system error is detected, the FAIL pin is asserted, a fail code message is driven onto the address bus, and the processor stops execution at the point of failure. The only way to resume normal operation is to perform a RESET operation. Because System Error generation may occur sometime after the bus confidence test and even after initialization during normal processor operation, the FAIL pin is HIGH (logic “ 1” ) before the detection of a System Error.

The processor uses only one read bus-transaction to signal the fail code message; the address of the bus transaction is the fail code itself. The fail code is of the form: 0xfeffffnn; bits 6 to 0 contain a mask recording the possible failures. Bit 7, when set to 1, indicates that the mask contains failures from the internal Built-In Self-Test (BIST); when 0, the mask indicates other failures.

Ignore reserved bits 0 and 1. Also ignore bits 5 and 6 when bit 7 is clear (=0).

The mask is shown in Table 2 and Table 3.

Table 2. Fail Codes For BIST (bit 7 = 1)

Bit

When Set

 

 

6

On-chip Data-RAM failure detected by BIST.

 

 

5

Internal Microcode ROM failure detected by BIST.

 

 

4

Instruction cache failure detected by BIST.

 

 

3

Data cache failure detected by BIST.

 

 

2

Local-register cache or processor core failure detected by BIST.

 

 

1

Reserved. Always zero.

 

 

0

Reserved. Always zero.

 

 

Table 3. Remaining Fail Codes (bit 7 = 0)

Bit

When Set

 

 

6

Reserved. Always one.

 

 

5

Reserved. Always one.

 

 

4

A data structure within the IMI is not aligned to a word boundary.

 

 

3

A System Error during normal operation has occurred.

 

 

2

The Bus Confidence test has failed.

 

 

1

Reserved. Always zero.

 

 

0

Reserved. Always zero.

 

 

12

Datasheet

80960HA/HD/HT

2.3Instruction Set Summary

Table 4 summarizes the 80960Hx instruction set by logical groupings.

Table 4. 80960Hx Instruction Set

Data Movement

Arithmetic

Logical

Bit / Bit Field / Byte

 

 

 

 

 

Add

 

 

 

Subtract

 

 

 

Multiply

And

Set Bit

 

Divide

Not And

 

Clear Bit

 

Remainder

And Not

 

Not Bit

Load

Modulo

Or

Alter Bit

Store

Shift

Exclusive Or

Scan For Bit

Move

Extended Shift

Not Or

Span Over Bit

Load Address

Extended Multiply

Or Not

Extract

Conditional Select2

Extended Divide

Nor

Modify

 

Add with Carry

Exclusive Nor

 

Scan Byte for Equal

 

Subtract with Carry

Not

 

Byte Swap2

 

Rotate

Nand

 

 

 

Conditional Add2

 

 

 

Conditional Subtract2

 

 

Comparison

Branch

Call/Return

Fault

 

 

 

 

Compare

 

 

 

Conditional Compare

 

Call

 

Compare and Increment

 

 

Unconditional Branch

Call Extended

 

Compare and Decrement

Conditional Fault

Conditional Branch

Call System

Compare Byte2

Synchronize Faults

Compare and Branch

Return

Compare Short2

 

 

Branch and Link

 

Test Condition Code

 

 

 

 

 

Check Bit

 

 

 

 

 

 

 

Debug

Processor Mgmt

Atomic

Cache Control

 

 

 

 

 

Flush Local Registers

 

 

Modify Trace Controls

Modify Arithmetic Controls

Atomic Add

Instruction Cache

Mark

Modify Process Controls

Control1, 2

Force Mark

Interrupt Enable/ Disable1, 2

Atomic Modify

Data Cache Control1, 2

 

System Control1

 

 

NOTES:

1.80960Hx extensions to the 80960 core instruction set.

2.80960Hx extensions to the 80960Cx instruction set.

Datasheet

13

80960HA/HD/HT

3.0Package Information

This section describes the pins, pinouts and thermal characteristics for the 80960Hx in the 168-pin ceramic Pin Grid Array (PGA) package, 208-pin PowerQuad2* (PQ4). For complete package specifications and information, see the Intel Packaging Handbook (Order# 240800).

The 80960HA/HD/HT is offered with eight speeds and two package types (Table 5). Both the 168-pin ceramic Pin Grid Array (PGA) and the 208-pin PowerQuad2* (PQ4) devices are specified for operation at VCC = 3.3 V ± 0.15 V over a case temperature range of 0 ° C to 85 ° C.

Table 5. 80960HA/HD/HT Package Types and Speeds

Package/Name

Device

Core Speed

 

Bus Speed

Order #

(MHz)

 

(MHz)

 

 

 

 

 

 

 

 

 

 

 

 

25

 

A80960HA25 S L2GX

 

 

 

 

 

 

80960HA

33

 

A80960HA33 S L2GY

 

 

 

 

 

 

 

40

 

A80960HA40 S L2GZ

 

 

 

 

 

 

168L PGA

 

50

 

25

A80960HD50 S L2GH

 

 

 

 

 

 

 

80960HD

66

 

33

A80960HD66 S L2GJ

 

 

 

 

 

 

 

 

80

 

40

A80960HD80 S L2GK

 

 

 

 

 

 

 

80960HT

75

 

25

A80960HT75 S L2GP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

 

FC80960HA25 S L2GU

 

 

 

 

 

 

80960HA

33

 

FC80960HA33 S L2GV

 

 

 

 

 

 

 

40

 

FC80960HA40 S L2GW

208L PQFP

 

 

 

 

 

 

50

 

25

FC80960HD50 S L2GM

(also known as PQ4)

 

 

 

 

 

 

 

 

80960HD

66

 

33

FC80960HD66 S L2GN

 

 

 

 

 

 

 

 

80

 

40

FC80960HD80 S L2LZ

 

 

 

 

 

 

 

80960HT

75

 

25

FC80960HT75 S L2GT

 

 

 

 

 

 

14

Datasheet

80960HA/HD/HT

3.1Pin Descriptions

This section defines the 80960Hx pins. Table 6 presents the legend for interpreting the pin descriptions in Table 7. All pins float while the processor is in the ONCE mode, except TDO, which may be driven active according to normal JTAG specifications.

Table 6. Pin Description Nomenclature

Symbol

 

 

Description

 

 

I

Input only pin.

 

 

O

Output only pin.

 

 

I/O

Pin may be input or output.

 

 

-

Pin must be connected as indicated for proper device functionality.

 

 

S(E)

Synchronous edge sensitive input. This input must meet the setup and hold times relative to

CLKIN to ensure proper operation of the processor.

 

 

 

S(L)

Synchronous level sensitive input. This input must meet the setup and hold times relative to

CLKIN to ensure proper operation of the processor.

 

 

 

A(E)

Asynchronous edge-sensitive input.

 

 

A(L)

Asynchronous level-sensitive input.

 

 

 

While the processor bus is in the HOLD state (HOLDA asserted), the pin:

H(...)

H(1) is driven to VCC

H(0) is driven to VSS

 

H(Z) floats

 

H(Q) continues to be a valid output

 

 

 

 

 

While the processor is in the bus backoff state

 

asserted), the pin:

 

(BOFF

B(...)

B(1) is driven to VCC

B(0) is driven to VSS

 

B(Z) floats

 

B(Q) continues to be a valid output

 

 

 

While the processor’s

 

pin is asserted, the pin:

 

RESET

R(...)

R(1) is driven to VCC

R(0) is driven to VSS

 

R(Z) floats

 

R(Q) continues to be a valid output

 

 

 

 

 

 

Datasheet

15

80960HA/HD/HT

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 1 of 4)

 

Name

 

Type

Description

 

 

 

 

 

 

 

 

 

 

 

 

O

ADDRESS BUS carries the upper 30 bits of the physical address. A31 is the most

 

 

 

 

 

significant address bit and A2 is the least significant. During a bus access, A31:2

 

A31:2

 

H(Z)

 

 

identify all external addresses to word (4-byte) boundaries. The byte enable

 

 

B(Z)

 

 

 

 

 

signals indicate the selected byte in each word. During burst accesses, A3 and

 

 

 

 

 

R(Z)

 

 

 

 

 

A2 increment to indicate successive addresses.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

DATA BUS carries 32, 16, or 8-bit data quantities depending on bus width

 

 

 

 

 

S(L)

 

D31:0

 

configuration. The least significant bit of the data is carried on D0 and the most

 

 

H(Z)

 

 

significant on D31. The lower eight data lines (D7:0) are used when the bus is

 

 

 

 

 

B(Z)

 

 

 

 

 

configured for 8-bit data. When configured for 16-bit data, D15:0 are used.

 

 

 

 

 

R(Z)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA PARITY carries parity information for the data bus. Each parity bit is

 

 

 

 

 

 

assigned a group of eight data bus pins as follows:

 

 

 

 

 

I/O

DP3 generates/checks parity for D31:24

 

DP3:0

 

S(L)

DP2 generates/checks parity for D23:16

 

 

H(Z)

DP1 generates/checks parity for D15:8

 

 

 

 

 

B(Z)

DP0 generates/checks parity for D7:0

 

 

 

 

 

R(Z)

Parity information is generated for a processor write cycle and is checked for a

 

 

 

 

 

 

processor read cycle. Parity checking and polarity are programmable. Parity

 

 

 

 

 

 

generation/checking is only performed for the size of the data accessed.

 

 

 

 

 

 

 

 

 

 

 

 

O

 

 

 

 

 

 

H(Q)

PARITY CHECK indicates the result of a parity check operation. An asserted

 

PCHK

 

 

B(Q)

PCHK indicates that the previous bus read access resulted in a parity check error.

 

 

 

 

 

 

 

 

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BYTE ENABLES select which of the four bytes addressed by A31:2 are active

 

 

 

 

 

 

during a bus access. Byte enable encoding is dependent on the bus width of the

 

 

 

 

 

 

memory region accessed:

 

 

 

 

 

 

32-bit bus:

 

 

 

 

 

 

BE3 enables D31:24

 

 

 

 

 

 

BE2 enables D23:16

 

 

 

 

 

O

BE1 enables D15:8

 

 

 

 

 

BE0 enables D7:0

 

 

 

 

 

H(Z)

16-bit bus:

 

BE3:0

 

 

B(Z)

BE3 becomes Byte High Enable (enables D15:8)

 

 

 

 

 

 

 

 

 

 

R(1)

BE2 is not used (state is undefined)

 

 

 

 

 

 

BE1 becomes Address Bit 1 (A1)

 

 

 

 

 

 

BE0 becomes Byte Low Enable (enables D7:0)

 

 

 

 

 

 

8-bit bus:

 

 

 

 

 

 

BE3 is not used (state is undefined)

 

 

 

 

 

 

BE2 is not used (state is undefined)

 

 

 

 

 

 

BE1 Address Bit 1 (A1)

 

 

 

 

 

 

BE0 Address Bit 0 (A0)

 

 

 

 

 

 

 

 

 

 

 

 

O

WRITE/READ is low for read accesses and high for write accesses.

 

 

 

 

 

W/R becomes valid during the address phase of a bus cycle and remains valid

 

 

 

 

 

H(Z)

until the end of the cycle for non-pipelined accesses. For pipelined accesses, W/

 

W/R

 

 

 

R changes state when the next address is presented.

 

 

B(Z)

 

 

 

 

 

 

 

 

 

 

0= Read

 

 

 

 

 

R(0)

 

 

 

 

 

 

1= Write

 

 

 

 

 

 

 

 

 

 

 

 

O

DATA/CODE indicates that a bus access is a data access or an instruction

 

 

 

 

 

H(Z)

access. D/C has the same timing as W/R.

 

D/C

 

 

 

0 = Code

 

 

B(Z)

 

 

 

 

 

 

 

 

 

 

R(0)

1 = Data

 

 

 

 

 

 

 

16

Datasheet

80960HA/HD/HT

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 2 of 4)

 

 

Name

 

Type

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

SUPERVISOR ACCESS indicates whether the current bus access originates

 

 

 

 

 

 

 

 

 

 

from a request issued while in supervisor mode or user mode. SUP may be used

 

 

 

 

 

 

 

 

 

 

H(Z)

by the memory subsystem to isolate supervisor code and data structures from

 

 

 

 

SUP

 

 

 

 

 

 

non-supervisor access.

 

 

 

 

 

B(Z)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R(1)

0 = Supervisor Mode

 

 

 

 

 

 

 

 

 

 

 

1 = User Mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H(Z)

ADDRESS STROBE indicates a valid address and the start of a new bus access.

 

 

 

ADS

 

 

 

 

B(Z)

ADS is asserted for the first clock of a bus access.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READY, when enabled for a memory region, is asserted by the memory

 

 

 

 

 

 

 

 

 

 

 

subsystem to indicate the completion of a data transfer.

READY

is used to

 

 

 

 

 

 

 

 

 

 

 

indicate that read data on the bus is valid, or that a write transfer has completed.

 

 

 

 

 

 

 

 

 

 

I

READY works in conjunction with the internal wait state generator to

 

READY

 

 

S(L)

accommodate various memory speeds. READY is sampled after any

 

 

 

 

 

 

 

 

 

 

programmed wait states:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

During each data cycle of a burst access

 

 

 

 

 

 

 

 

 

 

 

During the data cycle of a non-burst access

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

BURST TERMINATE, when enabled for a memory region, is asserted by the

 

 

 

 

 

 

 

 

 

 

memory subsystem to terminate a burst access in progress. When BTERM is

BTERM

 

S(L)

asserted, the current burst access is terminated and another address cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

occurs.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WAIT indicates the status of the internal wait-state generator. WAIT is asserted

 

 

 

 

 

 

 

 

 

 

H(Z)

 

 

 

WAIT

 

when the internal wait state generator generates NWAD, NRAD, NWDD and NRDD

 

 

 

 

B(Z)

 

 

 

 

 

 

 

 

 

 

wait states. WAIT may be used to derive a write data strobe.

 

 

 

 

 

 

 

 

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BURST LAST indicates the last transfer in a bus access.

 

 

 

is asserted in

 

 

 

 

 

 

 

 

 

 

O

BLAST

 

 

 

 

 

 

 

 

 

 

the last data transfer of burst and non-burst accesses after the internal wait-state

 

 

 

 

 

 

 

 

 

 

H(Z)

 

BLAST

 

generator reaches zero. BLAST remains active as long as wait states are inserted

 

 

B(Z)

 

 

 

 

 

 

 

 

 

 

through the READY pin. BLAST becomes inactive after the final data transfer in a

 

 

 

 

 

 

 

 

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

bus cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is

 

 

 

 

 

 

 

 

 

 

 

DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R

 

 

 

 

 

 

 

 

 

 

O

used with DEN to provide control for data transceivers connected to the data bus.

 

 

 

 

 

 

 

 

 

 

DT/R is driven low to indicate the processor expects data (a read cycle). DT/R is

 

 

 

 

 

 

 

 

 

 

H(Z)

 

 

 

DT/R

 

driven high when the processor is “transmitting” data (a store cycle). DT/R only

 

 

 

 

 

 

 

 

 

 

B(Z)

changes state when DEN is high.

 

 

 

 

 

 

 

 

 

 

R(0)

0 = Data Receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 = Data Transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA ENABLE indicates data transfer cycles during a bus access.

 

is

 

 

 

 

 

 

 

 

 

 

 

DEN

 

 

 

 

 

 

 

 

 

 

 

asserted at the start of the first data cycle in a bus access and de-asserted at the

 

 

 

 

 

 

 

 

 

 

O

end of the last data cycle. DEN remains asserted for an entire bus request, even

 

 

 

 

 

 

 

 

 

 

when that request spans several bus accesses. For example, a ldq instruction

 

 

 

 

 

 

 

 

 

 

H(Z)

 

 

 

DEN

 

starting at an unaligned quad word boundary is one bus request spanning at least

 

 

 

 

B(Z)

 

 

 

 

 

 

 

 

 

 

two bus accesses. DEN remains asserted throughout all the accesses (including

 

 

 

 

 

 

 

 

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

ADS states) and de-asserts when the Iqd instruction request is satisfied. DEN is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

used with DT/R to provide control for data transceivers connected to the data bus.

 

 

 

 

 

 

 

 

 

 

 

DEN remains asserted for sequential reads from pipelined memory regions.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

BUS LOCK indicates that an atomic read-modify-write operation is in progress.

 

 

 

 

 

 

 

 

 

 

LOCK may be used by the memory subsystem to prevent external agents from

 

 

 

 

 

 

 

 

 

 

H(Z)

 

LOCK

 

accessing memory that is currently involved in an atomic operation (e.g., a

 

 

B(Z)

 

 

 

 

 

 

 

 

 

 

semaphore). LOCK is asserted in the first clock of an atomic operation and de-

 

 

 

 

 

 

 

 

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

asserted when BLAST is deasserted in the last bus cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Datasheet

17

80960HA/HD/HT

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 3 of 4)

 

Name

Type

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HOLD REQUEST signals that an external agent requests access to the

 

 

 

 

 

 

 

 

processor’s address, data, and control buses. When HOLD is asserted, the

 

 

 

 

 

 

 

I

processor:

 

 

 

 

HOLD

Completes the current bus request.

 

 

 

 

S(L)

 

 

 

 

 

 

 

 

 

 

Asserts HOLDA and floats the address, data, and control buses.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When HOLD is deasserted, the HOLDA pin is deasserted and the processor

 

 

 

 

 

 

 

 

reassumes control of the address, data, and control pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

HOLD ACKNOWLEDGE indicates to an external master that the processor has

 

HOLDA

H(1)

relinquished control of the bus. The processor grants HOLD requests and enters

 

the HOLDA state while the RESET pin is asserted.

 

 

 

 

B(0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R(Q)

HOLDA is never granted while

LOCK

is asserted.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS BACKOFF forces the processor to immediately relinquish control of the bus

 

 

 

 

 

 

 

 

on the next clock cycle. When READY/BTERM is enabled and:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

When

BOFF

is asserted, the address, data, and control buses are floated on the

 

BOFF

next clock cycle and the current access is aborted.

 

 

 

 

S(L)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When BOFF is deasserted, the processor resumes by regenerating the aborted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bus access.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

See Figure 16 on page 48 for

BOFF

timing requirements.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

BUS REQUEST indicates that a bus request is pending in the bus controller.

 

BREQ

H(Q)

BREQ does not indicate whether or not the processor is stalled. See BSTALL for

 

B(Q)

processor stall status. BREQ may be used with BSTALL to indicate to an external

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R(0)

bus arbiter the processor’s bus ownership requirements.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

BUS STALL indicates that the processor has stalled pending the result of a

BSTALL

H(Q)

request in the bus controller. When BSTALL is asserted, the processor must

B(Q)

regain bus ownership to continue processing (i.e., it may no longer execute

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R(0)

strictly out of on-chip cache memory).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CYCLE TYPE indicates the type of bus cycle currently being started or processor

 

 

 

 

 

 

 

 

state. CT3:0 encoding follows:

 

 

 

 

 

 

 

 

 

 

 

Cycle Type

ADSCT3:0

 

 

 

 

 

 

 

O

Program-initiated access using 8-bit bus

00000

 

 

 

 

 

 

 

 

 

Program-initiated access using 16-bit bus

00001

 

 

 

 

 

 

 

 

 

H(Z)

 

 

 

CT3:0

Program-initiated access using 32-bit bus

00010

 

 

 

 

 

 

 

 

 

B(Z)

Event-initiated access using 8-bit bus

00100

 

 

 

 

 

 

 

 

 

R(Z)

Event-initiated access using 16-bit bus

00101

 

 

 

 

 

 

 

 

 

 

Event-initiated access using 32-bit bus

00110

 

 

 

 

 

 

 

 

 

 

Reserved

00X11

 

 

 

 

 

 

 

 

Reserved for future products

01XXX

 

 

 

 

 

 

 

 

Reserved

1XXXX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXTERNAL INTERRUPT pins are used to request interrupt service. These pins

 

 

 

 

 

 

 

 

may be configured in three modes:

 

 

 

 

 

 

 

 

 

 

 

Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated

 

 

 

 

 

 

 

I

inputs may be programmed to be level (low or high) or edge (rising or falling)

 

 

 

 

 

 

 

sensitive.

 

 

 

XINT7:0

A(E)

 

 

 

Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt

 

 

 

 

 

 

 

A(L)

 

 

 

 

 

 

 

pins are level sensitive in this mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pins

 

 

 

 

 

 

 

 

Mixed Mode: The

XINT7:5

pins act as dedicated sources and the

XINT4:0

 

 

 

 

 

 

 

 

act as the five most significant bits of a vectored source. The least significant bits

 

 

 

 

 

 

 

 

of the vectored source are set to “010” internally.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.

 

 

NMI

 

 

A(E)

NMI is the highest priority interrupt source. NMI is falling edge triggered.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

Datasheet

80960HA/HD/HT

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 4 of 4)

 

 

Name

Type

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLOCK INPUT provides the time base for the 80960Hx. All internal circuitry is

 

 

 

 

 

 

 

 

 

 

 

 

synchronized to CLKIN. All input and output timings are specified relative to

 

 

CLKIN

I

 

CLKIN.

 

 

 

For the 80960HD, the 2x internal clock is derived by multiplying the CLKIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

frequency by two. For the 80960HT, the 3x internal clock is derived by multiplying

 

 

 

 

 

 

 

 

 

 

 

 

the CLKIN frequency by three.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

RESET forces the device into reset.

RESET

causes all external and internal

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

signals to return to their reset state (when defined). The rising edge of RESET

 

 

A(L)

 

 

 

 

 

 

 

 

 

 

 

 

starts the processor boot sequence.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

SELF TEST, when asserted during the rising edge of

 

causes the

 

 

STEST

RESET,

 

 

S(L)

 

processor to execute its built in self-test.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

FAIL indicates a failure of the processor’s built-in self-test performed during

 

 

 

 

 

 

 

 

 

 

 

initialization. FAIL is asserted immediately out of reset and toggles during self-test

 

 

 

 

 

 

 

 

 

 

H(Q)

 

 

 

 

 

 

FAIL

 

to indicate the status of individual tests. When self-test passes, FAIL is de-

 

 

 

 

 

B(Q)

 

 

 

 

 

 

 

 

 

 

 

 

asserted and the processor branches to the user’s initialization code. When self-

 

 

 

 

 

 

 

 

 

 

R(0)

 

 

 

 

 

 

 

 

 

 

 

 

test fails, the FAIL pin asserts and the processor ceases execution.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ON-CIRCUIT EMULATION control: the processor samples this pin during reset.

 

 

 

 

 

 

 

 

 

 

I

 

When it is asserted low at the end of reset, the processor enters ONCE mode. In

 

 

 

ONCE

 

ONCE mode, the processor stops all clocks and floats all output pins except the

 

 

 

 

 

 

 

 

 

 

 

 

TDO pin. ONCE uses an internal pull-up resistor; see RPU definition in Table 22,

 

 

 

 

 

 

 

 

 

 

 

 

“80960Hx DC Characteristics” on page 40. Pull this pin high when not in use.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCK

I

 

TEST CLOCK provides the clocking function for IEEE 1149.1 Boundary Scan

 

 

 

 

 

 

testing.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

I

 

TEST DATA INPUT is the serial input pin for IEEE 1149.1 Boundary Scan testing.

 

 

 

 

 

 

TDI uses an internal pull-up resistor; see RPU definition in Table 22, “80960Hx DC

 

 

 

 

 

 

 

 

 

 

 

 

Characteristics” on page 40.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

O

 

TEST DATA OUTPUT is the serial output pin for IEEE 1149.1 Boundary Scan

 

 

 

 

 

 

testing. ONCE does not disable this pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST RESET asynchronously resets the Test Access Port (TAP) controller.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRST

 

 

 

 

 

 

 

 

 

 

I

 

must be held low at least 10,000 clock cycles after power-up. One method is to

 

 

 

 

TRST

 

provide TRST with a separate power-on-reset circuit. TRST includes an internal

 

 

 

 

 

 

 

 

 

 

 

 

pull-up resistor; see RPU definition in Table 22, “80960Hx DC Characteristics” on

 

 

 

 

 

 

 

 

 

 

 

 

page 40. Pull this pin low when not in use.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST MODE SELECT is sampled at the rising edge of TCK. TCK controls the

 

 

 

 

 

TMS

I

 

sequence of TAP controller state changes for IEEE 1149.1 Boundary Scan

 

 

 

 

 

 

testing. TMS uses an internal pull-up resistor; see RPU definition in Table 22,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

“80960Hx DC Characteristics” on page 40.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC5

I

 

5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O

 

 

 

 

buffers. Connect this signal to +5 V for use with inputs which exceed 3.3 V. When

 

 

 

 

 

 

 

 

 

 

 

 

all inputs are from 3.3 V components, connect this signal to 3.3 V.

 

 

 

 

 

 

VCCPLL

I

 

PLL VOLTAGE is the +3.3 VDC analog input for the PLL.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOLTAGE DETECT signal allows external system logic to distinguish between a

 

 

 

 

 

 

 

 

 

 

 

 

5 V 80960Cx processor and the 3.3 V 80960Hx processor. This signal is active

 

VOLDET

O

 

low for a 3.3 V 80960Hx (it is high impedance for 5 V 80960Cx). This pin is

 

 

available only on the PGA version.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = 80960Hx

 

 

 

 

 

 

 

 

 

 

 

 

1 = 80960Cx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Datasheet

19

80960HA/HD/HT

3.280960Hx Mechanical Data

3.2.180960Hx PGA Pinout

Figure 2 depicts the complete 80960Hx PGA pinout as viewed from the top side of the component (i.e., pins facing down). Figure 3 shows the complete 80960Hx PGA pinout as viewed from the pin-side of the package (i.e., pins facing up). Table 9 lists the 80960Hx pin names with package location. See Section 4.3, “ Recommended Connections” on page 38 for specifications and recommended connections.

Figure 2. 80960Hx 168-Pin PGA Pinout— View from Top (Pins Facing Down)

 

S R Q P N M L K J H G F E D C B

A

 

1

D25

D24

D21

D19

D17

D16

D15

D13

D12

D11

D9

D8

D7

D5

D3

BOFF

VSS

1

 

 

2

D29

D27

D23

D20

D18

VCC

D14

VCC

VCC

D10

VCC

D6

D4

D2

D1

STEST

FAIL

2

 

 

3

READY

D31

D26

D22

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VCC

D0

NC

ONCE

DP1

DP0

3

 

 

4

HOLDA BTERM D28

 

 

 

 

 

 

 

 

 

 

 

VSS

DP3

DP2

4

 

 

 

 

 

 

 

 

 

 

 

 

 

5

BE3

HOLD

D30

 

 

 

 

 

 

 

 

 

 

 

VCC5

TCK

VOLDET

5

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

VCC

 

 

 

 

 

 

 

 

 

 

 

VCC

TMS

TRST

6

 

BE2

ADS

 

 

 

 

 

 

 

 

 

 

 

 

7

 

VCC

VSS

 

 

 

A80960Hx

 

 

VSS

VCC

TDI

7

 

BE1

 

 

 

 

 

 

8

BLAST

VCC

VSS

 

 

 

 

 

VSS

PCHK

TDO

8

 

 

 

 

 

 

 

9

DEN

BE0

VSS

 

 

i M © 19xx

 

 

 

 

VSS

VCC

NC

9

 

 

 

 

 

 

 

 

10

W/R

VCC

VSS

 

 

 

 

 

 

VSS

VCCPLL

NC

10

11

DT/R

VCC

VSS

 

 

XXXXXXXX SS

 

 

 

 

VSS

VCC

CTO

11

 

 

 

 

 

 

 

 

12

WAIT

BSTALL

SUP

 

 

 

 

 

 

 

 

 

 

 

VSS

VCC

CT1

12

 

 

 

 

 

 

 

 

 

 

 

 

 

13

D/C

BREQ

A30

 

 

 

 

 

 

 

 

 

 

 

CLKIN

NC

CT2

13

 

 

 

 

 

 

 

 

 

 

 

 

 

14

LOCK

A29

A28

 

 

 

 

 

 

 

 

 

 

 

VCC

NC

CT3

14

 

 

 

 

 

 

 

 

 

 

 

 

 

15

A31

A26

A24

A20

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VCC

NMI

XINT4

XINT0

XINT1

15

 

 

16

A27

A23

A21

A19

A16

VCC

A13

VCC

VCC

VCC

A7

VCC

A4

A2

XINT6

XINT3

RESET

16

 

 

17

A25

A22

A18

A17

A15

A14

A12

A11

A10

A9

A8

A6

A5

A3

XINT7

XINT5

XINT2

17

 

 

 

S R Q P N M L K J H G F E D C B

A

 

20

Datasheet

80960HA/HD/HT

Figure 3. 80960Hx 168-Pin PGA Pinout— View from Bottom (Pins Facing Up)

A

B C D E F G H J K L M N P Q R S

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

VSS

BOFF

D3

D5

D7

D8

D9

D11

D12

D13

D15

D16

D17

D19

D21

D24

D25

2

 

D1

D2

D4

D6

VCC

 

 

 

 

 

 

 

 

 

2

FAIL

STEST

D10

VCC

VCC

D14

VCC

D18

D20

D23

D27

D29

3

 

ONCE

 

 

 

 

 

 

 

 

 

 

 

 

 

3

DP0

DP1

NC

D0

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VCC

D22

D26

D31

READY

4

DP3

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

4

DP2

 

 

 

 

 

 

 

 

 

 

 

D28

BTERM HOLDA

5

TCK

VCC5

 

 

 

 

 

 

 

 

 

 

 

 

 

5

VOLDET

 

 

 

 

 

 

 

 

 

 

 

D30

HOLD

BE3

6

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

6

TRST

TMS

 

 

 

 

 

 

 

 

 

 

 

VCC

ADS

BE2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

VCC

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

7

TDI

 

 

 

 

 

 

 

 

 

 

 

VSS

VCC

BE1

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

TDO

PCHK

VSS

 

 

 

 

Package Lid

 

 

 

 

VSS

VCC

BLAST

9

 

 

 

 

 

 

 

 

 

 

 

 

9

VCC

VSS

 

 

 

 

 

 

 

 

 

 

 

VSS

 

NC

 

 

 

 

 

 

 

 

 

 

 

BE0

DEN

10

VCCPLL

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

10

NC

 

 

 

 

 

 

 

 

 

 

 

VSS

VCC

W/R

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

CT0

VCC

VSS

 

 

 

 

 

 

 

 

 

 

 

VSS

VCC

DT/R

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

CT1

VCC

VSS

 

 

 

 

 

 

 

 

 

 

 

SUP

BSTALL

WAIT

13

 

CLKIN

 

 

 

 

 

 

 

 

 

 

 

 

 

13

CT2

NC

 

 

 

 

 

 

 

 

 

 

 

A30

BREQ

D/C

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

CT3

NC

VCC

 

 

 

 

 

 

 

 

 

 

 

A28

A29

LOCK

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

XINT1

XINT0

XINT4

NMI

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VCC

A20

A24

A26

A31

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A23

16

RESET

XINT3

XINT6

A2

A4

VCC

A7

VCC

VCC

VCC

A13

VCC

A16

A19

A21

A27

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

17

XINT2

XINT5

XINT7

A3

A5

A6

A8

A9

A10

A11

A12

A14

A15

A17

A18

A22

A25

A

B C D E F G H J K L M N P Q R S

Datasheet

21

80960HA/HD/HT

Table 8. 80960Hx 168-Pin PGA Pinout— Signal Name Order (Sheet 1 of 2)

Signal Name

PGA

Signal Name

PGA

Signal Name

PGA

Signal Name

PGA

Pin

Pin

Pin

Pin

 

 

 

 

 

 

 

 

 

 

 

 

A2

D16

ADS

R6

D14

L2

LOCK

S14

 

 

 

 

 

 

 

 

A3

D17

BE0

R9

D15

L1

NC

A9

 

 

 

 

 

 

 

 

A4

E16

BE1

S7

D16

M1

NC

A10

 

 

 

 

 

 

 

 

A5

E17

BE2

S6

D17

N1

NC

B13

 

 

 

 

 

 

 

 

A6

F17

BE3

S5

D18

N2

NC

B14

 

 

 

 

 

 

 

 

A7

G16

BLAST

S8

D19

P1

NC

D3

 

 

 

 

 

 

 

 

A8

G17

BOFF

B1

D20

P2

NMI

D15

 

 

 

 

 

 

 

 

A9

H17

BREQ

R13

D21

Q1

ONCE

C3

 

 

 

 

 

 

 

 

A10

J17

BSTALL

R12

D22

P3

PCHK

B8

 

 

 

 

 

 

 

 

A11

K17

BTERM

R4

D23

Q2

READY

S3

 

 

 

 

 

 

 

 

A12

L17

CLKIN

C13

D24

R1

RESET

A16

 

 

 

 

 

 

 

 

A13

L16

CT0

A11

D25

S1

STEST

B2

 

 

 

 

 

 

 

 

A14

M17

CT1

A12

D26

Q3

SUP

Q12

 

 

 

 

 

 

 

 

A15

N17

CT2

A13

D27

R2

TCK

B5

 

 

 

 

 

 

 

 

A16

N16

CT3

A14

D28

Q4

TDI

A7

 

 

 

 

 

 

 

 

A17

P17

D/C

S13

D29

S2

TDO

A8

 

 

 

 

 

 

 

 

A18

Q17

D0

E3

D30

Q5

TMS

B6

 

 

 

 

 

 

 

 

A19

P16

D1

C2

D31

R3

TRST

A6

 

 

 

 

 

 

 

 

A20

P15

D2

D2

DEN

S9

VCC

B7

A21

Q16

D3

C1

DP0

A3

VCC

B9

A22

R17

D4

E2

DP1

B3

VCC

B11

A23

R16

D5

D1

DP2

A4

VCC

B12

A24

Q15

D6

F2

DP3

B4

VCC

C6

A25

S17

D7

E1

DT/R

S11

VCC

C14

A26

R15

D8

F1

FAIL

A2

VCC

E15

A27

S16

D9

G1

VCC

F3

A28

Q14

D10

H2

VCC

F16

A29

R14

D11

H1

VCC

G2

A30

Q13

D12

J1

HOLD

R5

VCC

H16

A31

S15

D13

K1

HOLDA

S4

VCC

J2

22

Datasheet

80960HA/HD/HT

Table 8. 80960Hx 168-Pin PGA Pinout— Signal Name Order (Sheet 2 of 2)

Signal Name

PGA

Signal Name

PGA

Signal Name

PGA

Signal Name

PGA

Pin

Pin

Pin

Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

J16

VCCPLL

B10

VSS

H3

 

VSS

Q10

VCC

K2

VOLDET

A5

VSS

H15

 

VSS

Q11

VCC

K16

VSS

A1

VSS

J3

 

W/R

S10

VCC

M2

VSS

C4

VSS

J15

 

WAIT

S12

VCC

M16

VSS

C7

VSS

K3

 

XINT0

B15

VCC

N3

VSS

C8

VSS

K15

 

XINT1

A15

VCC

N15

VSS

C9

VSS

L3

 

XINT2

A17

VCC

Q6

VSS

C10

VSS

L15

 

XINT3

B16

VCC

R7

VSS

C11

VSS

M3

 

XINT4

C15

VCC

R8

VSS

C12

VSS

M15

 

XINT5

B17

VCC

R10

VSS

F15

VSS

Q7

 

XINT6

C16

VCC

R11

VSS

G3

VSS

Q8

 

XINT7

C17

VCC5

C5

VSS

G15

VSS

Q9

 

Datasheet

23

80960HA/HD/HT

Table 9. 80960Hx 168-Pin PGA Pinout— Pin Number Order (Sheet 1 of 2)

PGA

Signal Name

PGA

Signal Name

PGA

Signal Name

PGA

Signal Name

Pin

Pin

Pin

Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

 

VSS

B14

 

 

 

NC

E15

VCC

K15

VSS

A2

 

 

 

 

 

 

 

 

 

 

B15

 

 

 

 

 

 

 

E16

A4

K16

VCC

 

 

 

FAIL

 

 

 

 

 

 

 

 

XINT0

 

 

A3

 

 

 

DP0

B16

 

 

 

 

 

 

 

E17

A5

K17

A11

 

 

 

 

XINT3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A4

 

 

 

DP2

B17

 

 

 

 

 

 

 

F1

D8

L1

D15

 

 

 

 

XINT5

 

 

 

 

 

 

 

 

 

 

 

 

 

A5

VOLDET

C1

 

 

 

D3

F2

D6

L2

D14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

 

 

 

 

 

 

 

 

 

 

C2

 

 

 

D1

F3

VCC

L3

VSS

 

 

TRST

 

 

 

 

 

 

 

 

A7

 

 

 

TDI

C3

 

 

 

 

 

 

 

F15

VSS

L15

VSS

 

 

 

 

ONCE

 

A8

 

 

TDO

C4

 

 

 

VSS

F16

VCC

L16

A13

A9

 

 

 

NC

C5

 

 

VCC5

F17

A6

L17

A12

 

 

 

 

 

 

 

 

 

 

 

 

 

A10

 

 

 

NC

C6

 

 

VCC

G1

D9

M1

D16

A11

 

 

 

CT0

C7

 

 

 

VSS

G2

VCC

M2

VCC

A12

 

 

 

CT1

C8

 

 

 

VSS

G3

VSS

M3

VSS

A13

 

 

 

CT2

C9

 

 

 

VSS

G15

VSS

M15

VSS

A14

 

 

 

CT3

C10

 

 

 

VSS

G16

A7

M16

VCC

A15

 

 

 

 

 

 

 

 

 

 

C11

 

 

 

VSS

G17

A8

M17

A14

 

 

XINT1

 

 

 

 

 

A16

 

 

 

 

 

 

 

 

 

 

C12

 

 

 

VSS

H1

D11

N1

D17

 

RESET

 

 

 

 

A17

 

 

 

 

 

 

 

 

 

 

C13

CLKIN

H2

D10

N2

D18

 

 

XINT2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B1

 

 

 

 

 

 

 

 

 

 

C14

 

 

VCC

H3

VSS

N3

VCC

 

 

BOFF

 

 

 

 

B2

 

STEST

C15

 

 

 

 

 

 

 

H15

VSS

N15

VCC

 

 

 

XINT4

 

B3

 

 

 

DP1

C16

 

 

 

 

 

 

 

H16

VCC

N16

A16

 

 

 

 

XINT6

 

B4

 

 

 

DP3

C17

 

 

 

 

 

 

 

H17

A9

N17

A15

 

 

 

 

XINT7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B5

 

 

 

TCK

D1

 

 

 

D5

J1

D12

P1

D19

 

 

 

 

 

 

 

 

 

 

 

 

 

B6

 

 

TMS

D2

 

 

 

D2

J2

VCC

P2

D20

B7

 

 

 

VCC

D3

 

 

 

NC

J3

VSS

P3

D22

B8

 

 

 

 

 

 

 

 

 

 

D15

 

 

 

 

 

 

 

J15

VSS

P15

A20

 

 

PCHK

 

 

 

 

NMI

 

B9

 

 

 

VCC

D16

 

 

 

A2

J16

VCC

P16

A19

B10

VCCPLL

D17

 

 

 

A3

J17

A10

P17

A17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B11

 

 

 

VCC

E1

 

 

 

D7

K1

D13

Q1

D21

B12

 

 

 

VCC

E2

 

 

 

D4

K2

VCC

Q2

D23

B13

 

 

 

NC

E3

 

 

 

D0

K3

VSS

Q3

D26

24

Datasheet

80960HA/HD/HT

Table 9. 80960Hx 168-Pin PGA Pinout— Pin Number Order (Sheet 2 of 2)

PGA

Signal Name

PGA

Signal Name

PGA

Signal Name

PGA

Signal Name

Pin

Pin

Pin

Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q4

 

D28

Q16

 

 

 

A21

R11

 

 

VCC

S6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BE2

 

 

 

 

 

 

 

Q5

 

D30

Q17

 

 

 

A18

R12

BSTALL

S7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q6

 

VCC

R1

 

 

 

D24

R13

 

BREQ

S8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BLAST

 

Q7

 

VSS

R2

 

 

 

D27

R14

 

 

A29

S9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEN

 

 

 

 

Q8

 

VSS

R3

 

 

 

D31

R15

 

 

A26

S10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W/R

 

 

 

 

Q9

 

VSS

R4

 

 

 

 

 

 

 

R16

 

 

A23

S11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BTERM

 

 

 

 

 

 

DT/R

 

 

 

Q10

 

VSS

R5

 

HOLD

R17

 

 

A22

S12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WAIT

 

 

Q11

 

VSS

R6

 

 

 

 

 

 

 

S1

 

 

D25

S13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADS

 

 

 

 

 

 

 

 

D/C

 

 

Q12

 

 

 

R7

 

 

 

VCC

S2

 

 

D29

S14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SUP

 

 

 

 

 

 

 

 

LOCK

 

Q13

 

A30

R8

 

 

 

VCC

S3

 

 

 

 

 

S15

 

 

 

 

 

A31

 

 

 

 

 

READY

 

 

 

 

 

 

Q14

 

A28

R9

 

 

 

 

 

 

 

S4

 

HOLDA

S16

 

 

 

 

 

A27

 

 

 

 

BE0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q15

 

A24

R10

 

 

 

VCC

S5

 

 

 

 

 

S17

 

 

 

 

 

A25

 

 

 

 

 

 

BE3

 

 

 

 

 

 

Datasheet

25

80960HA/HD/HT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.2.2

80960Hx PQ4 Pinout

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4. 80960Hx 208-Pin PQ4 Pinout

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN 156

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN 105

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SS SS CC

CC SS

CC

SS

A5

A6

A7

CC

SS

CC

SS

 

CC

SS

SS

CC

A16

A17

A18

 

A19

CC

SS

A20

A21

A22

A23

CC

SS

CC SS

A24

A25

A26

A27

CC

SS

A28

A29

A30

 

 

 

V V V

V V A2 A3

V

V A4

V

V A8 A9 A10

A11 V

V A12 A13 A14 A15

V

V

V

V

 

V

V

V

V

V V

V V

PIN 104

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN 157

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A31

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

NMI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

XINT7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

XINT6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BREQ

 

XINT5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOCK

 

XINT4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SUP

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D/C

 

XINT3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

XINT2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

XINT1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

XINT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BSTALL

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WAIT

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DT/R

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W/R

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

CLKIN

 

 

 

 

 

 

 

 

 

 

i960

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

VCC

 

 

 

 

 

 

 

 

 

 

®

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEN

 

VCCPLL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BLAST

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BE0

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BE1

 

CT3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

CT2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

CT1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BE2

 

CT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BE3

 

VSS

 

 

 

 

 

 

 

 

 

 

i

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADS

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

VSS

 

 

 

 

 

 

 

 

 

 

FC80960Hx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

PCHK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HOLDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

XXXXXXXX SS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

TDI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

TMS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HOLD

 

TRST

 

 

 

 

 

 

 

 

 

 

 

M © 19xx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READY

 

TCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BTERM

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

VCC5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D31

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D30

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D29

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D28

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

DP3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

DP2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D27

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D26

 

DP0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D25

 

DP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D24

 

STEST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

PIN 208

CC

SS SS CC

SS

SS

CC

CC

 

 

 

 

SS CC SS CC

 

SS

CC

 

 

 

SS

CC SS

CC

 

 

 

 

 

CC

 

 

 

 

SS CC

D20

 

CC

SS

SS CC

 

 

 

 

PIN 53

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

V V V

FAIL ONCE V V V

BOFF V

D0

D1

D2

D3

V V V V

D4 D5

D6 D7 V

V D8

D9

D10

D11

V

V V

V

D12

D13

D14

D15

V

D16

D17

D18

D19

V V

V V V V

D21

D22

D23

 

 

 

 

 

 

 

PIN 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN 52

26

Datasheet

80960HA/HD/HT

Table 10. 80960Hx PQ4 Pinout— Signal Name Order (Sheet 1 of 2)

Signal Name

PQ4

Signal Name

PQ4

Signal Name

PQ4

Signal Name

PQ4

Pin

Pin

Pin

Pin

 

 

 

 

 

 

 

 

 

 

 

 

A2

151

BE0

83

D16

39

PCHK

189

 

 

 

 

 

 

 

 

A3

150

BE1

82

D17

40

READY

68

 

 

 

 

 

 

 

 

A4

147

BE2

79

D18

41

RESET

174

 

 

 

 

 

 

 

 

A5

146

BE3

78

D19

42

STEST

208

 

 

 

 

 

 

 

 

A6

145

BLAST

84

D20

45

SUP

97

 

 

 

 

 

 

 

 

A7

144

BOFF

10

D21

50

TCK

194

 

 

 

 

 

 

 

 

A8

141

BREQ

100

D22

51

TDI

191

 

 

 

 

 

 

 

 

A9

140

BSTALL

91

D23

52

TDO

188

 

 

 

 

 

 

 

 

A10

139

BTERM

67

D24

54

TMS

192

 

 

 

 

 

 

 

 

A11

138

CLKIN

175

D25

55

TRST

193

 

 

 

 

 

 

 

 

A12

135

CT0

183

D26

56

VCC

1

A13

134

CT1

182

D27

57

VCC

4

A14

133

CT2

181

D28

61

VCC

9

A15

132

CT3

180

D29

62

VCC

11

A16

127

D/C

96

D30

63

VCC

17

A17

126

D0

12

D31

64

VCC

19

A18

125

D1

13

DEN

85

VCC

25

A19

124

D2

14

DP0

206

VCC

31

A20

121

D3

15

DP1

207

VCC

33

A21

120

D4

20

DP2

203

VCC

38

A22

119

D5

21

DP3

202

VCC

44

A23

118

D6

22

DT/R

89

VCC

46

A24

113

D7

23

FAIL

5

VCC

49

A25

112

D8

26

VCC

59

A26

111

D9

27

VCC

60

A27

110

D10

28

VCC

66

A28

107

D11

29

HOLD

69

VCC

71

A29

106

D12

34

HOLDA

72

VCC

74

A30

105

D13

35

LOCK

99

VCC

76

A31

104

D14

36

NMI

159

VCC

81

ADS

77

D15

37

ONCE

6

VCC

87

Datasheet

27

80960HA/HD/HT

Table 10. 80960Hx PQ4 Pinout— Signal Name Order (Sheet 2 of 2)

Signal Name

PQ4

Signal Name

PQ4

Signal Name

PQ4

Signal Name

PQ4

Pin

Pin

Pin

Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

92

VCC

187

VSS

70

 

 

VSS

164

VCC

95

VCC

196

VSS

73

 

 

VSS

170

VCC

101

VCC

199

VSS

75

 

 

VSS

172

VCC

102

VCC

201

VSS

80

 

 

VSS

178

VCC

109

VCC

204

VSS

86

 

 

VSS

184

VCC

115

VCC5

197

VSS

93

 

 

VSS

186

VCC

117

VCCPLL

177

VSS

94

 

 

VSS

190

VCC

123

VSS

2

VSS

98

 

 

VSS

195

VCC

128

VSS

3

VSS

103

 

 

VSS

198

VCC

131

VSS

7

VSS

108

 

 

VSS

200

VCC

137

VSS

8

VSS

114

 

 

VSS

205

VCC

143

VSS

16

VSS

116

 

 

W/R

88

VCC

149

VSS

18

VSS

122

 

WAIT

90

VCC

153

VSS

24

VSS

129

 

XINT0

169

VCC

154

VSS

30

VSS

130

 

XINT1

168

VCC

158

VSS

32

VSS

136

 

XINT2

167

VCC

165

VSS

43

VSS

142

 

XINT3

166

VCC

171

VSS

47

VSS

148

 

XINT4

163

VCC

173

VSS

48

VSS

152

 

XINT5

162

VCC

176

VSS

53

VSS

155

 

XINT6

161

VCC

179

VSS

58

VSS

156

 

XINT7

160

VCC

185

VSS

65

VSS

157

 

 

28

Datasheet

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

80960HA/HD/HT

Table 11. 80960Hx PQ4 Pinout—

Pin Number Order (Sheet 1 of 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PQ4

Signal Name

 

PQ4

Signal Name

PQ4

Signal Name

PQ4

Signal Name

 

Pin

 

Pin

Pin

Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

VCC

 

31

VCC

61

 

 

 

 

 

 

D28

91

BSTALL

 

2

 

 

 

VSS

 

32

VSS

62

 

 

 

 

 

 

D29

92

 

 

VCC

 

3

 

 

 

VSS

 

33

VCC

63

 

 

 

 

 

 

D30

93

 

 

VSS

 

4

 

 

 

VCC

 

34

D12

64

 

 

 

 

 

 

D31

94

 

 

VSS

 

5

 

 

 

 

 

 

 

 

35

D13

65

 

 

 

 

 

 

VSS

95

 

 

VCC

 

 

 

 

FAIL

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

36

D14

66

 

 

 

 

 

 

VCC

96

 

 

 

 

 

 

 

 

 

ONCE

 

 

 

 

 

 

 

 

 

 

D/C

 

 

 

 

7

 

 

 

VSS

 

37

D15

67

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

97

 

 

 

 

 

 

 

 

 

 

 

 

 

BTERM

 

 

 

SUP

 

 

 

8

 

 

 

VSS

 

38

VCC

68

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

98

 

 

VSS

 

 

 

 

 

 

READY

 

 

 

 

9

 

 

 

VCC

 

39

D16

69

 

 

HOLD

99

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOCK

 

 

10

 

 

 

 

 

 

 

 

40

D17

70

 

 

 

 

 

 

VSS

100

BREQ

 

 

 

BOFF

 

 

 

 

 

 

 

 

 

11

 

 

 

VCC

 

41

D18

71

 

 

 

 

 

 

VCC

101

 

 

VCC

 

12

 

 

 

D0

 

42

D19

72

 

HOLDA

102

 

 

VCC

 

13

 

 

 

D1

 

43

VSS

73

 

 

 

 

 

 

VSS

103

 

 

VSS

 

14

 

 

 

D2

 

44

VCC

74

 

 

 

 

 

 

VCC

104

 

 

A31

 

15

 

 

 

D3

 

45

D20

75

 

 

 

 

 

 

VSS

105

 

 

A30

 

16

 

 

 

VSS

 

46

VCC

76

 

 </