Intel 8086, 8086-1, 8086-2 User Manual

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8086

16-BIT HMOS MICROPROCESSOR

8086/8086-2/8086-1

Direct Addressing Capability 1 MByte of Memory

Architecture Designed for Powerful Assembly Language and Efficient High Level Languages

14 Word, by 16-Bit Register Set with Symmetrical Operations

24 Operand Addressing Modes

Bit, Byte, Word, and Block Operations

8 and 16-Bit Signed and Unsigned Arithmetic in Binary or Decimal

Range of Clock Rates: 5 MHz for 8086, 8 MHz for 8086-2,

10 MHz for 8086-1

MULTIBUS System Compatible Interface

Available in EXPRESS Ð Standard Temperature Range Ð Extended Temperature Range

Available in 40-Lead Cerdip and Plastic Package

(See Packaging Spec. OrderÝ231369)

Including Multiply and Divide

The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations to achieve high performance levels.

40 Lead

Figure 2. 8086 Pin

Configuration

Figure 1. 8086 CPU Block Diagram

September 1990 Order Number: 231455-005

231455– 1

231455– 2

8086

Table 1. Pin Description

The following pin function descriptions are for 8086 systems in either minimum or maximum mode. The ‘‘Local Bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional bus buffers).

Symbol Pin No. Type Name and Function

AD15–AD02–16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed

memory/IO address (T analogous to BHE LOW during T of the bus in memory or I/O operations. Eight-bit oriented devices tied

to the lower half would normally use A functions. (See BHE.) These lines are active HIGH and float to 3-state

), and data (T2,T3,TW,T4) bus. A0is

for the lower byte of the data bus, pins D7–D0.Itis

when a byte is to be transferred on the lower portion

to condition chip select

OFF during interrupt acknowledge and local bus ‘‘hold acknowledge’’.

A19/S6, 35–38 O ADDRESS/STATUS: During T1these are the four most significant A

18/S5

17/S4

16/S3

, ,

address lines for memory operations. During I/O operations these lines are LOW. During memory and I/O operations, status information is available on these lines during T interrupt enable FLAG bit (S5) is updated at the beginning of each

2,T3,TW,T4

. The status of the

CLK cycle. A17/S4and A16/S3are encoded as shown. This information indicates which relocation register is presently being used for data accessing. These lines float to 3-state OFF during local bus ‘‘hold acknowledge.’’

A17/S

A16/S

Characteristics

0 (LOW) 0 Alternate Data 0 1 Stack 1 (HIGH) 0 Code or None 1 1 Data S6is 0 (LOW)

BHE/S

34 O BUS HIGH ENABLE/STATUS: During T1the bus high enable signal

) should be used to enable data onto the most significant half of

(BHE the data bus, pins D half of the bus would normally use BHE to condition chip select functions. BHE

is LOW during T1for read, write, and interrupt

. Eight-bit oriented devices tied to the upper

15–D8

acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S T

, and T4. The signal is active LOW, and floats to 3-state OFF in

‘‘hold’’. It is LOW during T

BHE A

status information is available during T2,

for the first interrupt acknowledge cycle.

Characteristics

0 0 Whole word 0 1 Upper byte from/to odd address 1 0 Lower byte from/to even address 1 1 None

RD 32 O READ: Read strobe indicates that the processor is performing a

memory or I/O read cycle, depending on the state of the S signal is used to read devices which reside on the 8086 local bus. RD

pin. This

is active LOW during T2,T3and TWof any read cycle, and is guaranteed to remain HIGH in T

until the 8086 local bus has floated.

This signal floats to 3-state OFF in ‘‘hold acknowledge’’.

8086

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

READY 22 I READY: is the acknowledgement from the addressed memory or I/O

INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled

TEST 23 I TEST: input is examined by the ‘‘Wait’’ instruction. If the TEST input is

NMI 17 I NON-MASKABLE INTERRUPT: an edge triggered input which causes

RESET 21 I RESET: causes the processor to immediately terminate its present

CLK 19 I CLOCK: provides the basic timing for the processor and bus controller.

40 VCC:a5V power supply pin.

GND 1, 20 GROUND

MN/MX 33 I MINIMUM/MAXIMUM: indicates what mode the processor is to

device that it will complete the data transfer. The READY signal from memory/IO is synchronized by the 8284A Clock Generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met.

during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

LOW execution continues, otherwise the processor waits in an ‘‘Idle’’ state. This input is synchronized internally during each clock cycle on the leading edge of CLK.

a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.

activity. The signal must be active HIGH for at least four clock cycles. It restarts execution, as described in the Instruction Set description, when RESET returns LOW. RESET is internally synchronized.

It is asymmetric with a 33% duty cycle to provide optimized internal timing.

operate in. The two modes are discussed in the following sections.

The following pin function descriptions are for the 8086/8288 system in maximum mode (i.e., MN/MXeVSS). Only the pin functions which are unique to maximum mode are described; all other pin functions are as described above.

S2,S1,S026–28 O STATUS: active during T4,T1, and T2and is returned to the passive state

(1, 1, 1) during T by the 8288 Bus Controller to generate all memory and I/O access control signals. Any change by S beginning of a bus cycle, and the return to the passive state in T used to indicate the end of a bus cycle.

or during TWwhen READY is HIGH. This status is used

,orS0during T4is used to indicate the

2,S1

or TWis

8086

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

S2,S1,S

(Continued)

RQ/GT0, 30, 31 I/O REQUEST/GRANT: pins are used by other local bus masters to force RQ

/GT

LOCK 29 O LOCK: output indicates that other system bus masters are not to gain

26–28 O These signals float to 3-state OFF in ‘‘hold acknowledge’’. These status

lines are encoded as shown.

Characteristics

0 (LOW) 0 0 Interrupt Acknowledge 0 0 1 Read I/O Port 0 1 0 Write I/O Port 0 1 1 Halt 1 (HIGH) 0 0 Code Access 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 Passive

the processor to release the local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0having higher priority than RQ

/GT1.RQ/GT pins have internal pull-up resistors and may be left unconnected. The request/grant sequence is as follows (see Page 2-24):

1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (‘‘hold’’) to the 8086 (pulse 1).

2. During a T4or T1clock cycle, a pulse 1 CLK wide from the 8086 to the requesting master (pulse 2), indicates that the 8086 has allowed the local bus to float and that it will enter the ‘‘hold acknowledge’’ state at the next CLK. The CPU’s bus interface unit is disconnected logically from the local bus during ‘‘hold acknowledge’’.

3. A pulse 1 CLK wide from the requesting master indicates to the 8086 (pulse 3) that the ‘‘hold’’ request is about to end and that the 8086 can reclaim the local bus at the next CLK. Each master-master exchange of the local bus is a sequence of 3 pulses. There must be one dead CLK cycle after each bus exchange. Pulses are active LOW. If the request is made while the CPU is performing a memory cycle, it will release the local bus during T conditions are met:

1. Request occurs on or before T

of the cycle when all the following

2. Current cycle is not the low byte of a word (on an odd address).

3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A locked instruction is not currently executing.

If the local bus is idle when the request is made the two possible events will follow:

1. Local bus will be released during the next clock.

2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied.

control of the system bus while LOCK

is active LOW. The LOCK signal is activated by the ‘‘LOCK’’ prefix instruction and remains active until the completion of the next instruction. This signal is active LOW, and floats to 3-state OFF in ‘‘hold acknowledge’’.

8086

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

QS1,QS024, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after

which the queue operation is performed. QS

and QS0provide status to allow external tracking of the internal

8086 instruction queue.

Characteristics

0 (LOW) 0 No Operation 0 1 First Byte of Op Code from Queue 1 (HIGH) 0 Empty the Queue 1 1 Subsequent Byte from Queue

The following pin function descriptions are for the 8086 in minimum mode (i.e., MN/MXeVCC). Only the pin functions which are unique to minimum mode are described; all other pin functions are as described above.

M/IO 28 O STATUS LINE: logically equivalent to S2in the maximum mode. It is used to

distinguish a memory access from an I/O access. M/IO

preceding a bus cycle and remains valid until the final T4of the cycle

the T

HIGH, IOeLOW). M/IO floats to 3-state OFF in local bus ‘‘hold

becomes valid in

acknowledge’’.

WR 29 O WRITE: indicates that the processor is performing a write memory or write

I/O cycle, depending on the state of the M/IO and TWof any write cycle. It is active LOW, and floats to 3-state OFF in

signal. WR is active for T2,T

local bus ‘‘hold acknowledge’’.

INTA 24 O INTA: is used as a read strobe for interrupt acknowledge cycles. It is active

LOW during T

and TWof each interrupt acknowledge cycle.

2,T3

ALE 25 O ADDRESS LATCH ENABLE: provided by the processor to latch the

address into the 8282/8283 address latch. It is a HIGH pulse active during T

of any bus cycle. Note that ALE is never floated.

DT/R 27 O DATA TRANSMIT/RECEIVE: needed in minimum system that desires to

use an 8286/8287 data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically DT/R maximum mode, and its timing is the same as for M/IO

is equivalent to S1in the

.(TeHIGH, R

LOW.) This signal floats to 3-state OFF in local bus ‘‘hold acknowledge’’.

DEN 26 O DATA ENABLE: provided as an output enable for the 8286/8287 in a

minimum system which uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles. For a read or INTA it is active from the middle of T it is active from the beginning of T state OFF in local bus ‘‘hold acknowledge’’.

until the middle of T4, while for a write cycle

until the middle of T4. DEN floats to 3-

cycle

HOLD, 31, 30 I/O HOLD: indicates that another master is requesting a local bus ‘‘hold.’’ To be HLDA

acknowledged, HOLD must be active HIGH. The processor receiving the ‘‘hold’’ request will issue HLDA (HIGH) as an acknowledgement in the middle of a T4or Ticlock cycle. Simultaneous with the issuance of HLDA the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor will LOWer the HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines. Hold acknowledge (HLDA) and HOLD have internal pull-up resistors. The same rules as for RQ

/GT apply regarding when the local bus will be released. HOLD is not an asynchronous input. External synchronization should be provided if the system cannot otherwise guarantee the setup time.

8086

FUNCTIONAL DESCRIPTION

General Operation

The internal functions of the 8086 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the block diagram of Figure 1.

These units can interact directly but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution.

The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently. Whenever there is space for at least 2 bytes in the queue, the BIU will attempt a word fetch memory cycle. This greatly reduces ‘‘dead time’’ on the memory bus. The queue acts as a First-In-First-Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU.

The execution unit receives pre-fetched instructions from the BIU queue and provides un-relocated operand addresses to the BIU. Memory operands are passed through the BIU for processing by the EU, which passes results to the BIU for storage. See the Instruction Set description for further register set and architectural descriptions.

MEMORY ORGANIZATION

The processor provides a 20-bit address to memory which locates the byte being referenced. The memory is organized as a linear array of up to 1 million

bytes, addressed as 00000(H) to FFFFF(H). The memory is logically divided into code, data, extra data, and stack segments of up to 64K bytes each, with each segment falling on 16-byte boundaries. (See Figure 3a.)

All memory references are made relative to base addresses contained in high speed segment registers. The segment types were chosen based on the addressing needs of programs. The segment register to be selected is automatically chosen according to the rules of the following table. All information in one segment type share the same logical attributes (e.g. code or data). By structuring memory into relocatable areas of similar characteristics and by automatically selecting segment registers, programs are shorter, faster, and more structured.

Word (16-bit) operands can be located on even or odd address boundaries and are thus not constrained to even boundaries as is the case in many 16-bit computers. For address and data operands, the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location. The BIU automatically performs the proper number of memory accesses, one if the word operand is on an even byte boundary and two if it is on an odd byte boundary. Except for the performance penalty, this double access is transparent to the software. This performance penalty does not occur for instruction fetches, only word operands.

Physically, the memory is organized as a high bank (D bytes addressed in parallel by the processor’s address lines A is transferred on the D dressed byte data (A D able signals, BHE

) and a low bank (D7–D0) of 512K 8-bit

15–D8

. Byte data with even addresses

19–A1

bus lines. The processor provides two en-

15–D8

and A0, to selectively allow read-

bus lines while odd ad-

7–D0

HIGH) is transferred on the

ing from or writing into either an odd byte location, even byte location, or both. The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary.

Memory Segment Register Segment

Reference Need Used Selection Rule

Instructions CODE (CS) Automatic with all instruction prefetch.

Stack STACK (SS) All stack pushes and pops. Memory references relative to BP

base register except data references.

Local Data DATA (DS) Data references when: relative to stack, destination of string

operation, or explicitly overridden.

External (Global) Data EXTRA (ES) Destination of string operations: explicitly selected using a

segment override.

231455– 3

Figure 3a. Memory Organization

In referencing word data the BIU requires one or two memory cycles depending on whether or not the starting byte of the word is on an even or odd address, respectively. Consequently, in referencing word operands performance can be optimized by locating data on even address boundaries. This is an especially useful technique for using the stack, since odd address references to the stack may adversely affect the context switching time for interrupt processing or task multiplexing.

8086

address FFFF0H through FFFFFH are reserved for operations including a jump to the initial program loading routine. Following RESET, the CPU will always begin execution at location FFFF0H where the jump must be. Locations 00000H through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt types has its service routine pointed to by a 4-byte pointer element consisting of a 16-bit segment address and a 16-bit offset address. The pointer elements are assumed to have been stored at the respective places in reserved memory prior to occurrence of interrupts.

MINIMUM AND MAXIMUM MODES

The requirements for supporting minimum and maximum 8086 systems are sufficiently different that they cannot be done efficiently with 40 uniquely defined pins. Consequently, the 8086 is equipped with a strap pin (MN/MX figuration. The definition of a certain subset of the pins changes dependent on the condition of the strap pin. When MN/MX 8086 treats pins 24 through 31 in maximum mode. An 8288 bus controller interprets status information coded into S control signals compatible with the MULTIBUS architecture. When the MN/MX the 8086 generates bus control signals itself on pins 24 through 31, as shown in parentheses in Figure 2. Examples of minimum mode and maximum mode systems are shown in Figure 4.

BUS OPERATION

The 8086 has a combined address and data bus commonly referred to as a time multiplexed bus. This technique provides the most efficient use of pins on the processor while permitting the use of a standard 40-lead package. This ‘‘local bus’’ can be buffered directly and used throughout the system with address latching provided on memory and I/O modules. In addition, the bus can also be demultiplexed at the processor with a single set of address latches if a standard non-multiplexed bus is desired for the system.

) which defines the system con-

pin is strapped to GND, the

0,S2,S2

to generate bus timing and

pin is strapped to VCC,

231455– 4

Figure 3b. Reserved Memory Locations

Certain locations in memory are reserved for specific CPU operations (see Figure 3b). Locations from

Each processor bus cycle consists of at least four CLK cycles. These are referred to as T

(see Figure 5). The address is emitted from the

processor during T bus during T ing the direction of the bus during read operations. In

and data transfer occurs on the

and T4.T2is used primarily for chang-

1,T2,T3

and

the event that a ‘‘NOT READY’’ indication is given by the addressed device, ‘‘Wait’’ states (T serted between T state is of the same duration as a CLK cycle. Periods

and T4. Each inserted ‘‘Wait’’

) are in-

8086

231455– 5

Figure 4a. Minimum Mode 8086 Typical Configuration

231455– 6

Figure 4b. Maximum Mode 8086 Typical Configuration

8086

can occur between 8086 bus cycles. These are referred to as ‘‘Idle’’ states (T The processor uses these cycles for internal house-

) or inactive CLK cycles.

keeping.

During T1of any bus cycle the ALE (Address Latch Enable) signal is emitted (by either the processor or the 8288 bus controller, depending on the MN/MX strap). At the trailing edge of this pulse, a valid address and certain status information for the cycle may be latched.

Status bits S mode, by the bus controller to identify the type of

, and S2are used, in maximum

0,S1

bus transaction according to the following table:

S1S

Characteristics

0 (LOW) 0 0 Interrupt Acknowledge

0 0 1 Read I/O

0 1 0 Write I/O

0 1 1 Halt

1 (HIGH) 0 0 Instruction Fetch

1 0 1 Read Data from Memory

1 1 0 Write Data to Memory

1 1 1 Passive (no bus cycle)

Figure 5. Basic System Timing

231455– 8

8086

Status bits S3through S7are multiplexed with highorder address bits and the BHE therefore valid during T cate which segment register (see Instruction Set de-

through T4.S3and S4indi-

signal, and are

scription) was used for this bus cycle in forming the address, according to the following table:

Characteristics

0 (LOW) 0 Alternate Data (extra segment)

0 1 Stack

1 (HIGH) 0 Code or None

1 1 Data

S5is a reflection of the PSW interrupt enable bit.

0 and S7is a spare status bit.

I/O ADDRESSING

In the 8086, I/O operations can address up to a maximum of 64K I/O byte registers or 32K I/O word registers. The I/O address appears in the same format as the memory address on bus lines A The address lines A tions. The variable I/O instructions which use regis-

are zero in I/O opera-

19–A16

15–A0

ter DX as a pointer have full address capability while the direct I/O instructions directly address one or two of the 256 I/O byte locations in page 0 of the I/O address space.

I/O ports are addressed in the same manner as memory locations. Even addressed bytes are transferred on the D bytes on D each register within an 8-bit peripheral located on

15–D8

bus lines and odd addressed

7–D0

. Care must be taken to assure that

the lower portion of the bus be addressed as even.

External Interface

PROCESSOR RESET AND INITIALIZATION

Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin. The 8086 RESET is required to be HIGH for greater than 4 CLK cycles. The 8086 will terminate operations on the high-going edge of RESET and will remain dormant as long as RESET is HIGH. The low-going transition of RESET triggers an internal reset sequence for approximately 10 CLK cycles. After this interval the 8086 operates normally beginning with the instruction in absolute location FFFF0H (see Figure 3b). The details of this operation are specified in the Instruction Set description of the MCS-86 Family User’s Manual. The RESET input is internally synchronized to the processor clock. At initialization the HIGH-to-LOW transition of RESET must occur no sooner than 50 ms after power-up, to allow complete initialization of the 8086.

NMI asserted prior to the 2nd clock after the end of RESET will not be honored. If NMI is asserted after that point and during the internal reset sequence, the processor may execute one instruction before responding to the interrupt. A hold request active immediately after RESET will be honored before the first instruction fetch.

All 3-state outputs float to 3-state OFF during RESET. Status is active in the idle state for the first clock after RESET becomes active and then floats to 3-state OFF. ALE and HLDA are driven low.

INTERRUPT OPERATIONS

Interrupt operations fall into two classes; software or hardware initiated. The software initiated interrupts and software aspects of hardware interrupts are specified in the Instruction Set description. Hardware interrupts can be classified as non-maskable or maskable.

Interrupts result in a transfer of control to a new pro-

gram location. A 256-element table containing address pointers to the interrupt service program locations resides in absolute locations 0 through 3FFH (see Figure 3b), which are reserved for this purpose. Each element in the table is 4 bytes in size and corresponds to an interrupt ‘‘type’’. An interrupting device supplies an 8-bit type number, during the interrupt acknowledge sequence, which is used to ‘‘vector’’ through the appropriate element to the new interrupt service program location.

NON-MASKABLE INTERRUPT (NMI)

The processor provides a single non-maskable interrupt pin (NMI) which has higher priority than the maskable interrupt request pin (INTR). A typical use would be to activate a power failure routine. The NMI is edge-triggered on a LOW-to-HIGH transition. The activation of this pin causes a type 2 interrupt. (See Instruction Set description.)

NMI is required to have a duration in the HIGH state of greater than two CLK cycles, but is not required to be synchronized to the clock. Any high-going transition of NMI is latched on-chip and will be serviced at the end of the current instruction or between whole moves of a block-type instruction. Worst case response to NMI would be for multiply, divide, and variable shift instructions. There is no specification on the occurrence of the low-going edge; it may occur before, during, or after the servicing of NMI. Another high-going edge triggers another response if it occurs after the start of the NMI procedure. The signal must be free of logical spikes in general and be free of bounces on the low-going edge to avoid triggering extraneous responses.

8086

MASKABLE INTERRUPT (INTR)

The 8086 provides a single interrupt request input (INTR) which can be masked internally by software with the resetting of the interrupt enable FLAG status bit. The interrupt request signal is level triggered. It is internally synchronized during each clock cycle on the high-going edge of CLK. To be responded to, INTR must be present (HIGH) during the clock period preceding the end of the current instruction or the end of a whole move for a blocktype instruction. During the interrupt response sequence further interrupts are disabled. The enable bit is reset as part of the response to any interrupt (INTR, NMI, software interrupt or single-step), although the FLAGS register which is automatically pushed onto the stack reflects the state of the processor prior to the interrupt. Until the old FLAGS register is restored the enable bit will be zero unless specifically set by an instruction.

During the response sequence (Figure 6) the processor executes two successive (back-to-back) interrupt acknowledge cycles. The 8086 emits the LOCK signal from T second. A local bus ‘‘hold’’ request will not be hon-

of the first bus cycle until T2of the

ored until the end of the second bus cycle. In the second bus cycle a byte is fetched from the external interrupt system (e.g., 8259A PIC) which identifies the source (type) of the interrupt. This byte is multiplied by four and used as a pointer into the interrupt vector lookup table. An INTR signal left HIGH will be continually responded to within the limitations of the enable bit and sample period. The INTERRUPT RETURN instruction includes a FLAGS pop which returns the status of the original interrupt enable bit when it restores the FLAGS.

HALT

When a software ‘‘HALT’’ instruction is executed the processor indicates that it is entering the ‘‘HALT’’ state in one of two ways depending upon which mode is strapped. In minimum mode, the processor issues one ALE with no qualifying bus control signals. In maximum mode, the processor issues appropriate HALT status on S 8288 bus controller issues one ALE. The 8086 will

, and S0; and the

2,S1

not leave the ‘‘HALT’’ state when a local bus ‘‘hold’’ is entered while in ‘‘HALT’’. In this case, the processor reissues the HALT indicator. An interrupt request or RESET will force the 8086 out of the ‘‘HALT’’ state.

READ/MODIFY/WRITE (SEMAPHORE) OPERATIONS VIA LOCK

The LOCK

status information is provided by the processor when directly consecutive bus cycles are required during the execution of an instruction. This provides the processor with the capability of performing read/modify/write operations on memory (via the Exchange Register With Memory instruction, for example) without the possibility of another system bus master receiving intervening memory cycles. This is useful in multi-processor system configurations to accomplish ‘‘test and set lock’’ operations. The LOCK

signal is activated (forced LOW) in the clock cycle following the one in which the software ‘‘LOCK’’ prefix instruction is decoded by the EU. It is deactivated at the end of the last bus cycle of the instruction following the ‘‘LOCK’’ prefix instruction. While LOCK

is active a request on a RQ/ GT pin will be recorded and then honored at the end of the LOCK.

Figure 6. Interrupt Acknowledge Sequence

231455– 9

8086

EXTERNAL SYNCHRONIZATION VIA TEST

As an alternative to the interrupts and general I/O capabilities, the 8086 provides a single softwaretestable input known as the TEST

signal. At any time the program may execute a WAIT instruction. If at that time the TEST

signal is inactive (HIGH), program execution becomes suspended while the processor waits for TEST

to become active. It must remain active for at least 5 CLK cycles. The WAIT instruction is re-executed repeatedly until that time. This activity does not consume bus cycles. The processor remains in an idle state while waiting. All 8086 drivers go to 3-state OFF if bus ‘‘Hold’’ is entered. If interrupts are enabled, they may occur while the processor is waiting. When this occurs the processor fetches the WAIT instruction one extra time, processes the interrupt, and then re-fetches and reexecutes the WAIT instruction upon returning from the interrupt.

Basic System Timing

Typical system configurations for the processor operating in minimum mode and in maximum mode are shown in Figures 4a and 4b, respectively. In minimum mode, the MN/MX the processor emits bus control signals in a manner similar to the 8085. In maximum mode, the MN/MX pin is strapped to VSSand the processor emits coded status information which the 8288 bus controller uses to generate MULTIBUS compatible bus control signals. Figure 5 illustrates the signal timing relationships.

pin is strapped to VCCand

SYSTEM TIMINGÐMINIMUM SYSTEM

The read cycle begins in T Address Latch Enable (ALE) signal. The trailing (low-

with the assertion of the

going) edge of this signal is used to latch the address information, which is valid on the local bus at this time, into the address latch. The BHE

and A signals address the low, high, or both bytes. From T to T4the M/IO signal indicates a memory or I/O operation. At T local bus and the bus goes to a high impedance

the address is removed from the

state. The read control signal is also asserted at T The read (RD

) signal causes the addressed device to enable its data bus drivers to the local bus. Some time later valid data will be available on the bus and the addressed device will drive the READY line HIGH. When the processor returns the read signal to a HIGH level, the addressed device will again 3state its bus drivers. If a transceiver is required to buffer the 8086 local bus, signals DT/R

and DEN

are provided by the 8086.

A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO

signal is again asserted to indicate a memory or I/O write operation. In the T dress emission the processor emits the data to be

immediately following the ad-

written into the addressed location. This data remains valid until the middle of T

the processor asserts the write control signal.

The write (WR ning of T somewhat into T

The BHE

) signal becomes active at the begin-

as opposed to the read which is delayed

to provide time for the bus to float.

and A0signals are used to select the prop-

. During T2,T3, and

er byte(s) of the memory/IO word to be read or written according to the following table:

BHE A0 Characteristics

0 0 Whole word 0 1 Upper byte from/to

odd address

1 0 Lower byte from/to

even address

1 1 None

0 1

Figure 7. 8086 Register Model

231455– 10

I/O ports are addressed in the same manner as memory location. Even addressed bytes are transferred on the D bytes on D

15–D8

bus lines and odd addressed

7–D0

The basic difference between the interrupt acknowledge cycle and a read cycle is that the interrupt acknowledge signal (INTA) is asserted in place of the read (RD

) signal and the address bus is floated. (See Figure 6.) In the second of two successive INTA cycles, a byte of information is read from bus

8086

lines D7–D0as supplied by the inerrupt system logic (i.e., 8259A Priority Interrupt Controller). This byte identifies the source (type) of the interrupt. It is multiplied by four and used as a pointer into an interrupt vector lookup table, as described earlier.

BUS TIMINGÐMEDIUM SIZE SYSTEMS

For medium size systems the MN/MX nected to V to the system as well as a latch for latching the sys-

and the 8288 Bus Controller is added

pin is con-

tem address, and a transceiver to allow for bus loading greater than the 8086 is capable of handling. Signals ALE, DEN, and DT/R are generated by the 8288 instead of the processor in this configuration although their timing remains relatively the same. The 8086 status outputs (S type-of-cycle information and become 8288 inputs.

, and S0) provide

2,S1

This bus cycle information specifies read (code, data, or I/O), write (data or I/O), interrupt

acknowledge, or software halt. The 8288 thus issues control signals specifying memory read or write, I/O read or write, or interrupt acknowledge. The 8288 provides two types of write strobes, normal and advanced, to be applied as required. The normal write strobes have data valid at the leading edge of write. The advanced write strobes have the same timing as read strobes, and hence data isn’t valid at the leading edge of write. The transceiver receives the usual DIR and G

inputs from the 8288’s DT/R and

DEN.

The pointer into the interrupt vector table, which is passed during the second INTA cycle, can derive from an 8259A located on either the local bus or the system bus. If the master 8259A Priority Interrupt Controller is positioned on the local bus, a TTL gate is required to disable the transceiver when reading from the master 8259A during the interrupt acknowledge sequence and software ‘‘poll’’.

8086

ABSOLUTE MAXIMUM RATINGS*

Ambient Temperature Under Bias АААААА0§Cto70§C

Storage Temperature ААААААААААb65§Ctoa150§C

Voltage on Any Pin with

Respect to GroundАААААААААААААА

Power DissipationАААААААААААААААААААААААААА2.5W

D.C. CHARACTERISTICS (8086: T

1.0V toa7V

(8086-1: T (8086-2: T

0§Cto70§C, V

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability.

5Vg10%)

5Vg5%)

Symbol Parameter Min Max Units Test Conditions

Input Low Voltage

Input High Voltage 2.0 V

Output Low Voltage 0.45 V I

Output High Voltage 2.4 V I

Power Supply Current: 8086 340

0.5

8086-1 360 mA T

0.8 V (Note 1)

0.5 V (Notes 1, 2)

2.5 mA

25§C

400 mA

8086-2 350

Input Leakage Current

Output Leakage Current

Clock Input Low Voltage

0.5

Clock Input High Voltage 3.9 V

Capacitance of Input Buffer 15 pF fce1 MHz

10 mA0V

10 mA 0.45VsV

0.6 V

1.0 V

VCC(Note 3)

OUT

(All input except AD0–AD15,RQ/GT)

NOTES:

tested with MN/MX Pine0V. VIHtested with MN/MX Pine5V. MN/MX Pin is a Strap Pin.

1. V

2. Not applicable to RQ

3. HOLD and HLDA I

Capacitance of I/O Buffer 15 pF fce1 MHz (AD

–AD15,RQ/GT)

/GT0 and RQ/GT1 (Pins 30 and 31). mine30 mA, maxe500 mA.

8086

A.C. CHARACTERISTICS (8086: T

(8086-1: T (8086-2: T

0§Cto70§C, V

CC CC CC

5Vg10%)

5Vg5%)

MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS

Symbol Parameter

8086 8086-1 8086-2

Units Test Conditions

Min Max Min Max Min Max

TCLCL CLK Cycle Period 200 500 100 500 125 500 ns

TCLCH CLK Low Time 118 53 68 ns

TCHCL CLK High Time 69 39 44 ns

TCH1CH2 CLK Rise Time 10 10 10 ns From 1.0V to 3.5V

TCL2CL1 CLK Fall Time 10 10 10 ns From 3.5V to 1.0V

TDVCL Data in Setup Time 30 5 20 ns

TCLDX Data in Hold Time 10 10 10 ns

TR1VCL RDY Setup Time 35 35 35 ns

into 8284A (See Notes 1, 2)

TCLR1X RDY Hold Time 0 0 0 ns

into 8284A (See Notes 1, 2)

TRYHCH READY Setup 118 53 68 ns

Time into 8086

TCHRYX READY Hold Time 30 20 20 ns

into 8086

TRYLCL READY Inactive to

8ns

CLK (See Note 3)

THVCH HOLD Setup Time 35 20 20 ns

TINVCH INTR, NMI, TEST 30 15 15 ns

Setup Time (See Note 2)

TILIH Input Rise Time 20 20 20 ns From 0.8V to 2.0V

(Except CLK)

TIHIL Input Fall Time 12 12 12 ns From 2.0V to 0.8V

(Except CLK)

8086

A.C. CHARACTERISTICS (Continued)

TIMING RESPONSES

Symbol Parameter

8086 8086-1 8086-2

Units

Min Max Min Max Min Max

TCLAV Address Valid Delay 10 110 10 50 10 60 ns

TCLAX Address Hold Time 10 10 10 ns

TCLAZ Address Float TCLAX 80 10 40 TCLAX 50 ns

Delay

TLHLL ALE Width TCLCH-20 TCLCH-10 TCLCH-10 ns

TCLLH ALE Active Delay 80 40 50 ns

TCHLL ALE Inactive Delay 85 45 55 ns

TLLAX Address Hold Time TCHCL-10 TCHCL-10 TCHCL-10 ns

TCLDV Data Valid Delay 10 110 10 50 10 60 ns *C

TCHDX Data Hold Time 10 10 10 ns

TWHDX Data Hold Time TCLCH-30 TCLCH-25 TCLCH-30 ns

After WR

TCVCTV Control Active 10 110 10 50 10 70 ns

Delay 1

TCHCTV Control Active 10 110 10 45 10 60 ns

Delay 2

TCVCTX Control Inactive 10 110 10 50 10 70 ns

Delay

TAZRL Address Float to 0 0 0 ns

READ Active

TCLRL RD Active Delay 10 165 10 70 10 100 ns

TCLRH RD Inactive Delay 10 150 10 60 10 80 ns

TRHAV RD Inactive to Next TCLCL-45 TCLCL-35 TCLCL-40 ns

Address Active

TCLHAV HLDA Valid Delay 10 160 10 60 10 100 ns

TRLRH RD Width 2TCLCL-75 2TCLCL-40 2TCLCL-50 ns

TWLWH WR Width 2TCLCL-60 2TCLCL-35 2TCLCL-40 ns

TAVAL Address Valid to TCLCH-60 TCLCH-35 TCLCH-40 ns

ALE Low

TOLOH Output Rise Time 20 20 20 ns From 0.8V to 2.0V

TOHOL Output Fall Time 12 12 12 ns From 2.0V to 0.8V

Test

Conditions

20–100 pF

for all 8086 Outputs (In addition to 8086 selfload)

NOTES:

1. Signal at 8284A shown for reference only.

2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

3. Applies only to T2 state. (8 ns into T3).

8086

A.C. TESTING INPUT, OUTPUT WAVEFORM

231455-11

A.C. Testing: Inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at 1.5V for both a Logic ‘‘1’’ and ‘‘0’’.

WAVEFORMS

MINIMUM MODE

A.C. TESTING LOAD CIRCUIT

Includes Jig Capacitance

231455– 12

231455– 13

8086

WAVEFORMS (Continued)

MINIMUM MODE (Continued)

SOFTWARE HALTÐ RD, WR, INTA DT/ReINDETERMINATE

NOTES:

1. All signals switch between V

2. RDY is sampled near the end of T

3. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control signals shown for second INTA cycle.

4. Signals at 8284A are shown for reference only.

5. All timing measurements are made at 1.5V unless otherwise noted.

and VOLunless otherwise specified.

2,T3,TW

to determine if TWmachines states are to be inserted.

231455– 14

A.C. CHARACTERISTICS

MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS

Symbol Parameter

TCLCL CLK Cycle Period 200 500 100 500 125 500 ns

TCLCH CLK Low Time 118 53 68 ns

TCHCL CLK High Time 69 39 44 ns

TCH1CH2 CLK Rise Time 10 10 10 ns From 1.0V to 3.5V

TCL2CL1 CLK Fall Time 10 10 10 ns From 3.5V to 1.0V

TDVCL Data in Setup Time 30 5 20 ns

TCLDX Data in Hold Time 10 10 10 ns

TR1VCL RDY Setup Time 35 35 35 ns

TCLR1X RDY Hold Time 0 0 0 ns

TRYHCH READY Setup 118 53 68 ns

TCHRYX READY Hold Time 30 20 20 ns

TRYLCL READY Inactive to

TINVCH Setup Time for 30 15 15 ns

TGVCH RQ/GT Setup Time 30 15 15 ns

TCHGX RQ Hold Time into 40 20 30 ns

TILIH Input Rise Time 20 20 20 ns From 0.8V to 2.0V

TIHIL Input Fall Time 12 12 12 ns From 2.0V to 0.8V

into 8284A (Notes 1, 2)

Time into 8086

into 8086

CLK (Note 4)

Recognition (INTR, NMI, TEST (Note 2)

(Note 5)

8086

(Except CLK)

)

8086 8086-1 8086-2

Min Max Min Max Min Max

8ns

Units

Test

Conditions

8086

A.C. CHARACTERISTICS (Continued)

TIMING RESPONSES

Symbol Parameter

TCLML Command Active 10 35 10 35 10 35 ns

Delay (See Note 1)

TCLMH Command Inactive 10 35 10 35 10 35 ns

Delay (See Note 1)

TRYHSH READY Active to 110 45 65 ns

Status Passive (See Note 3)

TCHSV Status Active Delay 10 110 10 45 10 60 ns

TCLSH Status Inactive 10 130 10 55 10 70 ns

Delay

TCLAV Address Valid Delay 10 110 10 50 10 60 ns

TCLAX Address Hold Time 10 10 10 ns

TCLAZ Address Float Delay TCLAX 80 10 40 TCLAX 50 ns

TSVLH Status Valid to ALE 15 15 15 ns

High (See Note 1)

TSVMCH Status Valid to 15 15 15 ns

MCE High (See Note 1)

TCLLH CLK Low to ALE 15 15 15 ns C

Valid (See Note 1)

TCLMCH CLK Low to MCE 15 15 15 ns

High (See Note 1)

TCHLL ALE Inactive Delay 15 15 15 ns

(See Note 1)

TCLMCL MCE Inactive Delay 15 15 15 ns

(See Note 1)

TCLDV Data Valid Delay 10 110 10 50 10 60 ns

TCHDX Data Hold Time 10 10 10 ns

TCVNV Control Active 5 45 5 45 5 45 ns

Delay (See Note 1)

TCVNX Control Inactive 10 45 10 45 10 45 ns

Delay (See Note 1)

TAZRL Address Float to 0 0 0 ns

READ Active

TCLRL RD Active Delay 10 165 10 70 10 100 ns

TCLRH RD Inactive Delay 10 150 10 60 10 80 ns

8086 8086-1 8086-2

Min Max Min Max Min Max

Units

Test

Conditions

20–100 pF

for all 8086 Outputs (In addition to 8086 self-load)

8086

A.C. CHARACTERISTICS (Continued)

TIMING RESPONSES (Continued)

Symbol Parameter

8086 8086-1 8086-2

Units

Min Max Min Max Min Max

TRHAV RD Inactive to Next TCLCL-45 TCLCL-35 TCLCL-40 ns

Address Active

TCHDTL Direction Control 50 50 50 ns C

Active Delay (Note 1)

TCHDTH Direction Control 30 30 30 ns

Inactive Delay (Note 1)

TCLGL GT Active Delay 0 85 0 38 0 50 ns

TCLGH GT Inactive Delay 0 85 0 45 0 50 ns

TRLRH RD Width 2TCLCL-75 2TCLCL-40 2TCLCL-50 ns

TOLOH Output Rise Time 20 20 20 ns From 0.8V to 2.0V

TOHOL Output Fall Time 12 12 12 ns From 2.0V to 0.8V

NOTES:

1. Signal at 8284A or 8288 shown for reference only.

2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

3. Applies only to T3 and wait states.

4. Applies only to T2 state (8 ns into T3).

Test

Conditions

20–100 pF

for all 8086 Outputs (In addition to 8086 self-load)

8086

WAVEFORMS

MAXIMUM MODE

231455– 15

WAVEFORMS (Continued)

MAXIMUM MODE (Continued)

8086

231455– 16

NOTES:

1. All signals switch between V

2. RDY is sampled near the end of T

3. Cascade address is valid between first and second INTA cycle.

4. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control for pointer address is shown for second INTA cycle.

5. Signals at 8284A or 8288 are shown for reference only.

6. The issuance of the 8288 command and control signals (MRDC lags the active high 8288 CEN.

7. All timing measurements are made at 1.5V unless otherwise noted.

8. Status inactive in state just prior to T

and VOLunless otherwise specified.

2,T3,TW

to determine if TWmachines states are to be inserted.

, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN)

8086

WAVEFORMS (Continued)

ASYNCHRONOUS SIGNAL RECOGNITION

NOTE:

1. Setup requirements for asynchronous signals only to guarantee recognition at next CLK.

231455– 17

BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY)

231455– 18

RESET TIMING

REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

NOTE:

The coprocessor may not drive the buses outside the region shown without risking contention.

231455– 19

231455– 20

WAVEFORMS (Continued)

HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

8086

231455– 21

8086

Table 2. Instruction Set Summary

Mnemonic and

DATA TRANSFER

MOV

Immediate to Register/Memory 1100011w mod000r/m data data if we1

Immediate to Register 1011wreg data data if we1

Memory to Accumulator 1010000w addr-low addr-high

Accumulator to Memory 1010001w addr-low addr-high

Segment Register to Register/Memory 10001100 mod0regr/m

PUSHePush:

Segment Register 000reg110

POPePop:

Segment Register 000reg111

XCHGeExchange:

INeInput from:

Fixed Port 1110010w port

Variable Port 1110110w

OUTeOutput to:

Fixed Port 1110011w port

Variable Port 1110111w

XLATeTranslate Byte to AL 11010111

LEAeLoad EA to Register 10001101 modregr/m

LDSeLoad Pointer to DS 11000101 modregr/m

LESeLoad Pointer to ES 11000100 modregr/m

LAHFeLoad AH with Flags 10011111

SAHFeStore AH into Flags 10011110

PUSHFePush Flags 10011100

POPFePop Flags 10011101

Description

Move: 76543210 76543210 76543210 76543210

Instruction Code

Table 2. Instruction Set Summary (Continued)

Mnemonic and

Description

ARITHMETIC 76543210 76543210 76543210 76543210

ADD

Add:

Reg./Memory with Register to Either 000000dw modregr/m

Immediate to Register/Memory 100000sw mod000r/m data data if s: we01

Immediate to Accumulator 0000010w data data if we1

ADCeAdd with Carry:

Reg./Memory with Register to Either 000100dw modregr/m

Immediate to Register/Memory 100000sw mod010r/m data data if s: we01

Immediate to Accumulator 0001010w data data if we1

INCeIncrement:

AAAeASCII Adjust for Add 00110111

BAAeDecimal Adjust for Add 00100111

SUBeSubtract:

Reg./Memory and Register to Either 001010dw modregr/m

Immediate from Register/Memory 100000sw mod101r/m data data if s we01

Immediate from Accumulator 0010110w data data if we1

SSBeSubtract with Borrow

Reg./Memory and Register to Either 000110dw modregr/m

Immediate from Register/Memory 100000sw mod011r/m data data if s we01

Immediate from Accumulator 000111w data data if we1

DECeDecrement:

NEGeChange sign 1111011w mod011 r/m

CMPeCompare:

Immediate with Register/Memory 100000sw mod111r/m data data if s we01

Immediate with Accumulator 0011110w data data if we1

AASeASCII Adjust for Subtract 00111111

DASeDecimal Adjust for Subtract 00101111

MULeMultiply (Unsigned) 1111011w mod100r/m

IMULeInteger Multiply (Signed) 1111011w mod101r/m

AAMeASCII Adjust for Multiply 11010100 00001010

DIVeDivide (Unsigned) 1111011w mod110r/m

IDIVeInteger Divide (Signed) 1111011w mod111r/m

AADeASCII Adjust for Divide 11010101 00001010

CBWeConvert Byte to Word 10011000

CWDeConvert Word to Double Word 10011001

Instruction Code

8086

Table 2. Instruction Set Summary (Continued)

Mnemonic and

LOGIC 76543210 76543210 76543210 76543210

NOTeInvert 1111011w mod010r/m

SHL/SALeShift Logical/Arithmetic Left 110100vw mod100r/m

SHReShift Logical Right 110100vw mod101r/m

SAReShift Arithmetic Right 110100vw mod111r/m

ROLeRotate Left 110100vw mod000r/m

ROReRotate Right 110100vw mod001r/m

RCLeRotate Through Carry Flag Left 110100vw mod010r/m

RCReRotate Through Carry Right 110100vw mod011r/m

ANDeAnd:

Reg./Memory and Register to Either 001000dw modregr/m

Immediate to Register/Memory 1000000w mod100r/m data data if we1

Immediate to Accumulator 0010010w data data if we1

TESTeAnd Function to Flags, No Result:

Immediate Data and Register/Memory 1111011w mod000r/m data data if we1

Immediate Data and Accumulator 1010100w data data if we1

OReOr:

Reg./Memory and Register to Either 000010dw modregr/m

Immediate to Register/Memory 1000000w mod001r/m data data if we1

Immediate to Accumulator 0000110w data data if we1

XOReExclusive or:

Reg./Memory and Register to Either 001100dw modregr/m

Immediate to Register/Memory 1000000w mod110r/m data data if we1

Immediate to Accumulator 0011010w data data if we1

STRING MANIPULATION

REPeRepeat 1111001z

MOVSeMove Byte/Word 1010010w

CMPSeCompare Byte/Word 1010011w

SCASeScan Byte/Word 1010111w

LODSeLoad Byte/Wd to AL/AX 1010110w

STOSeStor Byte/Wd from AL/A 1010101w

CONTROL TRANSFER

CALL

Direct within Segment 11101000 disp-low disp-high

Indirect within Segment 11111111 mod010r/m

Direct Intersegment 10011010 offset-low offset-high

Indirect Intersegment 11111111 mod011r/m

Description

Call:

Instruction Code

seg-low seg-high

Table 2. Instruction Set Summary (Continued)

Mnemonic and

Description

JMPeUnconditional Jump: 76543210 76543210 76543210

Direct within Segment 11101001 disp-low disp-high

Direct within Segment-Short 11101011 disp

Indirect within Segment 11111111 mod100r/m

Direct Intersegment 11101010 offset-low offset-high

Indirect Intersegment 11111111 mod101r/m

RETeReturn from CALL:

Within Segment 11000011

Within Seg Adding Immed to SP 11000010 data-low data-high

Intersegment 11001011

Intersegment Adding Immediate to SP 11001010 data-low data-high

JE/JZeJump on Equal/Zero 01110100 disp

JL/JNGEeJump on Less/Not Greater

JLE/JNGeJump on Less or Equal/

JB/JNAEeJump on Below/Not Above

JBE/JNAeJump on Below or Equal/

JP/JPEeJump on Parity/Parity Even 01111010 disp

JOeJump on Overflow 01110000 disp

JSeJump on Sign 01111000 disp

JNE/JNZeJump on Not Equal/Not Zero 01110101 disp

JNL/JGEeJump on Not Less/Greater

JNLE/JGeJump on Not Less or Equal/

JNB/JAEeJump on Not Below/Above

JNBE/JAeJump on Not Below or

JNP/JPOeJump on Not Par/Par Odd 01111011 disp

JNOeJump on Not Overflow 01110001 disp

JNSeJump on Not Sign 01111001 disp

LOOPeLoop CX Times 11100010 disp

LOOPZ/LOOPEeLoop While Zero/Equal 11100001 disp

LOOPNZ/LOOPNEeLoop While Not

JCXZeJump on CX Zero 11100011 disp

INTeInterrupt

Type Specified 11001101 type

Type 3 11001100

INTOeInterrupt on Overflow 11001110

IRETeInterrupt Return 11001111

or Equal

Not Greater

or Equal

Not Above

or Equal

Greater

or Equal

Equal/Above

Zero/Equal

01111100 disp

01111110 disp

01110010 disp

01110110 disp

01111101 disp

01111111 disp

01110011 disp

01110111 disp

11100000 disp

Instruction Code

seg-low seg-high

8086

Table 2. Instruction Set Summary (Continued)

Mnemonic and

Description

PROCESSOR CONTROL

CLCeClear Carry 11111000

CMCeComplement Carry 11110101

STCeSet Carry 11111001

CLDeClear Direction 11111100

STDeSet Direction 11111101

CLIeClear Interrupt 11111010

STIeSet Interrupt 11111011

HLTeHalt 11110100

WAITeWait 10011011

ESCeEscape (to External Device) 11011xxx modxxxr/m

LOCKeBus Lock Prefix 11110000

NOTES:

8-bit accumulator

16-bit accumulator

Count register

Data segment

Extra segment

ES Above/below refers to unsigned value

Greater Less if d if w

if mod if mod

if mod

if mod if r/m if r/m if r/m if r/m if r/m if r/m if r/m if r/m DISP follows 2nd byte of instruction (before data if re-

*except if mod

Mnemonics

more positive;

less positive (more negative) signed values

1 then ‘‘to’’ reg; if de0 then ‘‘from’’ reg

1 then word instruction; if we0 then byte instruc-

tion

11 then r/m is treated as a REG field

00 then DISPe0*, disp-low and disp-high are

absent

01 then DISPedisp-low sign-extended to

16 bits, disp-high is absent

10 then DISPedisp-high; disp-low

000 then EAe(BX)a(SI)aDISP

001 then EAe(BX)a(DI)aDISP

010 then EAe(BP)a(SI)aDISP

011 then EAe(BP)a(DI)aDISP

100 then EAe(SI)aDISP

101 then EAe(DI)aDISP

110 then EAe(BP)aDISP*

111 then EAe(BX)aDISP

quired)

disp-low.

00 and r/me110 then EAedisp-high;

Intel, 1978

76543210 76543210

ifsw

and

ifsw

to form the 16-bit operand

0 then ‘‘count’’e1; if ve1 then ‘‘count’’ in (CL)

if v

don’t care

x z is used for string primitives for comparison with ZF FLAG

SEGMENT OVERRIDE PREFIX

001reg110

REG is assigned according to the following table:

16-Bit (we1) 8-Bit (we0) Segment

000 AX 000 AL 00 ES 001 CX 001 CL 01 CS 010 DX 010 DL 10 SS 011 BX 011 BL 11 DS 100 SP 100 AH 101 BP 101 CH

110 SI 110 DH 111 DI 111 BH

Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file:

FLAGSeX:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)

Instruction Code

01 then 16 bits of immediate data form the oper-

11 then an immediate data byte is sign extended

DATA SHEET REVISION REVIEW

The following list represents key differences between this and the -004 data sheet. Please review this summary carefully.

1. The Intel 8086 implementation technology (HMOS) has been changed to (HMOS-III).

2. Delete all ‘‘changes from 1985 Handbook Specification’’ sentences.

Intel 8086, 8086-1, 8086-2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual