HP Probook 455 G3 Schematics

5

4

3

2

1

400 series Palazzo / X73A (UMA/DIS) Schematics

01

D D

DDR3L 1600MHz

16GB

PAGE 10

DDR3L 1600MHz

16GB

PAGE 09

Single Channel-B
DDR3L 1600

DDI0 x2

CARRIZO (L)

DDI1

DIS only

x2

For Carrizo L

gDDR3

1GB/2GB

gDDR3

1GB/2GB

gDDR3

1GB/2GB

gDDR3

1GB/2GB

4 pcs of x16 PAGE 16

C C

64bit

iGP

Processor : Daul Core
Power : 15 (Watt)

DDI2

x4

x4

Graphics Controller

AMD Meso Pro 64-bit gDDR3

M/B down dGPU S3 Package 18W TDP

PAGE 11~15

SATA - ODD

SATA1 3GB/s

PAGE 37

SATA0 6GB/sPrimary HDD

2.5" / 7, 9.5mm

PAGE 37

B B

InfineonTPM

48MHz

32.768KHz

PAGE 26SLB9670 TT1.2

LPC Interface

Keyboard

PAGE 32

Battery PAGE 57

FAN

A A

Function Conn.

PAGE 35 HD Audio

KBC

Nuvoton

NPCE586HA0MX

Embedded Controller

PAGE 39, 40

128TQFP

SPI Interface

System BIOS
SPI ROM 8MB

PAGE 41

PAGE 25

5

4

iFCH

USB2.0 Interface

PCIE Gen 1 x 1 Lane

PAGE 2~8

HD and FHD

eDP

PAGE 19

DP to VGA Controller

DP Switch IC

Realtek RTD2168

DP x2

PAGE 20

PS8339A PAGE 21

HDMI

HDMI CONN

PAGE 22

USB2.0 Interface USB 2.0 standard port

USB 2.0 standard ports

USB3.0 Interface

USB 3.0 standard port
CN18 (Upper Left)

USB 3.0 standard port
CN19 (Lower Left)

PAGE 29NGFF

WLAN Combo

USB3.0 Re-driver IC
PTN36001 PAGE 27

Camera

Port2

PAGE 19

Fingerprint

VFS495

Port 4

PAGE 17

10/100/1000 NIC

Realtek RTL8111HSH

PAGE 24

Card Reader controller

RTS5237-GR

PAGE 34

RJ45

MicroSD Socket

Digital MIC

PAGE 24

PAGE 34

PAGE 19

on Daugther Board

on Forced Pad Board

Conexant

CX7501

Speaker

PAGE 23

Combo Jack

PAGE 23

3

PAGE 24

2

CRT CONN

PAGE 20

PAGE 24

PAGE 24

PAGE 27

PAGE 27

PCB 6L STACK UP(1.2mm)

LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1(High)
LAYER 4 : IN2(Low)
LAYER 5 : SVCC
LAYER 6 : BOT

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Block Diagram

Block Diagram

NB5

NB5

NB5

Block Diagram

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1 62Friday, July 24, 2015

1 62Friday, July 24, 2015

1 62Friday, July 24, 2015

1A

5

4

3

2

1

QBCON TOPBSQ

Carrizo

Carrizo DB phase use AJ1802CUT00

D D

AJ1802CUT01

AJ1802CUT02

U24B

U10

PCIE_RXP0_LAN[24]
PCIE_RXN0_LAN[24]

PCIE_RXP1_WLAN[29]
PCIE_RXN1_WLAN[29]

PCIE_RXP3_CARD[34]
PCIE_RXN3_CARD[34]

U9
T6

T5
T9

T8
P7

P6
U7

P_GPP_RXP[0]
P_GPP_RXN[0]

P_GPP_RXP[1]
P_GPP_RXN[1]

P_GPP_RXP[2]
P_GPP_RXN[2]

P_GPP_RXP[3]
P_GPP_RXN[3]

P_ZVDDP

PCIE

P_GPP_TXP[0]
P_GPP_TXN[0]

P_GPP_TXP[1]
P_GPP_TXN[1]

P_GPP_TXP[2]
P_GPP_TXN[2]

P_GPP_TXP[3]
P_GPP_TXN[3]

P_ZVSS/P_RX_ZVDDP

R1

PCIE_TXP0_LAN_C

R2

PCIE_TXN0_LAN_C

R4

PCIE_TXP1_WLAN_C

R3

PCIE_TXN1_WLAN_C

N1
N2

N4

PCIE_TXP3_C

N3

PCIE_TXN3_C

U6

P_ZVSS_P_RX_ZVDD_095P_ZVDDP_P_TX_ZVDD_095

C445 0.1U/16V/X7R_4
C444 0.1U/16V/X7R_4

C447 0.1U/16V/X7R_4
C446 0.1U/16V/X7R_4

C443 0.1U/16V/X7R_4
C449 0.1U/16V/X7R_4

PCIE_TXP0_LAN [24]
PCIE_TXN0_LAN [24]

PCIE_TXP1_WLAN [29]
PCIE_TXN1_WLAN [29]

PCIE_TXP3_CARD [34]
PCIE_TXN3_CARD [34]

CZ support GFX 0~7 & Gen3

02

CZ-L only support GFX 0~3 & Gen2

P10

L10

P9
N6

N5
N9

N8
L7

L6

L9
K6

K5
K9

K8

J7
J6

P_GFX_RXP[0]
P_GFX_RXN[0]

P_GFX_RXP[1]
P_GFX_RXN[1]

P_GFX_RXP[2]
P_GFX_RXN[2]

P_GFX_RXP[3]
P_GFX_RXN[3]

P_GFX_RXP[4]
P_GFX_RXN[4]

P_GFX_RXP[5]
P_GFX_RXN[5]

P_GFX_RXP[6]
P_GFX_RXN[6]

P_GFX_RXP[7]
P_GFX_RXN[7]

PEG_RXP0[11]
PEG_RXN0[11]

PEG_RXP1[11]
PEG_RXN1[11]

PEG_RXP2[11]

C C

PEG_RXN2[11]
PEG_RXP3[11]

PEG_RXN3[11]

ALF@1028:
HP request to add 4Lanes

For DIS GPU

FP4 REV 1.0

*FP4

B B

+0.95V +0.95V

+0.95V

R81

C434

0.1U/16V/X7R_4

*CZL@1K/F_4

P_ZVSS_P_RX_ZVDD_095 P_ZVDDP_P_TX_ZVDD_095

P_GFX_TXP[0]
P_GFX_TXN[0]

P_GFX_TXP[1]
P_GFX_TXN[1]

P_GFX_TXP[2]
P_GFX_TXN[2]

P_GFX_TXP[3]
P_GFX_TXN[3]

P_GFX_TXP[4]
P_GFX_TXN[4]

P_GFX_TXP[5]
P_GFX_TXN[5]

P_GFX_TXP[6]
P_GFX_TXN[6]

P_GFX_TXP[7]
P_GFX_TXN[7]

M2
M1

L1
L2

L4
L3

J1
J2

J4
J3

H2
H1

G1
G2

G4
G3

GFX_TX0P_C
GFX_TX0N_C

GFX_TX1P_C
GFX_TX1N_C

GFX_TX2P_C
GFX_TX2N_C

GFX_TX3P_C
GFX_TX3N_C

R91
CZ@196/F_4

C450 DIS@0.22U/10V_4
C453 DIS@0.22U/10V_4

C458 DIS@0.22U/10V_4
C461 DIS@0.22U/10V_4

C454 DIS@0.22U/10V_4
C457 DIS@0.22U/10V_4

C456 DIS@0.22U/10V_4
C460 DIS@0.22U/10V_4

R84
*CZL@1.69K/F_4

PEG_TXP0 [11]
PEG_TXN0 [11]

PEG_TXP1 [11]
PEG_TXN1 [11]

PEG_TXP2 [11]
PEG_TXN2 [11]

PEG_TXP3 [11]
PEG_TXN3 [11]

Platform
Carrizo CH4222K9B04

Gen 3
Gen 1/Gen 2

P/NType

CH4103K1B08Carrizo-L

R78
CZ@196/F_4

A A

5

4

CZ: R91 & R78

Z-L: R81 & R84

C

3

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

NB5

NB5

2

NB5

Date: Sheet of

Date: Sheet of

Date: Sheet of

Carrizo 1/7 (PCIE)

Carrizo 1/7 (PCIE)

Carrizo 1/7 (PCIE)

Friday, July 24, 2015 2 62

Friday, July 24, 2015 2 62

Friday, July 24, 2015 2 62

1

1A

1A

1A

5

4

3

2

1

03

Ronny@1013:
2 So-Dimm per Channel (B)

D D

C C

B B

TP68

M_VREF

+1.35VSUS

R680
1K/F_4

M_VREF

AE28

MA_ADD[0]

Y27

MA_ADD[1]

Y29

MA_ADD[2]

Y26

MA_ADD[3]

W28

MA_ADD[4]

W29

MA_ADD[5]

W26

MA_ADD[6]

U29

MA_ADD[7]

W25

MA_ADD[8]

U26

MA_ADD[9]

AG29

MA_ADD[10]

U27

MA_ADD[11]

T28

MA_ADD[12]

AK26

MA_ADD[13]

T26

MA_ADD[14]/MA_BG[1]

T25

MA_ADD[15]/MA_ACT_L

AG26

MA_BANK[0]

AG27

MA_BANK[1]

T29

MA_BANK[2]/MA_BG[0]

E19

MA_DM[0]

D21

MA_DM[1]

K21

MA_DM[2]

F29

MA_DM[3]

AP28

MA_DM[4]

AV26

MA_DM[5]

AR22

MA_DM[6]

BC22

MA_DM[7]

K29

MA_DM[8]

H19

MA_DQS_H[0]

G19

MA_DQS_L[0]

B22

MA_DQS_H[1]

A22

MA_DQS_L[1]

F23

MA_DQS_H[2]

E23

MA_DQS_L[2]

G27

MA_DQS_H[3]

F27

MA_DQS_L[3]

AP25

MA_DQS_H[4]

AP26

MA_DQS_L[4]

AW27

MA_DQS_H[5]

AV27

MA_DQS_L[5]

AV22

MA_DQS_H[6]

AU22

MA_DQS_L[6]

BA21

MA_DQS_H[7]

AY21

MA_DQS_L[7]

L27

MA_DQS_H[8]

L26

MA_DQS_L[8]

AE25

MA_CLK_H[0]

AE26

MA_CLK_L[0]

AD26

MA_CLK_H[1]

AD27

MA_CLK_L[1]

AB28

MA_CLK_H[2]

AB29

MA_CLK_L[2]

AB25

MA_CLK_H[3]

AB26

MA_CLK_L[3]

N29

MA_RESET_L

AE29

MA_EVENT_L

P27

MA_CKE0

P29

MA_CKE1

AK27

MA0_ODT[0]

AL26

MA0_ODT[1]

AH25

MA1_ODT[0]

AL25

MA1_ODT[1]

AH26

MA0_CS_L[0]

AL29

MA0_CS_L[1]

AH29

MA1_CS_L[0]

AL28

MA1_CS_L[1]

AG24

MA_RAS_L/MA_RAS_L_ADD[16]

AK29

MA_CAS_L/MA_CAS_L_ADD[15]

AH28

MA_WE_L/MA_WE_L_ADD[14]

B19

MA_VREFDQ

T32

M_VREF

1013@RNY: Also need to check AMD whether it can float ot not?
1102@RNY: AMD recommend reserve test point at VREFDQ/ZVDDIO_MEM_S

U24A

MEMORY A

FP4 REV 1.0

H17

MA_DATA[0]

J17

MA_DATA[1]

F20

MA_DATA[2]

H20

MA_DATA[3]

E17

MA_DATA[4]

F17

MA_DATA[5]

K18

MA_DATA[6]

E20

MA_DATA[7]

A21

MA_DATA[8]

C21

MA_DATA[9]

C23

MA_DATA[10]

D23

MA_DATA[11]

B20

MA_DATA[12]

B21

MA_DATA[13]

B23

MA_DATA[14]

A23

MA_DATA[15]

G22

MA_DATA[16]

H22

MA_DATA[17]

E25

MA_DATA[18]

G25

MA_DATA[19]

J20

MA_DATA[20]

E22

MA_DATA[21]

H23

MA_DATA[22]

J23

MA_DATA[23]

F26

MA_DATA[24]

E27

MA_DATA[25]

J26

MA_DATA[26]

J27

MA_DATA[27]

H25

MA_DATA[28]

E26

MA_DATA[29]

G28

MA_DATA[30]

G29

MA_DATA[31]

AN26

MA_DATA[32]

AP29

MA_DATA[33]

AR26

MA_DATA[34]

AP24

MA_DATA[35]

AN29

MA_DATA[36]

AN27

MA_DATA[37]

AR29

MA_DATA[38]

AR27

MA_DATA[39]

AU26

MA_DATA[40]

AV29

MA_DATA[41]

AU25

MA_DATA[42]

AW25

MA_DATA[43]

AU29

MA_DATA[44]

AU28

MA_DATA[45]

AW26

MA_DATA[46]

AT25

MA_DATA[47]

AV23

MA_DATA[48]

AW23

MA_DATA[49]

AV20

MA_DATA[50]

AW20

MA_DATA[51]

AR23

MA_DATA[52]

AT23

MA_DATA[53]

AR20

MA_DATA[54]

AT20

MA_DATA[55]

BB23

MA_DATA[56]

BB22

MA_DATA[57]

BB20

MA_DATA[58]

AY19

MA_DATA[59]

BA23

MA_DATA[60]

BC23

MA_DATA[61]

BC21

MA_DATA[62]

BB21

MA_DATA[63]

K26

MA_CHECK[0]

K28

MA_CHECK[1]

N26

MA_CHECK[2]

N28

MA_CHECK[3]

J29

MA_CHECK[4]

K25

MA_CHECK[5]

L29

MA_CHECK[6]

N25

MA_CHECK[7]

AD29

MA_ZVDDIO_MEM_S

*FP4

TP21

M_B_A[15:0][9,10]

M_B_BS#[2..0][9,10]

M_B_DM[7..0][9,10]

CR-L only channel B

U24I

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_BS#0
M_B_BS#1
M_B_BS#2

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

TP75

M_B_DQSP0[9,10]
M_B_DQSN0[9,10]
M_B_DQSP1[9,10]
M_B_DQSN1[9,10]
M_B_DQSP2[9,10]
M_B_DQSN2[9,10]
M_B_DQSP3[9,10]
M_B_DQSN3[9,10]
M_B_DQSP4[9,10]
M_B_DQSN4[9,10]
M_B_DQSP5[9,10]
M_B_DQSN5[9,10]
M_B_DQSP6[9,10]
M_B_DQSN6[9,10]
M_B_DQSP7[9,10]
M_B_DQSN7[9,10]

M_B_CLKP0[9]
M_B_CLKN0[9]
M_B_CLKP1[9]
M_B_CLKN1[9]
M_B_CLKP2[10]
M_B_CLKN2[10]
M_B_CLKP3[10]
M_B_CLKN3[10]

M_B_RST#[9,10]

M_B_EVENT#[9,10]

M_B_CKE0[9,10]
M_B_CKE1[9,10]

M_B_ODT0[9]
M_B_ODT1[9]
M_B1_ODT0[10]
M_B1_ODT1[10]

M_B_CS#0[9]
M_B_CS#1[9]
M_B1_CS#0[10]
M_B1_CS#1[10]

M_B_RAS#[9,10]
M_B_CAS#[9,10]
M_B_WE#[9,10]

M_B_DM8

M_B_VREFDQ[9,10]

AG31

MB_ADD[0]

AC30

MB_ADD[1]

AC31

MB_ADD[2]

AB32

MB_ADD[3]

AA32

MB_ADD[4]

AA33

MB_ADD[5]

AA31

MB_ADD[6]

Y33

MB_ADD[7]

AA30

MB_ADD[8]

W32

MB_ADD[9]

AG32

MB_ADD[10]

Y32

MB_ADD[11]

W33

MB_ADD[12]

AL31

MB_ADD[13]

W30

MB_ADD[14]/MB_BG[1]

V32

MB_ADD[15]/MB_ACT_L

AH32

MB_BANK[0]

AG33

MB_BANK[1]

W31

MB_BANK[2]/MB_BG[0]

D25

MB_DM[0]

D29

MB_DM[1]

E33

MB_DM[2]

J33

MB_DM[3]

AR30

MB_DM[4]

AW30

MB_DM[5]

BC30

MB_DM[6]

BC26

MB_DM[7]

N33

MB_DM[8]

B26

MB_DQS_H[0]

A26

MB_DQS_L[0]

B30

MB_DQS_H[1]

A30

MB_DQS_L[1]

F32

MB_DQS_H[2]

E32

MB_DQS_L[2]

K32

MB_DQS_H[3]

J32

MB_DQS_L[3]

AR32

MB_DQS_H[4]

AR33

MB_DQS_L[4]

AW32

MB_DQS_H[5]

AW33

MB_DQS_L[5]

BA29

MB_DQS_H[6]

AY29

MB_DQS_L[6]

BA25

MB_DQS_H[7]

AY25

MB_DQS_L[7]

P32

MB_DQS_H[8]

N32

MB_DQS_L[8]

AE33

MB_CLK_H[0]

AE32

MB_CLK_L[0]

AE30

MB_CLK_H[1]

AE31

MB_CLK_L[1]

AD32

MB_CLK_H[2]

AD33

MB_CLK_L[2]

AC33

MB_CLK_H[3]

AC32

MB_CLK_L[3]

T33

MB_RESET_L

AG30

MB_EVENT_L

U32

MB_CKE0

U33

MB_CKE1

AL30

MB0_ODT[0]

AM32

MB0_ODT[1]

AJ32

MB1_ODT[0]

AM33

MB1_ODT[1]

AJ33

MB0_CS_L[0]

AL32

MB0_CS_L[1]

AJ30

MB1_CS_L[0]

AL33

MB1_CS_L[1]

AH33

MB_RAS_L/MB_RAS_L_ADD[16]

AK32

MB_CAS_L/MB_CAS_L_ADD[15]

AJ31

MB_WE_L/MB_WE_L_ADD[14]

A19

MB_VREFDQ

MEMORY B

FP4 REV 1.0

A25
C25
C27
D27
B24
B25
B27
A27

A29
C29
B32
D32
B28
B29
A31
C31

E30
E31
G33
G32
C33
D33
G30
G31

J30
J31
L33
L32
H32
H33
L30
L31

AN31
AP32
AT32
AU32
AN33
AN32
AR31
AT33

AU30
AV32
BA33
AY32
AU33
AU31
AW31
AY33

BC31
BB30
BB28
AY27
BB32
BA31
BC29
BB29

BB27
BB26
BB24
AY23
BA27
BC27
BC25
BB25

N30
N31
R33
R32
M32
M33
R30
R31

AF32

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7

M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15

M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23

M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31

M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39

M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47

M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55

M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_ZVDDIO

R670 39.2/F_4

MB_DATA[0]
MB_DATA[1]
MB_DATA[2]
MB_DATA[3]
MB_DATA[4]
MB_DATA[5]
MB_DATA[6]
MB_DATA[7]

MB_DATA[8]

MB_DATA[9]
MB_DATA[10]
MB_DATA[11]
MB_DATA[12]
MB_DATA[13]
MB_DATA[14]
MB_DATA[15]

MB_DATA[16]
MB_DATA[17]
MB_DATA[18]
MB_DATA[19]
MB_DATA[20]
MB_DATA[21]
MB_DATA[22]
MB_DATA[23]

MB_DATA[24]
MB_DATA[25]
MB_DATA[26]
MB_DATA[27]
MB_DATA[28]
MB_DATA[29]
MB_DATA[30]
MB_DATA[31]

MB_DATA[32]
MB_DATA[33]
MB_DATA[34]
MB_DATA[35]
MB_DATA[36]
MB_DATA[37]
MB_DATA[38]
MB_DATA[39]

MB_DATA[40]
MB_DATA[41]
MB_DATA[42]
MB_DATA[43]
MB_DATA[44]
MB_DATA[45]
MB_DATA[46]
MB_DATA[47]

MB_DATA[48]
MB_DATA[49]
MB_DATA[50]
MB_DATA[51]
MB_DATA[52]
MB_DATA[53]
MB_DATA[54]
MB_DATA[55]

MB_DATA[56]
MB_DATA[57]
MB_DATA[58]
MB_DATA[59]
MB_DATA[60]
MB_DATA[61]
MB_DATA[62]
MB_DATA[63]

MB_CHECK[0]
MB_CHECK[1]
MB_CHECK[2]
MB_CHECK[3]
MB_CHECK[4]
MB_CHECK[5]
MB_CHECK[6]
MB_CHECK[7]

MB_ZVDDIO_MEM_S

*FP4

M_B_DQ[0..63] [9,10]

+1.35VSUS

R678 *0_4/S

R679

A A

1K/F_4

C587
1000P/50V_4

C586

0.1U/16V/X7R_4

1 2

C585

0.47U/10V_4

Place within 1000mil of the APU

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Carrizo 2/7 (MEM)

Carrizo 2/7 (MEM)

NB5

NB5

5

4

3

2

NB5

Carrizo 2/7 (MEM)

Date: Sheet of

Friday, July 24, 2015 3 62

Date: Sheet of

Friday, July 24, 2015 3 62

Date: Sheet of

Friday, July 24, 2015 3 62

1

1A

1A

1A

5

4

3

2

1

Boot Voltage

1.1V

1.0V

0.8V

04

1A

1A

1A

+1.8V

APU_PROCHOT#

1
2

74LVC2G07GW

APU_RST#
APU_PW ROK

APU_PROCHOT#
APU_ALERT#
APU_SIC
APU_SID

KBC_SMDATA

1

2

3

U12
TC7SH08FU

4

C327

0.1U/16V/X7R_4

U11

A1

Y1

GND

VCC

A23Y2

5

KBC_SMCLK

KBC_PROCHOT[39]

APU_PROCHOT#[43,4 8,50]

OCP_PW M_OUT[40]

PJA138K
Q49

+3V

3 5

6
5
4

+3V CZ18V_CZL 30V

+1.8V

+1.8V

5

6

2

+1.8V

KBC_PROCHOT

APU_PROCHOT#

FAN_FULL_ SPEED# [35,36]

C331

0.1U/16V/X7R_4

2

APU_RST#

1

+3V

+1.8V

R295

R290

0_4

*0_4

1K/F_4

APU_PW ROK_BUF

R2

R169 *CZL@0_4

R1

R176 CZ@0_4

Z: R1

C
CZ

-L: R2

LS

43

APU_SIC

1

APU_SID

Q26
DMN5L06DW K/50V_0.302A

Q53

5

2
6

2N7002DW

+1.8V

R284

R288

1K/F_4

1016: Alfred
S

wap the DDI Port frm DDI2 to DDI1.

CZ only

HDMI

DP Switch or
DP to VGA Chip

eDP

INT

43

1

+1.8V

TP35

APU_TEST18
APU_TEST19
APU_RST_L_BUF
CPU_LDT_RST_HTPA#
APU_DBREQ#
APU_DBRDY
APU_TCK
APU_TMS
APU_TDI
APU_TRST#
APU_TDO
APU_PW ROK_BUF

Thermal Sensor

ALF@1025:
CZ & CZ-L for LS

TP25

APU_PG[48,50]

C251
*150P/50 V_4

HDT CONN

88511-20 01-20p-l

C294
*150P/50 V_4

J1

Close to HDT & No remove.

APU_TDI

R409 1K/F_4

APU_TCK

R407 1K/F_4

APU_TMS

R410 1K/F_4

APU_TRST#

R408 1K/F_4

APU_DBREQ#

R400 1K/F_4

4

DDI1_TX0_P[21]
DDI1_TX0_N[21]

DDI1_TX1_P[21]
DDI1_TX1_N[21]

DDI1_TX2_P[21]
DDI1_TX2_N[21]

DDI1_TX3_P[21]
DDI1_TX3_N[21]

INT_eDP_TXP0[19]
INT_eDP_TXN0[19]

INT_eDP_TXP1[19]
INT_eDP_TXN1[19]

APU_RST#
APU_PW ROK

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+1.8V

IN_D2[21]
IN_D2#[21]

IN_D1[21]
IN_D1#[21]

IN_D0[21]
IN_D0#[21]

IN_CLK[21]
IN_CLK#[21]

R255 *0_4/S

DISPLAY/SVI2/JTAG/TEST

B6

DP2_TXP[0]

A6

DP2_TXN[0]

D7

DP2_TXP[1]

C7

DP2_TXN[1]

A7

DP2_TXP[2]

B7

DP2_TXN[2]

D9

DP2_TXP[3]

C9

DP2_TXN[3]

A2

DP1_TXP[0]

A3

DP1_TXN[0]

B4

DP1_TXP[1]

A4

DP1_TXN[1]

D5

DP1_TXP[2]

C5

DP1_TXN[2]

A5

DP1_TXP[3]

B5

DP1_TXN[3]

E2

DP0_TXP[0]

E1

DP0_TXN[0]

E3

DP0_TXP[1]

E4

DP0_TXN[1]

D1

DP0_TXP[2]

D2

DP0_TXN[2]

C1

DP0_TXP[3]

B1

DP0_TXN[3]

SVT
SVC
SVD

GFX_SVT_R
GFX_SVC_ R
GFX_SVD_ R

APU_SIC
APU_SID

APU_RST#
APU_PW ROK

APU_PROCHOT#
APU_ALERT#

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

C15

SVT0

D17

SVC0

D19

SVD0

B15

SVT1

B16

SVC1

A18

SVD1

B18

SIC

C17

SID

D15

RESET_L

C19

PWROK

A15

PROCHOT_L

B17

ALERT_L

H15

TDI

H14

TDO

D13

TCK

G15

TMS

J14

TRST_L

C13

DBRDY

A11

DBREQ_L

IO Thermal Protect

ALF@1031:
Del NTC Circuit

3

FP4 REV 1.0

CZ: Ra+LS / 1.8V interface (level-shifter)
CZ-L: Rb / 3.3V interface

U24C

A9

DP_ZVSS

DP_AUX_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

DP2_AUXP
DP2_AUXN

DP2_HPD

DP1_AUXP
DP1_AUXN

DP1_HPD

DP0_AUXP
DP0_AUXN

DP0_HPD

TEMPIN0
TEMPIN1
TEMPIN2

TEMPINRETURN

TEST28_H
TEST28_L

DP_STEREOSYNC/TEST36

RSVD_1

TEST410
TEST411

TEST4
TEST5
TEST6

TEST9
TEST10
TEST14
TEST15
TEST16
TEST17
TEST11
TEST18
TEST19

TEST31

TEST37

DP_ZVSS

B9

DP_AUX_ZVSS

G5

APU_LVDS _BLON

G6

APU_DISP_ON

F11

APU_DPST_P WM

H9
G9
E9

F7
E7
F5

F8

INT_eDP_AUXP

E8

INT_eDP_AUXN

G8
K24

CORETYPE

E15

APU_TEMPIN0

E14

APU_TEMPIN1

E12

APU_TEMPIN2

F14

APU_TEMPRETURN

AK24

APU_TEST410

AL24

APU_TEST411

P24

APU_THERMDA

N24

APU_THERMDC

AN24

APU_TEST6

AB8

APU_TEST9

Y9

APU_TEST10

B10

APU_TEST14

D11

APU_TEST15

A10

APU_TEST16

C11

APU_TEST17

B11

APU_TEST11

A14

APU_TEST18

B14

APU_TEST19

A13

APU_TEST28_ H

B13

APU_TEST28_ L

P26

APU_TEST31

E11

DP_STEREOS YNC

A17

APU_TEST37

R458 2K/F_ 4
R451 150/F_4

APU_LVDS _BLON [19]
APU_DISP_ON [19]
APU_DPST_P WM [19]

TP34
TP17
TP16
TP64

R508 *0_4/S

TP22
TP23
TP20
TP19
TP31

R446 *1K/F_4

TP15
TP24

R452 *1K/F_4
R493 *1K/F_4
R482 *1K/F_4
R279 1K/F_4
R243 1K/F_4

TP66

R700 *1K/F_4

TP65

R693 *1K/F_4
R159 1K/F_4
R158 *1K/F_4
R531 *1K/F_4
R530 *1K/F_4

CZ only

IN_DDC_SCL [21]
IN_DDC_SDA [21]
IN_HPD [21]

INT_DDI1_AUX P [21]
INT_DDI1_AUX N [21]
DDI1_HPD_CON [21]

INT_eDP_AUXP [19 ]
INT_eDP_AUXN [19]
EDP_HPD [19]

TP14

+1.8V
CZ18V_CZL 30V
+1.8V

RNY@1122
Move LS to LCD side and follow CRB

DP_STEREOSYNC: HDMI enable pin.

TP46
TP12
TP62

DIFFERENTIAL ROUTING

GFX_FB_H [50]
APU_VDDNB _FB_H [48]
APU_VDD_FB_H [48 ]

GFX_FB_L [50]
APU_VDD_VDDNB_FB_L [48]

R566
*1K/F_4

R545
*CZ@1K/F_4

2

+1.8V

R576

R513

*1K/F_4

*1K/F_4

SVT
SVC
SVD

+1.8V

12/9: confirm AMD PAE Scoop no need setting

VFIX MODE

R536

R518

*CZ@1K/F_4

*CZ@1K/F_4

GFX_SVT_R
GFX_SVC_ R
GFX_SVD_ R

NB5

NB5

NB5

VID Override table (VDD)

SVDSVC

0

0
0
110 0.9V

11

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Nu mber Rev

Size Document Nu mber Rev

Size Document Nu mber Rev

Carrizo 3/7 (DIS/MISC)

Carrizo 3/7 (DIS/MISC)

Carrizo 3/7 (DIS/MISC)

Date: Sheet of

Friday, July 24, 2 015 4 62

Date: Sheet of

Friday, July 24, 2 015 4 62

Date: Sheet of

Friday, July 24, 2 015 4 62

1

H11

VDDCR_GFX_SENSE

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

*FP4

VDDCR_GFX_ SENSE

J12

VDDCR_NB_S ENSE

G12

VDDCR_CPU_SENSE

AY18

VDDP_SENSE

VDDP_SENSE

H12

VSS_SENSE

VSS_SENSE

APU Serial VID

ALF@1030:
Needs confirm with AMD

APU_SVT[48]
APU_SVC[48]

APU_SVD[48]

GFX Serial VID

ALF@1030:
Needs confirm with AMD

GFX_SVT[50]
GFX_SVC[50]

GFX_SVD[50]

R494 CZ@0_4
R481 *0_4/S
R471 *0_4/S

TP27

R487 CZ@0_4
R478 *0_4/S

CZ: R494, R487 Stuff
CZ-L: R494, R487 No Stuff

VDDCR_CPU_SENSE
VDDCR_NB_S ENSE
VDDCR_GFX_ SENSE

Place near APU within 500mil

R507 *0_4/S
R575 36/F_4
R565 36/F_4

PV, 0414, change SVID R to 0 ohm
PV, 0420, change SVID R to 36 ohm

Place near APU within 500mil

R512 CZ@0_4
R535 CZ@0_4
R544 CZ@0_4

R198 301/F_4
R242 301/F_4

CZ18V_CZL 30V

D D

C C

B B

A A

R181 1K/F_4
R523 1K/F_4
R549 1K/F_4
R548 1K/F_4

CZ: LS, CZ18V_CZL30V=1.8V
CZ-L: LS, CZ18V_CZL30V=3.3V

KBC_SMCLK[12,20,36,39]

KBC_SMDATA[12,20,36,39]

APU_PROCHOT# Signal Level:
CZ: +1.8V
CZ-L: +3.3V

+1.8V

R710

2.2K_4

3

2

KBC_PROCHOT

2N7002K
Q54

1

HDT+ Connector for Debug only

Can remove on MP

CPU_LDT_RST_HTPA#

APU_RST# APU_RST_L_BUF
APU_PW ROK

5

+3V_DEEP_SUS+3V_DEEP_SUS

U21

*MC74VHC1G08DFT2G

PCIE_RST#_R1[11,24,26,29,34]

D D

+3V_DEEP_SUS

R404 *1K/F_4

1 2

G2

*SOLDERJUMPER-2

PCIE_RST#_R1

SYS_RST# internal 10K pull up

SYS_RST#

4

R418 *0_4/S

R422
*4.7K/F_4

35

1
2

PV, 0415, reserve NMI_SMI_DBG# PU resistor

+3V_DEEP_SUS

R736
10K/F_4

NMI_SMI_DBG#

+3V

R540 2.2K_4

+3V_DEEP_SUS

R539 2.2K_4

R167 10K/F_4
R301 10K/F_4

R229 10K/F_4

R403 2.2K_4
R405 2.2K_4
R406 10K/F_4
R417 10K/F_4
R166 *10K/F_4

C C

PCIE_WAKE# PU & LAN use 0 ohm to open.

B B

A A

R92 10K/F_4
R448 *10K/F_4
R415 10K/F_4

R231 10K/F_4

R350 *100K/F_4

ACZ_SDOUT_AUDIO[23]

ACZ_SYNC_AUDIO[23]

BIT_CLK_AUDIO[23]

ACZ_RST#_AUDIO[23]

ALF@1030:
For dGPU VGA REQ

DGPU_PWROK[5,11]

From dGPU PG Ready
(As default)

to DDR3 SMBUS

FCH_3S_SMCLK
FCH_3S_SMDATA

CLKREQG#
PCIE_CLKREQ_CARD#

FPR_OFF

to TP SMBUS

SMB_NIC_SMCLK
SMB_NIC_SMDATA
PWR_BTN_OUT#
NIC_SMBUS_ALERT#
DGPU_PWROK

APU_VRM_GFX_PWRGD

WLAN_WAKE#
LOW_BAT#

PV, 0420, delete CR_PWREN# pull-up resistor

CR_RST#

For EMI

VGA_EN

To Azalia

C90 1K/F_4

SI, 0117, fine tune GPU sequence

ACZ_SDIN0[23]

Pure UMA can remove

R160 *DIS@0_4/S

C143
DIS@0.47U/6.3V_4

5

Only CZ Stuff

ALF@1119:
Reserved the CLKREQG# for dGPU

PV, 0420, change NMI_SMI_DBG#
from AGPIO86 to AGPIO17, and delete CR_PWREN#

for GPIO145~148
CZ pop those resistor
CZ-L can NC them

ALF@1109:
HP request to add the
Card Reader weak feature

Q21

2

ACZ_SDOUT_R
ACZ_SYNC_R

ACZ_BCLK_R

ACZ_RST#_R
ACZ_SDIN0

3

1

CLKREQG#

R162
*DIS@10K_4

R129 33_4
R134 33_4

PV, 0414, pull-down 1K for AZ timing issue

R122 BLM15BB470SN1D(47,300MA)
R138 33_4

DIS@2N7002K

4

PCIE_RST#_R PCIE_RST#

R107 33_4

C78 150P/50V_4

LPC_RST#[29,38,39]

RSMRST#[42]

PWR_BTN_OUT#[40]
SYS_PWRGD[42]

SYS_RST#[6]

NIC_SMBUS_ALERT#[24]

SLP_S3#_3R[40,42,52]

SLP_S5#_3R[24,27,29,40,42]
S0A3_GPIO[39,42,52]

S5_MUX_CTRL[47]

TP67

FPR_OFF[17]

RUNSCI_EC#[36,39]

ADP_PRES_OUT[12,39,52]
ZERO_ODD_DA#[37]
ZERO_ODD_DP#[37]

TPM_INT#[26]

LOW_BAT#[39]

PCIE_CLKREQ_WLAN#[29]

KBL_DET#[32]

PCIE_CLKREQ_CARD#[34]

CLKREQG#[12]

SPI_TPM_CS#_CZL[26]

NMI_SMI_DBG#[38,39]

CR_RST#[34]

R121 *10K/F_4
R132 *10K/F_4
R143 10K/F_4
R144 10K/F_4

RTC_CLK[6,40]

C448 18P/50V_4

C455 18P/50V_4

23

4 1

PCIE_CLKREQ_LAN#_D[24]

4

C479150P/50V_4

R495 33_4

C459 *100P/50V_4

TP45

LOW_BAT#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ_WLAN#

PCIE_CLKREQ_CARD#
CLKREQG#
SPI_TPM_CS#_CZL
NMI_SMI_DBG#
CR_RST#
VBIOS_ID2

ACZ_BCLK_R
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_RST#_R
ACZ_SYNC_R
ACZ_SDOUT_R

R484 10K/F_4
R479 10K/F_4
R477 10K/F_4
R476 10K/F_4

32K_X1

R412

Y3

20M_4

32.768KHZ

32K_X2

ALF@1030:
For dGPU Power Enable Sequence & GPIOs

VGA_EN[53,56]

SI, 0117, fine tune GPU sequence

3

ALF@1110:
HP confirmed the 00 for DIS, 11 for UMA,
need to set in BOM

VBIOS_ID

Discrete VRAM Group #1
Discrete VRAM Group #2
Discrete VRAM Group #3
UMA

LPC_RST#_R
PCIE_RST#

PWR_BTN_OUT#
SYS_RST#

NIC_SMBUS_ALERT#

S0A3_GPIO

APU_TEST0
APU_TEST1
APU_TEST2

EC_RCIN#
FPR_OFF
RUNSCI_EC#

GPIO145
GPIO146
GPIO147
GPIO148

+3V

BC19

BC15
BC17

BB12

AY15

BB13

BB17
BB18

BB16

BB10

AN7
AE4
AE1

BC9
AF2
AG2

AK7
AH5

AE8
AH8

AH6
AK8
AE3

AD7

AG3
AD5
AL8
AN8
AE2

AH9
AG1
AH2
AL9

AU6
AR8
AP6
AR5
AU9
AT9
AR7

BB9
BB7
BC7

AG7

AT1

AT2

VBIOS_ID1 VBIOS_ID2

LPC_RST_L

PCIE_RST_L/EGPIO26

S5

RSMRST_L

PWR_BTN_L/AGPIO0
PWR_GOOD
SYS_RESET_L/AGPIO1

S5

WAKE_L/AGPIO2

S5

SLP_S3_L
SLP_S5_L

S0A3_GPIO/AGPIO10

S5

S5_MUX_CTRL/EGPIO42

S5

TEST0
TEST1/TMS
TEST2

ESPI_RESET_L/KBRST_L/AGPIO129
GA20IN/AGPIO126

S0

LPC_PME_L/AGPIO22

S5

LPC_SMI_L/AGPIO86

S0

AC_PRES/USB_OC4_L/IR_RX0/AGPIO23
IR_TX0/USB_OC5_L/AGPIO13
IR_TX1/USB_OC6_L/AGPIO14
IR_RX1/AGPIO15
IR_LED_L/LLB_L/AGPIO12

CLK_REQ0_L/SATA_IS0_L/ SATA_ZP0_L/AGPIO92

CLK_REQ1_L/AGPIO115
CLK_REQ2_L/AGPIO116
CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
CLK_REQG_L/OSCIN/EGPIO132
USB_OC0_L/TRST_L/AGPIO16
USB_OC1_L/TDI/AGPIO17
USB_OC2_L/TCK/AGPIO18
USB_OC3_L/TDO/AGPIO24

AZ_BITCLK/I2S_BCLK_MIC
AZ_SDIN0/I2S_DATA_MIC[0]
AZ_SDIN1/I2S_LR_PLAYBACK
AZ_SDIN2/I2S_DATA_PLAYBACK
AZ_RST_L/I2S_LR_MIC
AZ_SYNC/I2S_BCLK_PLAYBACK
AZ_SDOUT/I2S_DATA_MIC1

I2C0_SCL/EGPIO145

S0

I2C0_SDA/EGPIO146

S0

I2C1_SCL/EGPIO147

S0

I2C1_SDA/EGPIO148

S0

RTCCLK

X32K_X1

X32K_X2

1029@RNY: Add PU for LAN CLKREQ#

Q44
*2N7002K

3

R524 *0_4/S

DGPU_PWR_EN[55]

VGA_EN

2

R519
10K/F_4

1

PCIE_CLKREQ_LAN#

ALF@1031:
Following AMD Leading to add LS

D17

2 1

DIS@RB751V40

DGPU_PWR_EN

R454 DIS@4.7K_4

C470
DIS@0.47U/6.3V_4

SLP_S3#_3R

3

AGPIO24AGPIO6

0
0
1
1 1

ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC

X

X
S5

X

S5
X

Power Domain

CZ CZ-L

S0

S0

S0
S5
X

S5

S5

S5

S5
S5

S5

S5

S5

S5
S5

S5
S0

S0

S0

S0

S0

S0

S0

S0

S5

S5

S5

S5

S5

S5
S5

S5

X
S0
S0
S0

21

0
1
0

U24D

S0

S0

FP4 REV 1.0

*FP4

D16
DIS@RB751V40

+3V

+3V

Default

+3V_DEEP_SUS

S0

S0
X

S0
S0

S5

S0

S0
S0

S0

S0
S0

S0

S0

S0
S0

S0

S5

S5

S5

S5
S5
S5
S5
S5
S5
S0
S0

S0

S0

S0

S0
S0

S0
S0

S0

S0

S0

S0
S5
S0

S0
S0

S0
S0

S0
S0
S0
S0

UART1_CTS_L/BT_I2S_BCLK/EGPIO140

S0

X

UART1_RXD/BT_I2S_SDI/EGPIO141

S5

S0
S0

X

UART1_TXD/BT_I2S_SDO/EGPIO143

S0

X

UART1_INTR/BT_I2S_LRCLK/AGPIO144

S5

S0

R442 *10K/F_4
R439 10K/F_4
R112 *10K/F_4

R436 10K/F_4
R428 10K/F_4
R474 *10K/F_4
R450 *10K/F_4

R76 *10K/F_4
R98 *10K/F_4

SD0_WP/EGPIO101

SD0_PWR_CTRL/AGPIO102

SD0_CD/AGPIO25

SD0_CLK/EGPIO95

SD0_CMD/EGPIO96

SD0_DATA0/EGPIO97

S0

SD0_DATA1/EGPIO98

S0

SD0_DATA2/EGPIO99

S0S5S0

SD0_DATA3/EGPIO100

S0S5S0

SD0_LED/EGPIO93

S0

SCL0/I2C2_SCL/EGPIO113

SDA0/I2C2_SDA/EGPIO114

SCL1/I2C3_SCL/AGPIO19

SDA1/I2C3_SDA/AGPIO20

S5

S5

S5

S5

S5

S5

AGPIO6/LDT_RST_L

S5

AGPIO7/LDT_PWROK

S5
S5
S5

VDDGFX_PD/AGPIO39

X
X
S0
S0

AGPIO66/SHUTDOWN_L

AGPIO68/SGPIO_CLK

AGPIO69/SGPIO_LOAD

AGPIO71/SGPIO_DATAOUT

AGPIO72/SGPIO_DATAIN

SPKR/AGPIO91

S0

BLINK/USB_OC7_L/AGPIO1 1

S0

GENINT1_L/AGPIO89

S0

GENINT2_L/AGPIO90

S0

FANIN0/AGPIO84

S0

FANOUT0/AGPIO85

S0

UART0_CTS_L/EGPIO135

X

UART0_RXD/EGPIO136

X

UART0_RTS_L/EGPIO137

X

UART0_TXD/EGPIO138

X

UART0_INTR/AGPIO139

X

UART1_RTS_L/EGPIO142

PLT_ID1
PLT_ID2
PLT_ID3

BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4

VBIOS_ID1
VBIOS_ID2

ALF@1110:
HP confirmed Okay!!

BB2
BB5
BC2
BB4
AY5

BC3
BA3
BC5
BA5
BB6

BA15
AY17

AG5
AG4

AL5

AGPIO3

AL6

AGPIO4

AJ1

AGPIO5

AJ3
AH1
AJ4

AGPIO8

AK5

AGPIO9

AD8
AG8

AGPIO40

AW15

AGPIO64

AU15

AGPIO65

AT15

R440 *0_4/S

AU12
AT14
AR14
BC13

BA17
AN5
BB14

BA19
BC18

BB19
AY9

AW8
AV5
AV8
AW9

AV11
AU7
AT11
AR11
AP9

2

R441 10K/F_4
R438 *10K/F_4
R111 10K/F_4

R433 *10K/F_4
R426 *10K/F_4
R456 10K/F_4
R449 10K/F_4

R82 10K/F_4
R105 10K/F_4

PLT_ID3

PLT_ID1
PLT_ID2

BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4

FCH_3S_SMCLK
FCH_3S_SMDATA

SMB_NIC_SMCLK
SMB_NIC_SMDATA

LANLINK#
VBIOS_ID1

WOL_EN
WLAN_WAKE#

VDDGFX_PD
APU_VRM_GFX_PWRGD

DGPU_PWR_EN

FPR_LOCK#
HDD_HALTLED

AGPIO11

R510 *150/F_4

ACCEL_INTH

2

1

Palazzo 15"

RD_ID1 BRD_ID2 BRD_ID3 BRD_ID4

BOARD REVISION

ODD_PWR [37]

FCH_3S_SMCLK [9,10,20,28]
FCH_3S_SMDATA [9,10,20,28]

SMB_NIC_SMCLK [34]
SMB_NIC_SMDATA [34]

RNY@1108: Changed LANLINK# to PU

AGPIO3 [6]
LANLINK# [24]

FCH_WAKE#_EC [39]

WOL_EN [52]

TP13
TP5

WLAN_OFF [29]
WLAN_TRANSMIT_OFF# [29]

SI, 0117, fine tune GPU sequence

DPTMDS_SEL [21]
FPR_LOCK# [17]
HDD_HALTLED [34]

DGPU_PWROK [5,11]

SPKR [23]
AGPIO11 [6]

GENINT1: HVB function
Vss:enabke; NC: disable

BT_OFF [29]
DGPU_HOLD_RST# [11]

+3V_DEEP_SUS

B
EG

PIO97 EGPIO98 EGPIO99 EGPIO100

DB0
DB1
DB2

SI1
SIB
SI2

PV1

MV1

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 10 1
1 1 0 0

ALF@1105:
Changed the "ODD_PWR" to EGPIO93

ALF@1107:
Changed WOL_EN and PD

+3V

3

1

R424 *2.2K_4
R475 *1K/F_4
R416 *2.2K_4

PLT_ID1 PLT_ID2 PLT_ID3

0 01

+3V

R147
10K/F_4

2

+3V

2N7002K
Q19

APU_TEST0
APU_TEST1
APU_TEST2

EGPIO101EGPIO96EGPIO95

111 0

111 0

1111

+3V_DEEP_SUS

LANLINK#

R435 10K/F_4

WOL_EN

R411 10K/F_4

Only CZ Stuff if no used

DGPU_HOLD_RST#

R550 *10K/F_4
R727 *10K/F_4

SI, 0201, reserved for
fine tune GPU sequence

PV, 0414, change ACCEL_INTH GPIO pin
and Pull-up power rail

R164
*10K/F_4

R726 10K/F_4

R447 *100K/F_4

Only CZ-L Stuff if no used

SI, 0201, fine tune GPU sequence

ACCEL_INTH# [28]

R425 15K/F_4
R473 15K/F_4
R420 15K/F_4

Follow AMD checklist 53537_1_03 suggestion to stuff R118/R120/R122

TEST2 TEST1 TEST0 Description

0

0 0

0

0

0

1

1

TMS

1 TMS

FCH TAP accessible from APU when TAPEN is asserted
FCH JTAG pins are overloaded for multiple
functions, in this configuration the FCH JTAG are
used as non-JTAG pins

1

Reserved

X

Reserved

FCH JTAG multi-function pins are configured as

0

JTAG pins, in this configuration the FCH TAP
can be accessed from FCH JTAG pins

Use on ATE only
Yuba JTAG enabled

1

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Carrizo 4/7 (GPIO/AZ/UARTH)

Carrizo 4/7 (GPIO/AZ/UARTH)

NB5

NB5

NB5

Carrizo 4/7 (GPIO/AZ/UARTH)

Friday, July 24, 2015 5 62

Date: Sheet of

Friday, July 24, 2015 5 62

Date: Sheet of

Friday, July 24, 2015 5 62

Date: Sheet

1

05

Default

+3V

DGPU_PWR_EN

of

1A

1A

1A

5

4

3

2

1

Only CZ Stuff if no used

1029@RNY: DEVSLP0 is used, PU no need

+3V

R179 *10K/F_4
R182 10K/F_4

R489 *10K/F_4

D D

ALF@1109:
HP request to add Card Reader weak feature

R455 10K/F_4

SI, 0203, change cap to fine tune XTAL

C74

4.7P/50V_4

C67

4.7P/50V_4

C C

+3V

R480
R514 10K/F_4
R597 10K/F_4

R488 *150/F_4

DEVSLP0
CAMERA_ON

SPI_TPM_CS#
EGPIO119

Y1

48MHZ +-10PPM

*MC74VHC1G08DFT2G

R83
1M/F_4

LED_3S_SATA#[34]

1

2

4

3

PV, 0414, change CLK_R3S_DEBUG R to 56ohm for CZ

4.7K_4

PCI_3S_CLKRUN#
SB_SATA_LED#
PCI_3S_SERIRQ

PCI_3S_CLKRUN#

+3V

U23

4

2
1

3 5

R522 *0_4/S

48M_X1

48M_X2

CLK_R3S_KBC[29,39]

CLK_R3S_DEBUG[38]

1029@RNY: follow Leading NC

PV, 0415, follow AMD DG to PD LPC_PD_L, no used

ALF@1103:
HP request to add SPI_WP to SPI

C492
*0.1U/16V/X7R_4

CLK_PCIE_LANP[24]
CLK_PCIE_LANN[24]

CLK_PCIE_CARDP[34]
CLK_PCIE_CARDN[34]

SPI_CS0#[41]
SPI_CLK[41]
SPI_SO[41]
SPI_SI[41]

SPI_TPM_CS#[26]

SPI_WP[41]

SATA_TXP0[37]

HDD

ODD

+0.95V

PV, 0414, change AGPIO90 to CAMERA_ON

Integrated Clock Mode:
Leave unconnected.

CLK_GFX_P[11]
CLK_GFX_N[11]

CLK_WLAN_P[29]
CLK_WLAN_N[29]

PV, 0414, change RP1 to 33ohm, RP2 to 47ohm for CZ

C485 *10P/50V_4

C473 *10P/50V_4

SPI_CS0#
SPI_CLK
SPI_SO
SPI_SI
SPI_TPM_CS#
SPI_WP

SATA_TXN0[37]
SATA_RXN0[37]

SATA_RXP0[37]
SATA_TXP1[37]

SATA_TXN1[37]
SATA_RXN1[37]

SATA_RXP1[37]

R427 1K/F_4
R434 1K/F_4

DEVSLP0[37]

CAMERA_ON[19]

2

RP1

4

33_4P2R_4

2

RP4

4

0_4P2R_4

2

RP2

4

47_4P2R_4

2

RP3

4

0_4P2R_4

SI, 0203, EMI solution

R496 BLM15BB470SN1D(47,300MA)

R486 56_4

LAD0[29,38,39]
LAD1[29,38,39]
LAD2[29,38,39]
LAD3[29,38,39]

LFRAME#[29,38,39]

TP39

PCI_3S_SERIRQ[38,39]

PCI_3S_CLKRUN#[39]

R156

TP41
TP1
TP40
TP36
TP42
TP53
TP44
TP60

C467

PV, 0421, TP42 change to 2075 for layout

*15P/50V_4

1
3

1
3

1
3

1
3

TP4

TP3

TP37

TP38

CLK_GFX_P_R
CLK_GFX_N_R

CLK_PCIE_LANP_R
CLK_PCIE_LANN_R

CLK_PCIE_WLAN_R
CLK_PCIE_WLAN#_R

CLK_PCIE_CARDP_R
CLK_PCIE_CARDN_R

PCI_3S_SERIRQ

10K/F_4

SATA_CALRN
SATA_CALRP
DEVSLP0
CAMERA_ON
SB_SATA_LED#

48M_X1

48M_X2

LPC_CLK0
LPC_CLK1

LFRAME#
LDRQ#0

LPC_PD#

SPI_CLK
SPI_CS0#
EGPIO119
SPI_SI
SPI_SO
SPI_WP
SPI_HOLD#
SPI_TPM_CS#

AU3

SATA_TX0P

AU4

SATA_TX0N

AV1

SATA_RX0N

AV2

SATA_RX0P

AY2

SATA_TX1P

AY1

SATA_TX1N

AW4

SATA_RX1N

AW3

SATA_RX1P

AW1

SATA_ZVSS

AW2

SATA_ZVDDP

AT17

DEVSLP[0]/EGPIO67

AT12

DEVSLP[1]/EGPIO70

BB15

SATA_ACT_L/AGPIO13 0

AU2

SATA_X1

AU1

SATA_X2

U4

GFX_CLKP

U3

GFX_CLKN

U1

GPP_CLK0P

U2

GPP_CLK0N

W4

GPP_CLK1P

W3

GPP_CLK1N

W1

GPP_CLK2P

W2

GPP_CLK2N

Y2

GPP_CLK3P

Y1

GPP_CLK3N

BC10

X25M_48M_OSC

T2

X48M_X1

T1

X48M_X2

AW14

LPCCLK0/EGPIO74

AY13

LPCCLK1/EGPIO75

BB11

LAD0

BA11

LAD1

AY11

LAD2

BA13

LAD3

AV14

LFRAME_L

BA1

ESPI_ALERT_L/LDRQ0 _L

BC14

SERIRQ/AGPIO87

BC11

LPC_CLKRUN_L/AGPIO88

AE9

LPC_PD_L/AGPIO21

BC6

SPI_CLK/ESPI_CLK/EG PIO117

BB8

SPI_CS1_L/EGPIO11 8

AW7

SPI_CS2_L/ESPI_CS _L/EGPIO119

BA9

SPI_DI/ESPI_DATA /EGPIO120

AY7

SPI_DO/EGPIO121

AW11

SPI_WP_L/EGPIO1 22

BA7

SPI_HOLD_L/EGPIO133

AW12

SPI_TPM_CS_L/AGPIO76

U24E

CLK/SATA/USB/SPI/LPC

FP4 REV 1.0

*FP4

USBCLK/25M_48M_OSC

USB_ZVSS

USB_HSD0P
USB_HSD0N

USB_HSD1P
USB_HSD1N

USB_HSD2P
USB_HSD2N

USB_HSD3P
USB_HSD3N

USB_HSD4P
USB_HSD4N

USB_HSD5P
USB_HSD5N

USB_HSD6P
USB_HSD6N

USB_HSD7P
USB_HSD7N

USB_SS_ZVSS

USB_SS_ZVDDP

USB_SS_0TXP
USB_SS_0TXN

USB_SS_0RXP
USB_SS_0RXN

USB_SS_1TXP
USB_SS_1TXN

USB_SS_1RXP
USB_SS_1RXN

USB_SS_2TXP
USB_SS_2TXN

USB_SS_2RXP
USB_SS_2RXN

USB_SS_3TXP
USB_SS_3TXN

USB_SS_3RXP
USB_SS_3RXN

AP8
AP5

USB_ZVSS

AR2
AR1

AR3
AR4

AN2
AN1

AN3
AN4

AM1
AM2

AL2
AL1

AL3
AL4

AK2
AJ2

R137 11.8K/F_4

USBP0+ [19]
USBP0- [19]

USBP1+ [24]
USBP1- [24]

USBP2+ [24]
USBP2- [24]

USBP4+ [29]
USBP4- [29]

USBP5+ [17]
USBP5- [17]

USBP6+ [27]
USBP6- [27]

USBP7+ [27]
USBP7- [27]

Camera USB

DB right side USB2.0 port
DB right side USB2.0 port

ALF@1029:
Del the USB2.0 for Touch Screen

WLAN Min-Card
Finger Printer
le

ft side USB Combo 3.0/2.0.

left side USB Combo 3.0/2.0.
CZ: Maximum 8 devices (Ex: 8 USB2.0 –OR-- 4 USB2.0 + 4 USB3.0 external, etc…)
CZ-L: Maximum 8 devices (Ex: 8 USB2.0 –OR-- 6 USB2.0 + 2 USB3.0 external, etc…)

+0.95V_DEEP_SUS

Support S3~S5 wake up

+0.95V

No support S3~S5 wake up

+3V_DEEP_SUS +3V_DEEP_SUS +3V_DEEP_SUS+3V_DEEP_SUS+3V +3V +3V

AD2
AD1

AA3
AA4

W9
W8

AA2
AA1

W5
W6

AC1
AC2

Y6
Y7

AC4
AC3

AB5
AB6

USBSS_CALRN
USBSS_CALRP

R931K/F_4
R941K/F_4

USB30_TX2+ [27]
USB30_TX2- [27]

USB30_RX2+ [27]

USB30_RX2- [27]
USB30_TX3+ [27]

USB30_TX3- [27]

USB30_RX3+ [27]

USB30_RX3- [27]

R73 *0_4/S

R74 *0_4

Left side USB Combo 3.0/2.0.

Left side USB Combo 3.0/2.0.

06

STRAPS PINS

AGPIO11

1

R401
10K/F_4

R421
*2K/F_4

normal reset mode

short reset modeLDT_RST#/LDT_PWRGD

SYS_RST#

DEFAULT

1A

1A

1A

R504

B B

1024@Ronny: AGPIO11 STRAP?

A A

5

4

OVERLAP COMMON PADS WHERE
POSSIBLE FOR DUAL-OP RESISTORS.

AGPIO3[5]
RTC_CLK[5,40]
AGPIO11[5]
SYS_RST#[5]

REQUIRED STRAPS

LPC_CLK0 BLINK

BOOT FAIL TIMER

PULL

ENABLED

HIGH

BOOT FAIL TIMER

PULL

DISABLED

LOW

3

DEFAULT

LPC_CLK0
LPC_CLK1
LFRAME#

CZ: pop R445
CZ-L:pop R457

LPC_CLK1

Use 48Mhz crystal clock
and generate both internal
and external clocks

DEFAULT

Use 100Mhz PCIE clock as
reference clock and generate
internal clocks only

Follow FAE comment: R659 change to 2K, R401 to 10k, R142 is NC

LFRAME#

SPI ROM

DEFAULT

LPC ROM

2

*10K/F_4

R506
2K/F_4

R491
10K/F_4

R485
*2K/F_4

AGPIO3
Int Pull-Up

CZ-L CZ

1.8V SPI ROM

3.3V SPI ROM

DEFAULT

R445

R174

CZ@10K/F_4

10K/F_4

R168

R457

*2K/F_4

*CZL@2K/F_4

RTC_CLK

Int Pull-Up Int Pull-Up Int Pull-Up

NB5

NB5

NB5

Coin battery is
on board.

Coin battery is
not on board.

Enhanced reset logic
(for quicker S5 resume)

DEFAULT DEFAULT DEFAULT

Default to
traditional reset logic

R142

R672

*10K/F_4

10K/F_4

R141

R659

*2K/F_4

*2K/F_4

LDT_RST#/LDT_PWRGD
output to APU

output to Pads

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Carrizo 5/7 (SATA/USB/SPI)

Carrizo 5/7 (SATA/USB/SPI)

Carrizo 5/7 (SATA/USB/SPI)

Date: Sheet of

Friday, July 24, 2015 6 62

Date: Sheet of

Friday, July 24, 2015 6 62

Date: Sheet of

Friday, July 24, 2015 6 62

5

4

3

2

1

07

U8
W7
W12
W15
W18
W21
Y8
Y10
Y13
Y16
Y19
Y22
AB7
AB9
AB12
AB15
AB18
AB21
AD6
AD10
AD13
AD16
AD19
AD22
AE7
AE12
AK9
AG10
AK10
AG13
AK13
AG16
AK16
AG19
AK19
AG22
AK22
AH7
AE18
AE21
AH21
AG6
AH12
AN6
AH15
AH18
AL7
AK6
AE15

L8
L13
L16
L19
L22
N7
N12
N15
N18
N21
P8
P13
P16
P19
P22
T7
F12
F15
G11
G14
J8
J9
J11
K7
K12
K13
K15
K16
T12
T15
T18
T21
U13
U16
U19
U22
K19

+1.5V_RTC

+VCC_CORE

C132
22U/6.3V_6

C168

0.22U/10V_4

C199
22U/6.3VS_6

C150

0.22U/10V_4

C159
22U/6.3V_6

C121

0.22U/10V_4

C171
22U/6.3V_6

C120

0.22U/10V_4

BOTTOM SIDE DECOUPLING UNDER APU

+0.95V

+APU_VDDGFX

C163

CZ@22U/6.3V_6

C125

CZ@0.22U/10V_4

BOTTOM SIDE DECOUPLING UNDER APU

C441

C452

10U/6.3VS_6

10U/6.3VS_6

C437

C178

0.22U/10V_4

0.22U/10V_4

C226

C170

C152

CZ@22U/6.3V_6

CZ@22U/6.3V_6

CZ@22U/6.3V_6

C182

CZ@0.22U/10V_4

C141

C192

CZ@0.22U/10V_4

CZ@0.22U/10V_4

BOTTOM SIDE DECOUPLING UNDER APU

CZ: All +APU_VDDGFX_RUN cap Stuff.
CZ-L: All +APU_VDDGFX_RUN cap No Stuff.

+VCCRTC_2

+3VPCU

12

CN13
BAT_CONN

DFHS02FS027

BAT-23_2-4_2

+BAT

R208 470/F_4

C439
10U/6.3V_6

C73

0.22U/10V_4

D25
BAT54CW

C203
22U/6.3VS_6

C149

0.22U/10V_4

C116

CZ@22U/6.3V_6

C209

CZ@0.22U/10V_4

C144
22U/6.3V_6

C157

0.22U/10V_4

C440
10U/6.3V_6

C438

0.22U/10V_4

C128

CZ@22U/6.3V_6

C180

CZ@0.22U/10V_4

+3VRTC

C320

0.1U/16V/X7R_4

C167
22U/6.3VS_6

C135

0.22U/10V_4

C442

0.22U/10V_4

C151

CZ@22U/6.3V_6

C118

CZ@0.22U/10V_4

20MIL

+3VRTC

C318

1U/10V_4

12

C193
22U/6.3VS_6

C136

0.22U/10V_4

C75

0.22U/10V_4

C131

CZ@22U/6.3V_6

C164

CZ@0.22U/10V_4

U10

3

VIN

IC AP2138N-1.5TRG1

C200
22U/6.3VS_6

C142
180P/50V_4

C179
180P/50V_4

SI, 0210, reserved 3528 cap

C198

CZ@22U/6.3V_6

C139

CZ@0.22U/10V_4

2

GND

1

VOUT

12

+

C621
*330U_2.5V_3528

C123

CZ@180P/50V_4

+1.5V_RTC

C325
10U/6.3V_6

+1.35VSUS

3A

P25

VDDIO_MEM_S3_1

P28

VDDIO_MEM_S3_2

T24

VDDIO_MEM_S3_3

T27

VDDIO_MEM_S3_4

C339
22U/6.3VS_6

C297
22U/6.3VS_6

C300
22U/6.3VS_6

C290
22U/6.3VS_6

C283

0.22U/10V_4

C211

D D

22U/6.3VS_6

C296
22U/6.3VS_6

C345

0.22U/10V_4

C289
22U/6.3VS_6

C286

0.22U/10V_4

C197
22U/6.3VS_6

C326

0.22U/10V_4

C288
*22U/6.3VS_6

C207

0.22U/10V_4

C298
*22U/6.3VS_6

C324

0.22U/10V_4

BOTTOM SIDE DECOUPLING UNDER APU

C205

C204

C346

0.22U/10V_4

DECOUPLING BETWEEN PROCESSOR AND DIMMs
ACROSS VDDNB AND VSS SPLIT

C122

0.22U/10V_4

+VDDP_GFX

R402
CZ: always pop

C C

CZ-L PX: Stuff

UMA: No Stuff

+0.95V +VDDP_GFX

R402 0_6

C436
10U/6.3VS_6

C206

0.22U/10V_4

0.22U/10V_4

R155

R155

only pop on

*0_4

CZ-L UMA SKU.

ALF@1031:
Changed Power Naming

+VDDCR_FCH_S5 +VDDCR_FCH_S5_R

+VDDCR_FCH_S5
R175
CZ: Stuff
CZ-L: No Stuff

R175 CZ@0_4

C148

0.22U/10V_4

C426

0.22U/10V_4

C188
CZ@10U/6.3VS_6

C433

0.22U/10V_4

C187
CZ@10U/6.3VS_6

C435

0.22U/10V_4

C429

0.22U/10V_4

C174
CZ@0.22U/10V_4

C201
22U/6.3V_6

0.22U/10V_4

C140
22U/6.3V_6

C208
180P/50V_4

+APU_VDDIO_AZ

+VDDP_GFX

+APU_VDD_33

+APU_VDD_18_S5

+APU_VDD_33_S5

+VDDP_S5

+VDDCR_FCH_S5_R

C137
22U/6.3V_6

+1.8V

+0.95V

+VDDNB_CORE

ACROSS VDDNB AND VSS SPLIT

B B

C173

0.22U/10V_4

C432

0.22U/10V_4

C183

0.22U/10V_4

C156

0.22U/10V_4

C154

0.22U/10V_4

C427

0.22U/10V_4

C430

0.22U/10V_4

C166

0.22U/10V_4

C299
*22U/6.3VS_6

C321
180P/50V_4

C323
180P/50V_4

C117
22U/6.3V_6

C431
180P/50V_4

AB24
AB27
AB30
AB33
AD25
AD28
AD30
AE24
AE27
AF30
AF33
AG25
AG28
AH24
AH27
AH30
AK25
AK28
AK30
AK33

AL27

AM30
AR19

AP19
AP21

AP16
AP18

AP10

AP15
AR15

AN12
AP12

AP13
AR12

AW19

AU17
AU19
AV17
AV19

AW17

AL12
AL13
AL15
AL18

AL21
AN13
AN16
AN19
AN22

AR17

U25
U28
V30

V33
W24
W27

Y25

Y28

Y30

AE6

AE5

AR9

VDDIO_MEM_S3_5
VDDIO_MEM_S3_6
VDDIO_MEM_S3_7
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDIO_MEM_S3_10
VDDIO_MEM_S3_11
VDDIO_MEM_S3_12
VDDIO_MEM_S3_13
VDDIO_MEM_S3_14
VDDIO_MEM_S3_15
VDDIO_MEM_S3_16
VDDIO_MEM_S3_17
VDDIO_MEM_S3_18
VDDIO_MEM_S3_19
VDDIO_MEM_S3_20
VDDIO_MEM_S3_21
VDDIO_MEM_S3_22
VDDIO_MEM_S3_23
VDDIO_MEM_S3_24
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDIO_MEM_S3_27
VDDIO_MEM_S3_28
VDDIO_MEM_S3_29
VDDIO_MEM_S3_30
VDDIO_MEM_S3_31
VDDIO_MEM_S3_32
VDDIO_MEM_S3_33
VDDIO_MEM_S3_34
VDDIO_MEM_S3_35

0.2A

VDDIO_AUDIO

1.5A

VDDP_GFX_2
VDDP_GFX_1

0.2A

VDD_33_1
VDD_33_2

1.5A

VDD_18_1
VDD_18_2

0.5A

VDD_18_S5_1
VDD_18_S5_2

0.2A

VDD_33_S5_1
VDD_33_S5_2

0.8A

VDDP_S5_1
VDDP_S5_2

0.2A

VDDCR_FCH_S5_1
VDDCR_FCH_S5_2

7A

VDDP_6
VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5

12A

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9

VDDBT_RTC_G

BOTTOM SIDE DECOUPLING UNDER APU

20MIL

VDDBT_RTC

12

G1

*SHORT_ PAD1

+1.5V

+APU_VDDIO_AZ

ALF@1031:
Changed Power Naming

1029@RNY: follow DG

+1.8V

+1.8V_DEEP_SUS +APU_VDD_18_S5

R209 *0_4/S

1.5V For HDA Only

A A

C202
1U/10V_4

C248
1U/10V_4

C242
1U/10V_4

C238
10U/6.3VS_6

C230

0.22U/10V_4

C322

0.22U/10V_4

R152 *0_4/S

C126
10U/6.3VS_6

12

C224
1U/10V_4

U24F

POWER

FP4 REV 1.0

*FP4

R287 1K/F_4

C113

0.22U/10V_4

22~39A

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8

VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15
VDDCR_CPU_16
VDDCR_CPU_17
VDDCR_CPU_18
VDDCR_CPU_19
VDDCR_CPU_20
VDDCR_CPU_21
VDDCR_CPU_22
VDDCR_CPU_23
VDDCR_CPU_24
VDDCR_CPU_25
VDDCR_CPU_26
VDDCR_CPU_42
VDDCR_CPU_31
VDDCR_CPU_43
VDDCR_CPU_32
VDDCR_CPU_44
VDDCR_CPU_33
VDDCR_CPU_45
VDDCR_CPU_34
VDDCR_CPU_46
VDDCR_CPU_35
VDDCR_CPU_47
VDDCR_CPU_36
VDDCR_CPU_28
VDDCR_CPU_29
VDDCR_CPU_40
VDDCR_CPU_30
VDDCR_CPU_37
VDDCR_CPU_49
VDDCR_CPU_38
VDDCR_CPU_39
VDDCR_CPU_48
VDDCR_CPU_41
VDDCR_CPU_27

22~30A

VDDCR_GFX_14
VDDCR_GFX_15
VDDCR_GFX_16
VDDCR_GFX_17
VDDCR_GFX_18
VDDCR_GFX_19
VDDCR_GFX_20
VDDCR_GFX_21
VDDCR_GFX_22
VDDCR_GFX_23
VDDCR_GFX_24
VDDCR_GFX_25
VDDCR_GFX_26
VDDCR_GFX_27
VDDCR_GFX_28
VDDCR_GFX_29

VDDCR_GFX_1

VDDCR_GFX_2

VDDCR_GFX_3

VDDCR_GFX_4

VDDCR_GFX_5

VDDCR_GFX_6

VDDCR_GFX_7

VDDCR_GFX_8

VDDCR_GFX_9
VDDCR_GFX_10
VDDCR_GFX_11
VDDCR_GFX_12
VDDCR_GFX_30
VDDCR_GFX_31
VDDCR_GFX_32
VDDCR_GFX_33
VDDCR_GFX_34
VDDCR_GFX_35
VDDCR_GFX_36
VDDCR_GFX_37
VDDCR_GFX_13

400 series 1002

400 series 1002

400 series 1002400 series 1002

+3V +APU_VDD_33

R188 *0_4/S

C219
10U/6.3VS_6

5

+3V_DEEP_SUS +APU_VDD_33_S5 +0.95V_DEEP_SUS +VDDP_S5

R187 *0_4/S

4

C223
10U/6.3VS_6

C222

0.22U/10V_4

R154 *0_6/S

C114
10U/6.3VS_6

C119

0.22U/10V_4

3

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Carrizo 6/7 (POWER)

Carrizo 6/7 (POWER)

NB5

NB5

2

NB5

Carrizo 6/7 (POWER)

Date: Sheet of

Friday, July 24, 2015 7 62

Date: Sheet of

Friday, July 24, 2015 7 62

Date: Sheet of

Friday, July 24, 2015 7 62

1

1A

1A

1A

5

4

3

2

1

08

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62

U24G

GND

FP4 REV 1.0

*FP4

VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124

L28
M4
M30
N10
N13
N16
N19
N22
N27
P1
P2
P4
P5
P12
P15
P18
P21
P30
P33
T4
T10
T13
T16
T19
T22
T30
U5
U12
U15
U18
U21
U24
V1
V2
V4
W10
W13
W16
W19
W22
Y4
Y5
Y12
Y15
Y18
Y21
Y24
AB1
AB2
AB4
AB10
AB13
AB16
AB19
AB22
AD4
AD9
AD12
AD15
AD18
AD21
AD24

AE10
AE13
AE16
AE19
AE22

AF1
AF4

AG9
AG12
AG15
AG18
AG21

AH4
AH10
AH13
AH16
AH19
AH22

AK1

AK4
AK12
AK15
AK18
AL16
AL19
AL22

AM4

AN9
AN10
AN15
AN18
AN21
AN25
AN28

AP1

AP2

AP4

AP7
AP22
AP27
AP30
AP33

AR6
AR25
AR28

AT4
AT19
AT22
AT30

AU5

AU8
AU11
AU14
AU20
AU23
AU27

AV4

AV7

AV9
AV12
AV15
AV25

D D

A8

ORIENT_APU#

TP55

C C

B B

A12
A16
A20
A24
A28
A32

B12
B33

D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30

F19
F22
F25
F30
F33

G17
G20
G23
G26

H30

J15
J19
J22
J25
J28

K10
K22
K27
K30
K33

L12
L15
L18
L21
L25

B2
B8

C3
D4
D6
D8

F1
F2
F4
F9

G7

H4

J5

K1
K2
K4

L5

VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186

U24H

GND

FP4 REV 1.0

*FP4

VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212

VSS_213
VSS_215
VSS_214

AV30
AV33
AW22
AY4
AY6
AY8
AY10
AY12
AY14
AY16
AY20
AY22
AY24
AY26
AY28
AY30
BB1
BB33
BC4
BC8
BC12
BC16
BC20
BC24
BC28
BC32

L24
AL10
AK21

TP32
TP33
TP77

APU_U30
APU_U31
APU_AN30

U30
U31

AN30

RSVD_2
RSVD_3
RSVD_4

U24J

FP4 REV 1.0

*FP4

A A

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Carrzio 7/7 (GND)

Carrzio 7/7 (GND)

NB5

NB5

5

4

3

2

NB5

Date: Sheet of

Date: Sheet of

Date: Sheet of

Carrzio 7/7 (GND)

Friday, July 24, 2015 8 62

Friday, July 24, 2015 8 62

Friday, July 24, 2015 8 62

1

1A

1A

1A

5

4

3

2

1

M_B_A[15:0][3,10]

D D

M_B_BS#0[3,10]
M_B_BS#1[3,10]
M_B_BS#2[3,10]
M_B_CS#0[3]
M_B_CS#1[3]
M_B_CLKP0[3]
M_B_CLKN0[3]
M_B_CLKP1[3]

FCH_3S_SMCLK[5,10,20,28]
FCH_3S_SMDATA[5,10,20,28]

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQSP[7:0][3,10]

M_B_DQSN[7:0][3,10]

M_B_CLKN1[3]
M_B_CKE0[3,10]
M_B_CKE1[3,10]
M_B_CAS#[3,10]
M_B_RAS#[3,10]
M_B_WE#[3,10]

M_B_ODT0[3]
M_B_ODT1[3]

Ronny@1013:
2 So-Dimm per 1 Channel

R309 4.7K_4

+3V

M_B_DM[7..0][3,10]

C C

B B

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

DIMM0_SA0

DIMM0_SA1
FCH_3S_SMCLK
FCH_3S_SMDATA

M_B_DQSP0

M_B_DQSP1

M_B_DQSP2

M_B_DQSP3

M_B_DQSP4

M_B_DQSP5

M_B_DQSP6

M_B_DQSP7

M_B_DQSN0

M_B_DQSN1

M_B_DQSN2

M_B_DQSN3

M_B_DQSN4

M_B_DQSN5

M_B_DQSN6

M_B_DQSN7

Place these Caps near So-Dimm0.

+1.35VSUS +0.65V_DDR_VTT

C349 1U/6.3V_4
C351 1U/6.3V_4
C347 1U/6.3V_4
C362 1U/6.3V_4
C395 10U/6.3VS_6
C344 10U/6.3VS_6
C364 10U/6.3VS_6
C352 10U/6.3VS_6
C379 10U/6.3VS_6
C350 10U/6.3VS_6

A A

C363 *10U/6.3VS_6
C361 10U/6.3VS_6
C372 10U/6.3VS_6

+VREF_DQ0

+VREF_CA0

5

C380 1U/6.3V_4
C342 1U/6.3V_4
C381 1U/6.3V_4
C360 1U/6.3V_4
C377 10U/6.3VS_6
C340 *10U/6.3VS_6

C354 0.1U/16V/X7R_4

C353 1000P/50V_4

C356 0.1U/16V/X7R_4

C368 1000P/50V_4

C355 *0.047U/10V_4

JDIM1A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

DDR3-DIMM1_H=4.0_RVS

ddr-ddrrk-20401-tp4b-204p-smt

DGMK0000158

SOCKET DDR3 SODIMM(204P,H4.0,RVS)QBCON

+1.35VSUS

EC6 180P/50V_4
EC16 180P/50V_4
EC9 180P/50V_4
EC26 220P/50V_4
EC12 220P/50V_4
EC20 220P/50V_4
EC23 220P/50V_4
EC22 220P/50V_4
EC24 220P/50V_4
EC15 220P/50V_4
EC17 220P/50V_4
EC8 0.1U/16V/X7R_4
EC11 2200P/50V_4

+0.65V_DDR_VTT

EC13 *120P/50V_4
EC7 *120P/50V_4

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

(204P)

PC2100 DDR3 SDRAM SO-DIMM

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

4

5

M_B_DQ5

7

M_B_DQ4

15

M_B_DQ3

17

M_B_DQ2

4

M_B_DQ0

6

M_B_DQ1

16

M_B_DQ6

18

M_B_DQ7

21

M_B_DQ9

23

M_B_DQ13

33

M_B_DQ14

35

M_B_DQ10

22

M_B_DQ8

24

M_B_DQ12

34

M_B_DQ11

36

M_B_DQ15

39

M_B_DQ20

41

M_B_DQ21

51

M_B_DQ18

53

M_B_DQ22

40

M_B_DQ17

42

M_B_DQ16

50

M_B_DQ19

52

M_B_DQ23

57

M_B_DQ25

59

M_B_DQ29

67

M_B_DQ27

69

M_B_DQ26

56

M_B_DQ28

58

M_B_DQ24

68

M_B_DQ31

70

M_B_DQ30

129

M_B_DQ36

131

M_B_DQ37

141

M_B_DQ35

143

M_B_DQ34

130

M_B_DQ33

132

M_B_DQ32

140

M_B_DQ39

142

M_B_DQ38

147

M_B_DQ44

149

M_B_DQ40

157

M_B_DQ42

159

M_B_DQ43

146

M_B_DQ45

148

M_B_DQ41

158

M_B_DQ46

160

M_B_DQ47

163

M_B_DQ49

165

M_B_DQ48

175

M_B_DQ54

177

M_B_DQ55

164

M_B_DQ52

166

M_B_DQ53

174

M_B_DQ50

176

M_B_DQ51

181

M_B_DQ61

183

M_B_DQ56

191

M_B_DQ63

193

M_B_DQ62

180

M_B_DQ57

182

M_B_DQ60

192

M_B_DQ58

194

M_B_DQ59

M_B_DQ[63:0] [3,10]

3

+1.35VSUS

R329
1K/F_4

M_B_EVENT#

M_B_EVENT#[3,10]

M_B_RST#[3,10]

+VREF_DQ0
+VREF_CA0

DDR_VTTREF[10,45]

M_B_VREFDQ[3,10]

R312 *0_6

3mA

R308 *0_6

3mA

2.48A

+3V

+VREF_DQ0
+VREF_CA0

2

+1.35VSUS

M_B_EVENT#

+1.35VSUS

R311
1K/F_4

R310
1K/F_4

+1.35VSUS

JDIM1B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26
31
32
37
38
43

1014: Ronny
follow DG use voltage divider

+VREF_CA0

53537_105 change:
Type 1: and Type 2: from 1K/2 voltage

R306
1K/F_4

+VREF_DQ0

R307
1K/F_4

PC2100 DDR3 SDRAM SO-DIMM

VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

DDR3-DIMM1_H=4.0_RVS

ddr-ddrrk-20401-tp4b-204p-smt

DGMK0000158

SOCKET DDR3 SODIMM(204P,H4.0,RVS)QBCON

NB5

NB5

NB5

44

VSS16

48

VSS17

49

VSS18

54

VSS19

55

VSS20

60

VSS21

61

VSS22

65

VSS23

66

VSS24

71

VSS25

72

VSS26

127

VSS27

128

VSS28

133

VSS29

134

VSS30

138

VSS31

139

VSS32

144

VSS33

145

VSS34

150

VSS35

151

VSS36

155

VSS37

156

VSS38

161

VSS39

162

VSS40

167

VSS41

168

VSS42

172

VSS43

173

VSS44

178

VSS45

179

VSS46

184

VSS47

185

VSS48

189

VSS49

190

VSS50

195

VSS51

196

VSS52

(204P)

203

VTT1

204

VTT2

205

GND

206

GND

207

GND

208

GND

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet of

+0.65V_DDR_VTT

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

System Memory 1/2 (4H)

System Memory 1/2 (4H)

System Memory 1/2 (4H)

09

+3V[4,5,6,7,10,11,17,19,20,21,22,23,24,25,26,28,29,31,34,35,36,37,39,41,42,43,48,50,52,58]

+1.35VSUS[3,7,10,45]

+0.65V_DDR_VTT[10,45,52]

1A

1A

1A

9 62Friday, July 24, 2015

9 62Friday, July 24, 2015

1

9 62Friday, July 24, 2015

5

4

3

2

1

2.48A

+VREF_DQ1
+VREF_CA1

+1.35VSUS

+3V

M_B_EVENT#

JDIM2B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26
31
32
37
38
43

PC2100 DDR3 SDRAM SO-DIMM

VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

DDR3-DIMM0_H=4.0_STD

ddr-ddrsk-20401-tp4b-204p-smt

DGMK0000160

SOCKET DDR3 SODIMM(204P,H4.0,STD)QBCON

44

VSS16

48

VSS17

49

VSS18

54

VSS19

55

VSS20

60

VSS21

61

VSS22

65

VSS23

66

VSS24

71

VSS25

72

VSS26

127

VSS27

128

VSS28

133

VSS29

134

VSS30

138

VSS31

139

VSS32

144

VSS33

145

VSS34

150

VSS35

151

VSS36

155

VSS37

156

VSS38

161

VSS39

162

VSS40

167

VSS41

168

VSS42

172

VSS43

173

VSS44

178

VSS45

179

VSS46

184

VSS47

185

VSS48

189

VSS49

190

VSS50

195

VSS51

196

VSS52

(204P)

203

VTT1

204

VTT2

205

GND

206

GND

207

GND

208

GND

+0.65V_DDR_VTT

DDR3 Thermal Sensor

1028: Ronny
delete DDR thermail IC, please refer to Page41

10

+3V[4,5,6,7,9,11,17,19,20,21,22,23,24,25,26,28,29,31,34,35,36,37,39,41,42,43,48,50,52,58]

+1.35VSUS[3,7,9,45]

+0.65V_DDR_VTT[9,45,52]

M_B_A[15:0][3,9]

D D

Ronny@1013:
2 So-Dimm per 1 Channel

M_B_BS#0[3,9]
M_B_BS#1[3,9]
M_B_BS#2[3,9]
M_B1_CS#0[3]
M_B1_CS#1[3]
M_B_CLKP2[3]
M_B_CLKN2[3]
M_B_CLKP3[3]
M_B_CLKN3[3]
M_B_CKE0[3,9]
M_B_CKE1[3,9]
M_B_CAS#[3,9]
M_B_RAS#[3,9]

FCH_3S_SMCLK[5,9,20,28]
FCH_3S_SMDATA[5,9,20,28]

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQSP[7:0][3,9]

M_B_DQSN[7:0][3,9]

M_B_WE#[3,9]

M_B1_ODT0[3]
M_B1_ODT1[3]

R314 4.7K_4

+3V

R313 4.7K_4

+3V

C C

B B

M_B_DM[7..0][3,9]

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

DIMM1_SA0
DIMM1_SA1

M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7

JDIM2A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12
29
47

64
137
154
171
188

10

27

45

62
135
152
169
186

PC2100 DDR3 SDRAM SO-DIMM

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

DDR3-DIMM0_H=4.0_STD

ddr-ddrsk-20401-tp4b-204p-smt

DGMK0000160

SOCKET DDR3 SODIMM(204P,H4.0,STD)QBCON

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

(204P)

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ2
M_B_DQ0
M_B_DQ1
M_B_DQ6
M_B_DQ7
M_B_DQ9
M_B_DQ13
M_B_DQ14
M_B_DQ10
M_B_DQ8
M_B_DQ12
M_B_DQ11
M_B_DQ15
M_B_DQ20
M_B_DQ21
M_B_DQ18
M_B_DQ22
M_B_DQ17
M_B_DQ16
M_B_DQ19
M_B_DQ23
M_B_DQ25
M_B_DQ29
M_B_DQ27
M_B_DQ26
M_B_DQ28
M_B_DQ24
M_B_DQ31
M_B_DQ30
M_B_DQ36
M_B_DQ37
M_B_DQ35
M_B_DQ34
M_B_DQ33
M_B_DQ32
M_B_DQ39
M_B_DQ38
M_B_DQ44
M_B_DQ40
M_B_DQ42
M_B_DQ43
M_B_DQ45
M_B_DQ41
M_B_DQ46
M_B_DQ47
M_B_DQ49
M_B_DQ48
M_B_DQ54
M_B_DQ55
M_B_DQ52
M_B_DQ53
M_B_DQ50
M_B_DQ51
M_B_DQ61
M_B_DQ56
M_B_DQ63
M_B_DQ62
M_B_DQ57
M_B_DQ60
M_B_DQ58
M_B_DQ59

M_B_DQ[63:0] [3,9]

+1.35VSUS

R327
1K/F_4

M_B_EVENT#

M_B_EVENT#[3,9]

M_B_RST#[3,9]

+VREF_DQ1
+VREF_CA1

Place these Caps near So-Dimm1.

5

+0.65V_DDR_VTT

+VREF_DQ1

+VREF_CA1

C365 1U/6.3V_4
C343 1U/6.3V_4
C376 1U/6.3V_4
C378 1U/6.3V_4
C357 10U/6.3VS_6
C358 *10U/6.3VS_6

C389 0.1U/16V/X7R_4

C393 1000P/50V_4

C392 0.1U/16V/X7R_4

C401 1000P/50V_4

C400 *0.047U/10V_4

+1.35VSUS

C383 1U/6.3V_4
C375 1U/6.3V_4
C382 1U/6.3V_4
C398 1U/6.3V_4
C348 10U/6.3VS_6
C373 10U/6.3VS_6
C394 10U/6.3VS_6
C399 10U/6.3VS_6
C371 10U/6.3VS_6

A A

C397 10U/6.3VS_6
C374 *10U/6.3VS_6
C396 10U/6.3VS_6
C287 10U/6.3VS_6

+1.35VSUS

EC28 180P/50V_4
EC19 180P/50V_4
EC18 220P/50V_4
EC27 220P/50V_4
EC25 220P/50V_4
EC10 220P/50V_4
EC29 220P/50V_4
EC14 220P/50V_4
EC21 220P/50V_4
EC30 220P/50V_4

53537_105 change:
Type 1: and Type 2: from 1K/2 voltage

+3V

C367 0.1U/16V/X7R_4
C370 2.2U/6.3V_6
C341 1000P/50V_4

4

1014: Ronny
follow DG use voltage divider

DDR_VTTREF[9,45]

M_B_VREFDQ[3,9]

R315 *0_6

3mA

R322 *0_6

3mA

+1.35VSUS

+1.35VSUS

3

R323
1K/F_4

R328
1K/F_4

R331
1K/F_4

R330
1K/F_4

+VREF_CA1

+VREF_DQ1

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

System Memory 2/2 (4H)

System Memory 2/2 (4H)

NB5

NB5

2

NB5

System Memory 2/2 (4H)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

10 62Friday, July 24, 2015

10 62Friday, July 24, 2015

10 62Friday, July 24, 2015

U28A

9/2: CZ use 0.22u(Gen 3) ; CZ-L use 0.1u(Gen 2)

PEG_TXP0[2]
PEG_TXN0[2] PEG_RXN0 [2]

PEG_TXP1[2]
PEG_TXN1[2]

PEG_TXP2[2]
PEG_TXN2[2] PEG_RXN2 [2]

PEG_TXP3[2]
PEG_TXN3[2]

ALF@1028:
HP request to add 4Lanes

CLK_GFX_P[6]
CLK_GFX_N[6]

R115 DIS@1K/F_4

PEG_TXP0
PEG_TXN0

PEG_TXP1
PEG_TXN1

PEG_TXP2
PEG_TXN2 C_PEG_RXN2

PEG_TXP3
PEG_TXN3

CLK_GFX_P
CLK_GFX_N

TEST_PG

PEGX_RST#

AF30

AE31

AE29
AD28

AD30
AC31

AC29
AB28

AB30
AA31

AA29

W31

W29

AK30
AK32

AL27

Y28

Y30

V28

V30
U31

U29

T28

T30

R31

R29
P28

P30
N31

N29
M28

M30

L31

L29

K30

N10

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

NC#V30
NC#U31

NC#U29
NC#T28

NC#T30
NC#R31

NC#R29
NC#P28

NC#P30
NC#N31

NC#N29
NC#M28

NC#M30
NC#L31

NC#L29
NC#K30

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN

TEST_PG

PERSTB

DIS@Meso_S3

PCI EXPRESS INTERFACE

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

NC#W24
NC#W23

NC#V27
NC#U26

NC#U24
NC#U23

NC#T26
NC#T27

NC#T24
NC#T23

NC#P27
NC#P26

NC#P24
NC#P23

NC#M27
NC#N26

AH30
AG31

AG29
AF28

AF27
AF26

AD27
AD26

AC25
AB25

Y23
Y24

AB27
AB26

Y27
Y26

W24
W23

V27
U26

U24
U23

T26
T27

T24
T23

P27
P26

P24
P23

M27
N26

Y22
AA22

C_PEG_RXP0
C_PEG_RXN0

C_PEG_RXP1
C_PEG_RXN1

C_PEG_RXP2

C_PEG_RXP3
C_PEG_RXN3

SUN_PCIE_CALRP
SUN_PCIE_CALRN

C571 DIS@0.22U/10V_4
C580 DIS@0.22U/10V_4

C583 DIS@0.22U/10V_4
C588 DIS@0.22U/10V_4

C273 DIS@0.22U/10V_4
C265 DIS@0.22U/10V_4

C254 DIS@0.22U/10V_4
C244 DIS@0.22U/10V_4

R212 DIS@1.69K/F_4
R213 DIS@1K/F_4

+1.0V_VGA

Platform
Carrizo CH4222K9B04

PEG_RXP0 [2]

PEG_RXP1 [2]
PEG_RXN1 [2]

PEG_RXP2 [2]

PEG_RXP3 [2]
PEG_RXN3 [2]

+3V_VGA

12/10:reserve for verify

+3V_VGA

PCIE_RST#_R1

DGPU_HIN_RST#

2

1

D9

DIS@BAT54AW-L

C313 *DIS@0.1U/16V/X7R_4

R218
DIS@1K/F_4

3

PEGX_RST#

PCIE_RST#_R1[5,24,26,29,34]

DGPU_HOLD_RST#[5] +3V_VGA[12,14,53,55]

1025@Ronny
GPU RST from APU

R278 *DIS@0_4/S

DGPU_HIN_RST#

*DIS@MC74VHC1G08DFT2G

2
1

U7

3 5

C303

*DIS@0.1U/16V/X7R_4

4

R211
DIS@100K/F_4

Gen 3
Gen 1/Gen 2

+1.0V_VGA

PEGX_RST#

P/NType

CH4103K1B08Carrizo-L

+1.8V_VGA

VDDC_PWRGD[53]

ALF@1031:
From PWRGD Gennrator

PEGX_RST# [12]

1.8V ( 40mA)

C272
DIS@10U/6.3VS_6

C247

DIS@1U/10V_4

1.0V ( 32mA)

5

+

6

-

C275
DIS@0.1U/16V/X7R_4

R372 *DIS@0_4

R373 *DIS@0_4
R363 DIS@10K_4

AS393MTR-G1
PU12B

7

C418

+3V

1 2

C229

DIS@1U/10V_4

PEGX_RST#

PCIE_RST#_R1

C465
*DIS@10U/6.3VS_6

ALF@1031:
Following the 2014 AMD Leading Schematic for DGPU_PWROK

DIS@0.47U/10V_4

PGVREF

U28G

AG15

NC_DP_VDDR#1

AG16

NC_DP_VDDR#2

AF16

NC_DP_VDDR#3

AG17

NC_DP_VDDR#4

AG18

NC_DP_VDDR#5

AG19

NC_DP_VDDR#6

AF14

DP_VDDR

AG20

NC_DP_VDDC#1

AG21

NC_DP_VDDC#2

AF22

NC_DP_VDDC#3

AG22

NC_DP_VDDC#4

AD14

DP_VDDC

AG14

NC_DP_VSSR#1

AH14

NC_DP_VSSR#2

AM14

NC_DP_VSSR#3

AM16

NC_DP_VSSR#4

AM18

NC_DP_VSSR#5

AF23

NC_DP_VSSR#6

AG23

NC_DP_VSSR#7

AM20

NC_DP_VSSR#8

AM22

NC_DP_VSSR#9

AM24

NC_DP_VSSR#10

AF19

NC_DP_VSSR#11

AF20

NC_DP_VSSR#12

AE14

DP_VSSR

AF17

NC_UPHYAB_DP_CALR

DIS@Meso_S3

+3V

C419 *DIS@0.1U/16V/X7R_4

U17

*DIS@MC74VHC1G08DFT2G

2
1

3 5

NB5

NB5

NB5

11

NC/DP POWERDP POWER

4

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

VGA_PWRGD [53]

R362
*DIS@0_4/S

+1.8V_VGA[12,14,53,55]
+1.0V_VGA[14,55]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

TOPAZ S3 PCIE/DP power

TOPAZ S3 PCIE/DP power

TOPAZ S3 PCIE/DP power

AE11

NC#AE11

AF11

NC#AF11

AE13

NC#AE13

AF13

NC#AF13

AG8

NC#AG8

AG10

NC#AG10

AF6

NC#AF6

AF7

NC#AF7

AF8

NC#AF8

AF9

NC#AF9

AE1

NC#AE1

AE3

NC#AE3

AG1

NC#AG1

AG6

NC#AG6

AH5

NC#AH5

AF10

NC#AF10

AG9

NC#AG9

AH8

NC#AH8

AM6

NC#AM6

AM8

NC#AM8

AG7

NC#AG7

AG11

NC#AG11

AE10

NC#AE10

DGPU_PWROK [5]

11 62Monday, July 27, 2015

11 62Monday, July 27, 2015

11 62Monday, July 27, 2015

1A

1A

1A

OCP_L[53]

+3V_VGA

+3V_VGA

R127

DIS@10K/F_4

R126 D IS@10K/F_4
R131 * DIS@10K/F_4
R460 * DIS@10K/F_4
R459 * DIS@10K/F_4
R462 * DIS@10K/F_4

*DIS@10K/F_4

R463
R520 * DIS@10K/F_4

R461 DIS@10K/F_4

AMD recommend

KBC_SMDATA[4,20,36 ,39]

KBC_SMCLK[4,20,36,39]

+3V_VGA

R124
*DIS@5.1K/F_4

TESTEN

R123
DIS@1K/F_4

R106 DIS@1K/F_4

AC_IN
DGPU_TDI
DGPU_TMS
DGPU_TDO
DGPU_TRSTB
PCIE_REQ_GPU#
DGPU_PROCHOT#

TEMP_FAIL

KBC_SMDATA

KBC_SMCLK

GPU_GPIO6

C79
DIS@0.1U/16V/X7R_4

R119 * DIS@10K/F_4

R241 * DIS@0_4

Q22A DIS@2N7002KDW

Dual

3 4

5

2

SI, 0204, double pull-up, remove one

6 1

Dual

Q22B DIS@2N7002KDW

R216 * DIS@0_4

C278 DIS@10P/50V_4

1

2

Y2

DIS@27MHZ +-10PPM

4

3

C295 DIS@10P/50V_4

R280 * DIS@0_4/S

R277 *DIS@4.7K_4

SI, 0203, change cap to fine tune XTAL

Thermal Solution(Close to GPU)

ALF@1029:
Del GPU Thermal IC Circuit...
and NC for those signals
GPU_THERMDA
GPU_THERMDC
VGA_ALERT

ADP_PRES_OUT[5,39 ,52]

DGPUT_DATA

9/9: follow AMD CRB design

+3V_VGA

DGPUT_CLK

EVGA-XTALI

R244
DIS@1M_4

EVGA-XTALO

+3V_VGA

+3V_VGA

D23 *DIS@RB751V40

PEGX_RST# [11]

10/2 : remove TP for no use

+1.8V_VGA

9/11: follow CRB change to 10K

R466

DIS@10K_4

TP51
TP61

R464 DIS@4.7K_4
R465 DIS@4.7K_4

R140 DIS@47K/F_4
R146 DIS@47K/F_4

DGPUT_DATA
DGPUT_CLK DGPUT_CLK_R
AC_IN

21

+1.8V_VGA

9/4: change to 47K ohm for CRB

R145 * DIS@0_4/S
R139 * DIS@0_4/S

R133 * DIS@0_4/S

TP7
TP57
TP50
TP10
TP54
TP11

TP8

R543 *DIS@0_4

TP18

R163 * DIS@0_4

CLKREQG#[5]

TP48

TP9
TP56
TP47
TP43

ALF@1119:
Reserved it for APU

TP72

DIS@HCB1608KF-121T30 (120+-25%,3A)

L12

GPIO8_ROMSO
GPIO9_ROMSI
GPIO10_ROMSCK

R607 D IS@10K/F_4
R612 D IS@10K/F_4

1.8V(13mA TSVDD)

C232

DIS@1U/10V_4

R467
DIS@10K_4

DGPUT_DATA_R

GPU_GPIO5
GPU_GPIO6

TEMP_FAIL

GPIO22_ROMCS
DGPU_PROCHOT#_ RDGPU_PROCH OT#

PCIE_REQ_GPU#
DGPU_TRSTB

DGPU_TDI
DGPU_TCK
DGPU_TMS
DGPU_TDO
TESTEN

PX_EN

EVGA-XTALI
EVGA-XTALO

+1.8V_TSVDD

U28B

DVO

N9

DBG_DATA16

L9

DBG_DATA15

AE9

DBG_DATA14

Y11

DBG_DATA13

AE8

DBG_DATA12

AD9

DBG_DATA11

AC10

DBG_DATA10

AD7

DBG_DATA9

AC8

DBG_DATA8

AC7

DBG_DATA7

AB9

DBG_DATA6

AB8

DBG_DATA5

AB7

DBG_DATA4

AB4

DBG_DATA3

AB2

DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

W6

NC#W6

V6

NC#V6

AC5

NC#AC5

AC6

N#CAC6

AA5

NC#AA5

AA6

NC#AA6

U1

NC#U1/BP_0

U3

NC#U3/BP_1

Y6

NC#Y6

R1

SCL

R3

I2C

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

PCC/GPIO_6

T7

NC_GPIO_7

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

NC_GPIO_11

N5

NC_GPIO_12

N3

NC_GPIO_13

N1

GPIO_15_PWRCNT L_0

M4

GPIO_16

R6

GPIO_17_THERMAL_INT

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNT L_1

P7

GPIO_21

N8

GPIO_22_ROMCSB

AK10

GPIO_29

AM10

GPIO_30

N7

CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

NC#AF24

W8

NC_GENERICB

W7

NC_GENERICD

AD10

NC_GENERICE_HPD4

AJ9

NC#AJ9

AL9

DBG_CNTL0

AB16

PX_EN

AC16

NC_DBG_VREFG

PLL/CLOCK

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

T4

DPLUS

T2

DMINUS

R5

GPIO28_FDO

AD17

TSVDD

AC17

TSVSS

DIS@Meso_S3

+1.8V_VGA [11,14,53,55]
+1.0V_VGA [11,14,55]

THERMAL

NC#AF2
NC#AF4

NC#AG3

DPA

NC#AG5
NC#AH3

NC#AH1

NC#AK3
NC#AK1

NC#AK5

NC#AM3

NC#AK6

NC#AM5

DPB

NC#AJ7

NC#AH6

NC#AK8
NC#AL7

DPC

NC#V4

NC#U5

NC#V2
NC#Y4

NC#W5

NC#Y2
NC#J8

NC#AA1/PLL_ANALOG_IN

NC#AA3/PLL_ANALOG_OU T

DCM/NC_R

NC_AVSSN#AK26

NC_AVSSN#AJ25

NC_AVSSN#AG25

DAC1

NC_HSYNC

NC_VSYNC/WAKEb

NC_RSET

NC_AVDD

NC_AVSSQ

NC_VDD1DI

NC_VSS1DI

NC_SVI2#1/GPIO_SVD
NC_SVI2#2/GPIO_SVT
NC_SVI2#3/GPIO_SVC

NC_GENLK_CLK

NC_GENLK_VSYNC

DAC2

NC_SWAPLOCKA
NC_SWAPLOCKB

DDC/AUX

NC_DDC1CLK

NC_DDC1DATA

NC_AUX1P
NC_AUX1N

NC_AUX2P
NC_AUX2N

NC#AE16
NC#AD16

NC_DDCVGACLK

NC_DDCVGADATA

AF2
AF4

AG3
AG5

AH3
AH1

AK3
AK1

AK5
AM3

AK6
AM5

AJ7
AH6

AK8
AL7

V4
U5

V2
Y4

W5

Y2
J8

AA1
AA3

AM26

R611 *DIS@10K/F_4

AK26
AL25

NC_G

AJ25
AH24

NC_B

AG25
AH26

AJ27

AD22
AG24

AE22
AE23

AD23

AM12

NC

AK12

GPU_SVD

AL11

GPU_SVT

AJ11

GPU_SVC

AL13
AJ13

AG13
AH12

AC19

PS_0

PS_0

AD19

PS_1

PS_1

AE17

PS_2

PS_2

AE20

PS_3

PS_3

AE19

R602 *DIS@0_4

TS_A

Reserved.
Do not connect on the PCB

AE6
AE5

AD2
AD4

AD13
AD11

AE16
AD16

AC1

TP49

AC3

TP52

For AMD tuning
timing purpose

+1.8V_VGA

R190
DIS@8.45K/F_4

PS_0 PS_1

+1.8V_VGA +1.8V_VGA

PS_2 PS_3

TP58

R470 DIS@16.2K/F_4

R189
DIS@2K/F_4

R185
*DIS@0_4

R184
DIS@4.75K/F_4

C227
*DIS@0.01U/50V/X7R_4

Follow AMD check list

+3V_VGA

R61 *DIS@4.7K_4
R270
*DIS@4.7K_4

R263
DIS@4.7K_4

2

Q16

1

9/

*DIS@2N7002K

4: follow CRB design by FAE

PS_3[3:1]

Vendor ID
00 = Samsung

01 = Hynix
10 = Micron
11 = Nanya

+1.8V_VGA

C217
*DIS@0.68U/4V_4

3

R591 *DIS@0_4/S
R542 *DIS@0_4/S
R559 *DIS@0_4/S

000

001
010
011
100
101

VRAM density
0=128Mx16

1=258Mx16

10/1 : Gen 3 support or not

Carrizo : PU 8.45K ; PD 2K
Carrizo-L : PU NC ; PD 4.75K

R194
DIS@8.45K/F_4

Beema : PU NC ; PD 4.75K

R193
DIS@2K/F_4

R195
DIS@8.45K/F_4

R196
DIS@2K/F_4

C231

*DIS@0.082U/16V_4

C239
*DIS@0.01U/50V/X7R_4

BIT5 => BIT1
PS0 => 11001
PS1 => 11001
PS2 => 11000
PS3 => 11001

TP2

9/11: Add for SR Tool review result

1108@RNY: AMD says reserved and non-stuff

R589 *DIS@10 K/F_4
R573 *DIS@10 K/F_4
R558 *DIS@10 K/F_4

SVI2_SVD [53]
SVI2_SVT [53]
SVI2_SVC [53]

ndor

Samsung- Q die
Samsung- E die

Hynix- Huma F die
Hynix- C(Polaris)

Micron- K die

Nanya- F die
Nanya- D die

12

GPU_SVD

R590 * DIS@10K/F_4

GPU_SVC

R569 * DIS@10K/F_4

GPU_SVT

R551 * DIS@10K/F_4

TypeVe

128Mx16 *4,1000Mhz K4W2G1646Q-BC1A
256Mx16 *4,1000Mhz
128Mx16 *4,1000Mhz
256Mx16 *4,1000Mhz

256Mx16 *4,1000MhzMicron- E die MT41J256M16HA-093G:E
128Mx16 *4,1000Mhz 10K
256Mx16 *4,1000Mhz

Meso Multi-level Pin Straps
MLPS Bit: PS_3

mappings between the bit values and resistor values

+1.8V_VGA

Vendor P/N

K4W4G1646E-BC1A
H5TC2G63FFR-11C
H5TC4G63CFR-N0C
MT41J128M16JT-093G:K128Mx16 *4,1000Mhz

5CB128M16FP-FL

NT
NT5CB256M16DP-FL

QCI P/N (BS/QCCON)

AKD5MGST508/AKD5MGST509
AKD5PGDT500/AKD5PGDT501
AKD5MZDTW02/AKD5MZDTW03
AKD5PZDTW01/AKD5PZDTW02
AKD5MGSTL16/AKD5MGSTL17
AKD5PZSTL00/AKD5PZSTL01
AKD5MGDTF00/AKD5MGDTF01110
AKD5PGDTF02/AKD5PGDTF03

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

TOPAZ_S3_Main

TOPAZ_S3_Main

NB5

NB5

NB5

TOPAZ_S3_Main

Date: Sheet of

Date: Sheet of

Date: Sheet

4.53K

6.98K

4.53K

3.4K

4.75K

4.75KNC

4.99K

4.99K

5.62K3.24K

of

12 62Friday, July 24, 2015

12 62Friday, July 24, 2015

12 62Friday, July 24, 2015

PDPU

2K8.45K
2K

NC111

1A

1A

1A

AA27
AB24

AB32
AC24
AC26
AC27
AD25
AD32

AE27

AF32
AG27
AH32

M32

W25
W26
W27

AA11

M12

K28
K32
L27

N25
N27
P25
P32
R27
T25
T32
U25
U27
V32

Y25
Y32

M6

N11
N13

N16
N18
N21

P6

P9
R12
R15
R17
R20
T13
T16
T18
T21

U15
U17
U20

U9
V13
V16
V18
Y10
Y15
Y17
Y20

V11

U28E

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31

GND#56
GND#57

GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71

T6

GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#86
GND#87
GND#88

DIS@Meso_S3

GND

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8

GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#84
GND#85

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
T11
R11

A32
AM1
AM32

U28F

LVDS CONTROL

NC_UPHYAB_TMDPA_TX0N
NC_UPHYAB_TMDPA_TX0P

NC_UPHYAB_TMDPA_TX1N
NC_UPHYAB_TMDPA_TX1P

NC_UPHYAB_TMDPA_TX2N
NC_UPHYAB_TMDPA_TX2P

NC_UPHYAB_TMDPA_TX3N
NC_UPHYAB_TMDPA_TX3P

TMDP

NC_UPHYAB_TMDPB_TX0N
NC_UPHYAB_TMDPB_TX0P

NC_UPHYAB_TMDPB_TX1N
NC_UPHYAB_TMDPB_TX1P

NC_UPHYAB_TMDPB_TX2N
NC_UPHYAB_TMDPB_TX2P

NC_UPHYAB_TMDPB_TX3N
NC_UPHYAB_TMDPB_TX3P

DIS@Meso_S3

NC_TXOUT_L3P

NC_TXOUT_L3N

NC_TXOUT_U3P
NC_TXOUT_U3N

AL15
AK14

AH16
AJ15

AL17
AK16

AH18
AJ17

AL19
AK18

AH20
AJ19

AL21
AK20

AH22
AJ21

AL23
AK22

AK24
AJ23

13

RECOMMENDED SETTINGS

CONFIGURATION STRAPS-- SEE EACH DATABOOK FOR STRAP DETAILS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,

THEY MUST NOT CONFLICT DURING RESET

STRAPS DESCRIPTION OF DEFAULT SETTINGSPIN

GPIO0 PCIE FULL TX OUTPUT SWINGTX_PWRS_ENB
GPIO1TX_DEEMPH_EN PCIE TRANSMITTER DE-EMPHASIS ENABLED

RSVD GPIO2 RESERVED 0
RSVD GPIO8 RESERVED 0

RSVD GPIO21 RESERVED 0

BIOS_ROM_EN

VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS (Removed on Seymour/Whistler)

RSVD H2SYNC RESERVED 0

RSVD GENERICC RESERVED 0

GPIO_22_ROMCSB

GPIO[13:11]ROMIDCFG(2:0)

HSYNC 0AUD[1]
VSYNC 0AUD[0]

ENABLE EXTERNAL BIOS ROM

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

SEE DATABOOK FOR DETAIL
SEE DATABOOK FOR DETAIL

NOTE1: AMD RESERVED CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED,
THEY MUST KEEP "LOW" AND NOT CONFLICT DURING RESET.

H2SYNC GENERICCGPIO21

GPIO8

GPIO2

0= DO NOT INSTALL RESISTOR
1 = INSTALL 3K RESISTOR

X = DESIGN DEPENDANT
NA = NOT APPLICABLE

0
X

0GPIO9 VGA ENABLEDBIF_VGA DIS

0

0 10

0

NB5

NB5

NB5

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

TOPAZ_S3_GND/LVDS/Strap

TOPAZ_S3_GND/LVDS/Strap

TOPAZ_S3_GND/LVDS/Strap

Date: Sheet of

Date: Sheet of

Date: Sheet of

13 62Friday, July 24, 2015

13 62Friday, July 24, 2015

13 62Friday, July 24, 2015

1A

1A

1A

+1.5V_VGA

+1.8V_VGA

+1.8V_VGA

1.5V ( DDR3, MVDDQ = 1.5V@2A)

C235

C245

C215

DIS@2.2U/6.3V_4

DIS@10U/6.3VS_6

C267

C260

DIS@0.1U/16V/X7R_4

DIS@0.01U/50V/X7R_4

Memory Phase Lock Loop Power :

L10 DIS@BLM18PG181SN1D(180,1.5A)_6\S

L9 DIS@HCB1608KF-121T30(120+-25%,3A)

1.8V @ 90mA

C162

DIS@1U/10V_4

Engine Phase Lock Loop Power :
analog power pin for engine PLL

1.8V @ 75mA

C87

DIS@1U/10V_4

+1.0V_VGA

C98
DIS@10U/6.3VS_6

C86
DIS@10U/6.3VS_6

L11 DIS@HCB1608KF-121T30(120+-25%,3A)

C293

C161

DIS@2.2U/6.3V_4

DIS@2.2U/6.3V_4

DIS@1U/10V_4

MPV18

SPV18

Engine Phase Lock Loop Power :
digital power pin for engine PLL

0.95V @ 100mA

DIS@2.2U/6.3V_4

+1.8V_VGA

C264

+3V_VGA

C93
DIS@10U/6.3VS_6

C185

DIS@2.2U/6.3V_4

VDD_GPIO18 @13mA

VDD_GPIO33@25mA

C237

DIS@1U/10V_4

+1.0V_VGA_SPV10

C95
DIS@0.1U/16V/X7R_4

C100

DIS@1U/10V_4

MPV18

SPV18

H13
H16
H19

K10
K23
K24

AA20
AA21
AB20
AB21

AA17
AA18
AB17
AB18

V12
U12

J10
J23
J24

J9

K9
L11
L12
L13
L20
L21
L22

Y12

L8

H7

H8

J7

U28D

MEM I/O

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17

LEVEL
TRANSLATION

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

I/O

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

NC_VDDR4#1
NC_VDDR4#2
NC_VDDR4#3

PLL

MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

DIS@Meso_S3

PCIE_PVDD

PCIE

NC#AB23
NC#AC23
NC#AD24
NC#AE24
NC#AE25
NC#AE26
NC#AF25
NC#AG26

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8

PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

VDDC#1

CORE

VDDC#2
VDDC#3

POWER

VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8

VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26

VDDC/VARY_BL

VDDC/DIGON
VDDC/GENERICA
VDDC/GENERICC

VDDC/DDC2CLK

VDDC/DDC2DATA

VDDC/HPD1
VDDC/GPIO_1
VDDC/GPIO_2

VDDC/GPIO_18

VDDC/GPIO_14_HPD2

BIF_VDDC_1
BIF_VDDC_2

VDDCI#1

ISOLATED

VDDCI#2

CORE I/O

VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

NC#W1/FB_VDDCI

NC#W3/FB_VSS

NC#FB_VDDC

NC#FB_VSS

PCIE_VDDR : 1.8V @ 100mA

AM30
AB23

AC23
AD24
AE24
AE25
AE26
AF25
AG26

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
AA12
M11
N12
U11
AB11
AB12
AB13
W9
AC11
AC13
AC14
U10
T10
W10
Y9

R21
U21

M13
M15
M16
M17
M18
M20
M21
N20

W1
W3

AC20
AD20

PCIE_VDDC : 0.95V @ 2.5A (GEN3.0)

TDP=25W/TDC=36A/EDC=TDCx1.5=54A(1ms)/EDP=35W(sustained)/Peak=53W(1ms)
VDDC+VDDCI

0.85~1.1V(36A peak )( Ripple < 87.2mV)

C252

DIS@2.2U/6.3V_4

C191

DIS@2.2U/6.3V_4

C81

DIS@10U/6.3VS_6

0.95V~1.1V(0.8A)

C176

DIS@0.1U/16V/X7R_4

R468 *DIS@0_4
R469 *DIS@0_4

R205 *DIS@0_4/S
R206 *DIS@0_4/S

DIS@2.2U/6.3V_4

DIS@2.2U/6.3V_4

+1.0V_VGA

C261
DIS@1U/10V_4

C85

DIS@1U/10V_4

C468

C243

C184

DIS@10U/6.3VS_6

C213

DIS@0.1U/16V/X7R_4

+VGA_CORE

+1.8V_VGA

C249

DIS@10U/6.3VS_6

C274

DIS@1U/10V_4

C246

DIS@2.2U/6.3V_4

C253

DIS@2.2U/6.3V_4

C158

DIS@10U/6.3VS_6

C127

DIS@1U/10V_4

VDDC_VSEN [53]
VDDC_VRTN [53]

ALF@1029:
Follow Power Side

C271

DIS@1U/10V_4

C177

DIS@2.2U/6.3V_4

C194

DIS@2.2U/6.3V_4

C186

DIS@10U/6.3VS_6

0.95V~1.1V(5A VDDCI)

C220

DIS@1U/10V_4

+1.0V_VGA

C263

DIS@1U/10V_4

+VGA_CORE

C134

DIS@2.2U/6.3V_4

C189

DIS@2.2U/6.3V_4

C83

DIS@10U/6.3VS_6

C262

DIS@1U/10V_4

C112

DIS@2.2U/6.3V_4

C216

DIS@2.2U/6.3V_4

C250

DIS@1U/10V_4

DIS@1U/10V_4

C212

DIS@2.2U/6.3V_4

DIS@2.2U/6.3V_4

C82

DIS@10U/6.3VS_6

C147

DIS@10U/6.3VS_6

C270

C214

12

14

C464

DIS@10U/6.3VS_6

C160

DIS@2.2U/6.3V_4

C175

DIS@2.2U/6.3V_4

+

C233
DIS@330U_2.5V_3528

+VGA_CORE

C172

DIS@10U/6.3VS_6

+1.5V_VGA [15,16,56]
+1.8V_VGA [11,12,53,55]
+1.0V_VGA [11,55]
+VGA_CORE [53,54]

NB5

NB5

NB5

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

TOPAZ S3 Power

TOPAZ S3 Power

TOPAZ S3 Power

Date: Sheet of

Date: Sheet of

Date: Sheet of

14 62Friday, July 24, 2015

14 62Friday, July 24, 2015

14 62Friday, July 24, 2015

1A

1A

1A

C306

DIS@1U/10V_4

VMA_RAS0#[16]
VMA_RAS1#[16]

VMA_CAS0#[16]
VMA_CAS1#[16]

VMA_CSA0#_0[16]
VMA_CSA1#_0[16]

VMA_WDQS[7..0][16]

VMA_RDQS[7..0][16]

VMA_DM[7..0][16]

VMA_DQ[63..0][16]

VMA_MA[15..0][16]

+1.5V_VGA

R267
DIS@40.2/F_4

R266
DIS@100/F_4

C304

DIS@1U/10V_4

VMA_ODT0[16]
VMA_ODT1[16]

VMA_WE0#[16]
VMA_WE1#[16]

VMA_CKE0[16]
VMA_CKE1[16]

VMA_CLK0[16]
VMA_CLK0#[16]

VMA_CLK1[16]
VMA_CLK1#[16]

VMA_BA0[16]
VMA_BA1[16]

VMA_BA2[16]

+1.5V_VGA

VMA_ODT0
VMA_ODT1

VMA_RAS0#
VMA_RAS1#

VMA_CAS0#
VMA_CAS1#

VMA_WE0#
VMA_WE1#

VMA_CSA0#_0
VMA_CSA1#_0
VMA_CKE0

VMA_CKE1
VMA_CLK0

VMA_CLK0#
VMA_CLK1

VMA_CLK1#
VMA_WDQS[7..0]
VMA_RDQS[7..0]

VMA_DM[7..0]
VMA_DQ[63..0]
VMA_MA[15..0]

VMA_BA0
VMA_BA1
VMA_BA2

support 1Gbit
VRAM ( 64M X 16 )

MVREFD

R264
DIS@40.2/F_4

MVREFS

R268
DIS@100/F_4

Rd

R265 DIS@120/F_4

C91

*DIS@0.1U/16V/X7R_4

U28C

K27

VMA_DQ0
VMA_DQ1
VMA_DQ2
VMA_DQ3
VMA_DQ4
VMA_DQ5
VMA_DQ6
VMA_DQ7
VMA_DQ8
VMA_DQ9
VMA_DQ10
VMA_DQ11
VMA_DQ12
VMA_DQ13
VMA_DQ14
VMA_DQ15
VMA_DQ16
VMA_DQ17
VMA_DQ18
VMA_DQ19
VMA_DQ20
VMA_DQ21
VMA_DQ22
VMA_DQ23
VMA_DQ24
VMA_DQ25
VMA_DQ26
VMA_DQ27
VMA_DQ28
VMA_DQ29
VMA_DQ30
VMA_DQ31
VMA_DQ32
VMA_DQ33
VMA_DQ34
VMA_DQ35
VMA_DQ36
VMA_DQ37
VMA_DQ38
VMA_DQ39
VMA_DQ40
VMA_DQ41
VMA_DQ42
VMA_DQ43
VMA_DQ44
VMA_DQ45
VMA_DQ46
VMA_DQ47
VMA_DQ48
VMA_DQ49
VMA_DQ50
VMA_DQ51
VMA_DQ52
VMA_DQ53
VMA_DQ54
VMA_DQ55
VMA_DQ56
VMA_DQ57
VMA_DQ58
VMA_DQ59
VMA_DQ60
VMA_DQ61
VMA_DQ62
VMA_DQ63

DRAM_RST_C VMA_WE1#

CLKTESTA
CLKTESTB

C92
*DIS@0.1U/16V/X7R_4

H30
H32
G29

C30

C28
E27
G26
D26

C25
E25
D24
E23

D22
E21

D20

D18

C17
E17
D16

D14

C13
E11

C11

K26

K25

J29

F28
F32
F30

F27
A28

F25
A25

F23
F21

F19
A19

F17
A17

F15
A15

F13
A13

A11
F11

A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3

E1
G7
G6
G1
G3

J6

J1

J3

J5

J26
J25

L10

K8

L7

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MVREFDA
MVREFSA

NC
MEM_CALRP0

DRAM_RST
CLKTESTA

CLKTESTB

DIS@Meso_S3

MEMORY INTERFACE

MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA0_8
MAA0_9

MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7

MMA1_8

MAA1_9

WCKA0_0

WCKA0B_0

WCKA0_1

WCKA0B_1

WCKA1_0

WCKA1B_0

WCKA1_1

WCKA1B_1

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3
EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3
DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3

ADBIAO

ADBIA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B
RASA1B

CASA0B
CASA1B

CSA0B_0
CSA0B_1

CSA1B_0
CSA1B_1

CKEA0
CKEA1

WEA0B
WEA1B

K17
J20
H23
G23
G24
H24
J19
K19
G20
L17

J14
K14
J11
J13
H11
G11
J16
L15
G14
L16

E32
E30
A21
C21
E13
D12
E3
F4

H28
C27
A23
E19
E15
D10
D6
G5

H27
A27
C23
C19
C15
E9
C5
H4

L18
K16

H26
H25

G9
H9

G22
G17

G19
G16

H22
J22

G13
K13

K20
J17

G25
H10

VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA13
VMA_MA15

VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_BA2
VMA_BA0
VMA_BA1
VMA_MA14

VMA_DM0
VMA_DM1
VMA_DM2
VMA_DM3
VMA_DM4
VMA_DM5
VMA_DM6
VMA_DM7

VMA_RDQS0
VMA_RDQS1
VMA_RDQS2
VMA_RDQS3
VMA_RDQS4
VMA_RDQS5
VMA_RDQS6
VMA_RDQS7

VMA_WDQS0
VMA_WDQS1
VMA_WDQS2
VMA_WDQS3
VMA_WDQS4
VMA_WDQS5
VMA_WDQS6
VMA_WDQS7

VMA_ODT0
VMA_ODT1

VMA_CLK0
VMA_CLK0#

VMA_CLK1
VMA_CLK1#

VMA_RAS0#
VMA_RAS1#

VMA_CAS0#
VMA_CAS1#

VMA_CSA0#_0

VMA_CSA1#_0

VMA_CKE0
VMA_CKE1

VMA_WE0#

25mm (max) 2

From GPU

DRAM_RST_C

Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.

R130 DIS@10/F_4

R136
DIS@4.99K/F_4

5mm (max)5mm (max)

R125 DIS@51_4

C88
DIS@120P/50V_4

15

DRAM_RST_M [16]

+1.5V_VGA [14,16,56]

R117

*DIS@51.1/F_4

route 50ohms

ingle-ended/100ohms diff

s
and keep short

R118

*DIS@51.1/F_4

NB5

NB5

NB5

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

TPOAZ_S3_MEM_Interface

TPOAZ_S3_MEM_Interface

TPOAZ_S3_MEM_Interface

Date: Sheet of

Date: Sheet of

Date: Sheet of

15 62Friday, July 24, 2015

15 62Friday, July 24, 2015

15 62Friday, July 24, 2015

1A

1A

1A

5

U6

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL
SDRAM DDR 3

DI

S@H5TC4G63A FR-11C

VREFC_VMA1

C301

DIS@0.1U/16V/X7R_4

R698
DIS@40.2/F_4

VMA_CLK0_COMM

R697
DIS@40.2/F_4

R150
DIS@40.2/F_4

VMA_CLK1_COMM

R149
DIS@40.2/F_4

5

VMA_MA[15..0]

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#M1
VSS#M9
VSS#P1
VSS#P9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

DIS@4.99K/F_4

DIS@4.99K/F_4

VSS#J2
VSS#J8

VSS#T1
VSS#T9

VMA_DQ[63..0][15]

VMA_RDQS[7..0][15]

E3

VMA_DQ19

DQL0

F7

VMA_DQ18

DQL1

F2

VMA_DQ23

DQL2

F8

VMA_DQ17

DQL3

H3

VMA_DQ22

DQL4

H8

VMA_DQ20

DQL5

G2

VMA_DQ21

DQL6

H7

VMA_DQ16

DQL7

D7

VMA_DQ11

DQU0

C3

VMA_DQ14

DQU1

C8

VMA_DQ9

DQU2

C2

VMA_DQ13

DQU3

A7

VMA_DQ10

DQU4

A2

VMA_DQ15

DQU5

B8

VMA_DQ8

DQU6

A3

VMA_DQ12

DQU7

R214

R215

9/4: Dual Rank : 80.6 ohm
Single Rank : 40.2 ohm

+1.5V_VGA +1.5V_VGA

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5V_VGA +1.5V_VGA+1.5V_VGA

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VG A

C596

DIS@0.01U/50V/X7R_4

C108

DIS@0.01U/50V/X7R_4

Should be 240
Ohms +-1%

VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 VREFC_VMA3 VREFD_VMA 3 VREFC_VMA4 VREFD_VMA4

C266

DIS@0.1U/16V/X7R_4

VREFC_VMA2
VREFD_VMA2

VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12

VMA_BA0
VMA_BA1
VMA_BA2

VMA_CLK0
VMA_CLK0#
VMA_CKE0

VMA_ODT0
VMA_CSA0#_0
VMA_RAS0#
VMA_CAS0#
VMA_WE0#

VMA_RDQS0

VMA_WDQS 0

VMA_DM0
VMA_DM3

VMA_RDQS3

VMA_WDQS 3

DRAM_RST_M

VMA_ZQ2 VMA_ZQ3 VMA_ZQ4

R628
DIS@243/F_4

R664

DIS@4.99K/F_4

R649

DIS@4.99K/F_4

DIS@1U/6.3V_4 C527

DIS@1U/6.3V_4

DIS@10U/6.3VS_6

VMA_MA[15..0][15]

VMA_DM[7..0][15] VMA_WDQS [7..0][15]

VREFC_VMA1
VREFD_VMA1

VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4

D D

VMA_CSA0#_0[15]

C C

Should be 240
Ohms +-1%

B B

A A

VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12

VMA_MA15 VMA_MA15 VMA_MA15 VMA_MA15

VMA_BA0[15]
VMA_BA1[15]
VMA_BA2[15]

VMA_CLK0[15]

VMA_CKE0[15]

VMA_ODT0[15]

VMA_CAS0#[15] VMA_CAS1#[15]
VMA_WE0#[15]

VMA_RDQS2
VMA_WDQS 2

VMA_DM2
VMA_DM1

VMA_RDQS1
VMA_WDQS 1

DRAM_RST_M[15]

DIS@4.99K/F_4

DIS@4.99K/F_4

VMA_ZQ1

R258
DIS@243/F_4

R245

R253

+1.5V_VGA

VMA_CLK0

VMA_CLK0#
VMA_CLK1

VMA_CLK1#

4

U33

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

K1
L2

J3

K3

L3

F3
G3

E7
D3

C7
B7

T2
L8

J1
L1
J9
L9

C568
DIS@0.1U/16V/X7R_4

+1.5V_VGA

C477

+1.5V_VGA

C277

+1.5V_VGA

C105

DQL0

VREFCA

DQL1

VREFDQ

DQL2
DQL3

A0

DQL4

A1
A2

DQL5

A3

DQL6

A4

DQL7
A5
A6
A7

DQU0
A8

DQU1
A9

DQU2
A10/AP

DQU3
A11

DQU4
A12/BC

DQU5

DQU6

A13

DQU7

A14
A15

BA0

VDD#B2

BA1

VDD#D9
VDD#G7

BA2

VDD#K2
VDD#K8
VDD#N1

CK

VDD#N9

CK

VDD#R1

CKE

VDD#R9

VDDQ#A1

ODT
CS

VDDQ#A8

RAS

VDDQ#C1

CAS

VDDQ#C9

WE

VDDQ#D2
VDDQ#E9
VDDQ#F1

DQSL

VDDQ#H2

DQSL

VDDQ#H9

VSS#A9

DML

VSS#B3

DMU

VSS#E1

VSS#G8

DQSU

VSS#J2

DQSU

VSS#J8
VSS#M1
VSS#M9

VSS#P1

RESET

VSS#P9

VSS#T1

ZQ

VSS#T9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

NC#J1

VSSQ#E8

NC#L1

VSSQ#F9

NC#J9

VSSQ#G1
VSSQ#G9

NC#L9

96-BALL

INT

SDRAM DDR 3

DI

S@H5TC4G63A FR-11C

R286

DIS@4.99K/F_4

R285

DIS@4.99K/F_4

C240

DIS@1U/6.3V_4 C478

DIS@1U/6.3V_4

C269

DIS@1U/6.3V_4

DIS@1U/6.3V_4

C307

DIS@10U/6.3VS_6

DIS@10U/6.3VS_6

4

1G/2G DDR3L

E3

VMA_DQ7

F7

VMA_DQ5

F2

VMA_DQ3

F8

VMA_DQ2

H3

VMA_DQ6

H8

VMA_DQ0

G2

VMA_DQ4

H7

VMA_DQ1

D7

VMA_DQ28

C3

VMA_DQ29

C8

VMA_DQ30

C2

VMA_DQ24

A7

VMA_DQ27

A2

VMA_DQ26

B8

VMA_DQ31

A3

VMA_DQ25

+1.5V_VGA +1.5V_VGA

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5V_VGA

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

C319

DIS@0.1U/16V/X7R_4 C234

C476

DIS@1U/6.3V_4

C258

DIS@1U/6.3V_4

C285

C511

C109

C501

DIS@10U/6.3VS_6

VMA_CLK1#[15]VMA_CLK0#[15]

VMA_CSA1#_0[15]

DIS@1U/6.3V_4

DIS@1U/6.3V_4

VMA_CLK1[15]

VMA_CKE1[15]

VMA_ODT1[15]
VMA_RAS1#[15]VMA_RAS0#[15]
VMA_WE1#[15]

Should be 240
Ohms +-1%

C256

DIS@1U/6.3V_4

C284

DIS@1U/6.3V_4

C530

DIS@10U/6.3VS_6

VREFC_VMA3
VREFD_VMA3

VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12

VMA_BA0
VMA_BA1
VMA_BA2

VMA_RDQS7

VMA_WDQS 7

VMA_DM7
VMA_DM5

VMA_RDQS5

VMA_WDQS 5

DRAM_RST_M DRAM_RST_M

DIS@4.99K/F_4

DIS@4.99K/F_4

C236

C528

R197
DIS@243/F_4

R186

R191

DIS@1U/6.3V_4

DIS@1U/6.3V_4

3

U5

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

DI

S@H5TC4G63A FR-11C

C475

C314

DIS@10U/6.3VS_6

3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

96-BALL
SDRAM DDR 3

DIS@4.99K/F_4

DIS@4.99K/F_4

DIS@0.1U/16V/X7R_4

C268

DIS@1U/6.3V_4

C544

DIS@1U/6.3V_4

+1.5V_VGA

C516

DIS@10U/6.3VS_6

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

R180

R177

DIS@1U/6.3V_4

DIS@1U/6.3V_4

C582

VMA_DQ60
VMA_DQ58
VMA_DQ62
VMA_DQ57
VMA_DQ61
VMA_DQ56
VMA_DQ63
VMA_DQ59

VMA_DQ43
VMA_DQ46
VMA_DQ40
VMA_DQ47
VMA_DQ41
VMA_DQ45
VMA_DQ42
VMA_DQ44

C513

C594

DIS@10U/6.3VS_6

Should be 240
Ohms +-1%

C169

DIS@0.1U/16V/X7R_4

+1.5V_VGA

DIS@1U/6.3V_4

+1.5V_VGA

DIS@1U/6.3V_4

C552

C560

DIS@10U/6.3VS_6

VREFC_VMA4
VREFD_VMA4

VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_MA13VMA_MA13VMA_MA13VMA_MA13
VMA_MA14VMA_MA14VMA_MA14VMA_MA14

VMA_BA0
VMA_BA1
VMA_BA2

VMA_CLK1
VMA_CLK1#
VMA_CKE1

VMA_ODT1
VMA_CSA1#_0
VMA_RAS1#
VMA_CAS1#
VMA_WE1#

DIS@4.99K/F_4

DIS@4.99K/F_4

C259

DIS@1U/6.3V_4

C590

DIS@1U/6.3V_4

C228

VMA_RDQS6

VMA_WDQS 6

VMA_DM6
VMA_DM4

VMA_RDQS4

VMA_WDQS 4

R490
DIS@243/F_4

R546

R541

DIS@1U/6.3V_4

DIS@10U/6.3VS_6

M8
H1

N3

P7
P3

N2

P8

P2
R8
R2

T8
R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7

K7

K9

K1

L2

J3

K3

L3

F3
G3

E7
D3

C7

B7

T2

L8

J1

L1

J9

L9

C110

C551

DIS@1U/6.3V_4

C279

2

U25

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

VDDQ#A1

ODT
CS

VDDQ#A8

RAS

VDDQ#C1

CAS

VDDQ#C9

WE

VDDQ#D2

VDDQ#E9
VDDQ#F1

DQSL

VDDQ#H2

DQSL

VDDQ#H9

DML
DMU

DQSU
DQSU

RESET
ZQ

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2

NC#J1

VSSQ#E8

NC#L1

VSSQ#F9

NC#J9

VSSQ#G1
VSSQ#G9

NC#L9

96-BALL
SDRAM DDR 3

DI

S@H5TC4G63A FR-11C

DIS@4.99K/F_4

DIS@4.99K/F_4
C491
DIS@0.1U/16V/X7R_4

C522

DIS@1U/6.3V_4

C595

DIS@1U/6.3V_4

C106

DIS@10U/6.3VS_6

2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7

VDD#K2

VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VSS#A9

VSS#B3

VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

R595

R592

E3

VMA_DQ53

F7

VMA_DQ54

F2

VMA_DQ49

F8

VMA_DQ55

H3

VMA_DQ50

H8

VMA_DQ51

G2

VMA_DQ48

H7

VMA_DQ52

D7

VMA_DQ37

C3

VMA_DQ32

C8

VMA_DQ38

C2

VMA_DQ33

A7

VMA_DQ36

A2

VMA_DQ34

B8

VMA_DQ39

A3

VMA_DQ35

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

DIS@1U/6.3V_4

C593

DIS@1U/6.3V_4

C255

DIS@10U/6.3VS_6

C526

DIS@0.1U/16V/X7R_4

C257

DIS@1U/6.3V_4

C542

DIS@1U/6.3V_4

C111

DIS@1U/6.3V_4

C276

DIS@1U/6.3V_4

1

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

Sun S3 VRAM(DDR3 BGA96P)

Sun S3 VRAM(DDR3 BGA96P)

NB5

NB5

NB5

Sun S3 VRAM(DDR3 BGA96P)

Date: S heet of

Date: S heet of

Date: S heet of

1

16

+1.5V_VGA [14,15,56]

16 62Fri day, July 24, 2015

16 62Fri day, July 24, 2015

16 62Fri day, July 24, 2015

1A

1A

1A

5

4

3

2

1

PV, 0415, follow leading project to add MOSFET for FPR_OFF

+3V +3V_FPR

R737 0_4

1

Q59
*AO3415

USBP5-_C
USBP5+_C

2

3

USBP5-_C
USBP5+_C

Fingerprint Conn

C311

C302

4.7U/6.3V_6

0.1U/16V/X7R_4

CN10

1
2
3
4
5
6

POWER BTN CONN

DFFC06FR062

88513-0601-6p-l-smt

1105@Ronny: need to change PN and FP

ESD1

USBP5+_C FPR_OFF
USBP5-_C

1

1

2

2

3

3

AZC099-04S

6

6

5

5

4

4

FPR_LOCK#

+3V

D D

R222
10K_4

USBP5-[6]
USBP5+[6]

FPR_LOCK#[5]

C C

B B

FPR_OFF[5]

USBP5­USBP5+

FPR_LOCK#
FPR_OFF

USBP5­USBP5+

R228 *0_4/S
R227 *0_4/S

17

A A

NB5

NB5

NB5

5

4

3

2

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet

Finger Printer

Finger Printer

Finger Printer

of

17 62Friday, July 24, 2015

17 62Friday, July 24, 2015

17 62Friday, July 24, 2015

1

1A

1A

1A

5

400 series 0930 Delete DP DemultiPlexter due to not support docking

400 series 0930 Delete DP DemultiPlexter due to not support docking

400 series 0930 Delete DP DemultiPlexter due to not support docking400 series 0930 Delete DP DemultiPlexter due to not support docking

400 series 1001 change to LVDS/eDP co-design

400 series 1001 change to LVDS/eDP co-design

400 series 1001 change to LVDS/eDP co-design400 series 1001 change to LVDS/eDP co-design

D D

4

3

2

1

18

C C

B B

A A

ALF@1119:
HP confirmed to remove the eDP to LVDS convertor.

+3V[4,5,6,7,9,10,11,17,19,20,21,22,23,24,25,26,28,29,31,34,35,36,37,39,41,42,43,48,50,52,58]

PROJECT : 400 SERIES

PROJECT : 400 SERIES

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

RTD2136

RTD2136

NB5

NB5

5

4

3

2

NB5

RTD2136

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

18 62Friday, July 24, 2015

18 62Friday, July 24, 2015

18 62Friday, July 24, 2015

1

400 series 1001 change LVDS/eDP co-design

LID Switch

LID_SW#_3[25,33,40]

EMU_LID[39]

A A

CZ-L only

B B

C C

D D

OUT_LVDS_BLON

OUT_DPST_PWM VADJ1

For eDP

Close to LVDS connector

INT_eDP_TXP1[4]

INT_eDP_TXN1[4]

INT_eDP_TXP0[4]

INT_eDP_TXN0[4]

INT_eDP_AUXN[4]

INT_eDP_AUXP[4]

R340 *0_4/S
R717 *0_4

OUT_LVDS_BLON

R343 *CZL@100K/F_4

R342

1K/F_4

C411 33P/50V_4

+VIN

C35
*4.7U/25V_6

400 series 1001 change LVDS/eDP co-design

400 series 1001 change LVDS/eDP co-design400 series 1001 change LVDS/eDP co-design

PN_BLON

R344 1K/F_4

C34

0.1U/25V_4

R31 close to U2
for eDP,stuff

For EDP Only: stuff Cap
For LVDS only stuff Resistor

2

2

1

3

C21
1U/6.3V_4

DISP_ON

C24 0.1U/16V/X7R_4

C23 0.1U/16V/X7R_4
C26 0.1U/16V/X7R_4

C25 0.1U/16V/X7R_4
C29 0.1U/16V/X7R_4

C30 0.1U/16V/X7R_4

BLON_CON

D14
BAT54AW

R33
100K/F_4

C408 22P/50V_4
R349 100K/F_4

1124@RNY
Follow T/L BLON circuit
& avoid assembly ESD protection

+VIN

+VIN

C31

0.1U/25V_4

U1

5

IN

4

IN

3

ON/OFF

AP2821KTR-G1

for eDP,stuff U2 & L8

for LVDS,stuff C29 & R23

OUT
GND

+3V

C11
*4.7U/25V_6

For eDP, close to CN2

1122@RNY
Follow CRB panel level shifter control

CZ only

TXLOUT1+
TXLOUT1-

TXLOUT0+
TXLOUT0-

EDIDDATA_R
EDIDCLK_R

APU_DISP_ON[4,19]

3

100mA

C20

0.1U/25V_4

L8

+VIN_BLIGHT

C32

0.1U/25V_4

*HCB1608KF-181T15_S0_6/S

R341 CZ@2.2K_4

R348
CZ@100K/F_4

C13 0.1U/25V_4
C19 0.01U/50V/X7R_4

1
2

+VIN_BLIGHT

C15

0.01U/50V/X7R_4

2 1

C27

0.1U/25V_4

C16

0.1U/16V/X7R_4

2 1

2

4

For EDP Only: Reserved

+3VLCD_CON

C28
10U/6.3V_6

+3V

R351

CZ@100K/F_4

3

2

1

Q36
CZ@METR3904-G

1 3

+3V

R15 *100K_4
R14 *100K_4

+3V

R346 *1K_4
R339 *1K_4

R352
CZ@4.7K_4

DISP_ON

Q37
CZ@2N7002K

APU_LVDS_BLON[4,19]

+3V

*0.01U/50V_4

5

EDIDDATA_R
EDIDCLK_R

OUT_DPST_PWM
OUT_LVDS_BLON

+3V_CAM

C38

C22

*4.7U/6.3V_6

CAMERA_ON[6]

DIGITAL_CLK[23]

DIGITAL_D1[23]

PV, 0421, L19 change to 300ohm bead for EMI

1029@RNY: follow DG, eDP HPD PD 100K

R355 CZ@2.2K_4

R356
CZ@100K/F_4

2

USBP0-[6]

USBP0+[6]

EDP_HPD[4]

EDP_HPD

CZ@100K/F_4

1 3

6

SI, 0209, EMI need to add CMC
PVR, 0720, delete USB2.0 0ohm co-lay

USBP0-_C

USBP0+_C

12

C619
*Clamp-Diode

C620
*Clamp-Diode

7

12

SI, 0209, EMI need to add CMC

1

2

4 3

+3VLCD_CON

R23 *0_6/S

+3V

1 2

1 2

C33 0.047U/25V_4

C37 0.047U/25V_4

L19 300/300MA_S0_4
L20 120/300MA_S0_4

R357
100K/F_4

C410

22P/50V_4

R358 *0_4/S

C409
22P/50V_4

+VIN_BLIGHT

11/06 for RF reserved

+3V +3V

2

R361
CZ@2.2K_4

61

Q39B

CZ@2N7002KDW

APU_DPST_PWM[4,19]

R366 CZ@2.2K_4

R360

Q38
CZ@METR3904-G

C39

*1000P/50V_4

R364
CZ@4.7K_4

C17

1000P/50V_4

8

19

LVDS Conn.

GS12401-1011-9H

lvds-50671-04041-001-40p-l

DFFC40FR063

CN2

40
39
38
37
36
35
34
33

5

R367
CZ@4.7K_4

OUT_DPST_PWMOUT_LVDS_BLON

34

Q39A

CZ@2N7002KDW

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

41 42

USBP0-_C
USBP0+_C

L6MCM2012B900GBE

+3V_CAM

EDIDCLK_R
EDIDDATA_R

TXLOUT1­TXLOUT1+

TXLOUT0­TXLOUT0+

ULT_EDP_HPD_REDP_HPD

DIGITAL_CLK_L

VADJ1
BLON_CON

ALF@1119:

1. Removed the LVDS Pin Define

2. Swapped Pin to sync up with 13"

R369
CZ@47K/F_4

2

Q40
CZ@METR3904-G

1 3

ALF@1113:
Swapped Pin to sync up with 13"

1

PROJECT : 400 SERIES

PROJECT : 400 SERIES

CZ-L only

APU_DISP_ON[4,19]
APU_LVDS_BLON[4,19]
APU_DPST_PWM[4,19]

2

3

R354 *CZL@0_4
R359 *CZL@0_4
R365 *CZL@0_4

DISP_ON
OUT_LVDS_BLON
OUT_DPST_PWM

4

+5VPCU[24,27,31,34,43,44,45,46,47,48,50,52,53,55,56,58]

+3V[4,5,6,7,9,10,11,17,20,21,22,23,24,25,26,28,29,31,34,35,36,37,39,41,42,43,48,50,52,58]

+3VPCU[7,25,32,33,35,36,38,39,40,41,42,43,44,45,47,52,55,57]

+5V[22,23,24,32,35,37,52,58]

+VIN[37,38,42,43,44,45,46,47,49,51,54,56]

5

6

NB5

NB5

NB5

PROJECT : 400 SERIES

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

LCD CONN/LID/CAM/D-MIC

LCD CONN/LID/CAM/D-MIC

LCD CONN/LID/CAM/D-MIC

Date: Sheet of

Date: Sheet of

Date: Sheet of

7

1A

1A

1A

19 62Monday, July 27, 2015

19 62Monday, July 27, 2015

19 62Monday, July 27, 2015

8