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MODEL:
REV DATE
4 4
2001/05/29
3B
RT2
CHANGE LIST
C2 Test (PCB P/N: DA0RT2MBAD1)
31. To Decrease volume of PC Beep,
Page25: Change R319 to 22K, R312 to 680
Page26: Change R288 to 22K, R303 to 680
32. Page47: For machenism interference, change C509, C510 to no-loading; C511,C512 to 270U.
33. Page14: For USB signals quality, change C415, C366, C391, C386, C429, C421 to no-loading.
34.Page15: Add 2'nd source for eeprom of Lan
35.Page8: Pull-up & pull-down already built in GMCH, so change R242, R38-40, R46-49, R52, R53, R60, R62-67, R72, R73 to no-loading.
36. Page42: Change spring to FDRT1010019(5mm): PAD100, PAD102, PAD106-108, 110-112.
Ramp ( PCB P/N: DA0RT2MBAE0 )
2001/06/20
3C
3 3
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2001/06/22
2001/06/28
2001/07/04
2001/07/10
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1.Page12: For ICH3 (B0 stepping, QB62), change R547 to 18.2_1%.
2.Page42: Hole1, Hole2 are NPTH, so change pin1 to NC.
3.Page34: To awake EC, change D32.2 to <SUSB#> from <SUSA#>.
4.Page17: Add discharge circuits for CD_VCC: Q116, R676.
5.Page44: Change PC69, PC71 footprint to TC1206.
6.Page22: Change Q48 to 2N7002.
7.Page14: Change R20 to 0805 for USB GND.
8.Page46: To avoid interference with Lan cable, move PFL2 to TOP side.
9. For EMI,
Page27: Change C858, C860 to 180P.
Page42: Load PAD107, PAD29, PAD37. Change PAD110 to no-loading. Change PAD37 to FDSS2002019.
10.Page15: For lan, change R385 to 124_1%. Reserve C967,C757. Add 2'nd source for U59:ATP119(this config can pass the lan test in intel
lab). Change C968,C969 to 1000P_2KV_1206(footprint is compatible with 1808 size).
11. Change U47(ATI M6-P) P/N to AJAFA120T03 for TOP.
12.Page16: Change CON18(HDD conn) to DFHS44FR096.
13.Page12: Change RTC cap: C797, C796 to 15P.
14.Page36: To avoid mechanism interference, change CON15(stick conn) to 5.5mm(ACS).
15.Page30: To avoid conflict with wireless card, change R318.2 (USB_DISCONN) to CON24.4; R622.2 (USB_RESET) to CON24.6
16.Page22: Change C483 from 10U/25V_4532 to 10U/25V_1210.
17. For ESD,
Page42: Change Hole1 to <GND_DC1> and connected gnd by R678, R680. Change Hole2, PAD100 to <GND_DC2> and connected gnd by R677, R679.
Page41: Change CON5.243,244 to NC from GND.
18. Change PCB to DA0RT2MBAE0, Rev E.
19.Page47: Change D5 footprint to DSMA.
20.Page8: Because of external graphic, pull down <DREF_CLK>: delete C963, change R666 to 10K.
21.Page26: Change R165 to 0603; add R681, but reserved.
22.Page41: U5,U6,U7 cghange foot print to APIC16861-RT2.
23.Page42: Change PAD37 to FDSS2002019 to avoid interference.
24.Page8: Reserve R666.
25.Page45: Deeper sleep voltage change to 0.85V, so reserve R12,R170,R219; change R220, R169, R13 to loading.
26. Add jumper wire(AWG26) to connect PQ43 pin3 and L124 pin2 on PCB top side, to avoid VGA core power <+1.8V_VGA> drop down.
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PROJECT : RT2.0
Quanta Computer Inc.
A
MB Assy' P/N: 31RT2MBAB5 Cover Sheet: 6 ofRev: 3CProject : RT2 MB
Project Manager : Jacky Lee Approved by : Jacky LeeProject Leader : T.S. Wan
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Document No.: 204
Drawing by : Allan Yu
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REV DATE
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1 1
3B
2001/04/25
2001/05/07
2001/05/09
2001/05/10
2001/05/15
2001/05/17
2001/05/18
2001/05/19
2001/05/24
PROJECT : RT2.0
Quanta Computer Inc.
RT2
CHANGE LIST
C2 Test (PCB P/N: DA0RT2MBAD1)
6. Page12: Move R600, C874, R609 close to ICH3.
7. Page28: To avoid floating, add pull-up R669 at <PCICSPK>.
8. Page47: For machenism interference, exchange the parts loaded on C510-512 with C81-83.
9. Page44: Change PQ47 from <1.8V_S5> to <+1.8V>.
10. Page46: Reserved PAD101.
11. Page47: Delete R299. Change PU9.18 to GND. Delete <S0>, <S1>, R80, R81, R70, R68, R69, R77.
12. Page46: Add PC101 470P, PC102 1000P for EMI.
13. Page15: For LAN performance,
(1) Delete L101-L104, short directly.
(2) Delete <GND_LAN>, R407.
(3) C745, C730 change to GND.
(4) Change R376 to 0805.
(5) Add LAN termination plane <GND_LAN_TERM >. Add C967-C969 1000P.
(6) Change U59 to Pulse H0022.
14. Page44: Delete PR71, PR75 short directly. Change PC82 to 1U_0805.
15. To avoid ICH3 SM bus leakage,
Page37: Change U21 to FST 3253.
Page12: Change R454, R445 to <3V_S5> from <+3V>.
Page3: Add Q114, Q115, R671, R672, R673.
16. Page44: Delete PFL3, short directly. Delete PD27 and PD24. Change PR72 to 240K, PC95 to 220P, PR80 to 20K_1%, PR74 to 200K.
17. Page42: Delete PAD103, 104, 105.
18. Page15: For LAN, add R674, R675 0_0805.
19. Page28: Add C970, C971 0.1u_0402 at L100.
20. Page15: Change R397 to BK2125HM121. Change CON23.15 to GND.
21. Page42: Delete PAD13, PAD32, PAD38.
22. Page23: Change the trace width or CRT RGB to 4 mil from 10 mil to approach the recommended impedance 75 ohm.
23. Page15: Add C972, C973 by intel recommendation for LAN.
24. For EMI
Page18: Add C974, L134.
Page24: Add C975, C976.
Page46: Change PL6, PL10 to FBMJ3216HS800-T.
Page47: Add L135 FBMJ3216HS800-T.
Page23: Delete TV_GND, change to GND. Delete R144.
25. To reduce Audio noise,
Page41: Change CON5.182 to AUDGND from GND.
Page26: Change Q62, Q60, C610, C64 to AUDGND.
Page30: Delete C65.
Page22: Delete C399-C403, C53, C464.
Page26,27: Change footprint of CON20,CON19,CON22. Delete R525, R550, R521, R523, R158, R568.
Page25: Delete R314, R313.
26. To Add regulator for VGA PLL power,
Page24: Delete C149, C121, C79. Add U89, C988, C985, C986, C989, C987, C978, C984, C982.
27. To fix VAUXPCIC leakage under Suspend to Disk,
Page12: Add U87(NC7SZ32), C977, <SUSCLK_ICH>.
28. Page42: For ICT test tool, change HOLE4,20,15,21,16 to NPTH.
29. Page23: Move C8 from TOP to BOT.
30. BOM changes: Page42: PAD109 no loading; Page18: Y1 change part to BG627000106; Page3: Update U24 to rev E; Page23:
Change CON12 to Yellow, and C803,C804,C808,C809,C811,C812 to 82P, and L34-36 to 1.8UH; Page27: Change CON19 to Blue,
CON20 to Pink; Page36: Change CON15 to vendor ACES; Page38: Change CON28 to vendor ACES; Page15: Change U59 from H0022
to H0029 (it's same as the former but lower cost for asia market). Page6: Change U17 to new ver, QC32.
Project Manager : Jacky Lee Approved by : Jacky LeeProject Leader : T.S. Wan
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MB Assy' P/N: 31RT2MBAB5 Cover Sheet: 5 ofRev: 3CProject : RT2 MB
Document No.: 204
Drawing by : Allan Yu
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48. Page35: For interference, change U58 to NC7SZ58.
2001/04/02
4 4
3A
2001/04/03
3 3
2001/04/09
2 2
2001/04/16
49. Page38: Change R614 to 680 ohm; CON28.1,R614 to be powered by +5V.
50. Page18: For ATI P6 D3 cold, add R659 to interconnect <PCIRST#> and P6. Change R518,Q80,U68,C841 to no-loading.
51. Page47: To interconnect pwrgood of MAX1718 and <HPWG> to EC, add D46, R660.
52. Page18: Change the gate of Q33,Q41 from <5VSUS> to <+5V>.
53. Page47: Change R299 to no-loading.
54. Page16: For<- HDDRESET>, change U83 to NAND(TC7SH00FU), add DTC144EU,10K to isolate different powers.
55. For ATI P6 D3 cold, delete <2.5VSUS>,
Page44: Delete <2.5VSUS>, PQ48,PR77, change PQ46 to no load and nets. Add R661,R662(no load). Change the control of U16.11 to <MAINON>
but option to <SUSON> by R662.
Page24: Delete L131,<2.5VSUS>.
56. Page24: Add regulators for DAC powers of CRT & TVout. Add U85,U86,C949-958. Delete L21,L93,C133,C515.
57. Page24, 44 ATI P6 power source options about D3 cold and D3 hot:
Power source option
for ATI P6 power states selection
ATI P6 power
states
Control
signals
Location
Q110
R661
L133
L130
R662
PQ46
L22
U68 Q80
R518 C841
58. To decrease volume of pc beep,
Page26: Change R288 to 6.8K.
Page25: Change R319 to 6.8K.
59. Page47: To fine tune CPU core voltage (VTT), change R89 to 1.82K_1%.
60. Page15: To improve Lan performance, change R385 to 110_1% from 100_1%, C757 to 1000P_2KV from 68P_2KV.
D3 cold
MAINON
Components options
Load
R659
L129
No load
D3 hot
SUSON
No load
Load
C2 Test (PCB P/N: DA0RT2MBAD1)
1. To fix wrong pins' definitions of ZV port buffer,
Page29: swap net names between U56.3 and U56.9; U56.17 and U56.11.
Page18: Change net name of U47.AA3 to <ZV_PCLK>.
Page25: Change net name of U43.50 to <ZV_SCLK>.
2001/04/23
3B
1 1
2001/04/24
PROJECT : RT2.0
Quanta Computer Inc.
2. For EMI,
Page3: Add R668, R664 0 ohm to connect GND planes.
Page6: Add R665, C960, but reserved.
Page7: Add C961, C962, C965, C966.
Page8: Add R666, C963, but reserved.
Page12: Add R667, C964, but reserved. Change R475 to 22 ohm from 68; C817 to 5P from 15P.
3. Page44: Change PC96 to 10U/10V/TAN.
4. Page15: Change C757 to 1000P_X7R_4520_3KV for LAN.
5. Page29: Change C723 to 0603 from 0402.
Page30: Change C733 to 0603 to 0402.
MB Assy' P/N: 31RT2MBAB5 Cover Sheet: 4 ofRev: 3CProject : RT2 MB
Project Manager : Jacky Lee Approved by : Jacky LeeProject Leader : T.S. Wan
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Document No.: 204
Drawing by : Allan Yu
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CHANGE LIST
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2001/03/15
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2001/03/22
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2001/03/29
15. Page47: Delete R644.
16. Page44: Change PQ48 to SI4800DY for larger current rating.
17. Page16: Change Q102, Q103 to DTC144EU to fix the problem that high level driven by 3.3V is lower than <HDD_VCC>.
18. Page44: Change PU16 pin20, 21 to 5VPCU.
19. Page47: Change D3 to EC31QS03L.
20. For Intel recommended on GMCH QS stepping,
Page6: Modify C430 and change value to 0.01U
Page3: Add R649 240K at U24.24.
21. Change part 1U_0805 to 1U_0603: C59-62, C521, C463, C545, C462, C533, C564, C559, C625, C624.
22. Page11: Add R658 pull-up for <RC> but reserved.
23. Page7: Change <SM_CLK> layout for Intel design change.
24. Page39: Change U30 power to <+5VA>, add C941 to reduce noise of <BEEP>.
25. For audio noise,
Page26: Change the power to <+5VA> and gnd to <AUDGND> for U12, Q47, C64, R54,R225, R256.
Page41: CON5 pin1,2,61,62,183,65 to <AUDGND> from <GND>.
Page27: Delete R292, R204, R269 and short the nets directly.
Page26: Delete R232.
26. Page41: Change R27 to <AUDGND> from <GND>, CON5 pin243, 244 to <GND> from <CHASIS_DOCK_1>(chasis gnd).
27. To prevent <HDD_VCC> and <CD_VCC> from power down during <PCIRST#> acting in warm-boot,
Page12: Delete the GPIO41, GPIO42 at U67(ICH3) pin G21, D23. Add <HDDVCC_EN> at pin W4(GPIO27), <CDVCC_EN> at pin Y3(GPIO28).
Page16: Add <HDDVCC_EN>, R653, R654(reserved), and <HDDVCC_ON> from EC. Change Q106 to 2N7002E.
Page17: Add <CDVCC_EN>, R655, R656(reserved), and <CDVCC_ON> from EC.
Page35: Add <HDDVCC_ON>,<CDVCC_ON> at U82 pin2, 5, controlled by EC (reserved).
28. Page12: Add R652 pull-low <PWROK>.
29. For RTC leakage, implement the design changes from Intel(WW08),
Page12: Add R652 pull-low <PWROK>. Add U84, C948, R651.
The rest changes have been done.
30. Page12: Move the RTC short pad G2 near CON29 under ninipci door.
31. Page16: For <-HDRESET>, Add U83, C942; delete Q102,103105, R630, R632.
32. Page16: Add C943. Change R629 to 1M.
33. Page17: Change R143 to 1M.
34. Page11: Add R657 10K at <APICD1>. Change R510 to 10K.
35. Page12 Change R547 to 22.6_1% for uab bias.
36. Page 24: For ATI P6 D3 cold, Change L131,L129,L22 to no-loading; L132,L130,L133 to loading.
37. For EC to control RF ON or OFF,
Page38: Add Q112, <RF_ON_OFF>.
Page35: Add <RF_ON_OFF> at U78.19.
38. Page36: For FAN driving current, change R458 to 1K; D41to loading; C895 to 4700P for <FANSIG>.
39. To prevent interference from wireless card,
Page30: Change C590,711,748 to 1U_0603.
Page25: Change C552 to 1U_0603.
Page28: Change C684 to 1U_0603.
40. Page46: To save power, change PR49,50,12,13 from 100K to 1M.
41. Page42: Add EMI Spring: PAD100-109.
42. Page5: Add C944-C947 for VTT.
43. For interference, move Q56,R380 away from CON29.
44. Page34: For interference, change C844 to 1U-0603.
45. Page33: Add IRGND plane under the ir module.
46. Page36: Move R458, Q73 to top side.
47. For impedance control, Change USB diffrrencial pairs to 7.5/7.5 mil (width/space).
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PROJECT : RT2.0
Quanta Computer Inc.
A
MB Assy' P/N: 31RT2MBAB5
Project Manager : Jacky Lee Drawing by : Allan Yu
B
Project Leader : T.S. Wan
C
Document No.: 204Project : RT2 MB Cover Sheet: 3 of
D
Rev: 3C 6
Approved by : Jacky Lee
E
MODEL:
REV DATE
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RT2 MB 16M
CHANGE LIST
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B Test (PCB P/N: DA0RT2MBAB5)
40. Page46: For power on squence, change PC36, PC38 to 1000P.
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2001/02/26
2001/02/27
2001/03/02
2001/03/06
41. Page4: Change R108 to 0603 size.
42. Page24,44: Change C149, C167, C171, C793 foot print to TC1206
43. Page38: Change R362 to 10K.
44. Page43: Change R516, R520 to no-loading for ITP.
45. Page25, 12, 15: ChangeY3 to Epson SG-710ECK, Y6 to MC-306, add 2nd source BG625000508.
46. Page12: Add L122 on <VCCRTC> for EMI.
47. Page46: Change R300 to 0603 size.
48. Page3: For EMI, add C900-C905(10P, reserved) and place near the destinations.
49. Page5: Add bypass cap 0.1U_0402 on VTT (C906-C926) and VCCT(C927-C936).
50. Page24: Modify power circuit for <VGA_PLL1.8>,<VGA_PNLPLL1.8>.
51. Page3: For EMI, modify GND of CLK generator. Add <CLK_GND>, R642, R643.
52. Page30, 35: Change the control of <-RF_ON_LED>, R633 from miniPCI to EC.
53. Page23, 38: To save power, change power plane from <5VPCU> to <+5V> on U39.8, R176, R3; from <3VSUS> to <3.3VAUX> on R369, R362.
54. Page47: Change Q6, Q12 to IRF7811A; Q5, Q10, Q11 to FDS7764A because of better characteristics.
55. Page20: Change L23 to no-loading, L24 to loading for Hyundai DDR. And change part to FCM2012V131DC10 for larger current rating.
56. Page36: Change R628 from 180K to 100K for part available.
57. Page12: For RTC leakage, change R455 to 22K at U67.Y6 ( INTRUDER# ).
C1 Test (PCB P/N: DA0RT2MBAC3)
2001/03/07
2001/03/08
2 2
3A
2001/03/12
2001/03/13
2001/03/15
1 1
1. Page22: Change R210 from 22_1206 to 22R_0805.
2. Modify 3V power circuits to simplify 3V resources and components. Delete <3V_ALWAYS> in entire schematics because it doesn't need
ALWAYS 3V.
Page49: Change PU15.28 from <VL> to <RVCC_ON>, change <3V_ALWAYS> to <3V_S5>.Change parts of PL4, PR63. Delete PC36, PC47. NC PD19.
3. Page21: Change memory I/O power of VGA chip, VDDR1, from <VDD_SDRAM> to <VDDQ_2.5V>. Because it must be same as VDDQ of VGA SDRAM(U23,
U60). Change VDDRH(U47.C5) to <VDDQ_2.5V> thru L123.
4. Page44, 46: Change net name from <MAINON_0> to <-MAIN_ON>, from <SUSON_0> to <-SUS_ON>.
5. Page47: Add L127, R644 but reserved for second source.
6. Page13: Change R432 from 0805 to 0603.
7. Page46: Delete fuse L33, L44. Change PL6 to FBM3216HS480NT(6 Amp) and add PL10 the same part.
8. Page 44: Modify 1.8 and 2.5 voltage circuits to switching power circuits for efficiency, change the source of <+1.5V> to be from
<+1.8V>.
9. As the changes of item 8, modify the VGA power circuits,
Page24: Delete regulators circuits: PU1, R98, R99 for <+1.8_VGA>; Q21, Q72, PU11, C285, C787-788, R447 for <VDDQ_2.5V>; U20, C173, C146,
R337-338 for <VGA_MEMPLL1.8>, and the relative discharging circuits. Then power them thru beads.
10. Page25, 35: Change <-M3_RST_EN> to <M3_RST_EN> for high-active.
11. Page47: Add discharge circuits for <VCCT>: R647, Q109; <VTT>: R645-646, Q107-108.
12. Page6: Change R324 footprint from 0603 to 0805.
13. Page17: Change Q78 from SI4800DY to SI3456 for small size.
14. For VGA D3-cold,
Page44: Add <+2.5V> power, PQ48, Q110, R648.
Page24: Add <2.5_VGA>, L131(reserved), L132 for option of power.
Page20: Change L24 to be powered with <2.5_VGA>.
Page24: Add <1.8_VGA>, L129(reserved), L130 for option of power.
Page24: Add L133( reserve L22 ) for option of power between <3VSUS> and <+3V>.
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
2A
2A
2A
2A
2A
2A
2A
2A
PROJECT : RT2.0
Quanta Computer Inc.
A
Project : RT2 MB 16M MB Assy' P/N: 31RT2MB0019
Project Manager : Jacky Lee Project Leader : T.S. Wan
B
C
Document No.: 204
Drawing by : Allan Yu
D
Rev: 3C
Cover Sheet: 2 of 6
Approved by : Jacky Lee
E
MODEL:
A
B
C
D
E
RT2 MB 16M RT2 MB 16M
CHANGE LISTREV DATE
Page From To
Page From To
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1A
1A
1A 2A
1A
1A
1A
1A
1A
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1A
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1A
1A
1A
1A
2000/01/04
1A
4 4
2001/01/12
2A
3 3
2 2
2001/02/26
1 1
A Test
First Release (PCB P/N: DA0RT2MBA7)
B Test (PCB P/N: DA0RT2MBAB5)
1. Change R103, R107, R61, R92, R97, R122, R123, R75, R379, R581, R582 from 22_1206 to 22_0805.
2. Page24: Modify footprint (UMAX8) of U19,U42.
3. For NS87570 strap pin,
Page34: Change R584 from 10K to no-loading, R585 from no-loading to 10K.
4. For Super I/O (PC87393) strap pin,
Page 31 Delete R463 at <TXD1>.
5. Page 5: Change R439 from 0805 to 0603.
6. The NMOS turn-on voltage (Q84, Q18) for 3V_S5, 3.3VAUX is not high enough,
Page44: Add Q98, Q97, R613, R612, <3V_S5_EN>, <3VAUX_EN>.
7. The voltage level of VGA_PLL1.8 and VGA_PNLPLL1.8 is not correct
Page24: Change R283, R51 to 44.2K_1%.
8. Spring arm ground contact
Page30, 10, 51: CON27.125.126; CON24.125.126; CON25.147.148; CON26.125.126.
9. Page15: Change U57(LAN PHY) to 82562EP(Kinnereth-M).
10. Simplify RI# circuits:
Page38: Delete U53, U54, C694, C695, R372, R373. Short D21.2, D22.2, D23.2, Q64.2.
11. Page 3: Exhange clock generator U24 66MHz output pin 22 & 23 for power down mode sequence.
12. Page 12: Delete USB pull low 1.5K: R559-R564, R541-R546.
13. Modify <DISPON> circuits :
Page22: Delete U35,U11, add D39, D40.
14.To prevent interference,
Page34, 51: change C789, C878, C810, C843 to 1U_0603_X5R.
15. To eliminate ground noise,
Page47: Change PU9.15 from inverter ground to system ground(GND).
16. Page15: Add one 4-pin lan pass through connector(CON29) for docking.
17. Page15: Add bypass cap C885-C889 for U56 (86562EP).
18. Page47: Delete SW2, add R618, change R272 from 0 to 15K_1%.
19. Page14: Change pin assignment of USB connector(CON6) and del U10. Change C422, C423 from 4.7Uf to 100uF
20. Page 16: Add reset and power control circuit for HDD.
21. Page 20: Pin 28 of U60 changes net name from VMCS1# to VMCS0#
22. Page 25: Add L120, L121for 49.152MHz oscillator for EMI.
23. Page 26: To increase the volume gain. Change R330 from 20K to 33K and R331 from 2.49K to 0.
24. Page 30: Add BlueTooth USB signals to 1st mini PCI connector.
25. Page 34: MY11 pin name is duplicated on BP4, pin5 and CON10, pin15. Change the net name to MY1_1.
26. Page 34,35: Add additional GPI and GPO for 87570.
27. Page 36: Add new fan drive circuit.
28. Page 36: Modify power LED control circuit for single color support, but reserved <-PWRLED1>.
29. Page 38: Add wireless LAN enable/disable circuit and add CON28 for antenna support.
30. Page 30: Route the AC-link signals to 1st mini PCI connector.
31. Page 14: Add two power control signals to USB ports and <USBOC0#>,<USBOC1#>.
32. Page 5: VID pullup resistor changes from 10K to 1K.
33. Page7, 9: New pin definition were added for GMCH-A3 silicon.
34. Page 7: Del R345 and make the length equals to 150+-50 mil.
35. Page 22: Modify <DIPON> circfuits, it controled by VGA(<-BLON>), ICH3(<DISP_ON>); simplify LCDVCC control circuits(<DIGON>).
36. Page46: Add spring ( PAD101 ) under power jack( PJ1 ).
37. For EMI,
Page25: Add L120, L121.
Page6: Add R639, C899(reserved), <CLK66_GBIN_1>.
38. Page6: R300 change to 0603 size.
39. Page25: Change R313 to noloading to disable modem auto detect by ES1988.
33
1A
34
1A
2A
35
1A
36
1A
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A 2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
PROJECT : RT2.0
Quanta Computer Inc.
A
Project : RT2 MB 16M MB Assy' P/N: 31RT2MB0019
Project Manager : Jacky Lee Project Leader : T.S. Wan
B
C
Document No.: 204
Drawing by : Allan Yu
D
Rev: 3C
Approved by :
Cover Sheet: 1 of
E
6
5
4
3
2
1
0711 modify
RT2 MB: PCB Rev E , Schematics Rev 3C
Schematics Page Index
D D
C C
B B
Pg#
Schematic Block Diagram
1
2
PAGE INDEX
3
Clock Generator
TUALATIN CPU(HOST BUS)-1
4
5
TUALATIN CPU(POWER/NC)-2
GMCH-M(HOST)-1
6
7
GMCH-M(DRAM)-2
8
GMCH-M(AGP)-3
9
GMCH-M(VCC,GND)-4
SDRAM,SODIMMX2
10
11
ICH3-M (CPU,PCI,IDE)-1
12
ICH3-M (USB,HUB,LPC)-2
13
ICH3-M (POWER&GND)-3
USBx2
14
15
LAN interface
Primary IDE (HDD interface)
16
17
Secondary IDE/FDD interface
18
ATI P6 (HOST,VIDEO O/P)-1
19
ATI P6 (VRAM)-2
20
Video DDR SDRAM
21
ATI M6 (PWR/GND)-3
LCD interface
22
S Video/Composite,CRT
23
VGA power
24
25
ESS1988
26
AMP/line out
Description
DNI LIST
Pg#
line in/mic in/CD audio in
27
TI1420 CARDBUS CONTROLLER
28
CARDBUS interface
29
MINI PCI-1 interface
30
super I/O (PC87393F)
31
LPT/FDD interface
32
COM/IR interface
33
PC87570F
34
35
570 I/O & RF/B CONN
570 access BUS/PS2/FAN/touch PAD
36
37
ICH SMBus
38
RING INDICATOR
39
1K Hz BEEP
40
upper,volume interface
FULL DOCK
41
hole PAD and EMI PAD
42
43 ITP interface
44
system special power
45
VID selector
46
power JACK/BATTERY CONN.
47 CPU power-VCCT/VTT
4850CHARGER & DISCHARGER
POWER CIRCUIT(MAX1632)
49
BATTERY SELECTOR
MINI PCI second interface51
Description
DNI LIST
11
10-LAYERS
STACKUP
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7
Layer 8
Layer 9
Layer 10
TOP
GND
IN1
IN4
GND1
IN5
IN2
IN3
VCC
BOT
Modified on C1 test
A A
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet of
FRONT-PAGE
PROJECT : RT2.0
Quanta Computer Inc.
1 57Tuesday, September 11, 2001
1
1A
5
4
3
2
1
RT2.0
D D
SO_DIMM*2
Page 10
LPC
PC87393F
Page 31
MAX1617
Page 4
IC9250-38
OR
FS6234-01
Clock Genrator
Page 3
PHY_82562EM H0009 LAN
Page 15
Page 15
USB1USB0
Page 14 Page 14
XBUS
PC87570F
Page 34
PS2 K/B TOUCH PADLINE_OUTLINE_IN MIC SPK_INT
Page 36
Page 34
BIOS
Page 34
connector
Page 15
CHARGE
GATE
Page 48
BAT2
Page 46 Page 46
BAT1
DC/DC
Page 47 Page 49
CLK66_AGP
LCD PANEL
XGA,SXGA+,UXGA TFT
(13.1/14.1/15.0")
C C
CRT port
S_VIDEO
TV OUT
Page 22
Page 23
Page 23
ZV_VIDEO
SHFCLK
LCD DATA
R,G,B
Y,C,COMP
ATI P6
VGA CONTROLLER
Page 18~21
27MHZ
Video-RAM Module
SDR: 8M/16MB
DDR: 16M/32MB
GAD[0--31], AGP control signal
MK1707
PVCLKI
PMCLKI
SHFCLK
spread spectrum
control
(Optional)
FDD
ZV_AUDIO
B B
PCI_AUDIO
ES1988
Page 25
AMP
Page 26
PCI_MODEM
802.11_LAN
BLUE_TOOTH
ACLINK_MODEM
Page 26Page 27Page 27
CPU: Tualatin
Page 20
Page 18
CD_AUDIO
SEC/IDE
Page 17Page 17 Page 16
MINI_PCI
first
Coppermine T
GMCH-M
PRY/IDE
PCI_BUS
Page 30 Page 28
ANTANA1
ANTANA2
MODEM
JACK
PSB
PCMCIA
TI1420
ZV_PORT
PCMCIA
SOCKET
HD#(0..63)HA#(3..31)
ICH3-M
AC_LINK
LPT/FDD COM1 IR
Page 29
DOCKING
Page 41
CPU thermal diode in
Page 04~05
Page 06~09
HUB
Page 11~13
Page 33 Page 33Page 32
MINI_PCI
second
Page 51
A A
Size Document Number Rev
C
5
4
3
2
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
BLOCK DIAGRAM
1
2 57Tuesday, September 11, 2001
1A
1
2
3
4
5
6
7
8
1 133MHZ
STSEM BUS FREQUENCYBSEL[1:0]
1
100MHZ10
Ramp_0704: Update
A A
+3V
C237
10P
R399
R400
330
R402 *0
SUSA#[12,18,25]
PCI_STP#[12]
CPU_STP#[12]
VTT_PWRGD#[5]
B B
BSEL0[4]
+3V
+3V
+3V
C C
+3V
+3V
C23910U/25V_1206
C241
0.1u_0402
C275
0.1u_0402
C959
0.1u_0402
C2_0423: Add
Q114
2N7002E
R673 100K
3
Q115
2N7002E
3
2
2
ICH_SMCLK[12,37]
D D
ICH_SMDATA[12,37]
12V
1
330
BK2125HM471
L25
BK2125HM471
L28
BK2125HM471
C242
0.1u_0402
BK2125HM471
C88110U/25V_1206
BK2125HM471
1
1
R124
10K
CK_VDD_REF
C250
1000P
L105
L118
L29
10U/25V_1206
+3V
+3V
2
R671
10K
CK_SMCLK
R672
10K
CK_SMDATA
12
C236
10P
12
CK_SMCLK
CK_SMDATA
C256
0.1u_0402
CK_VDD_3
C268
1000P
CK_VDD_CPU
1000P
C252
CK_VDD_48MHZ
C264
0.1u_0402
CK_VDDA
C277
12
R116
2M
C246
0.1u_0402
C269
0.1u_0402
0.1u_0402
C254
R411 221_1%
R120 10K
C274
0.1u_0402
12
CLK_XIN
Y2
14.318MHz
CLK_XOUT
BSEL2
BSEL1
BSEL0
C244
0.1u_0402
C263
0.1u_0402
Clock Generator
U24
2
XTAL_IN
3
XTAL_OUT
25
PWR_DWN#
34
PCI_STP#
53
CPU_STP#
28
PWRGD#
30
SCLK
29
SDATA
40
SEL2
55
SEL1
54
SEL0
1
VDD_REF
8
VDD_PCI_1
14
VDD_PCI_2
19
VDD_3V66_1
32
VDD_3V66_2
46
VDD_CPU_1
50
37
42
43
26
27
VDD_CPU_2
VDD_48MHZ
IREF
MULT0
VDD_CORE
GND_CORE
0.1u_0402
C247
CLK_GND
FOR GMCH A3
ICS: ICS9250EG-38 *** Used in C2 test, P/N:AL009250K17
Cypress: W320-03X
3
CK-TITAN
GND_REF
GND_PCI_2
GND_3V66_1
GND_3V66_2
GND_PCI_1
4
1511203147
9
66B2/3V66_4
66B1/3V66_3
66B0/3V66_2
GND_48MHZ
GND_IREF
36
41
CLK_GND
REF
CPU0
CPU#0
CPU1
CPU#1
CPU2
CPU#2
3V66_0
3V66_1/VCH
66IN/3V66_5
PCI_F2
PCI_F1
PCI_F0
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
48M_USB
48M_DOT
GND_CPU
4
56
52
51
49
48
45
44
33
35
24
23
22
21
7
6
5
18
17
16
13
12
10
39
38
CK-TITAN-A
CLK66_GBOUT
14M_S
T201 *PAD
T200 *PAD
CLK66_GBOUT
CLK66_ICHHUB_S
CLK66_GBIN_S
CLK66_AGP_S
PCLK_ICH_S
PCLK_CPUAPIC_S
T198 *PAD
PCLK_SIO_S
PCLK_PCIC_S
PCLK_AUD_S
PCLK_MINI2_S
PCLK_MINI_S
PCLK_DK_S
T199
CLK48_USB_S
CLK48_DREF_S
R128
33
12
C267
5P
R395 33
R391 33
*PAD
CLK_GND
CLK_GND
R434 33
R431 33
R417 33
R398 33
R118 33
R121 33
R413 33
R410 33
R409 33
R119 33
R401 33
R414 33
R426 22
0_0805
R668
0_0805
R664
0_0805
R642
0_0805
R643
5
C749
C744
*10P
*10P
C768
C778
*10P
*10P
C2_0423: Add
Add
Place near destination
C902
C903
C904
*10P
*10P
C782
C780
C762
*10P
*10P
*10P
PROJECT : RT2.0
Quanta Computer Inc.
CLOCK GENERATOR
C253
*10P
R649 240K
C755
*10P
6
C767
*10P
C900
*10P
C257
*10P
C901
*10P
*10P
0322: Add for QS stepping.
C750
C243
C756
*10P
C775
*10P
*10P
*10P
Size Document Number Rev
Custom
Date: Sheet of
7
C905
*10P
14M_SIO [31]
14M_ICH [12]
HCLK_CPU [4]
HCLK_CPU# [4]
HCLK_GMCH [6]
HCLK_GMCH# [6]
HCLK_ITP [43]
HCLK_ITP# [43]
CLK66_GBOUT [6]
CLK66_ICHHUB [12]BSEL1[4]
CLK66_GBIN [6]
CLK66_AGP [18]
PCLK_ICH [11]
PCLK_CPUAPIC [4]
PCLK_SIO [31]
PCLK_PCIC [28]
PCLK_AUD [25]
PCLK_MINI2 [51]
PCLK_MINI [30]
PCLK_DK [41]
CLK48_USB [12]
CLK48_DREF [8]
3 57Tuesday, September 11, 2001
8
2B
A
B
C
D
E
1617VCC
16
13
5
1
3
4
10K
R85
137_1%
R418
61.9_1%
HD#[0..63]
NC1
NC2
NC3
NC4
NC5
DXP
DXN
VCCT
+1.5V
D
+3V
15
STBY#
ALERT#
ADD1
ADD0
678910
R94
26.7_1%
HD#[0..63] [6]
R438
200_0805
2
SMBC
SMBD
R108
56.2_1%
U63
MAX1617A
VCC
14
12
11
GND1
GND2
DBSY# [6]
DRDY# [6]
PCLK_CPUAPIC [3]
CPURST# [6]
CPUINIT# [11]
HCLK_CPU [3]
HCLK_CPU# [3]
Size Document Number Rev
Custom
Date: Sheet of
+3V+3V
R436
R437
10K
10K
KBSMCLK [36]
KBSMDAT[36]
PROJECT : RT2.0
Quanta Computer Inc.
TUALATIN CPU(HOST BUS)-1
E
1A
4 57Tuesday, September 11, 2001
+1.5V
R433 1.5K
R115 10
+1.8V+1.5V
R131
1.5K
HA#[3..31]
ITP_TRST#[43]
ITP_PREQ#[43]
ITP_PRDY#[43]
H_DPSLP#[11,47]
HREQ#0[6]
HREQ#1[6]
HREQ#2[6]
HREQ#3[6]
HREQ#4[6]
HLOCK#[6]
DEFER#[6]
HTRDY#[6]
IGNNE#[11]
ITP_TDO[43]
ITP_TDI[43]
ITP_TMS[43]
ITP_TCK[43]
STPCLK#[11]
T171
T172
T174
T176
T186
ADS#[6]
T191
T189
T188
T173
T163
BPRI#[6]
BNR#[6]
HIT#[6]
HITM#[6]
T166
T168
T165
T167
RS#0[6]
RS#1[6]
RS#2[6]
T181
A20M#[11]
SMI#[11]
BSEL0[3]
BSEL1[3]
INTR[11]
NMI[11]
THERMDA
THERMDC
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
C255
2200P
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
IERR#
BREQ#0
FERR#
ITP_TDO
ITP_TDI
ITP_TMS
ITP_TRST#
ITP_TCK
ITP_PREQ#
ITP_PRDY#
U22A
K1
A3#
J1
A4#
G2
A5#
K3
A6#
J2
A7#
H3
A8#
G1
A9#
A3
A10#
J3
A11#
H1
A12#
D3
A13#
F3
A14#
G3
A15#
C2
A16#
B5
A17#
B11
A18#
C6
A19#
B9
A20#
B7
A21#
C8
A22#
A8
A23#
A10
A24#
B3
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RP#
ADS#
AERR#
AP0#
AP1#
BERR#
BINIT#
IERR#
BREQ0#
BPRI#
BNR#
LOCK#
HIT#
HITM#
DEFER#
BP2#
BP3#
BPM0#
BPM1#
TRDY#
RS0#
RS1#
RS2#
RSP#
A20M#
FERR#
IGNNE#
PWRGOOD
SMI#
TDO
TDI
TMS
TRST#
TCK
PREQ#
PRDY#
BSEL0
BSEL1
INTR/LINT0
NMI/LINT1
STPCLK#
DPSLP#
THERMDA
THERMDC
REQUEST
PHASE
SIGNALS
A13
A9
C3
C12
C10
A6
A15
A14
B13
A12
R1
L3
T1
U1
L1
T4
AA3
W2
AB3
P3
C14
AF23
AF4
A7
R2
L2
V3
AA2
U2
T3
AF22
AE20
AD22
AD21
W1
Y3
V1
U3
M5
AC3
AF6
AD9
AB4
AD3
AD11
AD7
AF7
AF15
AD10
AF19
AE22
AE12
AF10
AD15
AE14
AE4
AF8
AF13
AF14
B
TUALATIN
ERROR
SIGNALS
ARBITRATION
PHASE
SIGNALS
SNOOP PHASE
SIGNALS
RESPONSE
PHASE
SIGNALS
PC
COMPATIBILITY
SIGNALS
DIAGNOSTIC
& TEST
SIGNALS
EXECUTION
CONTROL
SIGNALS
THERMAL DIODE
TUALATIN_3
1 OF 3
DATA
PHASE
SIGNALS
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DBSY#
DRDY#
DEP0#
DEP1#
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#
PICCLK
PICD1
PICD0
FLUSH#
RESET#
INIT#
BCLK
BCLK#
EDGECTRLP
C
A16
B17
A17
D23
B19
C20
C16
A20
A22
A19
A23
A24
C18
D24
B24
A18
E23
B21
B23
E26
C24
F24
D25
E24
B25
G24
H24
F26
L24
H25
C26
K24
G26
K25
J24
K26
F25
N26
J26
M24
U26
P25
L26
R24
R26
M25
V25
T24
M26
P24
AA26
T26
U24
Y25
W26
V26
AB25
T25
Y24
W24
Y26
AB24
AA24
V24
W3
Y1
AE24
AD25
AE25
AC24
AF24
AD26
AC26
AD24
AF20
AD17
AD19
AF5
B15
AE6
AC1
AD1
AF16
FLUSH#
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
T160
T155
T156
T158
T161
T154
T153
T159
R425 150
HCLK_CPU_R
HCLK_CPU#_R
EDGCTRLP
PICD1
PICD0
R95
110_1%
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
R403
33
R404
33
+3V
C785
0.1u
THERMDA
THERMDC
R435 10K
R457
PCLK_CPUAPIC_1
R86 150
R93 150
+1.5V
R419
475_1%
R420
61.9_1%
HA#[3..31][6]
4 4
3 3
2 2
PWRGD_CPU[12]
1 133MHZ
1
1 1
R127
1.5K
FERR#[11]
STSEM BUS FREQUENCYBSEL[1:0]
100MHZ1 0
A
A
VAGTL_VCCA
C278
+
47u/6.3V_7343
VAGTL_VSSA
C226
C270
C225
0.1u_0402
0.1u_0402
0.1u_0402
CPUPERF#[12]
R117 1K
VCCT
R424 1K
VCCT
R129 1K
R132 1K
VCCT
C947
0.1u_0402
C1_0328: Add
C203
C593
1u_0805
C931
0.1u_0402
C936
0.1u_0402
C202
1u_0805
C233
1u_0805
C594
*1u
C930
0.1u_0402
C935
0.1u_0402
R134
14_1%
1u_0805
C784
0.1u_0402
N3
N2
A4
A21
N1
AF9
AF21
AA1
AB26
H26
AD5
AF12
L5
AE16
E2
AF11
M1
Y4
AD16
D6
D8
D10
D12
D14
D16
W21
AA11
AA13
AA15
AA17
AA19
AA21
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
D18
D20
D22
E11
E13
E15
E17
E19
E21
F10
F12
F14
F16
F18
F20
F22
G21
H22
K22
L21
M22
N21
P22
R21
T22
U21
V22
Y22
AA5
AA7
AA9
E5
E7
E9
F6
F8
G5
H6
J5
J21
K6
M6
N5
P6
R5
T6
U5
V6
W5
Y6
VTT
C786
VAGTLREF
R101
1K_1%
C759
C758
0.1u_0402
0.1u_0402
VTT
C946
0.1u_0402
C136
150u/6.3V_7343
C218
C726
1u_0805
1u_0805
C765
C766
*1u
*1u
1 2
L26
4.7uH
C174
0.1u_0402
R100
2K_1%
CMOSREF
RTTIMPEDP
R439
56.2_1%
C710
C273
1u_0805
1u_0805
C595
*1u
*1u
VCCT
VCCT
4 4
+1.5V
R406
1K_1%
R405
2K_1%
VCCT
VCCT
C272
1u_0805
C763
*1u
C945
0.1u_0402
VCCT
+
C271
1u_0805
C764
*1u
C944
3 3
0.1u_0402
2 2
assembly if breaket not sssembly.
VCCT
C927
C928
0.1u_0402
0.1u_0402
VCCT
1 1
C933
C932
0.1u_0402
0.1u_0402
C929
0.1u_0402
C934
0.1u_0402
Add
A
U22B
VCCA
VSSA
PLL ANALOG VOLTAGE
VREF0
VREF1
VREF2
VREF3
VREF4
VREF5
VREF6
VREF7
CMOSREF1
CMOSREF2
GHI#
RTTIMPEDP
TESTHI1
TESTHI2
TESTLO1
TESTLO2
NCTRL
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
B
TUALATIN
2 OF 3
POWER,
GROUND,
RESERVED
SIGNALS
TUALATIN_3
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
AB22
AC5
AC7
AC9
AC11
AC13
B
C
VTT
C907
A25
VSS01
B2
VSS02
B4
VSS03
B6
VSS04
B8
VSS05
B10
VSS06
B12
VSS07
B14
VSS08
B16
VSS09
B18
VSS10
B20
VSS11
B22
VSS12
B26
VSS13
C23
VSS14
C25
VSS15
D2
VSS16
D4
VSS17
D7
VSS18
D9
VSS19
D11
VSS20
D13
VSS21
D15
VSS22
D17
VSS23
D19
VSS24
D21
VSS25
E8
VSS26
E10
VSS27
E12
VSS28
E14
VSS29
E16
VSS30
E18
VSS31
E20
VSS32
E22
VSS33
E25
VSS34
F2
VSS35
F4
VSS36
F5
VSS37
F7
VSS38
F9
VSS39
F11
VSS40
F13
VSS41
F15
VSS42
F17
VSS43
F19
VSS44
F21
VSS45
F23
VSS46
G6
VSS47
G22
VSS48
G25
VSS49
H2
VSS50
H4
VSS51
H21
VSS52
H23
VSS53
J6
VSS54
J22
VSS55
J25
VSS56
K2
VSS57
K4
VSS58
K5
VSS59
K21
VSS60
K23
VSS61
L6
VSS62
L22
VSS63
L25
VSS64
M2
VSS65
M3
VSS66
M4
VSS67
M21
VSS68
M23
VSS69
N6
VSS70
N22
VSS71
N25
VSS72
P2
VSS73
P21
VSS74
P23
VSS75
R4
VSS76
R6
VSS77
R22
VSS78
R25
VSS79
T2
VSS80
T5
VSS81
T21
VSS82
T23
VSS83
U4
VSS84
U6
VSS85
U22
VSS86
U25
VSS87
V2
VSS88
V5
VSS89
V21
VSS90
V23
VSS91
W4
VSS92
W6
VSS93
W22
VSS94
W25
VSS95
Y2
VSS96
Y5
VSS97
Y21
VSS98
Y23
VSS99
AA6
VSS100
VCC77
VCC78
VCC79
VCC80
AC15
AC17
AC19
AC21
C906
VTT
C914
VTT
VTT
VTT
C656
0.47u_X7R
VTT
C922
0.1u_0402
VTT
12
VTT_PWRGD#[3]
0.1u_0402
0.1u_0402
C686
0.47u_X7R
C706
0.47u_X7R
0.47u_X7R
C649
10u/10V_1206
VTT_PWRGD[47]
VRON[34]
0.1u_0402
C915
0.1u_0402
C680
0.47u_X7R
C705
0.47u_X7R
C655
C923
0.1u_0402
12
C675
0.47u_X7R
C704
0.47u_X7R
C654
0.47u_X7R
Add
C687
10u/10V_1206
VTT_PWRGD
VTT_PWRGD#
C
C908
C909
0.1u_0402
0.1u_0402
C918
C917
C916
0.1u_0402
C668
0.47u_X7R
C703
0.47u_X7R
0.47u_X7R
C653
C924
0.1u_0402
12
C662
10u/10V_1206
VCCT +3V
Q15
DTC144EU
0.1u_0402
C707
0.47u_X7R
C925
0.1u_0402
12
C678
10u/10V_1206
R84
1K
2
C688
0.47u_X7R
C702
0.47u_X7R
CPU_VID0[45]
CPU_VID1[45]
CPU_VID2[45]
CPU_VID3[45]
CPU_VID4[45]
+3V
1 3
0.1u_0402
C926
0.1u_0402
12
R76
10K
C910
0.1u_0402
C681
0.47u_X7R
C701
0.47u_X7R
C657
0.47u_X7R
C692
10u/10V_1206
D17
1SS355
C911
0.1u_0402
C919
0.1u_0402
C676
0.47u_X7R
C660
0.47u_X7R
12
C669
10u/10V_1206
2
21
C920
0.1u_0402
C670
0.47u_X7R
C659
0.47u_X7R
R130
1K
VTT_PWRGD
12
C719
10u/10V_1206
C89 0.1u_0402
5
U16
7SH04
3
+3V
R274
10K
C912
0.1u_0402
R423
1K
4
D
C921
0.1u_0402
C708
0.47u_X7R
C658
0.47u_X7R
R422
1K
12
C720
10u/10V_1206
D
C913
0.1u_0402
VCCT
+3V
R133
R421
1K
1K
12
C650
10u/10V_1206
+3V
C99 0.1u_0402
5
1
2
3
E
Add
U22C
A26
VCCT1
C5
VCCT2
C7
VCCT3
C9
VCCT4
C11
VCCT5
C13
VCCT6
C15
VCCT7
TUALATIN
VCCT8
VCCT9
VCCT10
VCCT11
VCCT12
VCCT13
VCCT14
VCCT15
VCCT16
VCCT17
VCCT18
VCCT19
VCCT20
VCCT21
VCCT22
VCCT23
VCCT24
VCCT25
VCCT26
VCCT27
VCCT28
VCCT29
VCCT30
VCCT31
VCCT32
VCCT33
VCCT34
VCCT35
VCCT36
VCCT37
VCCT38
VID0
VID1
VID2
VID3
VID4
VTTPWRGD
C677
10u/10V_1206
3 OF 3
POWER, GROUND AND NC
VID
TUALATIN_3
ON_BOARD_CORE_ON [47]
Size Document Number Rev
Custom
Date: Sheet of
Quanta Computer Inc.
TUALATIN CPU(POWER/NC)-2
W23
AA23
AC4
AC23
AD6
AD8
AD12
AD14
AD18
AD20
AE18
C17
C19
C21
G23
N23
R23
U23
AA4
AE3
AF1
AF2
AB1
AC2
AE2
AF3
D5
E4
E6
G4
J4
J23
L4
L23
V4
R3
E3
12
4
U18
TC7SH08FU
AA8
VSS101
AA10
VSS102
AA12
VSS103
AA14
VSS104
AA16
VSS105
AA18
VSS106
AA20
VSS107
AA22
VSS108
AA25
VSS109
AB2
VSS110
AB5
VSS111
AB7
VSS112
AB9
VSS113
AB11
VSS114
AB13
VSS115
AB15
VSS116
AB17
VSS117
AB19
VSS118
AB21
VSS119
AB23
VSS120
AC6
VSS121
AC8
VSS122
AC10
VSS123
AC12
VSS124
AC14
VSS125
AC16
VSS126
AC18
VSS127
AC20
VSS128
AC22
VSS129
AC25
VSS130
AD2
VSS131
AE1
VSS132
AE5
VSS133
AE7
VSS134
AE9
VSS135
AE11
VSS136
AE13
VSS137
AE15
VSS138
AE17
VSS139
AE19
VSS140
AE21
VSS141
AE23
VSS142
AE26
VSS143
AF25
VSS144
AF26
VSS145
H5
VSS146
A2
NC1
A5
NC2
A11
NC3
B1
NC4
C1
NC5
C4
NC6
C22
NC7
D1
NC8
D26
NC9
E1
NC10
F1
NC11
N4
NC12
N24
NC13
P1
NC14
P4
NC15
P5
NC16
P26
NC17
AD4
NC18
AD13
NC19
AD23
NC20
AE8
NC21
AE10
NC22
AF17
NC23
AF18
NC24
PROJECT : RT2.0
E
T190*PAD
T180*PAD
T177*PAD
T192*PAD
T193*PAD
T183*PAD
T164*PAD
T194*PAD
T151*PAD
T195*PAD
T196*PAD
T184*PAD
T157*PAD
T197*PAD
T185*PAD
T182*PAD
T152*PAD
T187*PAD
T175*PAD
T162*PAD
T179*PAD
T178*PAD
T170*PAD
T169*PAD
5 57Tuesday, September 11, 2001
3A
A
HL[0..10][12]
HD#[0..63][4]
HA#[3..31][4]
ITP_CPURST#[43]
CLK66_GBIN[3]
PCIRST#[11,16,18,25,28,30,31,41,51]
ADS#[4]
HREQ#0[4]
HREQ#1[4]
HREQ#2[4]
HREQ#3[4]
HREQ#4[4]
BPRI#[4]
BNR#[4]
HLOCK#[4]
HIT#[4]
HITM#[4]
DEFER#[4]
DBSY#[4]
DRDY#[4]
HTRDY#[4]
RS#0[4]
RS#1[4]
RS#2[4]
CPURST#[4]
HLSTRB[12]
HLSTRB#[12]
CLK66_GBOUT
4 4
3 3
CLK66_GBOUT[3]
0322: Change
HCLK_GMCH[3]
2 2
1 1
HCLK_GMCH#[3]
VHUBREF[12]
A
HL[0..10]
HD#[0..63]
HA#[3..31]
R231 0
ADS#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
BPRI#
BNR#
HLOCK#
HIT#
HITM#
DEFER#
DBSY#
DRDY#
HTRDY#
RS#0
RS#1
RS#2
CPURST#
HLSTRB
HLSTRB#
R25
475_1%
R19
61.9_1%
HUBREF = 0.5 * VCC1_8
Place divider in the middle of
the bus
CLK66_GBIN
C430
0.01u
R28
61.9_1%
+1.8V
R298
301_1%
R307
301_1%
R270 0
R201
49.9_1%
R18
33
R24
33
C582
*470P
C588
0.1u_0402
CLK66_GBOUT_S
HCLK_GMCH_R
HCLK_GMCH#_R
HUBREF_CV
HUBREF_CG
PCIRST#_1
B
B
R315
*56.2_1%
R321
0
R639
C899
*10P
0
VHUBREF
C568
0.01u
CLK66_GBIN_1
EMI
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
PCIRST#_1
AA3
AD3
AB4
AB5
AA4
AA1
AA6
AB1
AC4
AA2
AB3
AD2
AD1
AC2
AB6
AC6
AC1
AF3
AD4
AD6
AC3
AH3
AE5
AE3
AG2
AF4
AF2
AJ3
AE4
AG1
AE1
AG4
AH4
AG3
AF1
AB24
C
W6
W5
W4
W3
W1
C
U4
P1
U2
U6
R1
N3
V4
P3
R3
U1
V6
T3
P2
V3
R2
T1
U3
Y4
V1
Y1
Y6
V2
Y3
Y2
GMCH3-M
U17A
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
RESET#
GMCH-M
HOST BUS INTERFACE (Processor
System Bus)
GTL_RCOMP
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
ADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
BPRI#
BNR#
HLOCK#
HIT#
HITM#
DEFER#
DBSY#
DRDY#
HTRDY#
RS0#
RS1#
RS2#
CPURST#
HTCLK
HTCLK#
GTL_REFA
GTL_REFB
GBOUT
GBIN
HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HLREF
HLSTRB
HLSTRB#
HL_RCOMP
H2
E3
G3
N4
M6
F1
F2
J3
F3
P6
G1
N5
H1
P4
T4
M2
J2
L2
R4
K1
L3
L1
J1
N1
T5
H3
M3
M1
K3
C1
K6
M4
K5
K4
L6
L4
E1
J6
D3
D1
J4
G5
F4
G4
H6
H4
G6
R6
AJ4
AH5
C2
J7
AA7
AD24
AG26
G26
H28
H29
H27
F29
F27
E29
E28
G25
G27
H26
H24
G29
F28
J23
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
ADS#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
BPRI#
BNR#
HLOCK#
HIT#
HITM#
DEFER#
DBSY#
DRDY#
HTRDY#
RS#0
RS#1
RS#2
CPURST#
HCLK_GMCH_R
HCLK_GMCH#_R
R324
80.6_1%_0805
CLK66_GBOUT_S
CLK66_GBIN_1
HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
VHUBREF
HLSTRB
HLSTRB#
HL_RCOMP
D
R300
54.9_1%
D
E
B2_0313: Change to 0805
VAGTLREF
CLK66_GBIN_1
C561
C460
0.1u_0402
0.1u_0402
Size Document Number Rev
B
Date: Sheet of
Quanta Computer Inc.
GMCH-M (HOST)-1
R665
C2_0423: Add,
*22
reserved
12
C960
Close to GMCH
*5P
PROJECT : RT2.0
E
2B
6 57Tuesday, September 11, 2001
A
B
C
D
E
GMCH-M
CS0#
CS1#
CS2#
CS3#
4 4
3 3
2 2
CLK_SDRAM0[10]
CLK_SDRAM1[10]
CLK_SDRAM2[10]
CLK_SDRAM3[10]
MD[0..63][10]
MA[0..12][10]
CS0#[10]
CS1#[10]
CS2#[10]
CS3#[10]
DQM0[10]
DQM1[10]
DQM2[10]
DQM3[10]
DQM4[10]
DQM5[10]
DQM6[10]
DQM7[10]
BMWEA#[10]
SRASA#[10]
SCASA#[10]
BS0[10]
BS1[10]
CKE0[10]
CKE1[10]
CKE2[10]
CKE3[10]
C965
*10P
MD[0..63]
MA[0..12]
C961
*10P
RP1
8P4R_10
RP2
8P4R_10
RP3
8P4R_10
R346 10
R347 10
R348 10
C962
C966
*10P
*10P
MA0
7 8
MA1
5
MA2
3
MA3
1
MA4
7 8
MA5
5
MA6
3
MA7
1
MA8
7 8
MA9
5
MA10
3
MA11
1
MA12
R349 10
R326 10
R350 10
R332 10
R351
10
SM_MA0
SM_MA1
6
SM_MA2
4
SM_MA3
2
SM_MA4
SM_MA5
6
SM_MA6
4
SM_MA7
2
SM_MA8
SM_MA9
6
SM_MA10
4
SM_MA11
2
SM_MA12
CS0#
CS1#
CS2#
CS3#
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
BMWEA#_1
SRASA#_1
SCASA#_1
BS0
BS1
CKE0
CKE1
CKE2
CKE3
CLK_SDRAM0_S
CLK_SDRAM1_S
CLK_SDRAM2_S
CLK_SDRAM3_S
3VSUS
R353
249_1%
R354
49.9_1%
C2_0423,24:
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
BMWEA#_1
SRASA#_1
SCASA#_1
BS0
BS1
CKE0
CKE1
CKE2
CKE3
SM_MA0
SM_MA1
SM_MA2
SM_MA3
SM_MA4
SM_MA5
SM_MA6
SM_MA7
SM_MA8
SM_MA9
SM_MA10
SM_MA11
SM_MA12
CLK_SDRAM0_S
CLK_SDRAM1_S
CLK_SDRAM2_S
CLK_SDRAM3_S
T137*PAD
T140*PAD
T139*PAD
T144*PAD
R352 27.4_1%
SM_REF
C622
0.1u_0402
E17
F16
D16
D15
F18
D18
D13
D12
E18
F17
F14
F13
A21
C20
D19
B16
C16
A13
C9
C13
A9
A20
B20
B19
C19
A18
A19
C17
C18
B17
A17
A16
C15
C14
A15
B2
B14
A3
F20
E20
F12
E11
F6
E5
F24
GMCH3-M
U17B
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7
SM_WE#
SM_RAS#
SM_CAS#
SM_BA0
SM_BA1
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_MA0
SM_MA1
SM_MA2
SM_MA3
SM_MA4
SM_MA5
SM_MA6
SM_MA7
SM_MA8
SM_MA9
SM_MA10
SM_MA11
SM_MA12
SM_CLK0
SM_CLK1
SM_CLK2
SM_CLK3
NC
NC
NC
NC
SM_RCOMP
SM_REFA
SM_REFB
A3
DRAM INTERFACE
SM_MD0
SM_MD1
SM_MD2
SM_MD3
SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8
SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13
SM_MD14
SM_MD15
SM_MD16
SM_MD17
SM_MD18
SM_MD19
SM_MD20
SM_MD21
SM_MD22
SM_MD23
SM_MD24
SM_MD25
SM_MD26
SM_MD27
SM_MD28
SM_MD29
SM_MD30
SM_MD31
SM_MD32
SM_MD33
SM_MD34
SM_MD35
SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40
SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45
SM_MD46
SM_MD47
SM_MD48
SM_MD49
SM_MD50
SM_MD51
SM_MD52
SM_MD53
SM_MD54
SM_MD55
SM_MD56
SM_MD57
SM_MD58
SM_MD59
SM_MD60
SM_MD61
SM_MD62
SM_MD63
SM_RCLK
SM_OCLK
D29
C29
D27
C27
A27
B26
E24
C25
E23
B25
C23
F22
B23
C22
E21
B22
C12
D10
C11
A10
C10
C8
A7
E9
C7
E8
A5
F8
C5
D6
B4
C4
E27
C28
B28
E26
C26
D25
A26
D24
F23
A25
G22
D22
A23
F21
D21
A22
F11
A11
B11
F10
B10
B8
D9
B7
F9
A6
C6
D7
B5
E6
A4
D4
C24
A24
SM_CLK
Add,
butreserved
1 1
Close to GMCH
UPDATE VER0.7A BY INTEL
LAYOUT 2'' AND 6'' FOR EACH LINE
A
B
C
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
12
C615
*22P
D
CHECK LAYOUT GUIDE
DEL R345(56.2_1%)
Length: 150 +- 50 MIL
Size Document Number Rev
B
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
GMCH-M (DRAM)-2
7 57Tuesday, September 11, 2001
E
2A
A
GAD[0..31][18]
4 4
3 3
GPAR[18]
2 2
1 1
R275
4.7K
+1.5V
R289
54.9_1%
A
GCBE0#[18]
GCBE1#[18]
GCBE2#[18]
GCBE3#[18]
GFRAME#[18]
GIRDY#[18]
GTRDY#[18]
GDEVSEL#[18]
GSTOP#[18]
SBA[0..7][18]
GREQ#[18]
GGNT#[18]
RBF#[18]
AD_STBA[18]
AD_STBA#[18]
AD_STBB[18]
AD_STBB#[18]
SB_STB[18]
SB_STB#[18]
ST0[18]
ST1[18]
ST2[18]
AGP_BUSY#[12,18]
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
PIPE#
WBF#
GMCH_GRCOMP
VAGPREF
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
+1.5V
C131
0.1u_0402
GMCH3-M
B
U17C
J29
G_AD0/DVOB_HS
J28
G_AD1/DVOB_VS
K26
G_AD2/DVOB_D1
K25
G_AD3/DVOB_D0
L26
G_AD4/DVOB_D3
J27
G_AD5/DVOB_D2
K29
G_AD6/DVOB_D5
K27
G_AD7/DVOB_D4
M29
G_AD8/DVOB_D6
M28
G_AD9/DVOB_D9
L24
G_AD10/DVOB_D8
M27
G_AD11/DVOB_D11
N29
G_AD12/DVOB_D10
M25
G_AD13/DVOBC_CLKINT
N26
G_AD14/DVOB_FLD/STL
N27
G_AD15
R25
G_AD16/DVOC_VSYNC
R24
G_AD17/DVOC_HSYNC
T29
G_AD18/DVOC_BLANK#
T27
G_AD19/DVOC_D0
T26
G_AD20/DVOC_D1
U27
G_AD21/DVOC_D2
V27
G_AD22/DVOC_D3
V28
G_AD23/DVOC_D4
U26
G_AD24/DVOC_D7
V29
G_AD25/DVOC_D6
W29
G_AD26/DVOC_D9
V25
G_AD27/DVOC_D8
W26
G_AD28/DVOC_D11
W25
G_AD29/DVOC_D10
W27
G_AD30/DVOBC_INTR#/DPMS_CLK
Y29
G_AD31/DVOC_FLD/STL
L27
G_CBE0#/DVOB_D7
P29
G_CBE1#/DVOB_BLANK#
R27
G_CBE2#/ZV_VS
T25
G_CBE3#/DVOC_D5
R29
G_FRAME#/M_DDC2_DATA
P26
G_IRDY#/M_I2C_CLK
P27
G_TRDY#/M_DDC2_CLK
R28
G_DEVSEL#/M_I2C_DATA
P28
G_PAR/DVO_DETECT
N25
G_STOP#
AA29
SBA0/ZV_D8
AA24
SBA1/ZV_D7
AA25
SBA2/ZV_D6
Y24
SBA3/ZV_D5
Y27
SBA4/ZV_D2
Y26
SBA5/ZV_D1
W24
SBA6/ZV_D0
Y28
SBA7/ZV_HREF
AC27
G_REQ#/ZV_CLK
AD29
G_GNT#/ZV_D15
AB25
RBF#/ZV_D11
AB26
PIPE#/ZV_D10
L29
AD_STB0/DVOB_CLK
L28
AD_STB0#/DVOB_CLK#
U29
AD_STB1/DVOC_CLK
U28
AD_STB1#/DVOC_CLK#
AA27
SB_STB/ZV_D4
AA28
SB_STB#/ZV_D3
AC28
ST0/ZV_D14
AC29
ST1/ZV_D13
AB27
ST2/ZV_D12
AB29
WBF#/ZV_D9
K24
AGP_RCOMP/DVOBC_RCOMP
J25
AGPREF
AC24
AGP_BUSY#
L23
VCCAGP_1
U24
VCCAGP_2
J26
VCCAGP_3
M26
VCCAGP_4
R26
VCCAGP_5
V26
VCCAGP_6
AA26
VCCAGP_7
AA23
VCCAGP_8
B
GMCH-M
AGP INTERFACE
VIDEO INTERFACE
DVOA_CLK#
DVOA_CLK
DVOA_D0
DVOA_D1
DVOA_D2
DVOA_D3
DVOA_D4
DVOA_D5
DVOA_D6
DVOA_D7
DVOA_D8
DVOA_D9
DVOA_D10
DVOA_D11
DVOA_HSYNC
DVOA_VSYNC
DVOA_BLANK#
DVOA_RCOMP
DVOA_INTR#
DVOA_CLKINT
DVOA_FLD/STL
DDC1_CLK
DDC1_DATA
I2C_CLK
I2C_DATA
DDC2_CLK
DDC2_DATA
RED
GREEN
BLUE
VSYNC
HSYNC
REFSET
RED#
GREEN#
BLUE#
DQ_A0
DQ_A1
DQ_A2
DQ_A3
DQ_A4
DQ_A5
DQ_A6
DQ_A7
DQ_B0
DQ_B1
DQ_B2
DQ_B3
DQ_B4
DQ_B5
DQ_B6
DQ_B7
RQ0
RQ1
RQ2
RQ3
RQ4
RQ5
RQ6
RQ7
CTM
CTM#
CFM
CFM#
CMD
SCK
RAM_REFA
RAM_REFB
GM_GCLK
GM_RCLK
DREF_CLK
C
SIO
C
AG24
AJ24
AJ22
AH22
AG22
AJ23
AH23
AG23
AE23
AE24
AJ25
AH25
AG25
AJ26
AF22
AF23
AD21
AC22
AE21
AD20
AE22
AE27
AD27
AD25
AC25
AE26
AD26
AF29
AG29
AH28
AE29
AD28
AJ27
AF28
AG28
AH27
AG17
AJ17
AG18
AJ18
AG19
AJ19
AG20
AJ20
AJ11
AH10
AJ10
AG10
AJ9
AG9
AJ8
AG8
AG11
AJ12
AG12
AH13
AG13
AJ13
AG14
AJ14
AH15
AJ15
AJ16
AH16
AH7
AF7
AJ7
AD14
AE14
AG6
AJ6
AC19
T113*PAD
T82 *PAD
T84 *PAD
T104*PAD
T114*PAD
T83 *PAD
T103*PAD
T134*PAD
T133*PAD
T81 *PAD
T102*PAD
T112*PAD
T80 *PAD
T130*PAD
T129*PAD
T136*PAD
T127*PAD
T110*PAD
T100*PAD
T132*PAD
T135*PAD
T79 *PAD
T128*PAD
T111*PAD
T101*PAD
T118*PAD
T88 *PAD
T117*PAD
T87 *PAD
T116*PAD
T86 *PAD
T115*PAD
T85 *PAD
T94 *PAD
T108*PAD
T95 *PAD
T123*PAD
T96 *PAD
T124*PAD
T97 *PAD
T125*PAD
T122*PAD
T93 *PAD
T121*PAD
T107*PAD
T120*PAD
T92 *PAD
T119*PAD
T91 *PAD
T106*PAD
T90 *PAD
T89 *PAD
T105*PAD
T109*PAD
T131*PAD
T98 *PAD
T126*PAD
T99 *PAD
CLK48_DREF
+1.5V
R4 2.2K
R245 54.9_1%
R6 100K
R7 100K
R5 100K
R26 4.7K
R29 4.7K
R211 4.7K
R218 4.7K
R200 4.7K
R37 4.7K
VAGPREF[18]
+1.8V
RAM_REF
D
PIPE# GFRAME#
GREQ#
C2_0529:
No-loading
+1.5V
GGNT# GIRDY#
SB_STB
AD_STBA GSTOP#
AD_STBB
Note: Pull-up close to GMCH.
+3V
C2_0529:
No-loading
+1.5V
C98 470P
R88
100_1%
1 2
VAGPREF
R87
100_1%
1 2
C100 470P
Place divider near the GMCH.
+1.5V
C1
4.7u/10V_0805
R83
82_1%
R82
82_1%
C506
0.1u_0402
C392
0.1u_0402
C488
82P
C528
0.1u_0402
@. One power pins put one bypass Cap.
R8
576_1%
R9
2K_1%
CLK48_DREF [3]
D
CLK48_DREF
R666
Ramp_0626: Change
*10K
R666, del C963
Size Document Number Rev
B
Date: Sheet of
Quanta Computer Inc.
GMCH-M (AGP)-3
E
+1.5V
R39
*8.2K
R40
*8.2K
R38
*8.2K
R48
*8.2K
R67
*8.2K
R60
*8.2K
WBF#
ST0
ST1
ST2
SB_STB#
AD_STBA#
AD_STBB#
C489
0.1u_0402
C482
82P
R52
*8.2K
R47
*8.2K
R49
*8.2K
R46
*8.2K
R53
*8.2K
R73
*8.2K
R63
*8.2K
R62
*8.2K
R64
*8.2K
R66
*8.2K
R65
*8.2K
R72
*8.2K
R242
*8.2K
PROJECT : RT2.0
E
C503
0.1u_0402
8 57Tuesday, September 11, 2001
GTRDY#
GDEVSEL#
RBF#
+1.5V
+1.5V
+1.5V
+1.5V
C537
0.1u_0402
1A
A
+1.2V_GMCH
4 4
THIS 68P PUT ON AE16 AND AE15
C547
3 3
+1.2V_GMCH
2 2
1 1
68P
C550
0.1u_0402
+1.5V
+1.2V_GMCH_H
C522
0.1u_0402
C507
0.1u_0402
+1.2V_GMCH
C553
0.1u_0402
A
+1.2V_GMCH
C502
0.1u_0402
C519
C554
82P
0.1u_0402
U17D
H7
VCC12_1
H23
VCC12_2
K7
VCC12_3
K23
VCC12_4
L7
VCC12_5
N6
VCC12_6
T6
VCC12_7
W7
VCC12_8
Y7
VCC12_9
AB7
VCC12_10
M24
VCC12_11
P24
VCC12_12
T24
VCC12_13
V24
VCC12_14
Y23
VCC12_15
M14
VCC12_16
M15
VCC12_17
M16
VCC12_18
P12
VCC12_19
R12
VCC12_20
T12
VCC12_21
P18
VCC12_22
R18
VCC12_23
T18
VCC12_24
V14
VDD_LM1
V15
VDD_LM2
V16
VDD_LM3
AE16 AE18
VDD_LM4 VCC_LM6
AE15
VDD_LM5
AD15
VDD_LM6
AD16
VDD_LM7
AE6
VCCA_HPLL
G7
VCCA_CPLL
F5
VCC_H0
J5
VCC_H1
M5
VCC_H2
R5
VCC_H3
V5
VCC_H4
AA5
VCC_H5
AD5
VCC_H6
AG5
VCC_H7
E2
VCC_H8
N24
VCCQ_AGP2
W23
VCCQ_AGP1
GMCH3-M
C480
C534
82P
0.1u_0402
C539
0.1u_0402
C457
0.1u_0402
C523
0.1u_0402
C508
82P
C518
82P
C505
0.1u_0402
GMCH-M
A3
C447
C446
0.1u_0402
0.1u_0402
C484
0.1u_0402
B
VCC_LM1
VCC_LM2
VCC_LM3
VCC_LM4
VCC_LM5
VCC_LM7
VCC_LM8
VCC_LM9
C556
0.1u_0402
AD23
AE25
D5
G10
D8
D11
G11
D14
A8
D17
E12
D20
D23
G23
D26
A12
G19
G20
F7
F15
E15
AC10
AC11
AD11
AD12
AD13
AD17
AD18
AD19
AE7
AF6
AC9
AC8
AF26
AG27
J24
F26
AF24
AF21
AC21
AC20
F25
C562
0.1u_0402
C513
82P
3VSUS
+1.8V
C476
0.1u_0402
10U/25V_1206
C166
VCCT
1 2
FBMJ2125HM330
C452
0.1u_0402
VCCT +1.2V_GMCH_H
1 2
FBMJ2125HM330
+1.5V
+1.5V 500mA
+1.2V_GMCH
C504
C471
0.1u_0402
82P
C450
0.1u_0402
VCC_GPIO1
VCC_GPIO2
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCCQ_SM1
VCCQ_SM2
VCCQ_SM3
VCCQ_SM4
VCCQ_SM5
VCC_CMOS1
VCC_CMOS2
VCC_CMOS3
VCC_CMOS4
VCCA_DAC0
VCCA_DAC1
VCC_HUB1
VCC_HUB2
VCC_DVO3
VCC_DVO2
VCC_DVO1
VCCA_DPLL0
VCCA_DPLL1
+1.2V_GMCH +1.8V
C
3VSUS
3VSUS
C621
C614
0.1u_0402
0.1u_0402
@. One power pins put one bypass Cap.
L92
C51
100U/6.3V_6032
L88
10U/25V_1206
C426
C477
0.1u_0402
@. One power pins put one bypass Cap.
+1.5V
C543
82P
C524
82P
C
C168
C558
0.1u_0402
C456
0.1u_0402
10U/25V_1206
B
C575
C576
0.1u_0402
0.1u_0402
C620
C613
0.1u_0402
82P
+1.2V_GMCH
12
C570
C580
C581
0.1u_0402
C617
0.1u_0402
C548
0.1u_0402
C514
0.1u_0402
0.1u_0402
C619
82P
C525
0.1u_0402
C122
82P
82P
C616
0.1u_0402
C470
4.7u/10V_0805
C531
0.1u_0402
+1.8V 250mA
C169
C445
10U/25V_1206
0.1u_0402
C569
82P
C638
0.1u_0402
C549
82P
C492
0.1u_0402
C459
C448
0.1u_0402
82P
C455
0.1u_0402
C478
0.1u_0402
C103
0.1u_0402
C449
0.1u_0402
C578
0.1u_0402
C577
0.1u_0402
C419
82P
C474
0.1u_0402
C579
82P
C479
82P
C127
0.1u_0402
C475
0.1u_0402
C458
82P
D
C618
0.1u_0402
C530
0.1u_0402
C496
0.1u_0402
C444
0.1u_0402
D
C37
82P
C2
0.1u_0402
E
GMCH-M
U17E
D2
VSS1
G2
VSS2
K2
VSS3
N2
VSS4
T2
VSS5
W2
VSS6
AB2
VSS7
AE2
VSS8
AH2
VSS9
B3
VSS10
E4
VSS11
H5
VSS12
L5
VSS13
P5
VSS14
U5
VSS15
Y5
VSS16
AC5
VSS17
AF5
VSS18
AJ5
VSS19
B6
VSS20
AH6
VSS21
E7
VSS22
AC7
VSS23
AG7
VSS24
AD8
VSS25
AE8
VSS26
AF8
C535
C491
0.1u_0402
0.1u_0402
C3
C591
0.1u_0402
82P
Size Document Number Rev
B
Date: Sheet of
VSS27
AH8
VSS28
B9
VSS29
G9
AD9
AE9
AF9
AH9
E10
AD10
AE10
AF10
AE11
AF11
AH11
B12
M12
N12
U12
V12
AE12
AF12
AH12
E13
M13
N13
P13
R13
T13
U13
V13
AE13
AF13
N14
P14
R14
T14
U14
AF14
A14
B13
C3
C21
E14
F19
GMCH3-M
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
G8
A3
VSSA_CPLL
AH26
PROJECT : RT2.0
Quanta Computer Inc.
GMCH-M (VCC,GND)-4
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSSA_DAC
VSSA_DPLL0
VSSA_DPLL1
VSSA_HPLL
AE20
G24
AD7
E
9 57Tuesday, September 11, 2001
AH14
B15
N15
P15
R15
T15
U15
AF15
AG15
E16
N16
P16
R16
T16
U16
AF16
AG16
M17
N17
P17
R17
T17
U17
V17
AE17
AF17
AH17
B18
M18
N18
U18
V18
AF18
AH18
E19
AE19
AF19
AH19
AF20
AH20
B21
G21
AG21
AH21
AJ21
E22
AD22
AB23
AC23
B24
AH24
E25
H25
L25
P25
U25
Y25
AF25
AC26
B27
AF27
D28
G28
K28
N28
T28
W28
AB28
AE28
1A
5
4
3
2
1
3VSUS 3VSUS
SODIMM0 SODIMM1
CON25
1
MD31
MD30
MD29
D D
C C
B B
MD[0..63][7]
MA[0..12][7]
SRASA#[7]
SCASA#[7]
BMWEA#[7]
CS0#[7]
CS1#[7]
CS2#[7]
CS3#[7]
DQM0[7]
DQM1[7]
DQM2[7]
DQM3[7]
DQM4[7]
DQM5[7]
DQM6[7]
DQM7[7]
CKE0[7]
CKE1[7]
CKE2[7]
CKE3[7]
CLK_SDRAM0[7]
CLK_SDRAM1[7]
CLK_SDRAM2[7]
CLK_SDRAM3[7]
RAM_SMCLK0[37]
RAM_SMCLK1[37]
RAM_SMDATA0[37]
RAM_SMDATA1[37]
MD[0..63]
MA[0..12]
SRASA#
SCASA#
BMWEA#
CS0#
CS1#
CS2#
CS3#
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
BS0[7]
BS1[7]
BS0
BS1
CKE0
CKE1
CKE2
CKE3
CLK_SDRAM0
CLK_SDRAM1
CLK_SDRAM2
CLK_SDRAM3
RAM_SMCLK0
RAM_SMCLK1
RAM_SMDATA0
RAM_SMDATA1
R357
R112
R387
*33
*33
12
12
C212
C737
*22P
*22P
R110
*33
*33
12
12
C197
C636
*22P
*22P
MD28
MD27
MD26
MD25
MD24
DQM3
DQM2
MA0
MA1
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
CLK_SDRAM0
SRASA#
BMWEA#
CS0#
CS1#
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MA6
MA8
MA9
MA10
DQM1
DQM0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
RAM_SMDATA0
VSS_1
3
DQ0
5
DQ1
7
DQ2
9
DQ3
11
VCC_1
13
DQ4
15
DQ5
17
DQ6
19
DQ7
21
VSS_2
23
CE0#
25
CE1#
27
VCC_2
29
A0
31
A1
33
A2
35
VSS_3
37
DQ8
39
DQ9
41
DQ10
43
DQ11
45
VCC_3
47
DQ12
49
DQ13
51
DQ14
53
DQ15
55
VSS_4
57
RESVD/DQ64
59
RESVD/DQ65
61
CLK0
63
VCC_4
65
RAS#
67
WE#
69
S0#
71
S1#
73
OE#
75
VSS_5
77
RESVD/DQ66
79
RESVD/DQ67
81
VCC_5
83
DQ16
85
DQ17
87
DQ18
89
DQ19
91
VSS_6
93
DQ20
95
DQ21
97
DQ22
99
DQ23
101
VCC_6
103
A6
105
A8
107
VSS_7
109
A9
111
A10
113
VCC_7
115
CE2#/RESVD
117
CE3#/RESVD
119
VSS_8
121
DQ24
123
DQ25
125
DQ26
127
DQ27
129
VCC_8
131
DQ28
133
DQ29
135
DQ30
137
DQ31
139
VSS_9
141
SDA
143
VCC_9
SODIMM_4.0
3VSUS
RESVD/DQ68
RESVD/DQ69
RESVD/DQ70
RESVD/DQ71
CE6#/RESVD
CE7#/RESVD
GND_PAD1
HOLE_1
HOLE_2
147
145
148
146
GND_PAD2
VSS_10
DQ32
DQ33
DQ34
DQ35
VCC_10
DQ36
DQ37
DQ38
DQ39
VSS_11
CE4#
CE5#
VCC_11
VSS_12
DQ40
DQ41
DQ42
DQ43
VCC_12
DQ44
DQ45
DQ46
DQ47
VSS_13
CKE0
VCC_14
CAS#
CKE1
CLK1
VSS_15
VCC_15
DQ48
DQ49
DQ50
DQ51
VSS_16
DQ52
DQ53
DQ54
DQ55
VCC_16
BA0
VSS_17
BA1
VCC_17
VSS_18
DQ56
DQ57
DQ58
DQ59
VCC_18
DQ60
DQ61
DQ62
DQ63
VSS_19
SCL
VCC_19
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
A3
32
A4
34
A5
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
A12
72
A13
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
A7
106
108
110
112
A11
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
DQM7
DQM6
MA3
MA4
MA5MA2
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
CKE0
SCASA#
CKE1
MA12
CLK_SDRAM1
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MA7
BS0
BS1
MA11
DQM5
DQM4
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
RAM_SMCLK0
R358
0
3VSUS 3VSUS
CON26
1
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
DQM3
DQM2
MA0
MA1
MA2
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
CLK_SDRAM2
SRASA#
BMWEA#
CS2#
CS3#
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MA6
MA8
MA9
MA10
DQM1
DQM0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
RAM_SMDATA1
VSS_1
3
DQ0
5
DQ1
7
DQ2
9
DQ3
11
VCC_1
13
DQ4
15
DQ5
17
DQ6
19
DQ7
21
VSS_2
23
CE0#
25
CE1#
27
VCC_2
29
A0
31
A1
33
A2
35
VSS_3
37
DQ8
39
DQ9
41
DQ10
43
DQ11
45
VCC_3
47
DQ12
49
DQ13
51
DQ14
53
DQ15
55
VSS_4
57
RESVD/DQ64
59
RESVD/DQ65
61
CLK0
63
VCC_4
65
RAS#
67
WE#
69
S0#
71
S1#
73
OE#
75
VSS_5
77
RESVD/DQ66
79
RESVD/DQ67
81
VCC_5
83
DQ16
85
DQ17
87
DQ18
89
DQ19
91
VSS_6
93
DQ20
95
DQ21
97
DQ22
99
DQ23
101
VCC_6
103
A6
105
A8
107
VSS_7
109
A9
111
A10
113
VCC_7
115
CE2#/RESVD
117
CE3#/RESVD
119
VSS_8
121
DQ24
123
DQ25
125
DQ26
127
DQ27
129
VCC_8
131
DQ28
133
DQ29
135
DQ30
137
DQ31
139
VSS_9
141
SDA
143
VCC_9
SODIMM_REV4.0
HOLE_1
HOLE_2
147
145
146
RESVD/DQ68
RESVD/DQ69
RESVD/DQ70
RESVD/DQ71
CE6#/RESVD
CE7#/RESVD
GND_PAD1
GND_PAD2
148
VSS_10
DQ32
DQ33
DQ34
DQ35
VCC_10
DQ36
DQ37
DQ38
DQ39
VSS_11
CE4#
CE5#
VCC_11
VSS_12
DQ40
DQ41
DQ42
DQ43
VCC_12
DQ44
DQ45
DQ46
DQ47
VSS_13
CKE0
VCC_14
CAS#
CKE1
A12
A13
CLK1
VSS_15
VCC_15
DQ48
DQ49
DQ50
DQ51
VSS_16
DQ52
DQ53
DQ54
DQ55
VCC_16
BA0
VSS_17
BA1
A11
VCC_17
VSS_18
DQ56
DQ57
DQ58
DQ59
VCC_18
DQ60
DQ61
DQ62
DQ63
VSS_19
SCL
VCC_19
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
A3
32
A4
34
A5
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
A7
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
DQM7
DQM6
MA3
MA4
MA5
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
CKE2
SCASA#
CKE3
MA12
CLK_SDRAM3
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MA7
BS0
BS1
MA11
DQM5
DQM4
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
RAM_SMCLK1
R113
0
C643
C637
C641
C631
C201
C640
C635
C198
C188
C193
C232
1000P
1000P
C195
C229
1000P
1000P
3VSUS
0.1u_0402
C740
0.1u_0402
0.1u_0402
C738
0.1u_0402
0.1u_0402
C227
0.1u_0402
0.1u_0402
C230
0.1u_0402
3
0.1u_0402
C228
0.1u_0402
0.1u_0402
C734
0.1u_0402
0.1u_0402
C206
0.1u_0402
0.1u_0402
C211
0.1u_0402
C642
C739
1000P
1000P
C629
C735
1000P
1000P
4
C632
C210
1000P
1000P
C634
C208
1000P
1000P
C205
1000P
1000P
C741
1000P
1000P
C190
1000P
A A
C215
1000P
5
C639
C199
0.1u_0402
C742
0.1u_0402
C200
0.1u_0402
C217
0.1u_0402
C633
0.1u_0402
C231
0.1u_0402
2
C628
0.1u_0402
C736
0.1u_0402
C196
0.1u_0402
C207
0.1u_0402
C194
0.1u_0402
C209
0.1u_0402
Quanta Computer Inc.
SDRAM,SODIMMx2
C630
0.1u_0402
C204
0.1u_0402
Size Document Number Rev
Custom
Date: Sheet of
C191
C192
0.1u_0402
C213
0.1u_0402
0.1u_0402
C216
0.1u_0402
C189
0.1u_0402
C214
0.1u_0402
PROJECT : RT2.0
1
10 57Tuesday, September 11, 2001
2A
1
NMI[4]
A20M#[4]
FERR#[4]
IGNNE#[4]
+3V
INTR[4]
CPUINIT#[4]
RC#[34]
KGA20[34]
R658
*10K
A A
C1_0328: Add but reserved.
B B
PCLK_ICH
R484
*68
AD[0..31][25,28,30,41,51]
PCIRST#[6,16,18,25,28,30,31,41,51]
PME#[25,28,30,41,51]
SERIRQ[28,31,41]
CLKRUN#[25,28,30,31,41,51]
C C
D D
PDDACK#[16]
PCLK_ICH[3]
PDD0[16]
PDD1[16]
PDD2[16]
PDD3[16]
PDD4[16]
PDD5[16]
PDD6[16]
PDD7[16]
PDD8[16]
PDD9[16]
PDD10[16]
PDD11[16]
PDD12[16]
PDD13[16]
PDD15[16]
PDCS1#[16]
PDCS3#[16]
PDA0[16]
PDA1[16]
PDA2[16]
PDIOR#[16]
PDIOW#[16]
PIORDY[16]
IRQ14[16]
PDDREQ[16]
1
C827
*15P
2
PME#
SERIRQ
CLKRUN#
PCLK_ICH
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDCS1#
PDCS3#
PDA0
PDA1
PDA2
PDIOR#
PDIOW#
PIORDY
IRQ14
PDDREQ
PDDACK#
2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AA21
AA23
AB23
H22
AC2
W12
AB11
AA10
AC10
W11
AB9
AA9
AC9
AB10
AC11
AA11
AC12
AC15
AB15
AA14
AC14
AA15
AC13
AB13
AB14
AB12
ICH3_F
Y21
V23
U22
Y22
Y10
Y11
Y12
Y13
U67A
NMI
A20M#
J22
FERR#
IGNNE#
INTR
INIT#
RCIN#
A20GATE
J2
AD0
K1
AD1
J4
AD2
K3
AD3
H5
AD4
K4
AD5
H3
AD6
L1
AD7
L2
AD8
G2
AD9
L4
AD10
H4
AD11
M4
AD12
J3
AD13
M5
AD14
J1
AD15
F5
AD16
N2
AD17
G4
AD18
P2
AD19
G1
AD20
P1
AD21
F2
AD22
P3
AD23
F3
AD24
R1
AD25
E2
AD26
N4
AD27
D1
AD28
P4
AD29
E1
AD30
P5
AD31
Y1
PCIRST#
W1
PME#
SERIRQ
CLKRUN#/GPIO24
T5
PCICLK
PDD0
PDD1
PDD2
PDD3
PDD4
Y9
PDD5
PDD6
PDD7
PDD8
PDD9
W9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDCS1#
PDCS3#
PDA0
PDA1
PDA2
PDIOR#
PDIOW#
PIORDY
IRQ14
PDDREQ
PDDACK#
3
3
ICH HUB
CPU
CPU_SLP#
PCI
GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#
GPIO0/REQA#
GPIO1/REQB#/REQ5#
GPIO16/GNTA#
GPIO17/GNTB#/GNT5#
IDE
APICD0
APICD1
APICCLK
SMI#
STPCLK#
DPSLP#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
SERR#
PERR#
PLOCK#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDCS1#
SDCS3#
SDA0
SDA1
SDA2
SDIOR#
SDIOW#
SIORDY
IRQ15
SDDREQ
SDDACK#
4
J20
J21
J19
Y23
U23
W21
AB22
K2
K5
N1
R2
F1
N3
H1
M3
H2
G5
L5
M2
M1
D3
F4
A3
R4
E4
A4
E3
D2
D5
B4
B1
C1
B2
A2
A6
B5
C5
A5
C4
D4
B6
B3
Y17
W17
AC17
AB16
W16
Y14
AA13
W15
W13
Y16
Y15
AC16
AB17
AA17
Y18
AC18
AC21
AC22
AC20
AA19
AB20
AC19
AA18
AB19
W19
AB18
Y19
4
REQA#
REQB#
GNTA#
GNTB#
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDCS1#
SDCS3#
SDA0
SDA1
SDA2
SDIOR#
SDIOW#
SIORDY
IRQ15
SDDREQ
SDDACK#
R510
10K
10K
R657
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
SERR#
PERR#
PLOCK#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#
PIRQE#
*PAD
T65
PAR
REQA# [41]
REQB# [28]
GNTA# [41]
GNTB# [28]
SDD0 [17]
SDD1 [17]
SDD2 [17]
SDD3 [17]
SDD4 [17]
SDD5 [17]
SDD6 [17]
SDD7 [17]
SDD8 [17]
SDD9 [17]
SDD10 [17]
SDD11 [17]
SDD12 [17]
SDD13 [17]
SDD14 [17]PDD14[16]
SDD15 [17]
SDCS1# [17]
SDCS3# [17]
SDA0 [17]
SDA1 [17]
SDA2 [17]
SDIOR# [17]
SDIOW# [17]
SIORDY [17]
IRQ15 [17]
SDDREQ [17]
SDDACK# [17]
5
C1_0328: Modify
SMI# [4]
STPCLK# [4]
H_DPSLP# [4,47]
C/BE0# [25,28,30,41,51]
C/BE1# [25,28,30,41,51]
C/BE2# [25,28,30,41,51]
C/BE3# [25,28,30,41,51]
FRAME# [25,28,30,41,51]
IRDY# [25,28,30,41,51]
TRDY# [25,28,30,41,51]
DEVSEL# [25,28,30,41,51]
STOP# [25,28,30,41,51]
SERR# [28,30,41,51]
PERR# [28,30,41,51]
PLOCK# [41]
REQ0# [41]
REQ1# [30]
REQ2# [28]
REQ3# [25]
REQ4# [51]
GNT0# [41]
GNT1# [30]
GNT2# [28]
GNT3# [25]
GNT4# [51]
PIRQA# [28,41]
PIRQB# [18,30,41,51]
PIRQC# [25,41]
PIRQD# [30,41,51]
5
for A0 version must be pull low 100 Ohm.
+3V +3V
R553
100K
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#
REQA# GNTA#
REQB# GNTB#
SERIRQ TI1420
6
R511*100
+3V
R533
100K
ES1988
ES1988
PC87393FSERIRQ
6
PAR [25,28,30,41,51]
R534
100K
IDE_ID0 [17]
IDE_ID1 [17]
IDE_ID2 [17]
AD21Device ID
TI1420
TI1420
TI1420
---
GNTA#
+3V
+3V
+3V
7
REQ0#
REQ1#
REQ2#
REQ3#
STOP#
TRDY#
FRAME#
IRDY#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
SERIRQ
PME#
PIRQE#
CLKRUN#
REQA#
REQB#
GNTB#
PCI Pullups
RP39
1
2
3
4
5
10P8R_8.2K
RP36
1
2
3
4
5
10P8R_8.2K
R452 10K
R552 8.2K
R532 8.2K
R554 100K
R531 100KR569 *1K
RP41
1
2
3
4
5
10P8R_8.2K
R512 8.2K
R467 10K
R535 10K
8
10
9
8
7
6
10
9
8
7
6
10
9
8
7
6
AD18AD20---AD19
DOCKING
ATI P6
DOCKING
MINI PCI 1
MINI PCI 2
DOCKING
DOCKING
MINI PCI 1
MINI PCI 2
DOCKING
MINI PCI 1
MINI PCI 2
DOCKING
DOCKING
Size Document Number Rev
B
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
ICH3-M (CPU,PCI,IDE)-1
7
11 57Tuesday, September 11, 2001
8
+3V
GNT0#
GNT1#
GNT2#
GNT3#
+3V
SERR#
DEVSEL#
PERR#
PLOCK#
+3V
+3V
+3V
+3V
+3V
+3V
REQ4#
GNT4#
IRQ14
IRQ15
+3V
3V_S5
+3V
3A
1
D34
3V_S5
A A
2 1
RB500
D_3VRTC RTCRST#
D37
RB500
2 1
R600
1K
RTC_N02
12
BT2
BAT3V
VCCRTC
R579
1K
R580 8.2K
C2_0425:
Change
size
R_3VRTC
1 3
BATT_AHL03014003(ML1220)
BATT_CONN_DFHS02FS021
B B
3V_S5
-RSMRST
C1_0402: Add
for RTC
C948
5
U84
VCC
3
YA
B
6
ORGND
GND
NC7SZ58
2
1
RVCC_ON[34,44,49]
leakage.Cover
page3 item
29(0328).
CLK66_ICHHUB
C C
CLK48_USB
C2_0423: Add
14M_ICH
R515
R475
*68
*22
C817
*5P
12
C836
*15P
C2_0423:
Change value
R667
C964
*33
*10P
DEL USB PULL LOW
1.5K
D D
R559-R564,
R541-R546
1
C874
0.047u_0402
Q94
2
MBT3904
0.1u_0402
4
2
3
@. G1 put in the SODIMM area.
12
C867
2.2u_1206
RTC_N01
G2
*SHORT PAD
C2_0425: Move
& close U67
R609
10M
5VPCU
R592
2.2K
CLK_32KX1
VBIAS
R593
4.7K
R594
15K
HL[0..10][6]
RTC
R651
22K
AC_shut bit set
to 1
D24
1SS355
AC_SDOUT
PCSPK
SMLINK0
SMLINK1
EE_DOUT
THRM#
AGP_BUSY#
RI#
KBSMI#
DNBSWON#
BATLOW#
PWROK
C1_0323: Add
for RTC
leakage.
USBOC0#
USBOC1#
USBOC2#
USBOC3#
USBOC4#
USBOC5#
2
RSMRST#
3V_S5
21
C791
R528 *10K
R514 *1K
R453 0
R443 0
R571 *1K
R428 10K
R474 10K
R442 10K
R466 8.2K
R451 10K
R429 10K
R652 22K
R558 10K
R540 10K
R557 10K
R539 10K
R556 10K
R537 10K
R446
100K
-RSMRST
0.1u_X7R
C2_0509:
Change
pwr
3V_S5
3V_S5
ICH_SMDATA[3,37]
RSMRST#
+3V
+3V
+3V
+3V
3V_S5
3V_S5
3V_S5
3V_S5
3VSUS
3
T210 *PAD
T212 *PAD
R454 10K
R445 10K
ICH_SMCLK[3,37]
RST_CDROM#[17]
CLK66_ICHHUB[3]
PM_DPRSLPVR[45,47]
PWRGD_CPU[4]
PM_GMUXSEL[45,47]
PM_VGATE[47]
AC_VID0[45]
AC_VID1[45]
AC_VID2[45]
AC_VID3[45]
AC_VID4[45]
USBOC0#[14,41]
USBP2+[30]
USBP2-[30]
USBOC2#
CLK48_USB[3]
HL[0..10]
HLSTRB[6]
HLSTRB#[6]
LAD0/FWH0[31]
LAD1/FWH1[31]
LAD2/FWH2[31]
LAD3/FWH3[31]
T74 *PAD
T76 *PAD
PWROK[34]
DNBSWON#[34]
AGP_BUSY#[8,18]
BATLOW#[34]
STP_AGP#[18]
14M_ICH[3]
PCSPK[39]
KBSMI#[31,34]
CPUPERF#[5]
EE_CLK[15]
EE_DOUT[15]
EE_DIN[15]
EE_CS[15]
R536
10K
RI#[38]
ICH_SMCLK
ICH_SMDATA
R538
10K
4
USBP0+
USBP0ÂUSBOC0#
USBP2+
USBP2ÂUSBOC2#
USBP4+
USBP4ÂUSBOC4#
CLK48_USB
CLK66_ICHHUB
AC_BITCLK
AC_SDIN0
AC_SDIN1
AC_SDOUT
PWROK
DNBSWON#
RI#
THRM#
AGP_BUSY#
BATLOW#
SMLINK0
SMLINK1
PCSPK
T66 *PAD
KBSMI#
EE_DOUT
AC_BITCLK
AC_SDIN1
AC_SDIN0
R555
10K
4
H20
G22
F21
G19
E22
E21
D19
D18
E12
E17
E16
C12
D15
D14
A12
F20
HL0
HL1
HL2
HL3
HL4
HL5
L22
M21
M23
N20
P21
R22
N22
P23
T19
V1
U3
T3
U2
D11
A7
B7
B11
C11
C7
AC4
AB5
AA6
AB1
AA7
AA1
U5
V4
AB3
V5
AB21
J23
AC3
AB2
H23
V2
W2
Y20
W23
U20
V19
D10
E8
D8
E9
HUBVSWING = 0.5 *
VCC1_8
Place divider in the middle of
the bus
ICH HUB
U67B
USB_LEDA0#/GPIO32
USB_LEDA1#/GPIO33
USB_LEDA2#/GPIO34
USB_LEDA3#/GPIO35
USB_LEDA4#/GPIO36
USB_LEDA5#/GPIO37
USBP0P
USBP0N
OC0#
USBP2P
USBP2N
OC2#
USBP4P
USBP4N
OC4#
CLK48
HI0
HI1
HI2
HI3
HI4
HI5
HL_STB
HL_STB#
HI_CLK
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
AC_RST#
AC_SYNC
AC_BITCLK
AC_SDIN0
AC_SDIN1
AC_SDOUT
SMBCLK
SMBDATA
PWROK
PWRBTN#
RSMRST#
RI#
THRM#
GPIO6/AGPBUSY#
BATLOW#
C3_STAT#/GPIO21
DPRSLPVR
CLK14
SMLINK0
SMLINK1
SPKR
GPIO7
GPIO8
CPUPERF#/GPIO22
CPUPWRGD
SSMUXSEL/GPIO23
VGATE
EE_SHCLK
EE_DOUT
EE_DIN
EE_CS
AC97&RTC
MISC&GPIO
ICH3_F
5
USB_LEDG0#/GPIO38
USB_LEDG1#/GPIO39
USB_LEDG2#/GPIO40
USB_LEDG3#/GPIO41
USB_LEDG4#/GPIO42
USB_LEDG5#/GPIO43
USB
HUB LINK
LFRAME#/FWH4
LPC&FWH
SMBALERT#/GPIO11
SM
SLP_S1#/GPIO19
PM
STP_PCI#/GPIO18
SpeedStep
LAN
+1.8V
R498
301_1%
R504
301_1%
5
USBP1P
USBP1N
OC1#
USBP3P
USBP3N
OC3#
USBP5P
USBP5N
OC5#
USBRBIAS
HI10
HI_PAR
HICOMP
HI_REF
HI_VSWING
LDRQ0#
LDRQ1#
VCCRTC
VBIAS
RTCX1
RTCX2
RTCRST#
INTRUDER#
SLP_S3#
SLP_S5#
SUSCLK
SUSSTAT#
STP_CPU#
GPIO12
GPIO13
GPIO25
GPIO27
GPIO28
LAN_CLK
LAN_PWROK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
C828
*470P
HUBVSWING_CV
C820
0.1u_0402
HUBVSWING_CG
HI6
HI7
HI8
HI9
6
H21
G23
F23
G21
D23
E23
A19
A18
D12
B17
B16
B12
A15
A14
A11
R547 18.2_1%
B21
R20
T23
M19
P19
N19
R19
ICH_RCOMP
K19
L20
L19
R479 10K
U1
T2
R427 10K
U4
AB6
AB7
AC7
AC6
Y7
Y6
AC5
W20
AA5
AA2
AA4
AB4
V21
U21
Y4
Y2
W3
W4
Y3
C9
Y5
D7
C8
A8
A9
B9
C10
A10
R488
*56.2_1%
R485
0
6
USBP1+
USBP1ÂUSBOC1#
USBP3+
USBP3-
USBOC3#
USBP5+
USBP5-
USBOC5#
HL6
HL7
HL8
HL9
HL10
HUBVSWING
VBIAS
CLK_32KX1
CLK_32KX2
RTCRST#
R455 22K
R430 100K
SUSCLK_ICH
HUBVSWING
Ramp_0620: Change
for B0 stepping
QB62
HL[0..10]
*PAD
T70
R508 36.5_1%
+3V
LPC_DRQ0#
+3V
VCCRTC
3V_S5
R461 10K
-SCI_1
-SWI_1
3V_S5
*PAD
T64
*PAD
T62
C2_0518: For leakage
C819
0.01u
Size Document Number Rev
Custom
Date: Sheet of
7
0322: Del
GPIO41-42
3MODE# [17,32]
SPKOFF [39]
DISP_ON [22]
*PAD
T214
*PAD
T215
RST_HDD# [16]
USBP1+ [14,41]USBP0+[14,41]
USBP1- [14,41]USBP0-[14,41]
USBOC1# [14,41]
LFRAME#/FWH4 [31]
LPC_DRQ0# [31]
SUSA# [3,18,25]
SUSB# [34]
SUSC# [34]
LPC_PD# [31]
CPU_STP# [3]
PCI_STP# [3]
D27 1SS355
DRAMENA [37]
LAN_CLK [15]
PM_LANPWORK [15,35]
LAN_SYNC [15]
LAN_RXD0 [15]
LAN_RXD1 [15]
LAN_RXD2 [15]
LAN_TXD0 [15]
LAN_TXD1 [15]
LAN_TXD2 [15]
SUSCLK_ICH
CLK_32KX1
CLK_32KX2
T208*PAD
T209*PAD
T211*PAD
T213*PAD
VHUBREF
L122
BK1608HS241-T
C795
0.1u_0402
For RTC leakage
R444 10K
D26 1SS355
2 1
2 1
HDDVCC_EN [16]
CDVCC_EN [17]
3.3VAUX
2
1
PROJECT : RT2.0
Quanta Computer Inc.
ICH3-M (USB,HUB,LPC)-2
7
8
EPSON MC-306 (12.5pF 10PPM)
R456
10M
32.768KHz/10ppm_RTC
Y6
14
C797
12
15P
23
C796
12
15P
Ramp_0620: Change
VHUBREF [6]
C834
0.1u_0402
VCCRTC
C789
1u/6.3V_0603
Add for EMI
3V_S5
-SCI [34]
-SWI [34]
0322: Add
C977
0.1u_0402
5
4
12 57Tuesday, September 11, 2001
8
SUSCLK [28,29]
3
U87
NC7SZ32 (P5X)
3A
1
2
3
4
5
6
7
8
ICH3
GND
NC1
NC2
NC3
E7
T21D6T1
K22
VSS051
K23
VSS052
L3
VSS053
L10
VSS054
L11
VSS055
L12
VSS056
L13
VSS057
L14
VSS058
L21
VSS059
L23
VSS060
M11
VSS061
M12
VSS062
M13
VSS063
M20
VSS064
M22
VSS065
N5
VSS066
N10
VSS067
N11
VSS068
N12
VSS069
N13
VSS070
N14
VSS071
N21
VSS072
N23
VSS073
P11
VSS074
P13
VSS075
P20
VSS076
P22
VSS077
R3
VSS078
R5
VSS079
R21
VSS080
R23
VSS081
T4
VSS082
T20
VSS083
T22
VSS084
V3
VSS085
V20
VSS087
W6
VSS088
W7
VSS089
W10
VSS090
W14
VSS091
W18
VSS092
W22
VSS093
Y8
VSS094
AA3
VSS095
AA8
VSS096
AA12
VSS097
AA16
VSS098
AA20
VSS099
AA22
VSS100
AB8
VSS101
AC1
VSS102
AC8
VSS103
AC23
VSS104
F19
NC4
NC5
C2
VSS105
VSS106
VSS107
A21
A22
A13
A16
A17
A20
A23
B10
B13
B14
B15
B18
B19
B20
B22
C14
C15
C16
C17
C18
C19
C20
C21
C22
D13
D16
D17
D20
D21
D22
E14
E15
E18
E19
E20
G20
H19
K11
K13
K20
K21
U67D
A1
VSS001
VSS002
VSS003
VSS004
VSS005
VSS006
B8
VSS007
VSS008
VSS009
VSS010
VSS011
VSS012
VSS013
VSS014
VSS015
C3
VSS016
C6
VSS017
VSS019
VSS020
VSS021
VSS022
VSS023
VSS024
VSS025
VSS026
VSS027
D9
VSS028
VSS029
VSS030
VSS031
VSS032
VSS033
VSS034
E5
VSS035
VSS036
VSS037
VSS038
VSS039
VSS040
F22
VSS041
G3
VSS042
VSS043
VSS044
J5
VSS046
VSS047
VSS048
VSS049
VSS050
ICH3_F
R432
+1.5V
C294
0.1u_0402
1K
D25
RB500
R549
0_0805
21
+1.5V 45mA
C306
0.1u_0402
+1.8V_ICH3_LAN1
12
R548
0_0805
+3V_ICH3_LAN3
12
+1.8V
A A
+3V
B B
+1.8V
C838
4.7u/10V_0805
0.1u_0402
U67C
E11
VCC1_8_1
J18
VCC1_8_2
K6
VCC1_8_3
K18
VCC1_8_4
M14
VCC1_8_5
P6
VCC1_8_6
P18
VCC1_8_7
R18
VCC1_8_8
T18
VCC1_8_9
U19
VCC1_8_10
V10
VCC1_8_11
V14
VCC1_8_12
F6
VCC3_3_1
G6
VCC3_3_2
G18
VCC3_3_3
H6
VCC3_3_4
H18
VCC3_3_5
J6
VCC3_3_6
M10
VCC3_3_7
P12
VCC3_3_8
R6
VCC3_3_9
T6
VCC3_3_10
U6
VCC3_3_11
V15
VCC3_3_12
V16
VCC3_3_13
V17
VCC3_3_14
V18
VCC3_3_15
ICH3_F
+1.8V 500mA
0.1u_0402
C310
0.1u_0402
C314
0.1u_0402
C316
0.1u_0402
C287
VCC
C307
0.1u_0402
VCC5REF_SUS1
VCC5REF_SUS2
0.1u_0402
C301
VCC5REF1
VCC5REF2
VCCCPU_IO1
VCCCPU_IO2
VCCCPU_IO3
VCCLAN1_8_1
VCCLAN1_8_2
VCCLAN1_8_3
VCCLAN3_3_1
VCCLAN3_3_2
VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6
VCCSUS1_8_1
VCCSUS1_8_2
VCCSUS1_8_3
VCCSUS1_8_4
VCCSUS1_8_5
VCCSUS1_8_6
VCCSUS1_8_7
VCCSUS1_8_8
VCCSUS1_8_9
VCCSUS1_8_10
0.1u_0402
C313
C317
0.1u_0402
C324
0.1u_0402
E6
W8
C13
W5
P14
U18
V22
F7
F8
K10
F9
F10
E10
F17
F18
K14
V8
V9
B23
C23
E13
F14
F15
F16
K12
P10
V6
V7
0.1u_0402
C344
C318
3V_S5
+1.5V
+1.8V_ICH3_LAN1
+3V_ICH3_LAN3
3V_S5
1.8V_S5
C311
0.1u_0402
5VREF_RUN
C333
0.1u_0402
C304
0.1u_0402
C850
4.7u/10V_0805
1.8VAUX
3.3VAUX
ICH3
B2: Change
size from
+5V
0805 to 0603
+3V
C816
0.1u_0402
C320
C849
4.7u/10V_0805
0.1u_0402
C337
C851
4.7u/10V_0805
0.1u_0402
C334
0.1u_0402
C336
0.1u_0402
C335
0.1u_0402
@. One power pins put one bypass Cap.
C C
+3V
C308
C319
C833
4.7u/10V_0805
0.1u_0402
C312
0.1u_0402
C315
C300
C303
0.1u_0402
0.1u_0402 T68 *PAD
0.1u_0402
0.1u_0402
C305
0.1u_0402
C302
0.1u_0402
C291
0.1u_0402
C292
0.1u_0402
C293
0.1u_0402
C326
0.1u_0402
C325
0.1u_0402
C330
0.1u_0402
C329
0.1u_0402
3V_S5
1.8V_S5
C840
4.7u/10V_0805
C805
4.7u/10V_0805
C342
0.1u_0402
C338
0.1u_0402
C296
0.1u_0402
C328
0.1u_0402
C299
0.1u_0402
C341
0.1u_0402
C290
0.1u_0402
C339
0.1u_0402
C327
0.1u_0402
C323
0.1u_0402
C322
0.1u_0402
C340
0.1u_0402
C289
0.1u_0402
C297
0.1u_0402
C298
0.1u_0402
C321
0.1u_0402
C309
0.1u_0402
T75 *PAD
T67 *PAD
T73 *PAD
T72 *PAD
C288
0.1u_0402
@. One power pins put one bypass Cap.
@. One power pins put one bypass Cap.
D D
Size Document Number Rev
Custom
1
2
3
4
5
6
Date: Sheet of
7
PROJECT : RT2.0
Quanta Computer Inc.
ICH3-M (POWER&GND)-3
13 57Tuesday, September 11, 2001
8
2B
1
5VSUS
A A
B B
FBMJ2125HM330
L85
2
M893VCC_0 M893VDD_0
C416
0.1u_0402
USBOC0#[12,41]
-USBPWRON0[35]
3
U4
1
IN
2
IN
8
F#
4
GND
MAX890
USBP0-[12,41]
USBP0+[12,41]
OUT
OUT
ON#
SET
4
6
7
3
5
R640 1K
BK1608HS600
L46
L55
BK1608HS600
C2_0529: No-loading
5
12
USBLP0-
USBLP0+
L87
FBMJ2125HM330
C423
100U/6.3V_6032
C366
*15P
C391
C386
*47P
*47P
6
USBPOWER_0
C431
0.1u_0402
7
C2_0529:
No-loading
Ramp_0620: Change
0_0805
R20
USBPOWER_1
USBLP1ÂUSBLP1+
1
2
3
4
CON6
PORT1-VCC
PORT1-DÂPORT1-D+
PORT1-GND
8
910
GND_1GND_2
USB CONNECTOR
USBPOWER_0
5VSUS
C C
FBMJ2125HM330
L84
M893VCC_1
C413
0.1u_0402
USBOC1#[12,41]
-USBPWRON1[35]
USBP1-[12,41]
USBP1+[12,41]
1
2
8
4
U3
IN
IN
F#
GND
MAX890
6
OUT
7
OUT
3
ON#
5
SET
L79 BK1608HS600
L83 BK1608HS600
M893VDD_1
R641 1K
L86
FBMJ2125HM330
12
C422
100U/6.3V_6032
C415
*15P
USBPOWER_1
C432
0.1u_0402
USBLP1ÂUSBLP1+
USBLP0ÂUSBLP0+
5
PORT0-VCC
6
PORT0-D-
7
PORT0-D+
8
PORT0-GND
USB_CONN.
0_0805
R17
C429
C421
*47P
*47P
Size Document Number Rev
A
Date: Sheet of
USBLP0+
D D
1
2
2
4
1
3
U1
C
D
GND1
GND2
SN75240
A
B
GND3
GND4
3
USBLP1+
8
USBLP1-USBLP0-
6
5
7
4
5
C2_0529: No-loading
PROJECT : RT2.0
Quanta Computer Inc.
USBx2
6
7
2A
14 57Tuesday, September 11, 2001
8
1
2
3
4
5
6
7
8
C2_0507: Del
LAN PHY
A A
U57
LAN_CLK
LAN_SYNC
LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_RXD2
LAN_RXD1
LAN_RXD0
T57 *PAD
LAN
T56 *PAD
R412 549_1%
R408 619_1%
R382
10K
3.3VAUX
LAN_CLK
LAN_SYNC
LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_RXD2
LAN_RXD1
LAN_RXD0
3.3VAUX
2
R381
47K
3
Q69
2N7002E
LAN_CLK[12]
LAN_SYNC[12]
LAN_TXD2[12]
LAN_TXD1[12]
B B
LAN_TXD0[12]
LAN_RXD2[12]
LAN_RXD1[12]
LAN_RXD0[12]
PM_LANPWORK[12,35]
A4
JCLK
B3
JRSTSYNC
B1
JTXD2
B2
JTXD1
A2
JTXD0
A5
JRXD2
A6
JRXD1
B6
JRXD0
A3
ADV10
B8
ISOL_TCK
C8
ISOL_T1
C7
ISOL_EX
D7
TOUT
E8
TESTEN
C3
VSS_1
C6
VSS_2
D3
VSS_3
D4
VSS_4
D5
VSS_5
D6
VSS_6
E3
VSS_7
E4
VSS_8
E5
VSS_9
E6
VSS_10
F3
VSS_11
F4
VSS_12
F5
VSS_13
F6
VSS_14
C4
VSSP_1
C5
VSSP_2
G2
VSSA_1
H2
VSSA_2
D1
VSSA2_1
E1
VSSA2_2
G7
VSSR_1
H7
VSSR_2
12
F2
RBIAS10
12
F1
RBIAS100
82562EP
uBGA 8X8, 64P
1
R397
BK2125HM121
4.7u/10V_0805
L99
1 2
FBMJ2125HM330
4.7u/10V_0805
4
+3V562ET
C760
+3V_LAN
C718
C C
U70
EE_DOUT[12] EE_DIN [12]
EE_CS[12]
EE_CLK[12]
3
1
2
DI
CS
SK
AT93C46
ORG
VCC
GND
4
DO
7
NC
R570 10K
6
8
5
3.3VAUX
C855
0.1u_0402
C2_0510: Change
3.3VAUX
3.3VAUX
C2_0529: Add
2'nd source: Fairchild FM93C46LM8X
AKE2EGA0E08
D D
1
2
3
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCCP_1
VCCP_2
VCCA_1
VCCA_2
VCCA2_1
VCCA2_2
VCCT_1
VCCT_2
VCCT_3
VCCT_4
VCCR_1
VCCR_2
ACTLED
SPDLED
LILED
C743
0.1u_0402
0.1u_0402
C724
TDP
TDN
RDP
RDN
X2
X1
0.1u_0402
G3
H3
H6
G6
A8
E7
A1
F7
F8
B4
B5
G1
H1
D2
E2
G4
G5
H4
H5
G8
H8
A7
B7
D8
C1
C2
C746
0.1u_0402
C722
0.1u_0402
C751
2nd Source ATP119: DB0TM7LAN22
1 2
1 2
+3V562ET
Pulse H0029 (Same as H0022, but lower cost)
LAN_XMT+_NB
R396
100_1%
R385
124_1%
LAN_XMT-_NB
C745
LAN_RCV+_NB
LAN_RCV-_NB
C730 0.01u
*0.1u
U59
7
TD+
8
TD-
6
CT4
1
RD+
2
RD-
3
CT1
H0029
TX+
TX-
CT3
RX+
RX-
CT2
C2_0507:
Change
10
9
11
16
15
14
Ramp_0620: Change
+3V_LAN
GND_LAN_TERM
LAN_ACTLED#
LAN_SPDLED#
LAN_LILED#
CLK_LAN_X2
CLK_LAN_X1
C776
22P
0.1u_0402
C754
+3V_LAN
12
0.1u_0402
C885
1 2
25MHz
C886
Y4
0.1u_0402
C887
GND_LAN_TERM
C969
1000P_1206_2KV
Add Y4 2nd Source :
BG625000508
12
C777
(FA-365,20pF,50ppm)
22P
C889
C888
GND_LAN_CHASIS
LAN_T+_D[41]
LAN_T-_D[41]
LAN_R+_D[41]
LAN_R-_D[41]
Watch out Pin 1
assignment in
0.1u_0402
C2_0516: Add
5
0.1u_0402
0.1u_0402
1 2
1 2
R674
R675
R376
GND_LAN_CHASIS
6
Layout
C972
0.1u/50V_0805
C973
0.1u/50V_0805
0_0805
C2_0509: Add
0_0805
0_0805
LAN_XMT+
LAN_XMT-
TXOC
R388 75_1%
LAN_RCV+
LAN_RCV-
RXIC
R386
75_1%
change in pin6 and 9,
pin 10 and 11 for pin
swap
R377 470
LAN_ACTLED#
1 2
R384 75_1%
75_1%
1 2
R390
C757
*1000P_1206_2KV
Ramp_0620
Size Document Number Rev
Custom
Date: Sheet of
7
Ramp_0620:
C967-969,C757: foot print is
compatible with 1206 & 1808
C967
GND_LAN_CHASIS
*1000P_1206_2KV
GND_LAN_TERM
C968
GND_LAN_CHASIS
GND_LAN_TERM
10
11
12
13
14
GND_LAN_CHASIS
CON29
1
2
3
4
53261-0410
LAN_SPDLED#
R378 470
LAN_RCV+
LAN_RCV-
LAN_1_2
LAN_1_1
LAN_XMT+
LAN_XMT-
C2_0507:
Del
L101-L104
LAN_T+_D
LAN_T-_D
LAN_R+_D
LAN_R-_D
1000P_1206_2KV
LAN_LILED#
LAN_ACTLED#_1
DFHD04MR400
14
PROJECT : RT2.0
Quanta Computer Inc.
LAN interface
GND_LAN_CHASIS
CON23
LAN_CONN.
1
LED_YEL_N
2
LED_YEL_P
3
LED_GRN_N
4
LED_GRN_P
5
NC
6
RD+
7
RD-
8
T4
9
T3
CHASIS_GND
T2
T1
TX+
TX-
C2_0510: Change
15 57Tuesday, September 11, 2001
8
GND_1 GND_2
15 16
3A
5
PDD7[11]
PDD6[11]
PDD5[11]
PDD4[11]
E E
D D
PDDREQ[11]
PDIOW#[11]
C C
B B
PDIOR#[11]
PIORDY[11]
-HDDLED[36]
PDD3[11]
PDD2[11]
PDD1[11]
PDD0[11]
PDA2[11]
PDA1[11]
IRQ14[11]
PDDACK#[11]
PDD8[11]
PDD9[11]
PDD10[11]
PDD11[11]
PDD15[11]
PDD14[11]
PDD13[11]
PDD12[11]
PDA0[11]
PDCS3#[11]
PDCS1#[11]
PDDREQ
PDIOW#
PDIOR#
PIORDY
RP34
RP37
RP42
RP11
RP12
RP43
R155 33
R156 33
R157 33
R160 33
RST_HDD#[12]
PCIRST#[6,11,18,25,28,30,31,41,51]
6
4
2
6
4
2
6
4
2
1
3
5
7 8
2
4
6
7 8
5
3
1
1 2
1 2
1 2
1 2
8P4R_33
8P4R_33
8P4R_33
8P4R_33
8P4R_33
8P4R_33
+3V
1
2
78
5
3
1
78
5
3
1
78
5
3
1
2
4
6
1
3
5
78
6
4
2
R_PDDREQ
-R_PDIOW
-R_PDIOR
R_PIORDY
5
3
4
IDEPD7
IDEPD6
IDEPD5
IDEPD4
IDEPD3
IDEPD2
IDEPD1
IDEPD0
R_PDA2
R_PDA1
R_IRQ14
-R_PDDACK
IDEPD8
IDEPD9
IDEPD10
IDEPD11
IDEPD15
IDEPD14
IDEPD13
IDEPD12
R_PDA0
-R_PDCS3
-R_PDCS1
-HDDLED
C942
0.1u_0402
4
U83
TC7SH00FU
2
Q113
DTC144EU
3
Change
pullup
power
plane
R_PIORDY
PDDREQ
PDD7
R161 1K
R154 5.6K
R147 10K
HDD connector
C1_0328: Change
to 1M from 100K
HDD_VCC
R663
10K
-HDRESET
C295
100P
1 3
HDD_VCC
0322
2
Ramp_0620: Change to new part number
CON18
0.1u_0402
Q101
SI3456DV
6
5
2
1
C897
0.1u_0402
+3V
R631
1M
2N7002E
R629
1M
Q104
2
-HDRESET
IDEPD7
IDEPD6
IDEPD5
IDEPD4
IDEPD3
IDEPD2
IDEPD1
IDEPD0
R_PDDREQ
-R_PDIOW
-R_PDIOR
R_PIORDY PSEL
-R_PDDACK
R_IRQ14
R_PDA1
R_PDA0 R_PDA2
-R_PDCS1 -R_PDCS3
-HDDLED
HDD_VCC
C864
100P
12V
+5V
3
1
45
46
1
1
45
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
HDD_CONN.
4
3
10u/10V/Tan_1206
46
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
2
2
4
4
6
6
8
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
HDD_VCC
12
+
C896
1
IDEPD8
IDEPD9
IDEPD10
IDEPD11
IDEPD12
IDEPD13
IDEPD14
IDEPD15
R159 470
HDD_VCC
C3500.1u_0402C349
2A: ADD
C943
0.1u_0402
3
C1_0403: Change
to NAND, add
A A
DTC144EU,10K.
HDDVCC_EN[12]
HDDVCC_ON[35]
R653 0
R654 *0
Q106
2
C1_0323: Add
5
4
3
2N7002E
1
Size Document Number Rev
A
Date: Sheet of
Primary IDE (HDD interface)
2
PROJECT : RT2.0
Quanta Computer Inc.
C1_0328: Add
16 57Tuesday, September 11, 2001
1
3A
5
SDIOW#[11]
SDIOR#[11]
SDDREQ[11]
SIORDY[11]
SDA0[11]
E E
D D
C C
B B
SDA1[11]
SDA2[11]
SDDACK#[11]
SDCS1#[11]
SDCS3#[11]
IRQ15[11]
SDD0[11]
SDD1[11]
SDD2[11]
SDD3[11]
SDD4[11]
SDD5[11]
SDD6[11]
SDD7[11]
SDD8[11]
SDD9[11]
SDD10[11]
SDD11[11]
SDD12[11]
SDD13[11]
SDD14[11]
SDD15[11]
-DEV_INS[35]
CD_R[27]
CD_L[27]
CD_GND[27]
DSKCHG#[31,41]
HEAD#[31,41]
RDATA#[31,41]
WP#[31,41]
TRK0#[31,41]
WGATE#[31,41]
WDATA#[31,41]
STEP#[31,41]
DIR#[31,41]
FDDDRV0#[31]
MTR0#[31]
INDEX#[31,41]
3MODE#[12,32]
IDE_ID0[11]
IDE_ID1[11]
IDE_ID2[11]
RST_CDROM#[12]
RP26
6
4
2
RP29
RP30
RP31
RP27
RP33
RP32
L30 BK1608HS241-T
L31 BK1608HS241-T
L32 BK1608HS241-T
DSKCHG#
HEAD#
RDATA#
WP#
TRK0#
WGATE#
WDATA#
STEP#
DIR#
FDDDRV0#
MTR0#
INDEX#
3MODE#
IDE_ID0
IDE_ID1
IDE_ID2
8P4R_33
6
4
2
8P4R_33
6
4
2
8P4R_33
2
4
6
8P4R_33
2
4
6
8P4R_33
2
4
6
8P4R_33
2
4
6
8P4R_33
R136 *0
0322
CDVCC_EN[12]
78
5
3
1
78
5
3
1
78
5
3
1
1
3
5
78
1
3
5
78
1
3
5
78
1
3
5
78
R655 0
4
-R_SDIOW
-R_SDIOR
R_SDDREQ
R_SIORDY
R_SDA0
R_SDA1
R_SDA2
-R_SDDACK
-R_SDCS1
-R_SDCS3
R_IRQ15
IDESD0
IDESD1
IDESD2
IDESD3
IDESD4
IDESD5
IDESD6
IDESD7
IDESD8
IDESD9
IDESD10
IDESD11
IDESD12
IDESD13
IDESD14
IDESD15
CD_R_1
CD_L_1
CD_GND_1
2
3
C280
C279
0.1u_0402
0.1u_0402
-R_SDDACK
R_SDA1
-CDRESET
-R_SDCS3 -R_SDCS1
R_SIORDY
-DEV_INS
IDESD4
IDESD3
IDE_ID0
DSKCHG#
STEP#
DIR#
INDEX#
FDDDRV0#
MTR0#
CD_R_1
CD_L_1
C1_0328: Change
to 1M from 100K
CD_VCC
R137
10K R459
Q22
DTC144EU
1 3
CD_VCC
R138
10K
-CDRESET
Q23
2
DTC144EU
1 3
C282
100P
2N7002E
CON13
+3V
Q76
2
65
66
65
66
1 2
1 2
3 4
3 4
5 6
5 6
7 8
7 8
9 10
9 10
11 12
11 12
13 14
13 14
15 16
15 16
17 18
17 18
19 20
19 20
21 22
21 22
23 24
23 24
25 26
25 26
27 28
27 28
29 30
29 30
31 32
31 32
33 34
33 34
35 36
35 36
37 38
37 38
41 42
41 42
43 44
43 44
45 46
45 46
47 48
47 48
49 50
49 50
51 52
51 52
53 54
53 54
55 56
55 56
57 58
57 58
59 60
59 60
61 62
61 62
64
67
64
67
1M
3
1
4039
4039
63
68
63
68
CD/FDD_CON
B2_0313: Change
to SI3456
12V
R143
1M
3
Q75
2
2N7002E
1
CD_VCC
R676
22R_0805
CD_VCCCD_VCC
Q78
SI3456DV
6
5
2
1
C286
0.1u
2
R141
*470
R_SDA2
R_SDA0
R_IRQ15
-R_SDIOW
-R_SDIOR
R_SDDREQ
IDESD14IDESD2
IDESD15IDESD1
IDESD12
IDESD13
IDESD10IDESD6
IDESD11IDESD5
IDESD8IDESD0
IDESD9IDESD7
IDE_ID1
WDATA#
WGATE#
TRK0#
HEAD#
IDE_ID2-DEV_INS
WP#
RDATA#
3MODE#
CD_GND_1
3
4
C281
0.1u_0402
C798
1000P
1
C283
0.1u_0402
CD_VCC
R_SIORDY
SDDREQ
SDD7
CD_VCC+5V
12
C800
10u/10V_1206
R139 1K
R140 5.6K
R142 10K
A A
CDVCC_ON[35]
C1_0323: Add
5
R656 *0
Ramp_0620: Add
4
3
3
2
Q116
TN0200N
1
2
Size Document Number Rev
B
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
Secondary IDE/FDD interface
17 57Tuesday, September 11, 2001
1
3A
5
4
3
2
1
ATI P6
U47A
D D
3VSUS
R518
*10K
Q80
VGARSTEN[34]
PCIRST#[6,11,16,25,28,30,31,41,51]
C C
2
*DTC144EU
3VSUS
C841
*0.1u
5
2
1
1 3
3
C1 Test_0402:
Add for D3
cold, but
reserved.
U68
*7SH32
CLK66_AGP[3]
4
R659
0
-SUSRST
PIRQB#
B B
A A
5
VAGPREF[8]
SUSA#[3,12,25]
GAD[0..31][8]
R309
*47
C574
*15P
R293 0
VGA_IO_3.3V
4
C88
15P
C95
15P
GCBE0#[8]
GCBE1#[8]
GCBE2#[8]
GCBE3#[8]
GREQ#[8]
GGNT#[8]
GPAR[8]
GDEVSEL#[8]
GTRDY#[8]
GIRDY#[8]
GFRAME#[8]
STP_AGP#[12]
AGP_BUSY#[8,12]
RBF#[8]
AD_STBA[8]
AD_STBB[8]
SB_STB[8]
SBA[0..7][8]
ST0[8]
ST1[8]
ST2[8]
SB_STB#[8]
AD_STBA#[8]
AD_STBB#[8]
R301
1K
4
2
TXC
6P27000019
GSTOP#[8]
PIRQB#[11,30,41,51]
T33 *PAD
3
1
GAD0
D24
AA26
AA23
AA25
AA24
AB25
AB26
AE25
AE19
AF19
AE20
AF20
AE21
AF21
AE18
AF18
AD20
AC20
AD21
AF25
AF26
M26
M24
N25
M25
N26
P23
P26
P24
R25
R24
R26
N23
Y24
K24
K26
K25
W24
W26
P25
V25
W25
V24
V26
V23
U26
U24
Y26
Y23
Y25
U25
N24
B26
C25
AC6
C26
D25
D26
E23
E25
E24
E26
F26
G23
G25
G24
G26
H24
H26
H25
L23
L26
L24
T23
T25
F23
J25
L25
J23
J24
J26
F25
T26
T24
F24
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
VGACORECLK
RESET#
REQ#
GNT#
PAR
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
INTR#
SERR#
STOP_AGP#
AGP_BUSY#
RBF#
AD_STB0
AD_STB1
SB_STB
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
ST0
ST1
ST2
4X_SBSTB#
4X_ADSTB0#
4X_ADSTB1#
4X_AGPREF
4X_AGPTEST
SUS_STAT#
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DVI_DDCLK
DVI_DDCDATA
HPD
XTALIN
XTALOUT
TESTEN
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24 ZV_UV0
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
R102 47
SUS#_01
T12 *PAD
T7 *PAD
T13 *PAD
T8 *PAD
T14 *PAD
T9 *PAD
T11 *PAD
T6 *PAD
T22 *PAD
T4 *PAD
T23 *PAD
CLK_P6
Y1
27MHz
CLK_P6_1
R74
1M
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
SSOUT
ZV_LCDD0
ZV_LCDD1
ZV_LCDD2
ZV_LCDD3
ZV_LCDD4
ZV_LCDD5
ZV_LCDD6
ZV_LCDD7
ZV_LCDD8
ZV_LCDD9
ZV_LCDD10
ZV_LCDD11
ZV_LCDD12
ZV_LCDD13
ZV_LCDD14
ZV_LCDD15
ZV_LCDD16
ZV_LCDD17
ZV_LCDD18
ZV_LCDD19
ZV_LCDD20
ZV_LCDD21
ZV_LCDD22
ZV_LCDD23
ZV_LCDCTL0
ZV_LCDCTL1
ZV_LCDCTL2
ZV_LCDCTL3
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXCLK_UN
TXCLK_UP
LTGIO0
LTGIO1
LTGIO2
DIGON
BLON#
HSYNC
VSYNC
RSET
MONID0
MONID1
CRTDDCCLK
CRTDDCDATA
COMP_B
H2SYNC
V2SYNC
CRT2DDCCLK
CRT2DDCDATA
R2SET
AUXWIN
RANGE_P6
3
SSIN
R
G
B
C_R
Y_G
Y2
Y1
W3
W2
W1
V4
V3
V2
V1
U3
U2
U1
T4
T3
AE7
AE6
ZV_Y0
AA4
ZV_Y1
AB1
ZV_Y2
AB2
ZV_Y3
AB3
ZV_Y4
AB4
ZV_Y5
AC1
ZV_Y6
AC2
ZV_Y7
AC3
AD1
ZV_UV1
AD2
ZV_UV2
AD3
ZV_UV3
AE1
ZV_UV4
AE2
ZV_UV5
AF1
ZV_UV6
AF2
ZV_UV7
AF3
AE3
AF4
AE4
AD4
AF5
AE5
AD5
AC5
Y4
AA1
AA2
AA3
TXLOUT0-
AC8
TXLOUT0+
AD8
TXLOUT1-
AC9
TXLOUT1+
AD9
TXLOUT2-
AE8
TXLOUT2+
AF8
TXLOUT3-
AC10
TXLOUT3+
AD10
TXLCLKOUT-
AE9
TXLCLKOUT+
AF9
TXUOUT0-
AD11
TXUOUT0+
AC11
TXUOUT1-
AE11
TXUOUT1+
AF11
TXUOUT2-
AD12
TXUOUT2+
AC12
TXUOUT3-
AD13
TXUOUT3+
AE13
TXUCLKOUT-
AE12
TXUCLKOUT+
AF12
AD7
AD6
AC7
AB10
AB9
AF24
AF23
AF22
AE24
AE23
R59 499_1%
AE22
AD24
AD25
AC25
AC26
AF16
AF15
AF14
AE14
AF13
AF6
AF7
R262 845_1%
AE16
VGA_IO_1
AC22
T32 *PAD
T37 *PAD
T36 *PAD
T35 *PAD
T34 *PAD
T39 *PAD
T38 *PAD
T202*PAD
T203*PAD
T205*PAD
PVCLKI_1
PMCLKI
ZV_Y[0..7]
ZV_UV[0..7]
T15 *PAD
T18 *PAD
T28 *PAD
T30 *PAD
T20 *PAD
T19 *PAD
T1 *PAD
T24 *PAD
T25 *PAD
T17 *PAD
T10 *PAD
R216 *10K
R214 *10K
R217 *10K
R215 *10K
LCDID0
LCDID1
LCDID2
LCDID3
LCDID4
R317 *10K
VGA_IO_3.3V
R260 0
ZV_Y[0..7] [29]
ZV_UV[0..7] [29]
LCDID0 [40]
LCDID1 [40]
LCDID2 [40]
LCDID3 [40]
LCDID4 [40]
TXLOUT0- [22]
TXLOUT0+[22]
TXLOUT1- [22]
TXLOUT1+[22]
TXLOUT2- [22]
TXLOUT2+[22]
TXLCLKOUT- [22]
TXLCLKOUT+ [22]
TXUOUT0- [22]
TXUOUT0+ [22]
TXUOUT1- [22]
TXUOUT1+ [22]
TXUOUT2- [22]
TXUOUT2+ [22]
TXUCLKOUT- [22]
TXUCLKOUT+ [22]
VGA_IO_3.3V
ZV_VREF [29]
ZV_HREF [29]
ZV_PCLK [29]
T27 *PAD
T21 *PAD
T26 *PAD
T16 *PAD
R198
R199
R259 10
C497
10P
VGA_IO_3.3V
C2_0517: Add L,C for EMI
L134
BK1608HS241-T
U41
6
T204*PAD
PVCLKI
PMCLKI_1
S0
7
S1
8
SD
1
ICLK
4
CLK
R261
33
MK1707S
C473
SHFCLK spread spectrum control
22p
LCDID0
LCDID1
LCDID2
LCDID3
LCDID4
R35 10K
R34 10K
R209 10K
R208 10K
R207 10K
2
VDD
5
LEE
3
GND
VGA_IO_3.3V
C70
0.01u
T206*PAD
LEE is internal pull high. high for
enable EMI function
(Optional)
C2_0423: Change net name from<ZV_SCLK>
CRT_R [23]
CRT_G [23]
CRT_B [23]
R264
75_1%
TV_LUMA
R249
75_1%
TV_GND
TV_GND
R263
75_1%
DIGON [22]
-BLON [22]
CRTHS_VGA [23]
CRTVS_VGA [23]
DDCCLK_0
DDCDAT_0
TV_CHROMA [23,41]
TV_LUMA [23,41]
TV_COMP [23,41]
EDIDCLK [22]
EDIDDATA [22]
R250
75_1%
R247 0_0805
TV_GND
Size Document Number Rev
C
Date: Sheet of
VGA_IO_3.3V
2.2K
2.2K
R265
75_1%
TV_CHROMA
TV_LUMA
TV_COMP
EDIDCLK
EDIDDATA
TV_CHROMA
TV_COMP
R251
75_1%
TV_GND
2
C974
0.1u_0402
VGA_IO_3.3V +5V
R185
4.7K
VGA_IO_3.3V +5V
R206
4.7K
Q33
2
2N7002E
1
Q41
2
2N7002E
1
Quanta Computer Inc.
ATI P6 (HOST, VIDEO O/P)-1
C1 Test_0402:
Change
3
3
DDCCLK [23,41]
C1 Test_0402:
Change
DDCDAT [23,41]
PROJECT : RT2.0
1
18 57Tuesday, September 11, 2001
3A
5
4
3
2
1
VMEMD[0..63][20]
D D
C C
B B
A A
VMA[0..13][20]
VMDQM#[0..7][20]
VMRAS#[20]
VMCAS#[20]
VMWE#[20]
VMCKE[20]
VMEMQS0[20]
VMEMQS4[20]
VMCS0#[20]
VMCLK0[20]
VMCLK0#[20]
VMCLK1[20]
VMCLK1#[20]
VMEMD[0..63]
VMA0
1
VMA1
3
VMA2
5
VMA3
7 8
VMA4
9
VMA5
11
VMA6
13
VMA7
15
VMA8
1
VMA9
3
VMA10
5
VMA11
7 8
VMA12
9
VMA13
11
13
VMDQM#0
VMDQM#1
VMDQM#2
VMDQM#3
VMDQM#4
VMDQM#5
VMDQM#6
VMDQM#7
VMRAS#
VMCAS#
VMCKE VMCKE_1
VMEMQS0
VMEMQS4
VMCS0# VMCS0#_1
VMCLK0
VMCLK0#
VMCLK1
VMCLK1#
C667
*10P
C184
*10P
15
16
14
12
10
6
4
2
*PAD
T207
R367 33
R109 33
R366 33
R365 33
C665
*10P
EMI reserved
C666
*10P
RP9
16P8R_33
RP24
16P8R_33
RP5
16P8R_33
RP19
8P4R_33
RP4
8P4R_33
2
4
6
10
12
14
16
2
4
6
10
12
14
16
15
13
11
9
78
5
3
1
12
34
56
78
12
34
56
78
VMCLK0_1
VMCLK0#_1
VMCLK1_1
VMCLK1#_1
VMMA0
VMMA1
VMMA2
VMMA3
VMMA4
VMMA5
VMMA6
VMMA7
VMMA8
VMMA9
VMMA10
VMMA11
VMMA12
VMMA13
VDQM#0
VDQM#1
VDQM#2
VDQM#3
VDQM#4
VDQM#5
VDQM#6
VDQM#7
VMRAS#_1
VMCAS#_1
VMWE#_1
VQS0
VQS4
VMCS1#_1
VMEMD0
VMEMD1
VMEMD2
VMEMD3
VMEMD4
VMEMD5
VMEMD6
VMEMD7
VMEMD8
VMEMD9
VMEMD10
VMEMD11
VMEMD12
VMEMD13
VMEMD14
VMEMD15
VMEMD16
VMEMD17
VMEMD18
VMEMD19
VMEMD20
VMEMD21
VMEMD22
VMEMD23
VMEMD24
VMEMD25
VMEMD26
VMEMD27
VMEMD28
VMEMD29
VMEMD30
VMEMD31
VMEMD32
VMEMD33
VMEMD34
VMEMD35
VMEMD36
VMEMD37
VMEMD38
VMEMD39
VMEMD40
VMEMD41
VMEMD42
VMEMD43
VMEMD44
VMEMD45
VMEMD46
VMEMD47
VMEMD48
VMEMD49
VMEMD50
VMEMD51
VMEMD52
VMEMD53
VMEMD54
VMEMD55
VMEMD56
VMEMD57
VMEMD58
VMEMD59
VMEMD60
VMEMD61
VMEMD62
VMEMD63
1
3
RP6
5
7 8
16P8R_33
9
11
13
15
1
3
RP20
5
7 8
16P8R_33
9
11
13
15
1
3
RP10
5
7 8
16P8R_33
9
11
13
15
1
3
RP25
5
7 8
16P8R_33
9
11
13
15
1
3
RP7
5
7 8
16P8R_33
9
11
13
15
1
3
RP22
5
7 8
16P8R_33
9
11
13
15
1
3
RP8
5
7 8
16P8R_33
9
11
13
15
1
3
RP23
5
7 8
16P8R_33
9
11
13
15
ATI P6
VMD0
2
VMD1
4
VMD2
6
VMD3
VMD4
10
VMD5
12
VMD6
14
VMD7
16
VMD8
2
VMD9
4
VMD10
6
VMD11
VMD12
10
VMD13
12
VMD14
14
VMD15
16
VMD16
2
VMD17
4
VMD18
6
VMD19
VMD20
10
VMD21
12
VMD22
14
VMD23
16
VMD24
2
VMD25
4
VMD26
6
VMD27
VMD28
10
VMD29
12
VMD30
14
VMD31
16
VMD32
2
VMD33
4
VMD34
6
VMD35
VMD36
10
VMD37
12
VMD38
14
VMD39
16
VMD40
2
VMD41
4
VMD42
6
VMD43
VMD44
10
VMD45
12
VMD46
14
VMD47
16
VMD48
2
VMD49
4
VMD50
6
VMD51
VMD52
10
VMD53
12
VMD54
14
VMD55
16
VMD56
2
VMD57
4
VMD58
6
VMD59
VMD60
10
VMD61
12
VMD62
14
VMD63
16
VMD0
VMD1
VMD2
VMD3
VMD4
VMD5
VMD6
VMD7
VMD8
VMD9
VMD10
VMD11
VMD12
VMD13
VMD14
VMD15
VMD16
VMD17
VMD18
VMD19
VMD20
VMD21
VMD22
VMD23
VMD24
VMD25
VMD26
VMD27
VMD28
VMD29
VMD30
VMD31
VMD32
VMD33
VMD34
VMD35
VMD36
VMD37
VMD38
VMD39
VMD40
VMD41
VMD42
VMD43
VMD44
VMD45
VMD46
VMD47
VMD48
VMD49
VMD50
VMD51
VMD52
VMD53
VMD54
VMD55
VMD56
VMD57
VMD58
VMD59
VMD60
VMD61
VMD62
VMD63
VMEM_MODE has internal pull-down.(1.8V plane).
Selection for voltage of memory IO power (VDDQ).
Pull-up for 2.5V.
A26
B25
A25
A24
B23
A23
C22
B22
C21
B21
A21
D20
C20
A20
C19
B18
A18
C17
B17
A17
D16
C16
B16
B15
A15
D14
C14
B14
A14
D13
C13
U47B
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
B1
MD32
C1
MD33
C2
MD34
D1
MD35
D2
MD36
E1
MD37
E2
MD38
F1
MD39
G2
MD40
G3
MD41
H1
MD42
H2
MD43
H3
MD44
J1
MD45
J2
MD46
J3
MD47
L1
MD48
L2
MD49
L3
MD50
L4
MD51
M1
MD52
M2
MD53
M3
MD54
N1
MD55
N4
MD56
P1
MD57
P2
MD58
P3
MD59
P4
MD60
R1
MD61
R2
MD62
R3
MD63
RANGE_P6
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13MD13
DQM#0
DQM#1
DQM#2
DQM#3
DQM#4
DQM#5
DQM#6
DQM#7
QS0
QS1
QS2
QS3
QS4
QS5
QS6
QS7
RAS#
CAS#
WE#
CS0#
CS1#
CKE
ROMCS#
CLK0
NC_1
CLK0#
NC_2
CLK1
NC_3
CLK#
NC_4
CLKFB
VREF
MEMV/MODE
B13
A13
C12
B12
A12
D11
C11
B11
A11
C10
B10
A10
D9
C9B20
A22
D21
A16
C15
F2
G1
N2
N3
A19
B19
D18
C18
J4
K1
K2
K3
A9
C8
D8
B9
B8
A8
Y3
A6
A7
B6
B7
A4
A5
B4
B5
B3
T2
T1
VMMA0
VMMA1
VMMA2
VMMA3
VMMA4
VMMA5
VMMA6
VMMA7
VMMA8
VMMA9
VMMA10
VMMA11
VMMA12
VMMA13
VDQM#0
VDQM#1
VDQM#2
VDQM#3
VDQM#4
VDQM#5
VDQM#6
VDQM#7
VQS0
VQS4
VMRAS#_1
VMCAS#_1VMWE#
VMWE#_1
VMCS0#_1
VMCS1#_1
VMCKE_1
VMCLK0_1
VMCLK0#_1
VMCLK1_1
VMCLK1#_1
C584
0.1u_0402
VM_VREF
*PAD
T53
*PAD
T48
*PAD
T49
*PAD
T45
*PAD
T46
*PAD
T47
*PAD
T31
*PAD
T55
*PAD
T52
*PAD
T54
*PAD
T51
*PAD
T50
VMEM_MODE
R213 4.7K
R241
*0
+1.8V_VGA
pull-down for 3.3V.
Both samsung's and hyundai's sdram are 2.5V on VDDQ.
5
4
3
2
Size Document Number Rev
B
Date: Sheet of
ATI P6 (VRAM)-2
PROJECT : RT2.0
Quanta Computer Inc.
19 57Tuesday, September 11, 2001
1
1A
5
4
3
2
1
8/16/32MB DDR 2/4MX32 SDRAM
8MB 32 BIT INTERFACE WITH ONE PIECE 2MX32 (U6)
8MB 64 BIT INTERFACE WITH TWO PIECES 2MX32 (U6,U7)
16MB 32 BIT INTERFACE WITH ONE PIECE 4MX32 (U6)
32MB 64 BIT INTERFACE WITH TWO PIECES 4MX32 (U6,U7)
VMEMD0
VMEMD1
VMEMD2
VMEMD3
VMEMD4
VMEMD5
VMEMD6
VMEMD7
VMEMD8
VMEMD9
VMEMD10
VMEMD11
VMEMD12
VMEMD13
VMEMD14
VMEMD15
VMEMD16
VMEMD17
VMEMD18
VMEMD19
VMEMD20
VMEMD21
VMEMD22
VMEMD23
VMEMD24
VMEMD25
VMEMD26
VMEMD27
VMEMD28
VMEMD29
VMEMD30
VMEMD31
VGA_IO_3.3V
0.1u_0402
VDDQ_2.5V
VDD_SDRAM VDD_SDRAM
Hyundai
HY58DU663222=2.5V VDD
2.5_VGA
Samsung
K4D62323HA=3.3V VDD
0.1u_0402
C714
L24
*FCM2012V131DC10
L23
FCM2012V131DC10
0.1u_0402
C716
C747
0.1u_0402
3
C731
0.1u_0402
0.1u_0402
C712
VM_VREF
VDD_SDRAM
0.1u_0402
C769
VDDQ_2.5V
C774
0.1u
0.1u_0402
0.1u_0402
C772
C779
0.1u_0402
0.1u_0402
C770
C715
VMA0
VMA1
VMA2
VMA3
VMA4
VMA5
VMA6
VMA7
VMA8
VMA9
VMA10
VMA11
VMA13VMA12
VMA12
VMCLK1#
VMCS0#
VMRAS#
VMCAS#
VMWE#
VMDQM#7
VMDQM#6
VMDQM#5
VMDQM#4
VMCLK1
VMCKE
VMEMQS4
C771
0.1u_0402
0.1u_0402
C725
31
32
33
34
47
48
49
50
51
45
36
37
29
30
38
39
40
41
42
43
44
87
88
89
90
91
52
93
58
54
28
27
26
25
57
24
56
23
55
53
94
C773
C727
0.1u_0402
U60
A0
A1
A2
A3
A4
A5
A6
A7
A8(AP)
NC/A9
NC/A10
NC/A11
BA0
BA1
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
DSF,MCL
RFU(QS)
VREF
CK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CK
CKE
QS
VDDQ_2.5V
C713
0.1u_0402
VDD_SDRAM
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDD_1
VDD_2
VDD_3
VDD_4
VSSQ_1
VSSQ_2
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VSS_1
VSS_2
VSS_3
VSS_4
98
100
1
3
4
6
7
60
61
63
64
68
69
71
72
9
10
12
13
17
18
20
21
74
75
77
78
80
81
83
84
2
8
14
22
59
67
73
79
86
95
15
35
65
96
5
11
19
62
70
76
82
92
99
16
46
66
85
VMEMD33
VMEMD34
VMEMD35
VMEMD36
VMEMD37
VMEMD38
VMEMD39
VMEMD40
VMEMD41
VMEMD42
VMEMD43
VMEMD44
VMEMD45
VMEMD46
VMEMD47
VMEMD48
VMEMD49
VMEMD50
VMEMD51
VMEMD52
VMEMD53
VMEMD54
VMEMD55
VMEMD56
VMEMD57
VMEMD58
VMEMD59
VMEMD60
VMEMD61
VMEMD62
VMEMD63
VDDQ_2.5V
VMEMD32
97
Default:
Hyundai
HY58DU663222
Size Document Number Rev
B
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
Video DDR SDRAM
20 57Tuesday, September 11, 2001
1
2B
E E
VMEMD[0..63][19]
VMA[0..13][19]
VMDQM#[0..7][19]
D D
C C
B B
VMEMQS0[19]
VMEMQS4[19]
VMRAS#[19]
VMCAS#[19]
VMWE#[19]
VMCS0#[19]
VMCKE[19]
VMCLK0[19]
VMCLK0#[19]
VMCLK1[19]
VMCLK1#[19]
VMEMD[0..63]
VMA[0..13]
VMDQM[0..7]
VMEMQS0
VMEMQS4
VMRAS#
VMCAS#
VMWE#
VMCS0#
VMCKE
VMCLK0
VMCLK0#
VMCLK1
VMCLK1#
VDDQ_2.5V
VM_VREF
C258
0.1u_0402
R125
121_1%
R126
121_1%
C753
0.1u_0402
VMCLK0#
VMA0
VMA1
VMA2
VMA3
VMA4
VMA5
VMA6
VMA7
VMA8
VMA9
VMA10
VMA11
VMA13
VMCS0#
VMRAS#
VMCAS#
VMWE#
VMDQM#3
VMDQM#2
VMDQM#1
VMDQM#0
VMCLK0
VMCKE
VMEMQS0
31
32
33
34
47
48
49
50
51
45
36
37
29
30
38
39
40
41
42
43
44
87
88
89
90
91
52
93
58
54
28
27
26
25
57
24
56
23
55
53
94
U23
A0
A1
A2
A3
A4
A5
A6
A7
A8(AP)
NC/A9
NC/A10
NC/A11
BA0
BA1
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
DSF,MCL
RFU(QS)
VREF
CK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CK
CKE
QS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDD_1
VDD_2
VDD_3
VDD_4
VSSQ_1
VSSQ_2
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VSS_1
VSS_2
VSS_3
VSS_4
97
98
100
1
3
4
6
7
60
61
63
64
68
69
71
72
9
10
12
13
17
18
20
21
74
75
77
78
80
81
83
84
2
8
14
22
59
67
73
79
86
95
15
35
65
96
5
11
19
62
70
76
82
92
99
16
46
66
85
Default:
Hyundai
HY58DU663222
C220
0.1u_0402
C238
0.1u
0.1u_0402
C234
0.1u_0402
0.1u_0402
C266
A A
0.1u_0402
5
C262
0.1u_0402
0.1u_0402
C224
C222
0.1u_0402
C245
0.1u_0402
C260
0.1u_0402
C223
C235
0.1u_0402
4
C259
C221
0.1u_0402
VDDQ_2.5V
C261
0.1u_0402
VDD_SDRAM
1
2
3
4
5
6
7
8
U47C
E5
VSS_1
C3
VSS_2
B2
VSS_3
A1
VSS_4
D4
VSS_5
T10
VSS_6
T11
VSS_7
ATI P6
T12
VSS_8
T13
VSS_9
T14
VSS_10
M10
M11
M12
M13
M14
M15
M16
M17
AE26
AD26
AC13
AD14
AB13
AC14
AE10
AF10
AC19
AD19
AD18
AD17
AC18
AE17
AF17
AD16
AD15
AC15
AC16
AE15
AD23
AD22
AC21
T15
T16
T17
K10
K11
K12
K13
K14
K15
K16
K17
L10
L11
L12
L13
L14
L15
L16
L17
N10
N11
N12
N13
N14
N15
N16
N17
P10
P11
P12
P13
P14
P15
P16
P17
R10
R11
R12
R13
R14
R15
R16
R17
U10
U11
U12
U13
U14
U15
U16
U17
C4
D3
E4
F5
D5
A2
A3
C5
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
PVDD
PVSS
LVDDR_1
LVDDR_2
LVSSR_1
LVSSR_2
LPVDD
LPVSS
TXVDDR_1
TXVDDR_2
TXVSSR_1
TXVSSR_2
TXVSSR_3
TPVDD
TPVSS
A2VDD
A2VDDQ
A2VSSN_1
A2VSSN_2
A2VSSQ
AVDD
AVSSN
AVSSQ
MPVDD
MPVSS
VDDRH
RANGE_P6
A A
B B
C C
VGA_PLL1.8
VGA_PNLIO1.8
C112
0.1u_0402
C499
0.1u_0402
C560
0.1u_0402
C500
0.1u_0402
C183
0.1u_0402
C498
0.1u_0402
3
C73
0.1u_0402
VGA_PNLPLL1.8
VGA_DAC2.5
VGA_DAC1.8
D D
VGA_MEMPLL1.8
VDDQ_2.5V
C937
1
C113
0.1u_0402
L123
BK1608HM121
0.1u_0402
2
0.1u_0402
0.1u_0402
C546
0.1u_0402
C177
0.1u_0402
VDDRH
C72
C111
4
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_19
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29
VDDR1_30
VDDR1_31
VDDR1_32
VDDR1_33
VDDR1_34
VDDR1_35
VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6
VDDR3_7
VDDR3_8
VDDR3_9
VDDR3_10
VDDR3_11
VDDR3_12
VDDR3_13
VDDR3_14
VDDR3_15
VDDR3_16
VDDR3_17
VDDR3_18
VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5
VDDP_6
VDDP_7
VDDP_8
VDDP_9
VDDP_10
VDDP_11
VDDP_12
VDDP_13
VDDP_14
VDDP_15
VDDP_16
VDDP_17
VDDP_18
VDDP_19
VDDP_20
VDDP_21
AB11
H5
K5
M5
R5
U5
W5
AB8
AB14
AB7
AB17
AB19
W22
U22
R22
M22
K22
H22
E19
E17
E15
E12
E10
E8
AB12
D10
C7
C23
D12
D17
E3
F4
B24
F3
D6
C6
D15
D19
D22
G4
E6
E7
E9
E11
E13
E14
E16
E18
E20
E21
G5
H4
J5
K4
L5
M4
N5
P5
R4
D7
T5
U4
V5
W4
Y5
AA5
AC4
AB5
AB6
AB15
AB16
AB18
AB20
AB21
AB22
AC17
AC23
AC24
E22
F22
G22
H23
J22
K23
L22
M23
N22
P22
R23
T22
U23
V22
W23
Y22
AA22
AB23
AB24
D23
C24
+1.8V_VGA
VDDQ_2.5V
VGA_IO_3.3V
VGA_VPPD_1.5V
@. Two power pins put one bypass Cap.
C159
C145
C120
0.1u_0402
0.1u_0402
0.1u_0402
C105
0.1u_0402
C125
0.1u_0402
C175
0.1u_0402
C154
0.1u_0402
C108
0.1u_0402
C156
C186
C106
0.1u_0402
C107
0.1u_0402
0.1u_0402
0.1u_0402
C158
C185
0.1u
C109
0.1u_0402
C116
0.1u_0402
6
C147
0.1u_0402
C176
0.1u_0402
C178
0.1u_0402
C104
0.1u_0402
C130
0.1u_0402
5
0.1u_0402
0.1u_0402
0.1u_0402
C119
0.1u_0402
C123
0.1u_0402
0.1u_0402
C160
0.1u_0402
C182
C124
0.1u_0402
C115
1000P
C148
1000P
C129
0.1u_0402
C153
C141
1000P
C110
C114
0.1u_0402
0.1u_0402
C161
C163
0.1u_0402
C152
C134
1000P
1000P
C585
C501
1000P
1000P
C162
1000P
Size Document Number Rev
Custom
Date: Sheet of
C157
C155
1000P
VDDQ_2.5V
VDDQ_2.5V
C144
1000P
C589
1000P
C138
1000P
1000P
12
+
C137
1000P
12
+
12
C102
+
10u/10V_1206
1000P
C181
10u/10V_1206
VGA_IO_3.3V
C75
10u/10V_1206
VGA_VPPD_1.5V
PROJECT : RT2.0
Quanta Computer Inc.
ATI P6 (PWR/ GND)-3
7
1000P
C74
+
10u/10V_1206
21 57Tuesday, September 11, 2001
8
+1.8V_VGA
12
C140
C135
1A
5
4
3
2
1
12V
D D
DIGON[18]
C C
B B
DISP_ON[12]
+3V
R186 4.7K
D14
1SS355
5
21
-BLON[18]
A A
+3V
5
2
U33
7SH04
3
Q49
DTC144EU
4
2
D39
1SS355
D40
1SS355
4
21
21
5VPCU
1 3
R253
10K
+3V
R252
330K
C67
3
Q48
2
2N7002E
R615
22K
1 2
0.1u_0402
1
+3V
TRACE 80MIL
578
Q7
SI9410
3 6
241
L14
FBMJ2125HM330
LCDVCC LCDVCC_1
C12
R210
22R_0805
LCDVCC_N01
3
2
1
D44
1SS355
3
Q40
TN0200N
+3V
2 1
2 1
D43
1SS355
TXUOUT0+A
TXUOUT1+A
TXUOUT1-A
TXUOUT2+A
TXUCLKOUT+A
TXUCLKOUT-A
0.01u
TXUOUT0+[18] TXLOUT0+ [18]
TXUOUT0-[18]
TXUOUT1+[18]
TXUOUT1-[18]
TXUOUT2+[18]
TXUOUT2-[18]
TXUCLKOUT+[18]
TXUCLKOUT-[18]
DISPON
C397
*33p
C11
0.1u_0402
C398
*33p
C45
4.7u/10V_0805
R197 0
R196 0
R195 0
R194 0
R193 0
R192 0
R191 0
R190 0
C420
*33p
CON7
1
1
3
3
5
5
EDIDDATA[18]
EDIDCLK[18]
VADJ[34]
TXUOUT0+A
TXUOUT0-A
TXUOUT1+A
TXUOUT1-A
TXUOUT2+A
TXUOUT2-A
TXUCLKOUT+A TXLCLKOUT+A
TXUCLKOUT-A
C2_0517
2
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31 32
31 32
33 34
33 34
35 36
35 36
37 38
37 38
39 40
39 40
TXLOUT0+A
TXLOUT0-ATXUOUT0-A
TXLOUT1+A
TXLOUT1-A
TXLOUT2+A
TXLOUT2-ATXUOUT2-A
TXLCLKOUT+A
TXLCLKOUT-A
10
12
14
16
18
20
22
24
26
28
30
GND_1 GND_2
41 42
C2_0517
Size Document Number Rev
B
Date: Sheet of
2
2
4
4
6
6
8
8
10
12
14
16
18
20
22
24
26
28
30
LCD_CONN.
C465
*33p
VIN_1
C55
C56
0.01u
0.1u_0402
Ramp_0620: Change
TXLOUT0+A
TXLOUT0-A
TXLOUT1+A
TXLOUT1-A
TXLOUT2+A
TXLOUT2-A
TXLCLKOUT-A
R230 0
R229 0
R228 0
R227 0
R226 0
R225 0
R224 0
R223 0
ODD chanelEVEN chanel
C466
C467
C469
C435
C468
*33p
*33p
*33p
*33p
*33p
PROJECT : RT2.0
Quanta Computer Inc.
LCD interface
FBMJ2125HM330
C483
10U/25V_1210
1
L15
TXLOUT0-[18]
TXLOUT1+ [18]
TXLOUT1-[18]
TXLOUT2+ [18]
TXLOUT2-[18]
TXLCLKOUT+ [18]
TXLCLKOUT- [18]
22 57Tuesday, September 11, 2001
VIN
2A
5
4
3
2
1
CRT PORT
F1
E E
CRT_HS[41]
CRT_VS[41]
CRT_R[18]
CRT_G[18]
CRT_B[18]
CRT_R
CRT_G
CRT_B
+5V
POLY_SWITCH
12
L3 BK2125HM560
L76 BK2125HM560
L77 BK2125HM560
Change power plane
from 5VPCU to +5V
U39B
7WT125FU
D D
C C
CRTVS_VGA[18]
CRTHS_VGA[18]
+5V
5 3
7
U39A
7WT125FU
2 6
1
8 4
+5V
R176 2K
R3 2K
DDCCLK[18,41]
CRT_VS
CRT_HS
DDCDAT[18,41]
DDCDAT
DDCCLK
C10
22P
CRT_R
CRT_G
CRT_B
C9
22P
L2 BK1608HM121
L1 BK1608HM121
L74 BK1608HM121
L73 BK1608HM121
C8
C7
22P
22P
L9 BK1608HM121
L8 BK1608HM121
L10 BK1608HM121
C411
C409
C410
10P
10P
10P
Change power plane from 5VPCU to +5V
TV_LUMA[18,41]
C808
C811
82P
82P
B B
TV_CHROMA[18,41]
L35
1.8UH
L36
1.8UH
TV-LUMA
C804
82P
TV-CHROMA
C812
82P
C363
22P
CON12
L4
FBMJ2125HM330
CRT_R_1
CRT_G_1
CRT_B_1
C361
22P
C365
22P
5
5
CRTVDD3CRTVDD2
C359
22P
46
89
R168
0_0805
T78
*PAD
C364
C362
22P
22P
D_RED [41]
D_GREEN [41]
D_BLUE [41]
to docking
46
89
1617
6
7
2
8
3
9
4
10
5
R15
0_0805
DDCCLK_1
CRT_VS_1
CRT_HS_1
DDCDAT_1
C360
22P
S-VIDEO
Yellow
CON3
CRT_CONN
111
12
13
14
15
+5V
5VSUS
R177
10K
+5V
3
*POST05C
D7
-CRT_SENSE [35,41]
D13
DA204U
1
3
2
D2
DA204U
1
3
2
D1
DA204U
1
3
2
D12
DA204U
1
3
2
D11
DA204U
1
3
2
TV_CHROMA
2
TV_LUMA
1
DDCCLK_1
DDCDAT_1
CRT_R_1
CRT_B_1
CRT_G_1
3
7
7
A A
TV_COMP[18,41]
C803
82P
L34
1.8UH
TV-COMP
C809
82P
C2_0518: For EMI, change GND.
5
4
3
13
2
2
R135 0_0805
R146 0_0805
Size Document Number Rev
B
2
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
S Video/Composite,CRT
1
1A
23 57Tuesday, September 11, 2001
8
D D
+2.5V
L132
FBMJ2125HM330
10u/10V/Tan_1206
C940
12
+
7
100 MIL
2.5_VGA
12
C781
0.1u
L27
FBMJ2125HM330
C761
0.1u_0402
2000mA
150u/6.3V_7343
6
For DDR SDRAM VDDQ &
P6 VDDR1
B2_0324: 100 MIL
VDDQ_2.5V
To VDDR1: Memory IO power
To VDDQ of DDR SRRAM: Power for DQ's
12
(output buffers)
C265
5
1.8VSUS
+1.8V
4
L129
*FBMJ2125HM330
L130
FBMJ2125HM330
10u/10V/Tan_1206
B2_0315: Add,
100 MIL
12
12
+
C171
3
C172
0.1u/50V_0805
2
1.8_VGA
0.1u/50V_0805
L124
FCM2012V131DC10
To TXVDDR : TMDS IO power : 40 mA
LVDDR : LVDS IO power : 40 mA
12
C142
1
For ATI P6 VDDC
Sch: 1000 mA
Actual max: 1318.8 mA
220u/2.5V_7343
+
C150
BK2125HM471
To VDDC: Internal logic
core power
L94
+1.8V_VGA
Sch: 80mA
VGA_PNLIO1.8
12
C527
+
4.7u/10V_0805
C1_0403: Add for CRT & TVOUT DAC POWER
C2_0518: Add regulators for
PLL power sources.
C C
150mA
+3V
C988
0.1u_0402
B B
12
C985
+
4.7u/10V_0805
U89
AIC1730-18CV
1
IN
2
GND
3
EN
BYPASS
C990
0.1u_0402
OUT
5
C986
4
C982
0.1u_0402
12
+
C989
0.1u_0402
10u/10V/Tan_1206
L16
LK2125-2R7K-0805
L17
LK2125-2R7K-0805
L98
BK2125HM471
4.7u/10V_0805
4.7u/10V_0805
12
+
12
C86
+
12
C90
+
C606
4.7u/10V_0805
C978
0.1u_0402
C984
0.1u_0402
C987
0.1u_0402
Sch: 20mA
VGA_PLL1.8
To PVDD: PLL power
Sch: 20mA
VGA_PNLPLL1.8
To TPVDD: TMDS PLL power : 10 mA
LPVDD: LVDS PLL power : 10 mA
Sch: 10mA
VGA_MEMPLL1.8
To MPVDD: Memory PLL power
AIC1730-18CV
2.5_VGA
C950
0.1u_0402
VGA_IO_3.3V
0.1u_0402
C953
U85
12
C949
+
4.7u/10V_0805
C954
4.7u/10V_0805
To AVDD: CRT DAC power : 90 mA
A2VDDQ: TV DAC band gap ref voltage:5 mA
1
IN
2
GND
3
EN
150mA
U86
AIC1730-25CV
1
12
2
+
3
IN
GND
EN
150mA
OUT
BYPASS
C952
0.1u_0402
BYPASS
5
4
OUT
C956
0.1u_0402
VGA_DAC1.8
12
+
C957
C951
0.1u_0402
10u/10V/Tan_1206
Sch: 90mA
Actual max: 123.05mA
5
4
12
C958
10u/10V/Tan_1206
+
VGA_DAC2.5
A2VDD:TV DAC power
C955
0.1u_0402
Sch: 95mA
C2_0517: Add cap for EMI
+3V
3VSUS
A A
+1.5V
L133
FCM2012V131DC10
L22
*FCM2012V131DC10
L20
BK2125HM471
8
To VDDP: AGP IO power
VGA_IO_3.3V
C975
0.1u_0402
VGA_VPPD_1.5V
7
C976
0.47u_X7R
For ATI P6 VREF
For DDR SDRAM VREF
VM_VREF
6
C752
0.1u_0402
VDDQ_2.5V
R394
1K_1%
R393
1K_1%
5
Power source option for
ATI P6 power states selection
ATI P6 power
states
Control
signals
Location
L133
L130
Page44:
R661
L22
L129
Page44:
PQ46
D3 cold
MAINON
Components options
Load
Q110
No load
R662
4
D3 hot
SUSON
No load
Load
Size Document Number Rev
B
3
Date: Sheet of
VGA power
2
PROJECT : RT2.0
Quanta Computer Inc.
24 57Tuesday, September 11, 2001
1
3A
5
E E
+3V
L120
D18 1SS355
AUDGND
8
EA
7
D
6
G
+5V
12
+3V
R344
10K
21
R319
22K
R312
680
Ramp_0620:
Change
R248
0
C42
+
10u/16V_3528
BK1608HS241-T
SG-710ECK (50PPM)
Y3
4
VCC
1
OE
C611
0.1u_0402
MICGNDAUDGND
Q3
SI3442DV
3 4
G S
2
D_2
D_4
1
D_1
D_3
C34
0.1u_0402
49.152MHZ
C564
1u/6.3V_0603
C536
1000P
(R2)
R189
10K_1%
(R1)
5
6
AUDGND
OUT
VSS
BEEP_1BEEP_0
AUDGND
C517
1000P
AUDGND
R179
28.7K_1%
12
+
C38
10u/16V_3528
D D
SUSA#[3,12,18]
C2_0529: Change
BEEP[39]
C C
B B
VOUT=1.235(1+R1/R2)
U34
5
1
EN
2
FLAG
3
GND
4 5
VP VDD
MIC5156
+5V
12V
C424
0.1u_0402
A A
-VOLUP_BTN[40]
-VOLDN_BTN[40]
3
2
BK1608HS241-T
L121
CD_COM[27]
CD_LINL[27]
CD_LINR[27]
LINE_IN_L[27]
LINE_IN_R[27]
AOUTL[26]
AOUTR[26]
C529
4.7u/10V_0805
AUDGND
+5VA_0
FBMJ2125HM330
0.1u_0402
4
-VOLUP[34]
-VOLDN[34]
C567 0.1u_0402
T2*PAD
MIC1[27]
T5*PAD
T3*PAD
C516
0.1u_0402
L91
C526
AUDGND
4
CLK_1988CLK_1988_1
R320
33
MIC1
CD_COM
CD_LINL
CD_LINR
LINE_IN_L
LINE_IN_R
AOUTL
AOUTR
C441
4.7u/10V_0805
C485
AUDGND
C587
22P
C436
0.1u_0402
3
+3VD
R334
10K
Q61
DTC144EU
2
NEW_DK_INS [35]
1 3
+3VD+3VD
R335
R336
10K
10K
D20 1SS355
21
21
D19 1SS355
T42
*PAD
OSCI
OSCO
64
PC_BEEP
65 83
PHONE AVDD2
81
MONO_OUT
69
MIC
67
CD_GND
66
CD_L
68
CD_R
70
LINE_IN_L
71
LINE_IN_R
79
LINE_OUT_L
80
LINE_OUT_R
84
GPIO1 / RXD
85
GPIO2 / TXD
75
AFILT1
76
AFILT2
77
VCM
78
VREFADC
73
AVSS1
82
AVSS2
89
GND_1
40
GND_2
21
GND_3
3
GND_4
B2_0313: Correct
polarity from
low-active to
high-active
+5VA
0.1u_0402
T40
*PAD
T44
*PAD
T43
T41
*PAD
*PAD
445759
GD4
GPIO13 / GD5
GPIO14 / GD6
GPIO15 / GD7
GD3 / ECLK / VOLDN#
AD5
AD4
AD3
AD2
AD1
AD0
38
AD5
AD0
AD2
AD1
AD4
AD3
606162
42
43584546474849
GD0
GD1 / EDOUT
GD2 / EDIN / VOLUP#
AD7
AD6
31323334353637
AD7
AD6
M3_RST_EN[35]
GPIO8 / SDI2
GPIO9 / SDFS2
GPIO10 / SCLK2
GPIO3 / SRESET2
GPIO6 / ISDATA / R0#
GPIO11 / SDO2 / VauxD
GPIO7 / MC97_DI / PCREQ# / VOLUP#
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
11
22232425262728
29
AD14
AD8
AD9
PCIRST#[6,11,16,18,28,30,31,41,51]
AD17
AD13
AD15
AD12
AD11
AD16
AD10
3.3VAUX
3
1988AC_RESET#
1988AC_DATAO
1988AC_SCLK_0 1988AC_SCLK
1988AC_SYNC
1988AC_DATAI1
1988MC_DATAI1
T29
*PAD
63
5051525356
GPIO4 / ISCLK / SIRQ#
GPIO5 / ISLR / GS0 / GT0#
GPIO12 / PCGNT# / GTO# / GS0
PME# / SPDIFO / VOLDN#
AD23
AD22
AD21
AD20
AD19
AD18
AD25
AD24
45678910
100
AD23
AD22
AD24
AD18
AD26
AD20
AD25
AD21
AD19
R356
10K
2
39
CLKRUN# / ECS
SPDIFO / R0# / IDSEL
DEVSEL#
AD31
AD30
AD29
AD28
AD27
AD26
93949596979899
AD29
AD31
AD28
AD27
AD30
C648
0.1u_0402
Q63
DTC144EU
1 3
VCC_1
VCC_2
VCC_3
AVDD1
VREF
REQ#
GNT#
PCICLK
RST#
C/BE3#
C/BE2#
C/BE1#
C/BE0#
STOP#
TRDY#
IRDY#
FRAME#
VAUX
INT#
PAR
2
1
1988AC_RESET# [30,41,51]
1988AC_DATAO [30,41,51]
1988AC_SYNC [30,41,51]
1988AC_DATAI1 [41]
1988MC_DATAI1 [30,51]
ZV_SDATA [29]
ZV_LRCLK [29]
ZV_SCLK [29]
CLKRUN# [11,28,30,31,41,51]
+3VD
90
41
12
+5VA
72
0.1u_0402
C544 0.1u_0402
74
C538 4.7u/10V_0805
92
91
88
87
-M3ERST
86
1
13
20
30
-APME
54
R276 100
2
19
18
17
16
15
14
55
3.3VAUX
U43
ES1988
AD19
3.3VAUX
5
4
U49
7SH32
3
2
C604
*22P
R339
22
C605
22P
1988AC_SCLK [30,41,51]
C2_0423: Change net name from<ZV_PCLK>
+3V
C563
L95
FBMJ2125HM330
C552
1u/6.3V_0603
C1_0328: Change to 0603
REQ3# [11]
GNT3# [11]
PCLK_AUD [3]
PIRQC# [11,41]
C/BE3# [11,28,30,41,51]
C/BE2# [11,28,30,41,51]
C/BE1# [11,28,30,41,51]
C/BE0# [11,28,30,41,51]
PAR [11,28,30,41,51]
STOP# [11,28,30,41,51]
DEVSEL# [11,28,30,41,51]
TRDY# [11,28,30,41,51]
IRDY# [11,28,30,41,51]
FRAME# [11,28,30,41,51]
3.3VAUX
R325
10K
AD[0..31] [11,28,30,41,51]
0.1u_0402
C598
C487
0.1u_0402
AUDGND
PCLK_AUD
Device ID is AD19
PIRQC#
REQ3#
GNT3#
2
1
C2_0517
PCLK_AUD
R257
*68
C486
*10P
Q54
2N7002E
1
3
PME# [11,28,30,41,51]
2
3.3VAUX
Size Document Number Rev
C
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
ESS ES1988
1
25 57Tuesday, September 11, 2001
3A
1
A A
B2_0323: Change to
Audio VCC and GND
+5VA
+5VA
B B
D4
1SS355
-D_SPKOFF[41]
AOUTR[25]
PCBEEP[39]
C2_0529: Change
C C
D D
21
AOUTL[25]
R288
22K
R303
680
R256
10K
2
AUDGND
R255
10K
1 3
C566
0.47u_X7R
C609
0.47u_X7R
PCBEEP_0
Q47
DTC144EU
AOUTR_2
AOUTL_2
SPKPLG
D_SPKOFF
+5VA
2
R54
10K
AUDGND
AUDGND
+5VA
+5VA
2
1
C625
C624
R330 33K
3
R296 0_0805
R308 0_0805
R165 0
R681 *0
AOUTL_3AOUTL_4
AOUTR_4
AOUTR_3
AOUTL_4
AOUTL_3
AUDGND
Audio amplifier
23
5
8
20
10
6
2
3
PCBEEP_1
14
15
17
22
C565
47nF
U45
LINE_INR
LINE_INL
R_IN+
R_HP_IN
L_IN+
L_HP_IN
ITSENSE
VOLCRTL
PC-BEEP
SE/-BTL
CLK
-SHDN
AUDGND_5
AUDGND_6
303132
AUDGND_7
AUDGND_8
33
AUDGND
Ramp_0626:
Add
C64
U12
7SH32
1u/6.3V_0603
1u/6.3V_0603
-MUTE
2
4
AUDGND
0.1u
R331
0
3
1
C2_0517
AOUTR_4 AOUTR_3
R306
10K
R341
10K
R305
15K
R342
15K
C559 1u/6.3V_0603
SE/-BTL
R304
+5VA
10K
Q57
2N7002E
5
3
4
Ramp_0626:
Change to 0603
21
R_OUT+
16
R_OUT-
4
L_OUT+
9
L_OUT-
7
PVDD_1
18
PVDD_2
19
VDD
11
BYPASS
1
GND_1
12
GND_2
13
GND_3
24
GND_4
AUDGND AUDGNDAUDGND
AUDGND_9
AUDGND_10
AUDGND_11
AUDGND_12
AUDGND_13
TPA0132
2526272829
5
R343
1M
VIN
R355
100K
5VPCU
5VPCU
C647
0.1u_0402
5
C608
AUDGND
1
4
2
U50
TC7SH08FU
3
SPK_ROUT+
L89BK1608HS241-T
SPK_ROUT-
L96BK1608HS241-T
SPK_LOUT+
L90BK1608HS241-T
SPK_LOUT-
L97BK1608HS241-T
C540
0.1u_0402
+5VA
C541
0.1u_0402 Q45
-VOLMUTE[34]
-MUTE_BTN[35,40]
0.1u_0402
C607
0.47u_X7R
2
AUDGND AUDGND
2
Q62
DTC144EU
1 3
AUDGND
-MUTE
2
-MUTE
2
Q53
2N7002E
SPK_ROUT- SPKR-IN
3
-MUTE
Q56
2N7002E
3
-MUTE
-MUTE
Q60
DTC144EU
1 3
C2_0517
3
1
3
1
2
2
Q44
2N7002E
2N7002E
SPKL+IN
Q34
2N7002E
SPKR+IN
Q35
2N7002E
-MUTE
1
SPKL-INSPK_LOUT-
1
6
C610
0.1u_X7R
3
-MUTE
3
AUDGND
R598
220K
7
R163
SPKPLG
2
Q29
DTC144EU
C40
1
1 2
R595
220K
1
SPKR+IN [40]
1 2
SPKL+IN [40]
SPKR-IN [40]
SPKL-IN [40]
SPKL
SPKR
100U/6.3V_6032
C41
100U/6.3V_6032
SPKR
SPKL
L115
BK1608HS241-T
L116
BK1608HS241-T
AUDGND
2
2
AUDGND
SPKL_01
SPKR_01
C875
470P
1 3
C879
470P
L117
BK1608HS241-T
100K
2
3
2
3
SPKL_GND
SPKPLG
Q31
2N7002E
1
Q36
2N7002E
1
2
6
3
4
5
AUDGND
1
CON22
JA6333L-1S0
7
8
8
12V
SPKR_DK [41]
SPKL_DK [41]
LINE OUT
C2_0517
Size Document Number Rev
C
1
2
3
4
5
6
Date: Sheet of
7
PROJECT : RT2.0
Quanta Computer Inc.
AMP/line out
8
26 57Tuesday, September 11, 2001
3A
1
2
3
4
5
6
+5VA
7
8
R480
9.1K
A A
B B
-D_MICOFF[41]
C C
CD_LINL[25]
CD_LINR[25]
CD_COM[25]
CD_LINL
CD_LINR
CD_COM
MICPLG
D8
1SS355
1u/6.3V_0603
1u/6.3V_0603
+5V
R471
10K
R470
10K
21
2
C533 1u/6.3V_0603
C462
1u/6.3V_0603
C545
1u/6.3V_0603
C463
R284
47K
+5V+5V
R203
1 3
47K
R145
10K
D_MICOFF
Q26
DTC144EU
R205
R287
47K
2
1
CD_AUX_LINL_1
CD_AUX_LINR_1
R271
47K
47K
+5V
5
3
CD_LINL_1
CD_LINR_1
CD_COM_1
4
U66
7SH32
R279 0
R202 0
C823
0.1u_0402
2
Q28
DTC144EU
R503
10K
+5V
0.1u_0402
1 3
0.1u_0402
+5VA
C472
MICGND
+5VA
C331
MICGND
CD_D_CDL [41]
CD_D_CDR [41]
CD_L [17]
CD_R [17]
CD_GND [17]
U40
5
4 3
5
4 3
VCC
OUT
CTL GND
TC4S66F
U28
VCC
OUT
CTL GND
TC4S66F
LINE_IN_L[25]
LINE_IN_R[25]
IN
IN
1
2
1
2
MIC_INT
MICGND
MICGND
MIC_INT [40]
1u/6.3V_0603
C59
1u/6.3V_0603
C62
1u/6.3V_0603
C61
C60
1u/6.3V_0603
MIC_D[41]
R294 1K
MIC1_3
LINER_1
LINEL_1
LINEL_2
LINER_2
R43
220K
R44
220K
MIC1_1MIC1_2
L112
BK1608HS241-T
R566
0
R45
220K
AUDGND
R481
100K
MICGND
0.47u_X7R
C557
C857
0.47u_X7R
Ramp_0620: Load
MICGNDAUDGND
R30 470
R33 470
R32 470
R31 470
R42
220KC521
B2_0324: Del R292, R204, R269
AUDGND
D D
Short directly
+5VA +5VA
Q25
2
MBT3904
1 3
C821
1u_0805
R500
2.2K
MIC1_5
C860
180P
MICGND
MICGND
LINER_3
L109
BK1608HS241-T
L111
BK1608HS241-T
L113
BK1608HS241-T
LINE IN
AUDGND
AUDGND
L110
BK1608HS241-T
MIC1_4
LINEL_4LINEL_3
LINER_4
C842
180P
2
MIC1 [25]
C858
180P
MICGND_0
LINER_D [41]
LINEL_D [41]
C846
180P
AUDGND_0
Q27
MBT3904
1 3
R501
2.2K
Pink
1
2
6
3
4
5
AUDGND
MICPLG
EXTERNAL MIC
Blue
1
2
6
3
4
5
7
AUDGND
AUDGND
C2_0517
CON20
7
8
JA6333L-1S0 PINK
C2_0517
CON19
8
JA6333L-1S0 BLUE
Size Document Number Rev
B
1
2
3
4
5
6
Date: Sheet of
line in/mic in/CD audio in
7
PROJECT : RT2.0
Quanta Computer Inc.
27 57Tuesday, September 11, 2001
8
2B
1
2
3
4
VAUXPCIC
5
6
7
8
C2_0425: Add
R669
47K
GNT2#[11]
REQ2#[11]
C/BE3#[11,25,30,41,51]
C/BE2#[11,25,30,41,51]
C/BE1#[11,25,30,41,51]
C/BE0#[11,25,30,41,51]
TRDY#[11,25,30,41,51]
IRDY#[11,25,30,41,51]
STOP#[11,25,30,41,51]
PERR#[11,30,41,51]
SERR#[11,30,41,51]
PAR[11,25,30,41,51]
3
PCBA14
PCBA15
PCBA16
PCBA19
PCBA20
PCBA21
PCBA22
B_BVD1
B_BVD2
-B_CD1
-B_CD2
B_RDY
-B_WAIT
B_WP
-B_INPACK
B_VS1
B_VS2
B_RESET
U51
RST#
VCC
GND
MAX6326UR29
PCLK_PCIC
-PCICGRST
C6B6A6F7A7B7A14C7F8
A11
PAR
SERR#
W10
B_D0/CAD27
U10
B_D1/CAD29
P10
B_D2/RSVD
H2
B_D3/CAD0
J1
B_D4/CAD1
J3
B_D5/CAD3
K1
B_D6/CAD5
K3
B_D7/CAD7
V10
B_D8/CAD28
R10
B_D9/CAD30
W11
B_D10/CAD31
H1
B_D11/CAD2
J2
B_D12/CAD4
J6
B_D13/CAD6
K2
B_D14/RSVD
K5
B_D15/CAD8
R8
B_A0/CAD26
W7
B_A1/CAD25
V7
B_A2/CAD24
W6
B_A3/CAD23
V6
B_A4/CAD22
U6
B_A5/CAD21
V5
B_A6/CAD20
U5
B_A7/CAD18
N1
B_A8/CC/BE1#
M3
B_A9/CAD14
L1
B_A10/CAD9
M1
B_A11/CAD12
T1
B_A12/CC/BE2#
N3
B_A13/CPAR
P1
B_A14/CPERR#
P5
B_A15/CIRDY#
P6
B_A16/CCLK
M6
B_A17/CAD16
N2
B_A18/RSVD
N6
B_A19/CBLOCK#
N5
B_A20/CSTOP#
R1
B_A21/CDEVSEL#
R2
B_A22/CTRDY#
R3
B_A23/CFRAME#
W4
B_A24/CAD17
R6
B_A25/CAD19
V9
B_BVD1/CSTSCHG
W9
B_BVD2/CAUDIO
H3
B_CD1#/CCD1#
R9
B_CD2#/CCD2#
V8
B_READY/CINT#
W8
B_WAIT#/CSERR#
U9
B_WP/CCLKRUN#
R7
B_INPACK/CREQ#
K6
B_CE1#/CC/BE0#
L2
B_CE2#/CAD10
P3
B_WE#/CGNT#
L5
B_IORD#/CAD13
M2
B_IOWR#/CAD15
L6
B_OE#/CAD11
U8
B_VS1#/CVS1
P7
B_VS2#/CVS2
P8
B_REQ#/CC/BE3#
W5 L18
B_RESET/CRST# A_RESET/CRST#
R363
*68
C651
*10P
-PCICGRST
1
2
GRST#
AD0
AD1
AD2
AD3
H5G1G3H6F1G5F2E1G6F5E3
AD3
AD1
AD0
AD2
-PCICGRST [29]
STOP#
PERR#
AD4
AD5
AD5
AD6
AD4
IRDY#
PRST#
TRDY#
DEVSEL#
AD6
AD7
AD8
AD9
AD9
AD8
AD10
AD7
A10E2A5C8A15
PCLK
C/BE0#
C/BE1#
C/BE2#
C/BE3#
FRAME#
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
C12A4E6B5F6B8A8E9F9B9A9
AD14
AD11
AD16
AD13
AD12
AD15
AD17
PIRQA#[11,41]
ZVEN[29]
B13
REQ#
AD18
AD19
AD18
AD20
AD19
AD21
C13
F14
E19
GNT#
DATA
AD20
AD21
AD22
AD23
F10
E10
F11
AD21
AD24
AD22
AD23
R364 100
F17
G15
LATCH
CLOCK
SPKROUT
AD24
AD25
AD26
AD27
AD28
E13
C11
B11
A12
AD26
AD28
AD25
AD27
-B_INPACK[29]
B_RESET[29]
PCBD0[29]
PCBD1[29]
PCBD2[29]
PCBD3[29]
PCBD4[29]
PCBD5[29]
PCBD6[29]
PCBD7[29]
PCBD8[29]
PCBD9[29]
PCBD10[29]
PCBD11[29]
PCBD12[29]
PCBD13[29]
PCBD14[29]
PCBD15[29]
PCBA0[29]
PCBA1[29]
PCBA2[29]
PCBA3[29]
PCBA4[29]
PCBA5[29]
PCBA6[29]
PCBA7[29]
PCBA8[29]
PCBA9[29]
PCBA10[29]
PCBA11[29]
PCBA12[29]
PCBA13[29]
PCBA14[29]
PCBA15[29]
PCBA17[29]
PCBA18[29]
PCBA19[29]
PCBA20[29]
PCBA21[29]
PCBA22[29]
PCBA23[29]
PCBA24[29]
PCBA25[29]
B_BVD1[29]
B_BVD2[29]
-B_CD1[29]
-B_CD2[29]
B_RDY[29]
-B_WAIT[29]
B_WP[29]
-B_CE1[29]
-B_CE2[29]
-B_WE[29]
-BIORD[29]
-BIOWR[29]
-BOE[29]
B_VS1[29]
B_VS2[29]
-BREG[29]
VAUXPCIC
PCLK_PCIC[3]
FRAME#[11,25,30,41,51]
DEVSEL#[11,25,30,41,51]
PCIRST#[6,11,16,18,25,30,31,41,51]
PCLK_PCIC
AD[0..31][11,25,30,41,51]
A A
B B
C C
D D
F18
VCCI
AD29
B12
E12
AD29
AD30
D1
E11
VCCP1
VCCP2
AD30
AD31
A13
C10
AD31
VAUXPCIC
B14C9E7F3G19L3N15U7W12
VCC1
VCC2
VCC3
VCC4
VCC5
IDSEL
IRQ3/INTA#
IRQ4/INTB#
SUSPEND#
IRQ7/DMAREQ#
F15
E17
D19
A16
C970
0.1u_0402
VCC6
VCC7
VCC8
VCC9
IRQ9/IRQSER
IRQ10/SCL
IRQ11/DMAGNT#
CLKRUN#
C15
E14
F13
B15
R375
10K
SERDATA [29]
SUSCLK [12,29]
SERLATCH [29]
-PCICSPK [39]
L100 FBMJ2125HM330
B_VCC
M5
VCCB
RIOUT#/PME#
GND1
GND2
C14
B10C5E8
VAUXPCIC
GND3
A_VCC
M17
VCCA
GND4
E18
GND5
F12G2J5
C2_0510: Add
A_D0/CAD27
A_D1/CAD29
A_D2/RSVD
A_D3/CAD0
A_D4/CAD1
A_D5/CAD3
A_D6/CAD5
A_D7/CAD7
A_D8/CAD28
A_D9/CAD30
A_D10/CAD31
A_D11/CAD2
A_D12/CAD4
A_D13/CAD6
A_D14/RSVD
A_D15/CAD8
A_A0/CAD26
A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A7/CAD18
A_A8/CC/BE1#
A_A9/CAD14
A_A10/CAD9
A_A11/CAD12
A_A12/CC/BE2#
A_A13/CPAR
A_A14/CPERR#
A_A15/CIRDY#
A_A16/CCLK
A_A17/CAD16
A_A18/RSVD
A_A19/CBLOCK#
A_A20/CSTOP#
A_A21/CDEVSEL#
A_A22/CTRDY#
A_A23/CFRAME#
A_A24/CAD17
A_A25/CAD19
A_BVD1/CSTSCHG
A_BVD2/CAUDIO
A_CD1#/CCD1#
A_CD2#/CCD2#
A_READY/CINT#
A_WAIT#/CSERR#
A_WP/CCLKRUN#
A_INPACK/CREQ#
A_CE1#/CC/BE0#
A_CE2#/CAD10
A_WE#/CGNT#
A_IORD#/CAD13
A_IOWR#/CAD15
A_OE#/CAD11
A_VS1#/CVS1
A_VS2#/CVS2
A_REQ#/CC/BE3#
GND6
GND7
GND8
GND9
GND10
K18P2P9
V14
C971
0.1u_0402
GND11
VAUXPCIC
C627
C644
C696
C601
0.1u_0402
0.1u_0402
C674
C673
0.1u_0402
0.1u_0402
PCAD0 [29]
PCAD1 [29]
PCAD2 [29]
PCAD3 [29]
PCAD4 [29]
PCAD5 [29]
PCAD6 [29]
PCAD7 [29]
PCAD8 [29]
PCAD9 [29]
PCAD10 [29]
PCAD11 [29]
PCAD12 [29]
PCAD13 [29]
PCAD14 [29]
PCAD15 [29]
PCAA0 [29]
PCAA1 [29]
PCAA2 [29]
PCAA3 [29]
PCAA4 [29]
PCAA5 [29]
PCAA6 [29]
PCAA7 [29]
PCAA8 [29]
PCAA9 [29]
PCAA10 [29]
PCAA11 [29]
PCAA12 [29]
PCAA13 [29]
PCAA14 [29]
PCAA15 [29]
PCAA17 [29]
PCAA18 [29]
PCAA19 [29]
PCAA20 [29]
PCAA21 [29]
PCAA22 [29]
PCAA23 [29]
PCAA24 [29]
PCAA25 [29]
A_BVD1 [29]
A_BVD2 [29]
-A_CD1 [29]
-A_CD2 [29]
A_RDY [29]
-A_WAIT [29]
A_WP [29]
-A_INPACK [29]
-A_CE1 [29]
-A_CE2 [29]
-A_WE [29]
-AIORD [29]
-AIOWR [29]
-AOE [29]
A_VS1 [29]
A_VS2 [29]
-AREG [29]
A_RESET [29]
VAUXPCIC
CLKRUN# [11,25,30,31,41,51]
GNTB# [11]
-PCICRI [38]
SERIRQ [11,31,41]
REQB# [11]
PCA16[29]
2
3
3.3VAUX
U52
H14
G18
G14
U11
R11
U12
R12
V13
H15
G17
F19
P11
V12
P12
W13
U13
J19
K14
K15
K19
L15
L17
L19
M15
W16
R14
W14
P14
N18
R17
N14
M14
P18
U15
T19
P15
R18
P17
P19
N17
N19
M18
H19
J15
V11
H17
J17
J14
H18
L14
P13
R13
R19
W15
V15
U14
J18
M19
K17
PCI1420GHK
VAUXPCIC
PCAA14
PCAA15
PCAA16
PCAA19
PCAA20
PCAA21
PCAA22
A_BVD1
A_BVD2
-A_CD1
-A_CD2
A_RDY
-A_WAIT
A_WP
-A_INPACK
A_VS1
A_VS2
A_RESET
0.1u_0402
C664
0.1u_0402
VAUXPCIC
R368
10K
0.1u_0402
C646
0.1u_0402
1
Q67 2N7002E
Device ID is AD21
SERIRQ
PIRQA#
C600
C626
0.1u_0402
0.1u_0402
C689
C652
0.1u_0402
0.1u_0402
B_VCC
PCBA22 B_BVD1
PCBA15 -B_WAIT
-B_INPACK B_BVD2
B_RESET
PCB16[29]
A_VCC
A_BVD2
-A_WAIT
-A_INPACK
PCAA15
PME# [11,25,30,41,51]
C602
1000P
VAUXPCIC
RP16
10
9
8
7 4
10P8R_47K
RP15
7 8
5
3
1
8P4R_47K
R361 47K
R360 22
C645 22P
RP21
10
9
8
7 4
10P8R_47K
RP18
1
3
5
7 8
8P4R_47K
R374 47K
R371 22
C685 22P
C599
4.7u/10V_0805
1
2
3
56
6
4
2
1
2
3
56
2
4
6
B_WP
PCBA19
PCBA20
PCBA14
PCBA21
B_RDY
PCBA16
A_RESET
A_WP
PCAA22
A_BVD1
PCAA19
PCAA14
PCAA20
PCAA21
A_RDY
PCAA16
C603
0.1u_0402
-B_CD2
B_VS1
B_VS2
-B_CD1
A_VCCB_VCC
C693
C700
0.1u_0402
1000P
C679
C684
4.7u/10V_0805
1u/6.3V_0603
C1_0328: Change to 0603
VAUXPCIC
RP17
10P8R_47K
-A_CD1
1
-A_CD2
2
A_VS1
3
A_VS2
56
10
9
8
7 4
REQ2#
GNT2#
REQB#
GNTB#
1
2
3
4
5
6
Size Document Number Rev
C
Date: Sheet of
7
PROJECT : RT2.0
Quanta Computer Inc.
TI1420 CARDBUS CONTROLLER
28 57Tuesday, September 11, 2001
8
3A
1
C672
C219
0.1u_0402
0.1u_0402
C721
4.7u/10V_0805
ZV_Y[0..7][18]
ZV_HREF[18]
ZV_VREF[18]
ZV_UV[0..7][18]
VAUXPCIC
A A
SERDATA[28]
SUSCLK[12,28]
SERLATCH[28]
-PCICGRST[28]
B B
C C
5VSUS
C671
4.7u/10V_0805
2
12VSUS
7
24
1
2
30
15
16
17
3
4
5
14
6
13
19
18
12
C682
0.1u_0402
U55
12V_1
12V_2
5V_1
5V_2
5V_3
3V_1
3V_2
3V_3
DATA
CLOCK
LATCH
/RESET
RESET
/APWR_GOOD
STBY
/OC
GND
TPS2216
ZV_HREF
ZV_VREF
ZV_Y0
ZV_Y2
ZV_Y1
ZV_Y4
ZV_Y3
ZV_Y6
ZV_Y5
ZV_Y7
ZV_UV0
ZV_UV2
ZV_UV1
ZV_UV4
ZV_UV3
ZV_UV6
R340
R316
3
25
N.C
8
AVPP
9
AVCC_1
10
AVCC_2
11
AVCC_3
23
BVPP
20
BVCC_1
21
BVCC_2
22
BVCC_3
26
N.C_1
N.C_2
N.C_3
MODE
2
3
4
5
6
7
8
9
19
1
4.7K
2
3
4
5
6
7
8
9
19
1
4.7K
U48
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
74LVC245
U46
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
74LVC245
R370
27
100K
28
29
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
B8
20
VCC
10
GND
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
B8
20
VCC
10
GND
VAUXPCIC
PCAA10
PCAA11
PCAA9
PCAA8
PCAA17
PCAA13
PCAA18
PCAA14
C612
0.1u_0402
PCAA19
PCAA20
PCAA21
PCA16
PCAA22
PCAA15
PCAA23
PCAA12
C583
0.1u_0402
C699
0.1u_0402
C571 1000P
C572 1000P
C240 1000P
C729 1000P
VAUXPCIC
VAUXPCIC
C683
0.1u_0402
C691
1000P
4
-B_CD1
-A_CD1
-A_CD2
-B_CD2
C709
0.1u_0402
C690
0.1u_0402
C698
1000P
A_VPP
A_VCC
B_VPP
B_VCC
5
PCBD3[28]
-B_CD1[28]
PCBD4[28]
PCBD11[28]
PCBD5[28]
PCBD12[28]
PCBD6[28]
PCBD13[28]
PCBD7[28]
PCBD14[28]
-B_CE1[28]
PCBD15[28]
PCBA10[28]
-B_CE2[28]
-BOE[28]
B_VS1[28]
PCBA11[28]
-BIORD[28]
PCBA9[28]
-BIOWR[28]
PCBA8[28]
PCBA17[28]
PCBA13[28]
PCBA18[28]
PCBA14[28]
PCBA19[28]
-B_WE[28]
PCBA20[28]
B_RDY[28]
PCBA21[28]
B_VCC
B_VPP
PCB16[28]
PCBA22[28]
PCBA15[28]
PCBA23[28]
PCBA12[28]
PCBA24[28]
PCBA7[28]
PCBA25[28]
PCBA6[28]
B_VS2[28]
PCBA5[28]
B_RESET[28]
PCBA4[28]
-B_WAIT[28]
PCBA3[28]
-B_INPACK[28]
PCBA2[28]
-BREG[28]
PCBA1[28]
B_BVD2[28]
PCBA0[28]
B_BVD1[28]
PCBD0[28]
PCBD8[28]
PCBD1[28]
PCBD9[28]
PCBD2[28]
PCBD10[28]
B_WP[28]
-B_CD2[28]
6
CON9
B1
GND1
B2
GND2
B3
D3
B4
CD1#
B5
D4
B6
D11
B7
D5
B8
D12
B9
GND3
B10
D6
B11
D13
B12
D7
B13
D14
B14
CE1#
B15
D15
B16
GND4
B17
A10
B18
CE2#
B19
OE#
B20
VS1#
B21
A11
B22
GND5
B23
IORD#
B24
A9
B25
IOWR#
B26
A8
B27
A17
B28
GND6
B29
A13
B30
A18
B31
A14
B32
A19
B33
WE#
B34
A20
B35
RDY
B36
A21
B37
VCC1
B38
VCC2
B39
VPP1
B40
VPP2
B41
A16
B42
GND7
B43
A22
B44
A15
B45
A23
B46
A12
B47
A24
B48
A7
B49
GND8
B50
A25
B51
A6
B52
VS2#
B53
A5
B54
RESET
B55
A4
B56
WAIT#
B57
GND9
B58
A3
B59
INPACK#
B60
A2
B61
REG#
B62
A1
B63
BVD2
B64
A0
B65
GND10
B66
BVD1
B67
D0
B68
D8
B69
D1
B70
D9
B71
D2
B72
D10
B73
GND11
B74
WP
B75
CD2#
B76
GND12
B77
GND13
BREGCARDBUS
C
D
GND27
GND28
IOWR#_1
RESET_1
INPACK#_1
GND29
GND30
E
F
GND14
GND15
D3_1
CD1#_1
D4_1
D11_1
D5_1
D12_1
GND16
D6_1
D13_1
D7_1
D14_1
CE1#_1
D15_1
GND17
A10_1
CE2#_1
OE#_1
VS1#_1
A11_1
GND18
IORD#_1
A9_1
A8_1
A17_1
GND19
A13_1
A18_1
A14_1
A19_1
WE#_1
A20_1
RDY_1
A21_1
VCC3
VCC4
VPP3
VPP4
A16_1
GND20
A22_1
A15_1
A23_1
A12_1
A24_1
A7_1
GND21
A25_1
A6_1
VS2#_1
A5_1
A4_1
WAIT#_1
GND22
A3_1
A2_1
REG#_1
A1_1
BVD2_1
A0_1
GND23
BVD1_1
D0_1
D8_1
D1_1
D9_1
D2_1
D10_1
GND24
WP_1
CD2#_1
GND25
GND26
7
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
PCAD3 [28]
-A_CD1 [28]
PCAD4 [28]
PCAD11 [28]
PCAD5 [28]
PCAD12 [28]
PCAD6 [28]
PCAD13 [28]
PCAD7 [28]
PCAD14 [28]
-A_CE1 [28]
PCAD15 [28]
PCAA10 [28]
-A_CE2 [28]
-AOE [28]
A_VS1 [28]
PCAA11 [28]
-AIORD [28]
PCAA9 [28]
-AIOWR [28]
PCAA8 [28]
PCAA17 [28]
PCAA13 [28]
PCAA18 [28]
PCAA14 [28]
PCAA19 [28]
-A_WE [28]
PCAA20 [28]
A_RDY [28]
PCAA21 [28]
A_VCC
A_VPP
PCA16 [28]
PCAA22 [28]
PCAA15 [28]
PCAA23 [28]
PCAA12 [28]
PCAA24 [28]
PCAA7 [28]
PCAA25 [28]
PCAA6 [28]
A_VS2 [28]
PCAA5 [28]
A_RESET [28]
PCAA4 [28]
-A_WAIT [28]
PCAA3 [28]
-A_INPACK [28]
PCAA2 [28]
-AREG [28]
PCAA1 [28]
A_BVD2 [28]
PCAA0 [28]
A_BVD1 [28]
PCAD0 [28]
PCAD8 [28]
PCAD1 [28]
PCAD9 [28]
PCAD2 [28]
PCAD10 [28]
A_WP [28]
-A_CD2 [28]
8
C2_0423: Swap
4
A_VCC
C179
1000P
B_VCC
C661
4.7u/10V_0805
5
6
C187
4.7u/10V_0805
Size Document Number Rev
C
Date: Sheet of
7
PROJECT : RT2.0
Quanta Computer Inc.
CARDBUS interface
29 57Tuesday, September 11, 2001
8
1A
R380
U56
2
A1
B1
3
A2
B2
4
A3
B3
5
A4
B4
6
A5
B5
7
A6
B6
8
A7
B7
9
A8
B8
19
G
VCC
1
DIR
GND
74LVC245
4.7K
PCAA24
18
A_WPZV_PCLK
17
PCAA25
16
15
14
13
A_BVD2ZV_SDATA
12
PCAA7
11
20
10
3
VAUXPCIC
C723
0.1u
C2_0424:
0402 -> 0603
ZV_PCLK[18]
ZV_LRCLK[25]
ZV_SDATA[25]
ZV_SCLK[25]
C2_0423: Swap net name
ZVEN[28]
D D
1
ZV_UV5
ZV_UV7
ZV_LRCLK -A_INPACK
ZV_SCLK
VAUXPCIC
R383
10K
2
5
Q59
2N7002E
3
3.3VAUX
1988AC_RESET#
1988AC_SYNC
1988AC_SCLK
1988MC_DATAI1
1988AC_DATAO
PCLK_MINI
AD[0..31]
PIRQB#
PIRQD#
REQ1#
GNT1#
PCIRST#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
SERR#
PERR#
CLKRUN#
2
-MODEM_RI
MODEMSPK
3.3VAUX
1
R329
33
C597
22P
R333
10K
MINIPCI_PME#
E E
D D
C C
B B
AD[0..31][11,25,28,41,51]
PIRQB#[11,18,41,51]
PIRQD#[11,41,51]
REQ1#[11]
GNT1#[11]
PCIRST#[6,11,16,18,25,28,31,41,51]
C/BE0#[11,25,28,41,51]
C/BE1#[11,25,28,41,51]
C/BE2#[11,25,28,41,51]
C/BE3#[11,25,28,41,51]
FRAME#[11,25,28,41,51]
IRDY#[11,25,28,41,51]
TRDY#[11,25,28,41,51]
DEVSEL#[11,25,28,41,51]
STOP#[11,25,28,41,51]
PAR[11,25,28,41,51]
SERR#[11,28,41,51]
PERR#[11,28,41,51]
CLKRUN#[11,25,28,31,41,51]
PME#[11,25,28,41,51]
1988AC_RESET#[25,41,51]
1988AC_SYNC[25,41,51]
1988AC_SCLK[25,41,51]
1988MC_DATAI1[25,51]
1988AC_DATAO[25,41,51]
-MODEM_RI[38,51]
MODEMSPK[39,51]
PCLK_MINI[3]
USB_CONNECT[35]
AGND_MINI1
4
RF_ENABLE[35]
USBP2+[12]
L119
BK1608HS241-T
R302 0
AGND_MINI1
3
+3V
CON24
1
TIP
3
LAN1
5
R624 0
R623 0
PIRQB#
PCLK_MINI
REQ1#
AD31
AD29
AD27
AD25
C/BE3# AD24
AD23
AD21
AD19
AD17
C/BE2#
IRDY#
CLKRUN#
SERR#
PERR#
C/BE1#
AD14
AD12
AD10
AD8
AD7
AD5
AD3
+5V
AD1
1988AC_SYNC
1988MC_DATAI1
1988AC_SCLK
MODEMSPK
-MODEM_RI
+5V
+3V+5V 3.3VAUX
GND
LAN3
7 8
LAN5 LAN6
9 10
LAN7 LAN8
11 12
LED_GP LED_YP
13 14
LED_GN LED_YN
15
NC1
17 18
-INTB +5V_1
19 20
+3V_0 -INTA
21 22
R(IRQ3) R(IRQ4)
23 24
GND_1 +3VAUX_1
25 26
PCICLK -RST
27 28
GND_2 +3V_3
29 30
-REQ -GNT
31 32
+3V_1 GND_9
33 34
AD31 -PME
35 36
AD29 (V)_3
37 38
GND_3 AD30
39 40
AD27 +3V_4
43
(V)_1
45 46
-CBE3 AD24
47 48
AD23 IDSEL
49 50
GND_4 GND_10
51 52
AD21 AD22
53 54
AD19 AD20
55 56
GND PAR
57 58
AD17 AD18
59 60
-CBE2 AD16
61 62
-IRDY GND_11
63 64
+3V -FRAME
65 66
-CLKRUN -TRDY
67 68
-SERR -STOP
69 70
GND_5 +3V_5
71 72
-PERR -DEVSEL
73 74
-CBE1 GND_12
75 76
AD14 AD15
77 78
GND_6 AD13
79 80
AD12 AD11
81 82
AD10 GND_13
83 84
GND_7 AD9
85 86
AD8 -CBE0
87 88
AD7 +3V_6
89 90
+3V_2 AD6
91 92
AD5 AD4
93 94
(V)_2 AD2
95 96
AD3 AD0
97 98
+5V_0 (V)_4
99 100
AD1 SERIRQ
101 102
GND_8 GND_14
103 104
SYNC M66EN
105 106
SDIN0 SDOUT
107 108
BITCLK SDIN1
109 110
-AC_PRIMARY -RESET
111 112
BEEP -MPCICACK
113 114
AGND_1 AGND_3
115 116
+MIC +SPK
117 118
-MIC -SPK
119 120
AGND_2 AGND_4
121 122
-RI NC4
123 124
+5VA +3VAUX_2
GND_15
125
126
RING
LAN2
LAN4
AD28AD25
AD26
GND_16
MINIPCI_5.2
NC2
2
4
6
16
4241
44
2
Ramp_0620: Change from pin8,10 to pin4,6.
+3V
+5V
3.3VAUX
MINIPCIID
1988AC_DATAO
1988AC_RESET#
AGND_MINI1
PIRQD#
PCIRST#
GNT1#
MINIPCI_PME#
AD30
AD28
AD26
R359 100
AD22
AD20
PAR
AD18
AD16
FRAME#
TRDY#
STOP#
DEVSEL#
AD15
AD13
AD11
AD9
C/BE0#
AD6
AD4
AD2
AD0
3.3VAUX
1
R318 0
R622 0
R311 0
USBP2-USBP2-_1USBP2+_1
USBP2- [12]
USB_DISCONN [35]
USB_RESET [35]
ACTIVE LO OR HI?
AD20
Device ID is AD20
PIRQB#
PIRQD#
GNT1#
REQ1#
C717
0.1u_0402
A A
C733
0.1u
1u/6.3V_0603
C2_0424:
0402 -> 0603
5
4
C590
C697
0.1u_0402
C663
0.1u_0402
3
C623
0.1u_0402
C596
0.1u_0402
1u/6.3V_0603
C711
C2_0517
C1_0328: Change to 0603 from 0805
C592
0.1u_0402
2
C748
1u/6.3V_0603
Size Document Number Rev
B
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
MINI PCI interface
30 57Tuesday, September 11, 2001
1
3A
A
B
C
D
E
+3V
R469
10K
4 4
3 3
2 2
1 1
LPC_PD#[12]
KBSMI#[12,34]
PCLK_SIO[3]
PCIRST#[6,11,16,18,25,28,30,41,51]
LFRAME#/FWH4[12]
LPC_DRQ0#[12]
14M_SIO[3]
CLKRUN#[11,25,28,30,41,51]
SERIRQ[11,28,41]
DIRTX[33]
DIRRX1[33]
DIRRX2[33]
LAD0/FWH0[12]
LAD1/FWH1[12]
LAD2/FWH2[12]
LAD3/FWH3[12]
DSKCHG#[17,41]
HEAD#[17,41]
RDATA#[17,41]
WP#[17,41]
TRK0#[17,41]
WGATE#[17,41]
WDATA#[17,41]
STEP#[17,41]
DIR#[17,41]
FDDDRV0#[17]
MTR0#[17]
INDEX#[17,41]
FDDDRV1#[41]
MTR1#[41]
PD[0..7][32,41]
SLCT[32,41]
PE[32,41]
BUSY[32,41]
ACK#[32,41]
SLIN#[32,41]
INIT#[32,41]
ERROR#[32,41]
AFD#[32,41]
STRB#[32,41]
-PNF[32]
DCD1#[33]
DSR1#[33]
RXD1[33]
RTS1#[33]
TXD1[33]
CTS1#[33]
DTR1#[33]
RI1#[33]
XA[0..18][34]
AEN[34]
XMEMW#[34]
XMEMR#[34]
XIOW#[34]
XIOR#[34]
XIOCHRDY[34]
IRQ1[34]
IRQ12[34]
A
D28 1SS355
DIRTX
DIRRX1
DIRRX2
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
FDDDRV0#
FDDDRV1#
DCD1#
DSR1#
RXD1
RTS1#
TXD1
CTS1#
DTR1#
RI1#
Q79
*DTC144EU
PCLK_SIO
PCIRST#
LFRAME#/FWH4
LPC_DRQ0#
14M_SIO
CLKRUN#
SERIRQ
DSKCHG#
HEAD#
RDATA#
WP#
TRK0#
WGATE#
WDATA#
STEP#
DIR#
MTR0#
INDEX#
MTR1#
SLCT
PE
BUSY
ACK#
SLIN#
INIT#
ERROR#
AFD#
STRB#
-PNF
AEN
21
+3V
2
LPC_PD#_1
13
+3V +3V
R476
10K
KBSMI#_1
R465
*68
C802
*10P
+3V
R468
10K
R493
10K
+3V
PCLK_SIO
14M_SIO
R460
*68
C799
*10P
R494
10K
XMEMW#
XMEMR#
XIOW#
XIOR#
XIOCHRDY
IRQ1
IRQ12
B
AEN
+3V
C792
10U/25V_1206
R491
10K
C806
0.1u_0402
C807
0.1u_0402
+3V
+3V
C
C825
0.1u_0402
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
PCLK_SIO
PCIRST#
LFRAME#/FWH4
LPC_DRQ0#
LPC_PD#_1
CLKRUN#
SERIRQ
KBSMI#_1
14M_SIO
DSKCHG#
RDATA#
WP#
TRK0#
WGATE#
WDATA#
STEP#
DIR#
FDDDRV0#
MTR0#
INDEX#
XA0
XA1
XA2
XA3
R492 *10K
IRQ1
IRQ12
R486 10K
XIOR#
XIOW#
XA12
XA13
XA14
XA15
XA16
XA17
XA18
INDEX#
TRK0#
WP#
RDATA#
DSKCHG#
T69*PAD
R441
1K
1
3
5
7 8
RP28
8P4R_1K
Super I/O
U65
15
LAD0
16
LAD1
17
LAD2
18
LAD3
8
LCLK
9
LRESET#
12
LFRAME#
11
LDRQ#
7
LPCPD#
6
CLKRUN#/GPIO36
10
SERIRQ
19
SMI#/GPIO35
20
CLKIN
21
DSKCHG#
22
HDSEL#
23
RDATA#
24
WP#
25
TRK0#
26
WGATE#
27
WDATA#
28
SETP#
29
DIR#
30
DR0#
31
MTR0#
32
T58*PAD
T59*PAD
T63*PAD
2
4
6
INDEX#
33
DENSEL
34
DRATE0/IRSL3
95
XA0/GPIO20
94
XA1/GPIO21
93
XA2/GPIO22
92
XA3/GPIO23
91
XA4/GPIO24/XSTB0#
90
XA5/XSTB1#/XCNF2
87
XA6/GPIO26/PRIQA/XSTB2#
86
XA7/GPIO27/PIRQB
85
XA8/GPIO30/PIRQC
84
XA9/GPIO31/MTR1#/PIRQD
83
XA10/GPIO32/XIORD#/MDRX
82
XA11/GPIO33/XIOWR#/MDTX
81
XA12/GPIO10/JOYABTN1/RI2#
80
XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2
79
XA14/GPIO12/JOYAY/CTS2#
78
XA15/GPIO13/JOYBY/SOUT2
77
XA16/GPIO14/JOYBX/RTS2#
76
XA17/GPIO15/JOYAX/SIN2
75
XA18/GPIO16/JOYBBTN0/DSR2#
74
XA19/DCD2#/JOYABTN0/GPIO17
PC87393F
+3V
D
+3V
143963
88
VDD1
VDD2
VDD3
VDD4
PC87393
XIOWR#/XCS1#/MTR1#/DRATE0
XIORD#/GPIO37/IRSL2/DR1#
VSS1
VSS2
VSS3
VSS4
133864
89
Size Document Number Rev
B
Date: Sheet of
PD0/INDEX#
PD1/TRK0#
PD2/WP#
PD3/RDATA#
PD4/DSKCHG#
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1
PNF/XRDY
SLCT/WGATE#
PE/WDATA#
BUSY_WAIT#/MTR1#
ACK#/DR1#
SLIN#_ASTRB#/SETP#
INIT#/DIR#
ERR#/HDSEL#
AFD#_DSTRB#/DENSEL
STB#_WRITE#
DCD1#
DSR1#
SIN1
RTS1#/TEST
SOUT1/XCNF0
DTR1#_BOUT1/BADDR
XD0/GPIO00/JOYABTN1
XD1/GPIO01/JOYBBTN1
XD2/GPIO02/JOYAY
XD3/GPIO03/JOYBY
XD4/GPIO04/JOYBX
XD5/GPIO05/JOYAX
XD6/GPIO06/JOYBBTN0
XD7/GPIO07/JOYABTN0
XRD#/GPIO34/WDO#
GPIO25/XCS0#/DR1#/XDRY
CTS1#
RI1#
IRTX
IRRX1
IRRX2_IRSL0
IRSL1
IRSL3/PWUREQ#
XER#/XCNF1
Quanta Computer Inc.
super I/O(PC87393F)
PD0
52
PD1
50
PD2
48
PD3
46
PD4
45
PD5
44
PD6
43
PD7
42
-PNF
35
SLCT
36
PE
37
BUSY
40
ACK#
41
SLIN#
47
INIT#
49
ERROR#
51
AFD#
53
STRB#HEAD#
54
DCD1#
55
DSR1#
56
RXD1
57
RTS1#
58
TXD1
59
CTS1#
60
DTR1#
61
RI1#
62
DIRTX
70
DIRRX1
69
DIRRX2
68
T61*PAD
67
T60*PAD
66
XA4
3
XA5
2
XA6
1
XA7
100
XA8
99
XA9
98
XA10
97
XA11
96
XMEMW#
4
XMEMR#
5
MTR1#
73
FDDDRV1#
71
XIOCHRDY
72
PROJECT : RT2.0
E
1A
31 57Tuesday, September 11, 2001
1
2
3
4
5
6
7
8
+5V
21
D9
STRB#
+5V
RB751V
7
Q30
SI4953DY
R173
1K
152
4683
R174
100K
C393
0.1u_0402
A A
PD[0..7][31,41]
ACK#[31,41]
B B
BUSY[31,41]
PE[31,41]
SLCT[31,41]
AFD#[31,41]
ERROR#[31,41]
INIT#[31,41]
SLIN#[31,41]
STRB#[31,41]
-PNF[31]
ACK#
BUSY
PE
SLCT
AFD#
ERROR#
INIT#
SLIN#
STRB#
-PNF
PRINTER
PORT
L75
FBMJ2125HM330
1 2
C368
180P
STRB_D
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
-D_ACK
D_BUSY
D_PE
D_SLCT
CON4
D-SUB25FM
DFDS25FR568
R11
0_0805
2627
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
R1
0_0805
-D_AFD
-D_ERROR
-D_INIT
-D_SLIN
+5V
R16
10K
1 3
R164 1K
R175
*100K
C383
0.1u_0402
Q2
DTC144EU
3MODE [41]
+5V
2
PNF
3MODE# [12,17]
2
-PNF
Q1
DTC144EU
1 3
PNF [35,41]
C C
AFD# -D_AFD
L57 BK1608HS241-T
PD0 LPD0
L58 BK1608HS241-T
ERROR# -D_ERROR
L59 BK1608HS241-T
PD1 LPD1
L60 BK1608HS241-T
C372
C371
C370
C369
180P
180P
INIT# -D_INIT
L61 BK1608HS241-T
PD2 LPD2
L62 BK1608HS241-T
SLIN#
L63 BK1608HS241-T
PD3 LPD3
D D
1
L64 BK1608HS241-T
2
C373
180P
C374
180P
180P
C375
180P
180P
-D_SLIN
C376
180P
3
PD4
L65 BK1608HS241-T
PD5
L66 BK1608HS241-T
PD6
L67 BK1608HS241-T
PD7
L68 BK1608HS241-T
C379
C378
C377
180P
ACK# -D_ACK
L69 BK1608HS241-T
BUSY D_BUSY
L70 BK1608HS241-T
PE D_PE
L71 BK1608HS241-T
SLCT
L72 BK1608HS241-T
C381
180P
4
180P
C382
180P
180P
C384
180P
LPD4
LPD5
LPD6
LPD7
C380
180P
D_SLCT
C385
180P
5
Size Document Number Rev
B
6
Date: Sheet of
+5V
RP14
SLIN#
INIT#
ERROR#
AFD#
10
9
8
7 4
+5V
10
PD0 PD5
PD1 PD6
PD2 PD7
PD3
9
8
7 4
10P8R_4.7K
RP13
10P8R_4.7K
1
2
3
56
1
2
3
56
PROJECT : RT2.0
Quanta Computer Inc.
LPT1/FDD interface
7
ACK#
BUSY
PE
SLCT
PD4
+5V
+5V
1A
32 57Tuesday, September 11, 2001
8
5
4
3
2
1
D D
C C
R258
10K
RTS1#[31]
DTR1#[31]
TXD1[31]
DSR1#[31]
RXD1[31]
CTS1#[31]
DCD1#[31]
RI1#[31]
+5V
RTS1#
DTR1#
TXD1
DSR1#
RXD1
CTS1#
DCD1#
RI1#
0.1u_X7R
C407
0.47u_X7R
C493
U38
14
T1I
13
12
19 4
18
17
16
15
23
22
21
20
28
24
1 3
2 25
T1O
T2I
T2O
T3I
T3O
RIO R1I
R2O
R3O
R4O
R5O
FORCEON
FORCEOFF#
INVAILD#
R2OUTB
C1+
VCC
C1ÂC2+ VÂC2- GND
MAX3243
R2I
R3I
R4I
R5I
V+
-MRTS1
9
-MDTR1
10
MTXD1
11
-MDSR1
MRXD1
5
-MCTS1
6
-MDCD1
7
8
+5V
26
27
C408
0.47u_X7R
D15
1SS355
C494
0.47u_X7R
21
-MRTS1 [41]
-MDTR1 [41]
MTXD1[41]
-MDSR1 [41]
MRXD1 [41]
-MCTS1 [41]
-MDCD1 [41]
C495
0.47u_X7R
C358
180P
MRI1-0
-MDTR1-0
-MCTS1-0
MTXD1-0
-MRTS1-0
MRXD1-0
-MDSR1-0
C357
180P
MRI1
L47 BK1608HS241-T
-MDTR1
L48 BK1608HS241-T
-MCTS1
L49 BK1608HS241-T
MTXD1
L50 BK1608HS241-T
-MRTS1
L51 BK1608HS241-T
MRXD1
L52 BK1608HS241-T
-MDSR1
MRI1 -MDCD1-0
R180
1K
MRI1 [38,41]
L53 BK1608HS241-T
-MDCD1
L54 BK1608HS241-T
C356
180P
C355
180P
C354
180P
C353
180P
C352
180P
C351
180P
5
9
4
8
3
7
2
6
1
CON1
D-SUB9M
DFDS09MR554
11
10
R2 0_0805
R10 0_0805
COM PORT
FIR
B B
DIRTX[31]
DIRRX1[31]
DIRRX2[31]
A A
5
DIRTX
DIRRX1
DIRRX2
R152
10K
IRGND
R150 4.99K_1%
R151 22
R153 4.99K_1%
R149
*4.7K
4
IRTX
IRRX1
IRRX2
IRGND
9
4
5
8
3
TXD
MD0
MD1
RXD
FIR_SEL
+5V
IRGND
10
LEAD
GND_1
7
R148
4.7_2010
1
+3V
3
VCC
IRGND
11
GND_2
IRGND
U27
6
NC
AGND
HSDL3600007
2
C343
0.47u_0805
C345
10U/25V_1206
C2_0529: Change
2
PAD112
EMI_SPRING_RT1
1
1 2
IRGND
G1
*SHORT PAD
Size Document Number Rev
B
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
COM/IR interface
33 57Tuesday, September 11, 2001
1
3A
5
CP1
8P4C_220P
1
2
CP3
8P4C_220P
-ECIOWR
-ECIORD
5VPCU
0.1u_0402
FUN_1[35,40]
FUN_2[35,40]
MY13
4
MY12
6
MY0
MY2
2
MY11
4
MY14
6
MY10
MY1515
1
MY1212
3 4
MY22
5 6
7 8
MY99
9 10
MY77
11 12
MY55
13 14
MY1_1
15 16
17 18
MX66
19 20
MX33 MX77
21 22
MX11
23 24
MX22
25
C868
0.1u_0402
1
2
5VPCU
R606
10K
BA0
BA1
-ECIOWR
-IOSEL
C876
5VPCU
2
5VPCU
2
5
3
5
7 8
1
3
5
7 8
D D
C C
B B
A A
MY9MY15
MY8
MY7
MY6
MY5
MY3
MY1
MY4
CON10
MY15
MY13
MY12 MY0
MY2 MY11
MY14 MY10
MY9 MY8
MY7 MY6
MY5 MY3
MY1 MY4
NC MX5
MX6 MX0
MX3 MX7
MX1 MX4
MX2
KEYBOARD_CONN.
5VPCU
0.1u_0402
53
4
U75
7SH86
U74
74VHC138
1
A0
2
A1
3
A2
4
E1
5
E2
6
E3
16
VDD
8
GND
13
Q85
DTA124EU
13
Q87
DTA124EU
CP2
8P4C_220P
1
2
3
4
5
6
78
CP4
8P4C_220P
1
2
3
4
5
6
78
MY1313
2
MY00
MY1111
MY1010MY1414
MY88
MY66
MY33
MY44
MX55
MX00
MX44
+5V
RP38
10
MY4
9
MY5 MY1
8
MY6 MY0
7 4
MY7
10K_10P8R
+5V
RP35
10
MY13
9
MY12 MY8
8
MY11
7 4
MY10
10K_10P8R
5VPCU
C829
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
U61
2
VCC
3
GND
S-80745AH
15
PORTA_WR [35]
14
PORTB_WR [35]
13
PORTC_WR [35]
12
PORTD_WR [35]
11
PORTA_RD [35]
10
PORTB_RD [35]
9
PORTC_RD [35]
7
FUN_3[35,40]
2
2
FUN_4[35,40]
C1_0328: Change to 0603
5VPCU
0.1u_0402
C839
C853
0.1u_0402
BK3216M121
MX00
7 8
MX11
BP6
5
MX22
3
MX33
1
MX44
7 8
MX55
5
MX66
BP5
3
MX77
1
MY00
7 8
MY1_1
5
MY22
BP4
3
MY33
1
MY44
7 8
MY55
5
MY66
BP3
3
MY77
1
MY88
1
MY99
3
MY1010
BP2
5
MY1111
7 8
MY1212
1
MY1313
3
MY1414
BP1
5
MY1515
7 8
IRQ1[31]
-SCI[12]
MY3
1
MY2
2
3
56
+5V
MY15
1
MY14
2
3
MY9
56
+5V
RST
IRQ12[31]
1
R490
*10K
NEW ADD
Ramp_0620
5VPCU
13
Q88
DTA124EU
5VPCU
13
Q86
DTA124EU
1u/6.3V_0603
C844
C830
0.1u_0402
MX0
MX1
6
MX2
4
MX3
2
MX4
MX5
6
MX6
4
MX7
2
MY0
MY1
6
MY2
4
MY3
2
MY4
MY5
6
MY6
4
MY7
2
MY8
2
MY9
4
MY10
6
MY11
MY12
2
MY13
4
MY14
6
MY15
5VPCU
NPWROK
VCCRTC
Y5
1 4
2 3
32.768KHz/20ppm_570
3VAUXEN[44]
R495
10M
1 4
2 3
C826
22P
*32.768KHz/20ppm_570
MBDATA[36]
VGARSTEN[18]
FANSIG[36]
-NBSWON[40,41]
RVCC_ON[12,44,49]
CELL-SET[48]
S_UNDOCK[41]
-SLPBTN[35,40,41]
UNDOCK[35,41]
4
C869
0.1u_0402
156
155
154
153
165
R496
10M
CLK_570_X2_1
C831
22P
ACIN
REF5V
REFP
D35
2 1
1SS355
92
AGND
36
KBSIN0
35
KBSIN1
34
KBSIN2
33
KBSIN3
32
KBSIN4
31
KBSIN5
30
KBSIN6
29
KBSIN7
56
KBSOUT0
55
KBSOUT1
54
KBSOUT2
53
KBSOUT3
52
KBSOUT4
51
KBSOUT5
50
KBSOUT6
49
KBSOUT7
48
KBSOUT8
47
KBSOUT9
42
KBSOUT10
41
KBSOUT11
40
KBSOUT12
39
KBSOUT13
38
KBSOUT14
37
KBSOUT15
IRQ1
IRQ8#
IRQ11
IRQ12
79
PFAIL#
HPWRON
28
VBAT
CLK_570_X1
R497
51K
CLK_570_X2
ACIN
5VPCU
2
D32 1SS355
D33 1SS355
D31 1SS355
C870
0.1u_0402
242666
109
GND_1
GND_2
GND_3
PD6/MAINON
PD7/HWPG
93
94
5VPCU 5VPCU
13
Q83
DTA124EU
2 1
2 1
2 1
1
2
Q95
2N7002E
3
C877
0.1u_0402
160
2367108
161
80
91
AVCC
VCC_1
VCC_2
VCC_3
GND_4
R529
4.7K
GND_5
32KX1
32KX2
25
27
VCC_4
PB0/RING
PB1/SCL
PB2/SDA
PB3/TA
PB4/TB
HMR
164
2
PB5/GA20
7172737475767778616263706958605759
R530
4.7K
5VPCU
13
Q82
DTA124EU
-HOLD
REF5V[48,50]
REFP[50]
5VPCU
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
MY0 BA9
MY1 BA10
MY2
MY3 BA12
MY4 BA13 BA17
MY5 BA14
MY6
MY7 BA16
MY8 BA17
MY9 BA18
MY10
MY11
MY12 BD0
MY13 BD1
MY14
MY15 BD3
T77*PAD
CLK_570_X2_1CLK_570_X1
SUSB#[12]
HWPG[44,47,49]
Y7
MBCLK[36]
KGA20[11]
RC#[11]
-SWI[12]
SUSB#[12]
ACIN[48]
4
3
NS87570 Version : C4, code:05
XA4
XA5
XA6
XA7
XA8
C878
1u/6.3V_0603
AVREF
PB6/HRSTO
PB7/SWIN
PC0
XA0
XA1
XA2
XA3
XA4
XA5
XA6
XA7
XA8
XA9
XA10
XA11
XA12
XA13
XA14
XA15
XA16
XA17
166
167
168
169
170
171
172
173
174345678910111516171819202122157
HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HA11
HA12
HA13
HA14
HA15
HA16/PA3
HA17/PA4
PC1
PC2
PC6/PSCLK3
PC7/PSDAT3
PSCLK1
PSCLK2
PSDAT1
PSDAT2
PD0/AD0
PD1/AD1
PD2/AD2
PD3/AD3
PD4/AD4
PC3/EXINT0
PC4/EXTINT11
PC5/EXINT15
646568
CELL-SET
R551
R524
100K
3
PD5/AD5
81
8283848586
*10K
R567
0
XA9
XA18
12
HD0
HD1
HD2
HD3
HD4
HD5
PE0/HA18
DA0
DA1
DA2
DA3
959697
98
5VPCU
XA10
XA11
HD6
HD7
PH0/BST0
104
+5V
XA[0..18]
162
163
HMENCS#/PA0
HMEMRD#/PA1
HMENWR#/PA2
PH1/BST1
PH3/PFS#
PH2/BST2
PH4/PLI#
103
101
10299100
RP40
5 6
3
2
1
10K_10P8R
2
12
R517 0
13
158
159
14
2434445468788
NC_2
HIOR#
HIOW#
HIOCHRDY
HAEN/FXASTB#
>
PH5/ISE#
NC_13
NC_14 NC_1
NC_15
NC_16
132
131 1
90
89
R596
10K
D36
21
1SS355
MAINON
TEMP_ABAT
TEMP_MBAT
ABATV
MBATV MBATV
74
8
9
10
+5V
XA[0..18] [31]
XMEMR#[31]
XMEMW# [31]
AEN [31]
XIOR# [31]
XIOW# [31]
XIOCHRDY [31]
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13/BE0
A14/BE1
A15/PG1
A16/PA5
A17/PA6
PE1/A18
D0
D1
D2
D3
D4
D5
D6
D7
RD#
SEL0#
WR0#
PG0/SELIO#
PG2/CLK
PG3/SEL1#
PG4/WR1#
PF0/D8
PF1/D9
PF2/D10
PF3/D11
PF4/D12
PF5/D13
PF6/D14
PF7/D15
NC_10
NC_11
NC_12
NC_9
175
134
133
176
-VOLUP [25]
-VOLDN [25]
BATLOW# [12]
MAINON [36,41,44,46,47,49]
SUSON [44,46,49]
VRON [5]
VFAN [36]
VADJ [22]
CV-SET [48]
CC-SET [48]
SUSC# [12]
TEMP_ABAT [46]
TEMP_MBAT[46]
KPDATA [36,41]
MSDATA [36,41]
KPCLK [36,41]
MSCLK [36,41]
TPDATA [36]
TPCLK [36]
STERLING 1.0 : INSTALL R13,R101/10K
STERLING 1.5 : INSTAL R101/0 ,
REMOVE R13
2
U69
PC87570-176PIN
BA0
114
BA1 BD1
115
BA2 BD2
116
BA3 BD3
117
BA4 BD4
118
BA5 BD5
119
BA6 BD6
120
BA7 BD7
121
BA8
122
123
124
BA11
125
126
127
128
BA15
129
130
135
136
137
138
BD2
139
140
BD4
141
BD5
142
BD6
143
BD7
144
111
-CE
105
112
-IOSEL
110
NPWROK
107
106
113
145
146
147
148
149
150
151
152
D30 1SS355
D29 1SS355
21
D381SS355
21
21
CLOSE TO NS570
ABATV
12
C880
0.01u
BD[0..7][35]
U25
SST28SF040A
12
A0
11
A1
10
A2
9
A3
8
A4
7
A5
6
A6
5
A7
27
A8
26
A9
23
A10
25
A11
4
A12
28
A13
29
A14
3
A15
2
A16
22
CE#
24
OE#
31
WE#
1
VPP
R589
R588
R587
-ECIORD
-ECIOWR
-VOLMUTE [26]
DOCKWELL [41]
M/A- [50]
D/C- [50]
BL/C- [50]
DOCK_ON [41]
ENDSREQ [41]
REFON [50]
DNBSWON# [12]
KBSMI# [12,31]
ABAT+
R601
102K_1%
3
Q96
2N7002E
REFP
2
1
R608
34K_1%
12
C862
0.01u
Size Document Number Rev
C
Date: Sheet of
R585
10K
10K
10K
10K
ABAT+ [46,50]
3
Q91
2N7002E
1
1
5VPCU
BA16
R584 *10K
BA15
R586 *10K
BA18
R565 *10K
BA17
R575 10K
BD[0..7]
BD0
13
D0
14
D1
15
D2
17
D3
18
D4
19
D5
20
D6
21
D7
30
A17
5VPCU
32
VCC
GND
MBAT+
R578
102K_1%
R577
34K_1%
C284
0.1u_0402
16
5VPCU
+3V
R597
1K
PWROK [12]
REF5V
R590
10K_1%
3
Q89
2N7002E
REFP
2
1
TEMP_ABAT
12
C871
0.01u
MBAT+ [46,50]
REF5V
R576
10K_1%
REFP
2
3
Q90
2N7002E
REFP
2
1
TEMP_MBAT
12
C861
0.01u
PROJECT : RT2.0
Quanta Computer Inc.
PC87570F
1
34 57Tuesday, September 11, 2001
3A
5
5VPCU 5VPCU
D D
C C
B B
A A
-D_PCMOCCB[41]
DS_PWRGD[41]
-SLPBTN[34,40,41]
UNDOCK[34,41]
-DEV_INS[17]
-CRT_SENSE[23,41]
-D_FLOPPY[41]
-MUTE_BTN[26,40]
8
U29C
3 5
7W14
SW1
1
2
LID_SW
-DOCKED[41]
PNF[32,41]
FUN_1[34,40]
FUN_2[34,40]
FUN_3[34,40]
FUN_4[34,40]
-ECLID BD0
-ECDOCKED
R599
R591
10K
100K
FUN_1
FUN_2
FUN_3
FUN_4
5VPCU
R166
10K
-LID -ECLID
3
4
5
1 2
5VPCU
R605
100K
R167
R392
10K
1 2
R389
PORTA_RD[34]
5VPCU 5VPCU5VPCU 5VPCU 5VPCU5VPCU
R574
100K
5VPCU
0.1u_0402
1K
1K
0.1u_0402
R573
100K
PORTB_RD[34]
C389
C390
0.1u_0402
5VPCU
0.1u_0402
C732
R572
100K
1 7
C728
8
R583
100K
R604
100K
U29A
7W14
4
R603
100K
3
6
4
R607
100K
VCC
GND
2
5
B
U76
2
AI0
4
AI1
6
AI2
8
AI3
17
BI0
15
BI1
13
BI2
11
B13
1
/AOE1
19
-BOE1
SN74AHC244PW
U73
2
AI0
4
AI1
6
AI2
8
AI3
17
BI0
15
BI1
13
BI2
11
B13
1
/AOE1
19
-BOE1
SN74AHC244PW
8
U29B
6 2
7W14
U58
YA
ORGND
NC7SZ58
1
18
AO0
16
AO1
14
AO2
12
AO3
3
BO0
5
BO1
7
BO2
9
BO3
20
VCC
10
GND
18
AO0
16
AO1
14
AO2
12
AO3
3
BO0
5
BO1
7
BO2
9
BO3
20
VCC
10
GND
ADD BUT
RESERVED
-ECDOCKED
4
C1 Test_0402:
Change
PORTD_WR[34]
BD1
BD2
BD3
BD4
BD5
BD6
BD7
5VPCU
C866
0.1u_0402
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
5VPCU
C863
0.1u_0402
DEL PULL
LOW
-ECLID
3
NEW ADD
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
R626 *4.7K
3
BD[0..7]
PORTA_WR[34]
PORTB_WR[34]
PORTC_WR[34]
USB_CONNECT[30]
U82
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18 19
D8 Q8
1
G#CKVCC
11
GND
*SN74AHC374PW
BD[0..7] [34]
RF_SWON[38]
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
20
10
2
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
R611 4.7K
RF_SWON
USB_CONNECT
PORTC_RD[34]
HDDVCC_ON [16]
CDVCC_ON [17]
U72
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18 19
D8 Q8
1
G#CKVCC
11
GND
SN74AHC374PW
4.7K
U77
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18 19
D8 Q8
1
G#CKVCC
11
GND
SN74AHC374PW
R610
4.7K
U78
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18 19
D8 Q8
1
G#CKVCC
11
SN74AHC374PW
U79
2
AI0
4
AI1
6
AI2
8
AI3
17
BI0
15
BI1
13
BI2
11
B13
1
/AOE1
19
-BOE1
SN74AHC244PW
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
2
5
6
9
12
15
16
20
10
2
5
6
9
12
15
16
20
10
2
Q1
5
Q2
Q3
Q4
Q5
Q6
Q7
6
9
12
15
16
20
10
AO0
AO1
AO2
AO3
BO0
BO1
BO2
BO3
VCC
GND
RF_ENABLE
USB_DISCONN
USB_RESET
18
16
14
12
3
5
7
9
20
10
5VPCU
C859
0.1u_0402R602
2A:
INVERSION
BATSEL0
DK_SMB_EN
5VPCU
C865
0.1u_0402
C882
0.1u_0402
C883
0.1u_0402
1
-MBATLED0 [36]
-MBATLED1 [36]
-ABATLED0 [36]
-ABATLED1 [36]
-CAPSLED [40]
-PADLED [40]
-NUMLED [40]
-SCROLED [40]
PWRLED0 [36]
-PWRLED1 [36]
BATSEL0 [36]
M3_RST_EN [25]
DK_PME_EN [41]
NEW_DK_INS [25]
DK_SMB_EN [36]
PM_LANPWORK [12,15]
R633 0
P-RF_ON_OFF [38]
5VPCU
C1_0328: Add,to
control radio
on/off
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
5VPCU
B2_0313: Invert
polarity.
-RF_ON_LED [38]
-USBPWRON0 [14]
-USBPWRON1 [14]
RF_ENABLE [30]
USB_DISCONN [30]
USB_RESET [30]
C1_0323: Add
but reserved
5VPCU
C893
*0.1u_0402
Size Document Number Rev
B
2
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
570 I/O & RF/B CONN
35 57Tuesday, September 11, 2001
1
3A
5
U71
SCL
SDA
WP
24C08
BATSEL0
DK_SMB_EN
MBCLK
MBDATA
A0
A1
A2
VCC
GND
1A
2A
1OE#
2OE#
5VPCU
1
2
3
8
4
2
5
1
7
2
C854
0.1u_0402
KBSMCLK [4]
5VPCU5VPCU
R44910K
Q74
DTC144EU
1 3
BATSEL0[35]
DK_SMB_EN[35]
MBCLK[34]
MBDATA[34] MCLK [46]
D D
MBCLK
MBDATA
MBCLK
C C
MBDATA
MAINON
C783
0.1u_0402
6
5
7
U62
3
1B
6
2B
8
VCC
4
GND
SN74CBTD3306
BATSEL0
MBCLK
MBDATA
4
C801
0.1u_0402
MBCLK
MBDATA
DK_SMB_EN
5VPCU
R462
4.7K
C406
0.1u_0402
U64
16
VCC
6
INH
10
A
9
B
13
X
3
Y
74HC4052
U36
3
1B
6
2B
8
VCC
4
GND
SN74CBTD3306
1OE#
2OE#
3
12
X0
VEE
GND
14
X1
15
X2
11
X3
1
Y0
5
Y1
2
Y2
4
Y3
7
8
ACLK [46]
To battery connector
MDATA [46]
ADATA [46]
TPCLK[34]
TPDATA[34]
-HDDLED[16]
-PWRLED1[35]
-MBATLED1[35]
-MBATLED0[35]
-ABATLED1[35]
-ABATLED0[35]
Reserved
Ramp_0620: Change
to 5.3mm(ACS)
To docking connectorTo Thermal decector for CPU
2
1A
5
2A
1
7
2
Q39
DTC144EU
1 3
R181
10K
DKSMCLK [41]KBSMDAT [4]
DKSMDATA [41]
2A:
INVERSION
Reserved for different
charge & discharge
time
5VPCU5VPCU
PWRLED0[35]
D45
*1SS355
2 1
R627 100K
2
C835
100P
L108 FCM1608K221
L107 FCM1608K221
-HDDLED
-PWRLED0_1
-PWRLED1
-MBATLED1
-MBATLED0
-ABATLED1
-ABATLED0
From 180K to 100K
R635
*47K
12
+
+5V
STICK_CONN.
100K
R628
C894
10u/10V_1206
CON15
2
NC_1
VDD
GND
DAT
CLK
NC_2
L42
C837
100P
1
2
3
4
5
6
TP_GND
-PWRLED0_1
31
Q100
2SC4081
+5V
FBMJ2125HM330
PS2_STK_DAT
PS2_STK_CLK
C346
0.1u_0402
+5V
12
1
L38
FBMJ2125HM330
L37
FCM1608K221
TPCLK_1
TPDATA_1
5VPCU
5VTP
TP_GNDTP_GND
TP_GND
TOUCH_PAD_15P
52610-1590
C332
0.1u_0402
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CON16
STICK PORT
C1_0406: Change part
F2
FUSE2A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
B B
FBMJ2125HM330
L56
+5V
Q24
2SA1797
3 2
1
3 1
Q73
VFAN
FANSIG
2SC4081
A A
VFAN[34]
FANSIG[34]
D41
1SS355
2
21
12
C276
+
10u/10V_1206
+5V
R458
1K
R448
100K
C1_0329: Move to Top side
5
4
+5V_FAN
D42
1SS355
2 1
C1_0328: Change to 1K
C895
4700P
CON11
3
2
1
FAN_CONN.
FAN
CONNECTOR
C1_0328: Change to 4700P
3
MSDATA[34,41]
KPDATA[34,41]
MSCLK[34,41]
KPCLK[34,41]
2
L80
L45
L81
BK1608HS241-T
BK1608HS241-T
BK1608HS241-T
BK1608HS241-T
C387
100P
Size Document Number Rev
B
Date: Sheet of
5VPS_N01
L5
5VPS_N02
C394
100P
C367
100P
C396
100P
Quanta Computer Inc.
570 access BUS/PS2/FAN/touch PAD
PS/2 PORT
R162
0_0805
1
1
2
2
3
3
4
5
6
7 8
7 8
36 57Tuesday, September 11, 2001
CON2
PS2_CONN.
Foxconn
R140_0805
4
5
6
C395
0.1u_0402
PROJECT : RT2.0
1
3A
5
4
3
2
1
D D
DRAMENA[12]
ICH_SMCLK
ICH_SMDATA
C C
ICH_SMCLK[3,12]
ICH_SMDATA[3,12]
B B
ICH_SMCLK
ICH_SMDATA
+3V
C180
0.1u_0402
C2_0509: Modify
U21
16
R114
4.7K
VCC
14
S0
2
S1
1
-OE1
15
-OE2
7
X
9
Y
FST3253MTCX
X0
X1
X2
X3
Y0
Y1
Y2
Y3
GND
6
5
4
3
10
11
12
13
8
RAM_SMCLK0
RAM_SMCLK1
RAM_SMDATA0
RAM_SMDATA1
3VSUS
R104 10K
R105 10K
R106 10K
R111 10K
RAM_SMCLK0
RAM_SMCLK1
RAM_SMDATA0
RAM_SMDATA1
RAM_SMCLK0[10]
RAM_SMCLK1[10]
RAM_SMDATA0[10]
RAM_SMDATA1[10]
A A
5
RAM_SMCLK0
RAM_SMCLK1
RAM_SMDATA0
RAM_SMDATA1
Size Document Number Rev
A
4
3
Date: Sheet of
2
PROJECT : RT2.0
Quanta Computer Inc.
ICH SMBus
37 57Tuesday, September 11, 2001
1
1A
5
4
3
2
1
RING INDICATOR
MODIFY RI#
CIRCUITS
D D
D21 1SS355
-MODEM_RI[30,51]
D22 1SS355
-PCICRI[28]
-DKPCMRI[41]
D23
1SS355
C C
RF S/W CKT
3.3VAUX 3.3VAUX
R369
10K
21
2
21
21
C892
VCCRTC
0.1u
1 3
VCCRTC
Change power plane from 3VSUS to 3VAUX
R362
10K
2
Q64
DTC144EU
R619
100K
Q65
DTC144EU
1 3
VCCRTC
2
Q66
1 3
DTC144EU
RI# [12]
MRI1 [33,41]
C1_0328: Change to +5V
+5V
NEW ADD IN
REV: 2A
B B
Q99
DTC144EU
RF_SW
A A
P-RF_ON_OFF[35]
High Pulse
5
2
C891
0.1u
R620
10K
1 3
2
Q112
DTC144EU
1 3
U81
2
1
4
TC7W74FU
C1_0328: Add,
D
CLK
GND
76
VCC
-PR-CLR
-Q
8
5
Q
3
R621
VCCRTC
10K
controlled by EC
4
3
C890
0.1u
RF_SW
RF_SWON [35]
R634*0
+5V
-RF_ON_LED [35]
R614
680
CON28
1
1
2
2
3
3
4
4
ANTENNA_CONN
C1 Test_0402:
Change
Size Document Number Rev
A
Date: Sheet of
2
PROJECT : RT2.0
Quanta Computer Inc.
RING INDICATOR & RF S/W CKT
38 57Tuesday, September 11, 2001
1
3A
5
4
3
2
1
+3V
+3V
+3V
D D
R56
10K
-D_PCMSPK[41]
MODEMSPK[30,51]
R55
10K
53
1
2
4
+3V
U13
7SH86
53
1
-PCICSPK[28]
C C
2
U14
7SH86
4
+3V
53
+5VA
C941
1
PCSPK[12]
2
U15
7SH86
53
0.1u_0402
4
AUDGND
1
+5V
+3V
2
4
BEEP [25]
U30
8
U37A
B B
1 7
7W14
8
U37B
6 2
7W14
U37C
8
3 5
7W14
R212
5
2
4
AUDGND
1
U31
7SH32
7SH86
PCBEEP [26]
3
C451
39K
0.01u
SPKOFF[12]
A A
PROJECT : RT2.0
Quanta Computer Inc.
Size Document Number Rev
A
5
4
3
Date: Sheet of
IK BEEP
2
39 57Tuesday, September 11, 2001
1
2B
5
CON8
1
1
3
3
5
5
7
D D
+5V
LCDID0
LCDID1
LCDID2
LCDID3
LCDID4
-NBSWON
-PADLED
-SCROLED
-NUMLED
C71
0.1u_0402
LCDID0[18]
LCDID1[18]
LCDID2[18]
LCDID3[18]
LCDID4[18]
-NBSWON[34,41]
-PADLED[35]
-CAPSLED[35]
-SCROLED[35]
-NUMLED[35]
C C
7
9
9
11
11_GND
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29_GND
31 32
31 32
33 34
33 34
35 36
35 36
37 38
37 38
39 40
39 40
GND_2
41
42
2
2
4
4
6
6
8
8
10
10
12
12_GND
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30_GND
GND_1
UPPER_CONN
QTS1040A-2121-40P-RDV
4
-SLPBTN
FUN_1
FUN_2
FUN_3
FUN_4
SPKR+IN
SPKR-IN-CAPSLED
SPKL-IN
SPKL+IN
-SLPBTN [34,35,41]
FUN_1 [34,35]
FUN_2 [34,35]
FUN_3 [34,35]
FUN_4 [34,35]
SPKR+IN [26]
SPKR-IN [26]
SPKL-IN [26]
SPKL+IN [26]
MIC_INT [27]
3
2
1
B B
A A
-MUTE_BTN[26,35]
-VOLDN_BTN[25]
-VOLUP_BTN[25]
-MOFF_BTN[41,49]
5
L39 BK1608HS241-T
L40 BK1608HS241-T
L41 BK1608HS241-T
L43 BK1608HS241-T
VCCRTC
+3V
CON17
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
210303-095-08G2
CON21
1
1
2
2
3
3
4
4
210303-095-04G2
4
Size Document Number Rev
B
3
2
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
upper,volume interface
40 57Tuesday, September 11, 2001
1
1A
1
QBVCC
C16
0.1u_0402
GNTA#[11]
CLKRUN#[11,25,28,30,31,51]
PCLK_DK
12
R244
*33
C454
*22P
SERIRQ[11,28,31]
C/BE0#[11,25,28,30,51]
C/BE1#[11,25,28,30,51]
C/BE2#[11,25,28,30,51]
-DKPCMRI[38]
DEVSEL#[11,25,28,30,51]
C/BE3#[11,25,28,30,51]
AD0[11,25,28,30,51]
AD1[11,25,28,30,51]
AD2[11,25,28,30,51]
AD3[11,25,28,30,51]
AD5[11,25,28,30,51]
AD7[11,25,28,30,51]
C19
0.1u_0402
AD4[11,25,28,30,51]
AD6[11,25,28,30,51]
FRAME#[11,25,28,30,51]
IRDY#[11,25,28,30,51]
AD11[11,25,28,30,51]
PAR[11,25,28,30,51]
AD9[11,25,28,30,51]
PLOCK#[11]
AD8[11,25,28,30,51]
PERR#[11,28,30,51]
AD13[11,25,28,30,51]
AD15[11,25,28,30,51]
AD12[11,25,28,30,51]
AD10[11,25,28,30,51]
AD14[11,25,28,30,51]
STOP#[11,25,28,30,51]
AD19[11,25,28,30,51]
AD16[11,25,28,30,51]
TRDY#[11,25,28,30,51]
AD20[11,25,28,30,51]
C24
0.1u_0402
SERR#[11,28,30,51]
AD17[11,25,28,30,51]
AD21[11,25,28,30,51]
AD18[11,25,28,30,51]
AD23[11,25,28,30,51]
AD22[11,25,28,30,51]
PIRQA#[11,28]
PIRQB#[11,18,30,51]
PIRQC#[11,25]
PIRQD#[11,30,51]
AD24[11,25,28,30,51]
AD25[11,25,28,30,51]
AD26[11,25,28,30,51]
AD28[11,25,28,30,51]
AD29[11,25,28,30,51]
AD27[11,25,28,30,51]
AD30[11,25,28,30,51]
AD31[11,25,28,30,51]
REQA#[11]
1
A A
B B
C C
1988AC_SCLK
12
R243
*33
D D
C453
*22P
-QPCIEN
QBVCC
-QPCIEN
QBVCC
-QPCIEN
PIC16861/QS32X861
PIC16861/QS32X861
PIC16861/QS32X861
1988AC_DATAI1[25]
1988AC_SYNC[25,30,51]
1988AC_SCLK[25,30,51]
1988AC_DATAO[25,30,51]
1988AC_RESET#[25,30,51]
PCIRST#[6,11,16,18,25,28,30,31,51]
PCLK_DK[3]
QBVCC
36 48
2
3
4
5
6
1
7
8
9
10
11
13
14
15
16
17
18
35
19
20
21
22
23
47
12 24
36 48
2
3
4
5
6
1
7
8
9
10
11
13
14
15
16
17
18
35
19
20
21
22
23
47
12 24
36 48
2
3
4
5
6
1
7
8
9
10
11
13
14
15
16
17
18
35
19
20
21
22
23
47
12 24
REQ0#[11]
GNT0#[11]
U5
VCC_1 VCC_2
A0
A1
A2
A3
A4
NC_1
A5
A6
A7
A8
A9
NC_2
A10
A11
A12
A13
A14
BE2
A15
A16
A17
A18
A19
BE1
GND_1GND_2
U6
VCC_1 VCC_2
A0
A1
A2
A3
A4
NC_1
A5
A6
A7
A8
A9
NC_2
A10
A11
A12
A13
A14
BE2
A15
A16
A17
A18
A19
BE1
GND_1GND_2
U7
VCC_1 VCC_2
A0
A1
A2
A3
A4
NC_1
A5
A6
A7
A8
A9
NC_2
A10
A11
A12
A13
A14
BE2
A15
A16
A17
A18
A19
BE1
GND_1GND_2
1 2
R23
10K
2
46
B0
45
B1
44
B2
43
B3
42
B4
41
B5
40
B6
39
B7
38
B8
37
B9
34
B10
33
B11
32
B12
31
B13
30
B14
29
B15
28
B16
27
B17
26
B18
25
B19
46
B0
45
B1
44
B2
43
B3
42
B4
41
B5
40
B6
39
B7
38
B8
37
B9
34
B10
33
B11
32
B12
31
B13
30
B14
29
B15
28
B16
27
B17
26
B18
25
B19
46
B0
45
B1
44
B2
43
B3
42
B4
41
B5
40
B6
39
B7
38
B8
37
B9
34
B10
33
B11
32
B12
31
B13
30
B14
29
B15
28
B16
27
B17
26
B18
25
B19
1988AC_SCLK
PCLK_DK
-QPCIENA
1 2
R22
22K
2
QBVCC
-D_GNTA
D_SERIRQ
-D_CBE0
-D_CBE1
-D_CBE2
-D_PCMRI
-D_DEVSEL
-D_CBE3
D_AD0
D_AD1
D_AD2
D_AD3
D_AD5
D_AD7
QBVCC
D_AD4
D_AD6
-D_FRAME
-D_IRDY
D_AD11
D_PAR
D_AD9
-D_PLOCK
D_AD8
-D_PERR
D_AD13
D_AD15
D_AD12
D_AD10
D_AD14
-D_STOP
D_AD19
D_AD16
-D_TRDY
D_AD20
QBVCC
-D_SERR
D_AD17
D_AD21
D_AD18
D_AD23
D_AD22
-D_INTA
-D_INTB
-D_CLKRUN
-D_INTC
-D_INTD
D_AD24
D_AD25
D_AD26
D_AD28
D_AD29
D_AD27
D_AD30
D_AD31
-D_REQA
10
11
13
2
3
4
5
6
7
8
9
1
U8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9B0B9
/ON
/VBIAS
TI6800
C18
0.1u_0402
Ramp_0622: Change
U5, U6, U7
footprint
LAN_T+_D[15]
LAN_T-_D[15]
LAN_R+_D[15]
LAN_R-_D[15]
C20
SERIRQ
0.1u_0402
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ0#
GNT0#
REQA#
GNTA#
C25
0.1u_0402
DS_PWRGD
QBVCC
24
VCC
D_SDI2
23
D_SDFS2
22
B1
D_SCLK2
21
B2
D_SDO2
20
B3
D_SRST2
19
B4
18
B5
-D_REQ0
17
B6
-D_GNT0
16
B7
-D_RESET
15
B8
D_PCLKDOCK
14
3
LAN_T+_D
LAN_T-_D
LAN_R+_D
LAN_R-_D
3
S_UNDOCK
5VSUS
2
C22
0.1u_0402
+5V
-D_FLOPPY[35]
-D_SPKOFF[26]
R222
100K
3
1
-DOCKED[35]
-NBSWON[34,40]
L82
FBMJ3216HS800-T
QBVCC
3VSUS
DDCDAT[18,23]
5VPCU
-MDSR1[33]
MRXD1[33]
-MCTS1[33]
MRI1[33,38]
PD5[31,32]
USBP0-[12,14]
CRT_HS[23]
CRT_GND
VA
C434
0.1u_0402
2
1
Q4
2N7002E
4
CON5A
1
4
4
-D_PME
-QPCIENA
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
1
AUDGND AUDGND
-D_GNTA
NOT USED
NOT USED
+5V_DOCK
D_PCLKDOCK
-D_CBE0
-D_CBE2
-D_CBE3
D_AD0
D_AD4
-D_PLOCK
D_AD10
D_AD14
-D_PERR
D_AD18
D_AD22
D_SDI2
D_SDFS2
-D_INTC
D_AD26
D_AD30
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
5VSUS
Ramp_0620: Change
for ESD
5
U9
7SH32
3
DK_PME_EN[35]
61
P1
P61
62
P2
P62
63
P3
P63
64
P4
P64
65
P5
P65
66
P6
P66
67
P7
P67
68
P8
P68
69
P9
P69
70
P10
P70
71
P11
P71
72
P12
P72
73
P13
P73
74
P14
P74
75
P15
P75
76
P16
P76
77
P17
P77
78
P18
P78
79
P19
P79
80
P20
P80
81
P21
P81
82
P22
P82
83
P23
P83
84
P24
P84
85
P25
P85
86
P26
P86
87
P27
P87
88
P28
P88
89
P29
P89
90
P30
P90
91
P31
P91
92
P32
P92
93
P33
P93
94
P34
P94
95
P35
P95
96
P36
P96
97
P37
P97
98
P38
P98
99
P39
P99
100
P40
P100
101
P41
P101
102
P42
P102
103
P43
P103
104
P44
P104
105
P45
P105
106
P46
P106
107
P47
P107
108
P48
P108
109
P49
P109
110
P50
P110
111
P51
P111
112
P52
P112
113
P53
P113
114
P54
P114
115
P55
P115
116
P56
P116
117
P57
P117
118
P58
P118
119
P59
P119
120
P60
P120
P241
P243
P244
241
243
244
DOCK_CON
R27
0_0805
AUDGND
B2_0324: Change
GND
2
3
Q43
2N7002E
NC
NOT USED
-D_RESET
D_SERIRQ
-D_CBE1
-D_DEVSEL
D_AD2
D_AD6
-D_FRAME
D_AD8
D_AD12
-D_STOP
D_AD16
D_AD20
D_SCLK2
D_SDO2
-D_INTA
-D_CLKRUN
D_AD24
D_AD28
-D_REQA
D_SMDATA
NOT USED
NOT USED
NOT USED
-QPCIEN
NOT USED
Ramp_0620: Change
for ESD
12VSUS
DKSMDATA[36]
R183
10K
2
1 3
5
3VSUS
MAINON [34,36,44,46,47,49]
VA
DKSMCLK[36]
R57
100K
3.3VAUX3.3VAUX
R182
10K
Q42
DTC144EU
5
LINEL_D [27] MIC_D[27]
STEP# [17,31]
WDATA# [17,31]
-MOFF_BTN [40,49]
DDCCLK [18,23]
PNF [32,35]
-MDCD1 [33]
MTXD1 [33]
-MDTR1 [33]
-MRTS1 [33]
PD7 [31,32]
PD3 [31,32]
USBP0+ [12,14]
CRT_VS [23]
D_GREEN [23]
D_RED [23]
D_BLUE [23]
ENDSREQ [34]
Q9
2N7002E
3
3
Q32
2
DTC144EU
1 3
CD_D_CDL[27]
CD_D_CDR[27]LINER_D [27]
-CRT_SENSE[23,35]
-D_PCMSPK[39]
DOCK_ON[34]
3.3VAUX
DOCKWELL[34]
MSDATA[34,36]
INDEX#[17,31]
WGATE#[17,31]
FDDDRV1#[31]
3MODE[32]
TV_LUMA[18,23]
5VSUS
USBOC1#[12,14]
-D_PCMOCCB[35]
ERROR#[31,32]
1
2
1
Q46
2N7002E
2
PME# [11,25,28,30,51]
KPCLK[34,36]
TRK0#[17,31]
SLCT[31,32]
ACK#[31,32]
DIR#[17,31]
TV_GND
PD4[31,32]
PD2[31,32]PD1[31,32]
PE[31,32]
6
L6
BK1608HS601
L12
FBMJ3216HS800-T
VA
Q50
2N7002E
1
2
Q8
2N7002E
1
2
6
NOT USED
3VAUX
NOT USED
NOT USED
-D_PCMRI
D_AD5
-D_IRDY
D_AD9
D_AD13
-D_TRDY
D_AD17
D_AD21
-D_REQ0
-D_INTB
D_AD25
D_AD29
KPCLK
MSDATA
D_SMCLK
NC
5VSUS_1
NOT USED
3
3
3VSUS
D_SMCLK
D_SMDATA
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
CON5B
7
181
P121
P181
182
P122
P182
183
P123
P183
184
P124
P184
185
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P143
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P158
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174
P175
P176
P177
P178
P179
P180
242
3VSUS
5VSUS
VA
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
P202
P203
P204
P205
P206
P207
P208
P209
P210
P211
P212
P213
P214
P215
P216
P217
P218
P219
P220
P221
P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P233
P234
P235
P236
P237
P238
P239
P240
P242
DOCK_CON
C27
0.1u_0402
C28
0.1u_0402
C33
0.1u_0402
S_UNDOCK
186
LAN_T+_D
187
LAN_T-_D
188
189
LAN_R+_D
190
LAN_R-_D
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
7
NOT USED
D_AD1
D_AD3
D_AD7
D_PAR
D_AD11
D_AD15
-D_SERR
+5V_DOCK
D_AD19
D_AD23
NOT USED
D_SRST2
-D_GNT0
-D_INTD
D_AD27
D_AD31
-D_PME
5VSUS_1
NOT USED
DS_PWRGD
R178
0_0805
C21
C23
0.1u_0402
0.1u_0402
C30
C29
0.1u_0402
0.1u_0402
C31
C32
0.1u_0402
0.1u_0402
Size Document Number Rev
C
Date: Sheet of
SPKL_DK [26]SPKR_DK[26]
C2_0517
AUDGNDAUDGND
12VSUS
S_UNDOCK [34]
-SLPBTN [34,35,40]
KPDATA [34,36]
MSCLK [34,36]
DSKCHG# [17,31]
HEAD# [17,31]
MTR1# [31]
RDATA# [17,31]
WP# [17,31]
TV_CHROMA [18,23]
TV_COMP [18,23]
-D_MICOFF [27]
UNDOCK [34,35]
USBP1+ [12,14]USBP1-[12,14]
USBOC0# [12,14]
PD6 [31,32]
BUSY [31,32]
PD0 [31,32]
AFD# [31,32]
INIT# [31,32]
SLIN# [31,32]
STRB# [31,32]
VA
DS_PWRGD [35]
R184
10K
QBVCC
CRT_GND
TV_GND
C17
0.1u_0402
C26
0.1u_0402
+5V
C425
0.1u_0402
PROJECT : RT2.0
Quanta Computer Inc.
FULL DOCK
-QPCIEN
L11
BK1608HS241-T
L7
BK1608HS241-T
12VSUS5VPCU
C15
0.1u_0402
8
C412
0.1u_0402
41 57Tuesday, September 11, 2001
8
C405
0.1u_0402
2B
A
B
C
D
E
PAD108
EMI_SPRING_RT1
Ramp_0620: NPTH
HOLE1
*SCREW HOLE
4 4
3 3
HOLE-S315D110N-8
67
8
C2_0507
5
4
193
2
GND_DC1 GND_DC2
HOLE3
*SCREW HOLE
HOLE-TC236BS315D102P2
1
HOLE5
*SCREW_HOLE
HOLE-TC354BS315D197PB
1
1
Ramp_0620:
Change for ESD
C2_0507
8
HOLE4 *SCREW HOLE
HOLE-TC315BS394D118NP2-4
1
2
PAD109
*EMI_SPRING_RT1
1
HOLE2
*SCREW HOLE
HOLE-S315D110N-8
67
5
4
193
2
HOLE7
*SCREW_HOLE
HOLE-TC354BC315D197PB
1
5
4
3
C2_0517: For ICT
HOLE8
HOLE12
*HEATSINK_HOLE
HOLE-S315D118P2
1
2 2
HOLE9
*HEATSINK_HOLE
HOLE-S315D118P2
1
C2_0517: For ICT
HOLE20 *SCREW HOLE
HOLE-TC354BS315D118NP2-4
5
1
1 1
2
4
3
*HEATSINK_HOLE
HOLE-S315D118P2
1
HOLE15 *SCREW HOLE
HOLE-S394D118NP2-4
5
1
2
HOLE22
*SCREW HOLE
HOLE-S315D102P2
4
3
1
PAD110
EMI_SPRING_RT1
1
HOLE14
SCREW_HOLE_01011
HOLE-C315D236P2
1
HOLE23
SCREW_HOLE_01011
HOLE-C315D236P2
1
HOLE13
*SCREW HOLE
HOLE-C315D146P2
1
C2_0425: Change drill size
HOLE16
*SCREW HOLE
HOLE-S157D118NP2
1
HOLE18
*SCREW HOLE
HOLE-S394D110P2
1
HOLE17
SCREW_HOLE_16017
HOLE-C236D158P2
1
PAD111
EMI_SPRING_RT1
1
C2_0529: Change
C2_0510:
Del
HOLE11
*HDD_PAD
HOLE-OB128X58D98X28P2
1
HOLE21
*SCREW HOLE
HOLE-TC236BC315D118NP2
NPTH
1
C2_0510:
Del
HOLE25
*HDD_PAD
HOLE-OB207X58D177X28P2
C2_0508:
1
Change size
HOLE19
*SCREW HOLE
HOLE-S394D118P2
1
AUDGND AUDGND
Ramp_0620: Add for ESD
HOLE6
SCREW_HOLE_83014
HOLE-TC276BC197D158P2
1
EMI_SPRING_RT1
PAD100
EMI_SPRING_RT1
1
GND_DC2
GND_DC1
PAD102
1
0_0805
R677
R679
0_0805
R678
0_0805
R6800_0805
PAD29
EMI_SPRING_RT1
1
Ramp_0620: Load
C2_0517: For ICT
A
B
C
PAD37
SPRING_2.0X3.0X4.5
PAD4
1 2
*SHORT
PAD14
1 2
*SHORT
PAD25
1 2
*SHORT
PAD17
1 2
*SHORT
PAD12
1 2
*SHORT
PAD1
1 2
*SHORT
PAD39
1 2
*SHORT
PAD50
1 2
*SHORT
PAD42
1 2
*SHORT
Ramp_0622:
Change
1
C2_0510: Del
PAD5
1 2
*SHORT
PAD16
1 2
*SHORT
PAD21
1 2
*SHORT
PAD30
1 2
*SHORT
PAD41
1 2
*SHORT
PAD46
1 2
*SHORT
PAD38
1 2
*SHORT
PAD6
1 2
*SHORT
PAD19
1 2
*SHORT
C2_0517
C2_0517
PAD20
1 2
*SHORT
AUDGNDAUDGND
PAD31
1 2
*SHORT
PAD44
1 2
*SHORT
C2_0517
C2_0517
PAD45
1 2
AUDGND AUDGND
*SHORT
Size Document Number Rev
B
D
Date: Sheet of
PAD106
EMI_SPRING_RT1
1
PAD7
1 2
*SHORT
PAD23
1 2
*SHORT
PAD26
1 2
*SHORT
PAD2
1 2
*SHORT
C2_0510: Del
PAD48
1 2
*SHORT
PAD51
1 2
*SHORT
PAD28
1 2
*SHORT
PAD107
EMI_SPRING_RT1
1
PAD8
1 2
*SHORT
C2_0510: Del
PAD11
1 2
*SHORT
PAD3
1 2
*SHORT
PAD33
1 2
*SHORT
PAD43
1 2
*SHORT
PAD36
1 2
*SHORT
PROJECT : RT2.0
Quanta Computer Inc.
hole PAD and EMIPAD
E
3A
42 57Tuesday, September 11, 2001
5
4
3
2
1
R506
39_1%
+1.5V
R513
39_1%
VCCT
ITP_CPURST#
ITP_TCK
ITP_TMS
+1.5V
VCCT
VCCT
D D
ITP_CPURST#[6]
ITP_TCK[4]
ITP_TMS[4]
R487
56.2_1%
240_1%
R499
R516
*1.5K
Reserved
C C
ITP_TDI[4]
ITP_TDO[4]
ITP_TRST#[4]
ITP_PREQ#[4]
ITP_PRDY#[4]
ITP_TDI
ITP_TRST#
ITP_PREQ#
ITP_PRDY#
Reserved
R520
*1.5K
R502
56.2_1%
R507
200
R509
240_1%
R522
150
R519
200
ITP_TDI
ITP_TDO
ITP_TRST#
ITP_PREQ#
ITP_PRDY#_1
R489
510
HCLK_ITP_1
ITP_CPURST#
ITP_TCK
ITP_TMS
ITP_TDI
ITP_TDO
CON14
1
3
5
7
9
11
13
ITP_CONN.
1
3
5
7
9
11
13
10
12
14
2
2
4
6
8
4
6
8
10
12
14
ITP_TRST#
ITP_PREQ#
ITP_PRDY#_1ITP_TDO
B B
HCLK_ITP[3]
R483
475_1%
HCLK_ITP#[3]
R472
61.9_1%
A A
5
4
R477 33
R482 33
R478
61.9_1%
3
HCLK_ITP_1
Size Document Number Rev
A
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
ITP interface
2
2A
43 57Tuesday, September 11, 2001
1
5
4
3
2
1
B2 Test change the power circuits
D D
+2.5V
3
1
SI3456DV
MAIND [46]
SUSD [46]
R648
22R_0805
3
Q110
2N7002E
1
R123
22R_0805
Q71
2N7002E
PQ41
1.8V_S5
VAUX_EN
2
6
524
1
-SUS_ON
R612
1M
VAUX_EN
3
Q97
2N7002E
1
PC79
0.1u/50V_0805
VCCTBST2
PC87
0.1u/50V_0805
+1.5V
12
PC98
0.01u
C2_0509: Del
VIN_1.8
876
123
0322: Change to 5VPCU
2
PD26
DAP202U
1
876
123
C2_0509: Del
RVCC_ON[12,34,49]
4
5
PQ42
SI4834DY
4
5
4
2
Q81
DTC144EU
PC72
0.1u/50V_0805
C2_0509: Del
PC84
0.1u/50V_0805
PC85
4.7u/25V_1210
PQ44
SI4834DY
PL8
1 2
10UH/4A
1 3
FBMJ3216HS800-T
PC73
4.7u/25V_1210
PL7
1 2
10UH/4A
VIN_1.8
PC86
4.7u/25V_1210
PC89
47u/6.3V_7343
VIN
R527
1M
R526
1M
L126
47u/6.3V_7343
+
PC90
47u/6.3V_7343
3V_S5
2
+
PC75
+
R582
22R_0805
3
Q93
2N7002E
1
VIN
PC74
4.7u/25V_1210
47u/6.3V_7343
+
PC76
PC91
0.01u
0.1u_X7R
2
1.8V_S5
PC92
EC10QS04
R581
22R_0805
3
Q92
2N7002E
1
3
0312: Change to system GND
PQ43
5
6
7
8
2 1
SI4936DY
0312: Power or
System GND
C1_0403: Modify &
delete 2.5VSUS relative
circuits
-MAIN_ON
VIN 1.8VAUX3.3VAUX 15V
2
Q19
DTC144EU
1 3
PD28
PC77
0.01u
2 1
0.1u_X7R
+2.5V
3VAUXEN[34]
1.8V_S5
PC78
PD25
EC10QS04
-MAIN_ON[46,47]
MAIND
4
3
2
1
+1.8V
SUSD
1.8VSUS
B2_0315: Add
+1.5V
+1.8V
R379
22R_0805
3
2
2N7002E
1
R415
1M
R416
1M
R75
22R_0805
3
R122
22R_0805
3
Q70
2N7002E
1
1
Q14
2N7002E
2
2
2
2
Q68
2
VCCTOUT1
PC67
1000P
1 2
+1.8V
578
3 6
1 2
PR73
10
PQ47
SI4800DY
241
C2_0509:
Del
12
+
PC96
10u/10V/Tan_1206
VCCTLX1
VCCTDH1
VCCTBST1
VCCTDL1
PC81
4.7u/16V_X7R
5VPCU
3
12
PC83
4.7u/16V_X7R
VCCTLX2
VCCTDL2
VCCTDH2
C2_0509: Del
+1.5V is controlled by +12V. If +12V shut down
controlled by <MAINON>, +1.5V will power down
caused by PQ47 turned off.
12
PC94
0.1u_X7R
C2_0424:
Change
C2_0509: Change
PR72
HWPG[34,47,49]
REF2V
RVCC_ON[12,34,49]
240K
PC80
1u_0805
PC82
1u_0805
ON_2.5V
200K
C C
0509: Change to
0805
C2_0509: Change
B B
C1_0403:
Modify
MAINON
SUSON[34,46,49]
REF2V
A A
PR78
1 2
3.3K_1%
1 2
R6610
R662*0
PR79
10K_1%
C2_0509: Change
1
2
12
3
4
5
6
7
8
9
10
11
PR74
12
12
13
14 15
PC88
1000P
ON_2.5V
12V
84
3
+
2
-
PR80
1 2
20K_1%
5
PU16
OUT1
FB1
MAX1715
ILIM1
V+
TON
SKIP
PGOOD
AGND
REF
ON1
ON2
ILIM2
FB2
OUT2 N.C.
VCCTOUT2
BST1
PGND
BST2
28
N.C.
27
LX1
26
DH1
25
24
DL1
23
N.C.
22
21
VCC
20
VDD
19
DL2
18
17
DH2
16
LX2
C2_0507: Change
12
PC93
0.01u
1
PU17A
LM358
PC95
12
220P
12
PC97
0.1u_X7R
1.8VAUX
12
+
PC71
PC70
10u/10V/Tan_1206
0.01u
3
+2.5V power source option
for ATI P6 power states selection
ATI P6 power
states
Control
signals
Location
R661
Q110
R662
PQ46
3
PQ46
2
*2N7002E
1
-SUS_ON[46]
PC99
1000P
Size Document Number Rev
C
Date: Sheet of
3VAUX1.8VAUX
3V_S5
6
PQ40
5
SI3456DV
VAUX_EN
D3 cold D3 hot
MAINON SUSON
Components options
Load
-SUS_ON
Quanta Computer Inc.
system special power
4
2
1
3
No load
LoadNo load
1.8VSUS
PR76
22R_0805
3
2
1
PROJECT : RT2.0
1
3.3VAUX
PC68
0.01u
10u/10V/Tan_1206
PQ45
2N7002E
44 57Tuesday, September 11, 2001
12
+
PC69
3A
5
4
3
2
1
E E
CPU_VID0[5]
CPU_VID1[5]
come from CPU VID
come from ICH-3 GPO for performance mode
D D
High for performance mode
Low for battery mode
C C
+3V
B B
R221 10K
R219 *10K
R13 10K
R170 *10K
R171 10K
DSLP_VID0
DSLP_VID1
DSLP_VID2
DSLP_VID3
DSLP_VID4
CPU_VID2[5]
CPU_VID3[5]
CPU_VID4[5]
AC_VID0[12]
AC_VID1[12]
AC_VID2[12]
AC_VID3[12]
AC_VID4[12]
PM_GMUXSEL[12,47]
MUX_VID0
MUX_VID1
MUX_VID2
MUX_VID3
MUX_VID4
CPU VID selector
U2
3
7
11
17
21
4
8
14
18
22
1
13
3
7
11
17
21
4
8
14
18
22
A0
A1
A2
A3
A4
B0
B1
B2
B3
B4
BE#
BX
SN74CBT3383
U32
A0
A1
A2
A3
A4
B0
B1
B2
B3
B4
VCC
GND
C0
C1
C2
C3
C4
D0
D1
D2
D3
D4
C0
C1
C2
C3
C4
D0
D1
D2
D3
D4
2
6
10
16
20
5
9
15
19
23
24
12
2
6
10
16
20
5
9
15
19
23
MUX_VID0
MUX_VID1
MUX_VID2
MUX_VID3
MUX_VID4
+5V
C4
0.1u_0402
VR_VID0 [47]
VR_VID1 [47]
VR_VID2 [47]
VR_VID3 [47]
VR_VID4 [47]
+5V
1
R41
Ramp_0704: Change to 0.85V
A A
0.85V:
ID4 ID3 ID2 ID1 ID0
R12
*0
0
*0
0
R220
R169
R172
*0
PM_DPRSLPVR[12,47]
High for deeper sleep mode
Low pass through VID of performance or battery mode.
BE#
13
BX
SN74CBT3383
1 0 1 0 1
5
4
VCC
GND
3
24
12
C388
0.1u_0402
Size Document Number Rev
A
Date: Sheet of
VID selector
2
45 57Tuesday, September 11, 2001
1
1A
5
C2_0517: Change part for EMI
E E
MBAT+[34,50]
TEMP_MBAT[34]
MCLK[36]
MDATA[36]
MBAT+
TEMP_MBAT
12
PL6 FBMJ3216HS800-T
PC66
47P
0.1u/50V_0805
MBAT+_1
PC19
PC65
47P
4
3
2
470P
PC101
1
C2_0507: Add
PJP2
1
PJ1
POWER_JACK
J1-1
1
2
3
J1-2
PC22
0.1u/50V_0805
1
1
2
2
PR70
330
3
3
4
4
5
5
6
7
6
7
BAT_CONN
PAD101
*EMI_SPRING_TM3
12
12
PC63
47P
PR69
330
12
PC64
47P
PC1021000P
PFL2
FBMJ3216HS800-T
PFL1
FBMJ3216HS800-T
VA
PC23
0.1u/50V_0805
C2_0507: No loading
2
PQ15
PC42
0.1u_X7R
SUSD
5VPCU
876
123
1 3
5
PQ31
SI4936
4
MAIND
+5V
PC38
0.1u_X7R
VIN +3V 15V+5V
PR12
1M
PR13
2
1M
2
3
1
PR64
22R_0805
2
PQ33
2N7002E
3V_S5
876
123
3VSUS
PC41
0.1u_X7R
SUSD
2
PQ37
3
1
PR11
1M
MAIND
PQ14
2N7002E
PR65
22R_0805
3
2N7002E
1
Size Document Number Rev
B
Date: Sheet of
5
PQ32
SI4936
4
MAIND
+3V
PC40
0.1u_X7R
MAIND [44]
PC18
1000P
PROJECT : RT2.0
Quanta Computer Inc.
POWER JACK / BATTERY conn.
46 57Tuesday, September 11, 2001
1
3A
PD22
ZD5.6V
D D
2 1
PD23
ZD5.6V
2 1
C2_0517: Change part for EMI
PR7
330
PD14
ZD5.6V
PJP1
1
2
3
4
5
SUSD [44]
1
2
3
4
5
6
6
7
7
3
BAT_CONN
MAINON[34,36,41,44,47,49]
5VSUS
MAINON
DTC144EU
-MAIN_ON[44,47]
12
2
PL10 FBMJ3216HS800-T
PC7
0.1u/50V_0805
PR49
1M
3
PR50
2
1M
1 3
1
PC9
47P
PR58
22R_0805
2N7002E
12
PQ25
ABAT+_1
12
PC10
47P
330
2 1
5VSUS 15VVIN 3VSUS
PR59
22R_0805
3
2
4
1
2
PQ29
2N7002E
PR6
PD15
ZD5.6V
3
1
PQ30
2N7002E
PR61
1M
12
PC11
SUSD
47P
2 1
C1_0328: Change to1M from 100K
PC36
1000P
ABAT+[34,50]
TEMP_ABAT[34]
C C
ACLK[36]
ADATA[36]
ABAT+
TEMP_ABAT
PC5
47P
C1_0328: Change to1M from 100K
B B
SUSON[34,44,49]
A A
5
SUSON
PQ26
DTC144EU
-SUS_ON[44]
5
4
3
2
1
VIN
12
C440
4.7u/25V_1210
C2_0529: Change
+
C83
270u/2V_7343
C82
270u/2V_7343
+
270u/2V_7343
+
C81
C509
*220u/2.5V_7343
+
C1_0409: Change value
PM_GMUXSEL
PM_DPRSLPVR
0
Q13
2
MBT3904
1 3
PM_DPRSLPVR [12,45]
270u/2V_7343
+
C510
*220u/2.5V_7343
R267
1 2
10K
C511
+
270u/2V_7343
+
C512
H_DPSLP# [4,11]
VTT
C84
0.01u
0312: ADD
ON_BOARD_CORE_ON
VTT
5VPCU
R645
22R_0805
R646
3
1M
2
Q108
2N7002E
1
Q107
2N7002E
3
2
1
GND
C428
R90
1K_1%
10
V+
INH
12
0.001_2512
7
6
4
5
FBMJ3216HS800-T
R79
+3V
1 2
R278
1 2
0
1 2
R240
L135
R266
10K
C2_0507: Change
+5V
VCC1
21
22
23
24
25
19
11
12
10
2
3
6
7
8
PU9
D4
D3
D2
D1
D0
ZMODE
SKP/SDN#
TIME
CC
REF
ILIM
S0
S1
TON
MAX1718
HWPG[34,44,49]
C93
0.22u_0805
MAX1718
R96
100K
E E
VR_VID4[45]
VR_VID3[45]
VR_VID2[45]
R286
VR_VID1[45]
0
VTT-REF
1 2
1 2
24.9K_1%
VR_VID0[45]
R285
1 2
51K
C532
47P
VTT-REF
R310
12
R322
27.4K_1%
TON
C2_0507:
Change to NC
PM_VGATE[12]
C1 Test_0402: Add
for indicating EC.
R291
*0
PM_GMUXSEL[12,45]
ON_BOARD_CORE_ON[5]
D D
B1
1 2
1 2
R272 15K_1%
R618 10K_1%
C96
0.22u_0805 Q10
R290
1 2
22R_0805
9
17
VCC
VDD
VIN
1
V+
26
BST
28
DH
27
LX
16
DL
18
SUS
4
FB
5
NEG
13
POS
14
VGATE
20
OVP#
15
GND
+3V
12
D46
2 1
RB500
R660
1 2
0
C1_0402: Add for verify
C C
to GND.
C573
1u_0805
D5
C586
2 1
0.1u/50V_0805
RB501
R281
1 2
0_0805
VTTDH
LXVTT
VTTDL
(30MIL)
(30MIL)
C520
1000P
Change GND plane
C2_0507: Del
C66
*.01U
1718FB
NEG
POS
Q6
IRF7811A
Q5
FDS7764A
1 2
TON
578
3 6
578
3 6
R280
100
1 2
VCC1
12
12
241
241
R323
1K_1%
R297
*0
R78
*0
VTT-REF
12
FDS7764A
R71
*0
578
3 6
578
241
3 6
241
C418
0.1u/50V_0805
Q12
IRF7811A
Q11
FDS7764A
1 2
R277
61.9K_1%
R239
16.2K_1%
R246
604K_1%
R238
19.6K_1%
12
C6
4.7u/25V_1210
578
3 6
241
U44
1
MAX4322
R89
1.82K_1%
1 2
1 2
1 2
1 2
12
C35
4.7u/25V_1210
4.7u/25V_1210
EC31QS03L
2 1
+5V
C551
0.1u_X7R
52
3
+
4
-
PU7
8
N00
3
N01
1
N02
2
N03
MAX4524
12
C43
C48
4.7u/25V_1210
L127
*NC
0.6UH/27A
L18
D3
R91 1K_1%
1 2
1 2
9
COM
MAX4524
12
4.7u/25V_1210
ADDA
ADDB
C461
4.7u/16V_X7R
+3V
12
R273
B B
VTT_PWRGD[5]
MAINON[34,36,41,44,46,49]
R236
220K
A A
5
1K
Q52
MBT3904
R233 0
R237
10K
2
C481
0.47u_0805
13
RUNPWROK
VIN
4
R254
+5V
10
PU8
15
VCC
18
SKIP
17
V+
10
PGOOD
3
SHDN
6
2
7
16
ILIM
N/C
REF
TON
MAX1714A
PGND
N/C_1
N/C_2
C490
4.7u/16V_X7R
21
D16
BST1.5
C443
0.1u_X7R
1SS355
C442
0.1u/50V_0805
14
VDD
19
BST
1
DH
20
LX
13
DL
12
9
11
5
OUT
48
FBAGND
Q37
SI4884DY
Q38
SI4884DY
VIN3
578
3 6
578
3 6
VIN
L78
FBMJ3216HS800-T
C427
C438
4.7u/25V_1210
0.1u/50V_0805
241
241
L13
5.6UH_8A
+
D10
EC10QS04
2 1
3
C47
220u/2.5V_7343
C404
4.7u/25V_1210
+
C437
220u/2.5V_7343
R235
20K_1%
R234
100K_1%
1.2V/7.1A
VCCT
C439
0.01u
VCCT
R647
B2_0312:
ADD
-MAIN_ON[44,46]
22R_0805
3
2
Q109
2N7002E
1
0312: Power or system GND
Size Document Number Rev
C
2
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
CPU power - VCC/VTT
1
47 57Tuesday, September 11, 2001
3A
8
7
6
5
4
3
2
1
VH
2 1
PC24
0.1u/50V_0805
PD13
1SS355
PC35
10U/25V_1210
PC34
10U/25V_1210
C814
10U/25V_1210
BAT-V [50]
411
PU5A
3
+
2
5 4
2 1
321
876
2 1
PQ18
DTC144EU
1 3
PR9
0.02
VA1
PL2
FBMJ3216HS800-T
VA2
PC17
0.1u/50V_0805
4.7u/25V_1210
PQ13
SI4435DY
PL3
L1-1
22uH
PD8
EC20QS03L
PR32
590_1%
PC15
PR31
182K_1%
PR30
PC30
1000P
4.7K
VA1 [50]
PC13
4.7u/25V_1210
PC16
4.7u/25V_1210
PR41
1.82K_1%
VH
PR43
10K
13
PQ19
2SA1576A
PR60
L1-2
0.02
PR19
PR20
118_1%
118_1%
5
6
PR17
10K
2
2
21
PD12
1SS355
PR18
22K
PU5B
LM324
+
7
-
PC25
0.01u
AC
D D
PD7
VA
2 1
RB051L-40
PD6
2 1
RB051L-40
21
PD3
1SS355
21
PD1
PR26
1K
1SS355
PR2
1K
5
4
321 6
VAD
PR8
22K
PC12
C C
0.01u
5
4
PQ8
IMZ2
3
D6
DA204U
2
1
VH
PC8
0.1u/50V_0805
321 6
PC1
220P
PR1
100K
PQ1
IMZ2
PD9
EC20QS03L
1
2
-
LM324
PC31
0.01u
PR42
1.82K_1%
13
PQ20
2SA1576A
PR4
169K_1%
PR37
7.5K_1%
5
4
PU6A
LM339
PC2
0.1u/50V_0805
6
PR3
47K
PC27
4700P
PC6
0.1u_X7R
PR34
10K
PR33
10K
PR35
100K
PU6D
11
+
10
-
LM339
PR36
60.4K/D
3
AC
2
1
4
PR38
10K
PC29
1000P
PR27
4.7K
13
21
PR39
10K
PC28
0.01u
PU6C
9
+
14
8
-
LM339
ACIN[34]
VAD
PD2
ZD15V
5
PR25
PR21
47K
B B
PR22
22K
PC26
220P
47K
PU6B
7
+
1
6
-
LM339
PR24
10K
312
+
2
-
OSC 200KHz
A A
8
7
PQ17
2N7002E
PR40
182K_1%
PR46
20K_1%
PR45
7.5K_1%
PR44
60.4K/D
PC32
0.1u_X7R
CELL-SET [34]
REF5V [34,50]
CV-SET [34]CC-SET[34]
3
Size Document Number Rev
C
Date: Sheet of
2
PROJECT : RT2.0
Quanta Computer Inc.
CHARGER & DISCHARGER
48 57Tuesday, September 11, 2001
1
1A
A
B
C
D
E
B2 Test: ADD
CSH3
4 4
PQ24
IRLML5103
SUSON[34,44,46]
3 3
MAINON[34,36,41,44,46,47]
PQ38
DTC144EU
2 2
2
PQ21
DTC144EU
2
HWPG[34,44,47]
PQ39
IRLML5103
1 3
4.7u/16V_X7R
PC60
1 3
PR67
220K
2
REF2.5V
12VSUS VIN_5
3
2
PR51
220K
12V
3
1
12
PC61
4.7u/16V_X7R
PR68
10K
1
12VOUT
15V
VL
12
-MOFF_BTN[40,41]
RVCC_ON[12,34,44]
PU15
1
CSH3
2
CSL3
3
FB3
4
12OUT
5
VDD
6
SYNC
7
TIME/ON5
8
GND
9
REF
10
SKIP-
11
RESET-
12
FB5
13
CSL5
14 15
CSH5 SEQ
MAX1632
RUN/ON3
PR14
1K
DH3
LX3
BST3
DL3
SHDN-
PGND
DL5
BST5
LX5
DH5
2 1
PR15
100K
28
27
26
25
24
23
22
V+
21
VL
20
19
18
17
16
PD11
ZD5.6V
DL3
VL
3
12
PC20
0.1u/50V_0805
DH3
PC62
4.7u/16V_X7R
DL5
PR16
2
1
10
LX3
PC59
0.1u/50V_0805
PD21
DAP202U
876
123
PC21
0.1u/50V_0805
LX5
5
4
FBMJ3216HS800-T
PC54
4.7u/25V_1210
PQ35
SI4834DY
876
123
DH5
L128
2 1
PD19
*NC
PC53
0.1u/50V_0805
5
PQ34
SI4834DY
4
CSH5
VIN
4.7u/25V_1210
PL4
10UH/4A
4.7u/25V_1210
PC57
VIN_5
PC55
LX15
21
43
PL5
10UH-CDRH125B
PD18
*NC
2 1
PR63
0.02_2512
PC56
4.7u/25V_1210
DEL PC36,PC47
NC PD19
CHANGE PL4,PR63
PC48
0.1u_X7R
PC45
150u/6.3V_7343
21
PR62
0.015_2512
12
PR66
100K
PC52
0.01u
PD20
1SS355
2 1
EC11FS2
12
PC46
150u/6.3V_7343
PD10
PC44
150u/6.3V_7343
PC51
0.1u_X7R
12
PC49
0.1u_X7R
15V
12
PC58
4.7u/16V_X7R
12
PC43
150u/6.3V_7343
3V_S5
PD16
EC10QS04
2 1
PC50
0.1u_X7R
5VPCU
PD17
EC10QS04
2 1
1 1
Size Document Number Rev
B
A
B
C
D
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
POWER CIRCUIT(MAX1632)
49 57Tuesday, September 11, 2001
E
2B
1
2
3
4
5
6
7
8
PQ4
PQ3
PQ9
IMD2
1
2
3
SI4435DY
PR5
10K
4
3
2
1
MBAT+[34,46]
A A
ADISCHG
12
PC3
0.1u/50V_0805
DTC144EU
PQ2
3216
2
1 3
5
4
ACHG
B B
BAT-V[48]
5
6
7
8
SI4936
PQ10
PQ11
IMD2
1
2
3
SI4435DY
PR10
10K
ABAT+[34,46]
C C
MDISCHG
12
2
PQ12
DTC144EU
PC14
0.1u/50V_0805
1 3
3216
5
4
MCHG
D D
1
2
PQ5
8
8
7
7
6
6
54
5 4
SI4435DY
2 1
2 1
PQ6
8
8
7
7
6
6
54
5 4
SI4435DY
3
PD4
ZD15V
PD5
ZD15V
PR52
470K
PR53
470K
1
2
3
PR47
10K
PQ27
1 6
VIN
PQ22
2
MDISCHG
2
3
DTC144EU
1 3
VH
PR28
PU5C
10
+
8
9
-
1M
MCHG
LM324
REFON[34]
VH
PR23
10K
IMD2
5
4
REFON
36
241
REFP [34]
REFP
PC33
0.1u/50V_0805
VIN
PQ7
SI4800DY
PU12
1
NC_1
IN
TEMP
GND TRIM
REF-02
NC_2
NC_3
OUT
2
3
4 5
8
7
REF5V
6
PC37
0.1u_X7R
REF5V [34,48]
PU5D
14
13
-
LM324
PR29
100K
2
PQ16
DTC144EU
578
VA1 [48]
ACHG
12
+
1 3
1
2
3
PR48
10K
DTC144EU
1 3
M/A-[34]
D/C-[34]
BL/C-[34]
2
PQ23
ADISCHG
VL
PU4
PC4
0.1u_X7R
1514131211109
16
Y0Y1Y2Y3Y4Y5Y6
VDD
ABCGLG1
12346
74HC237
78
Y7GND
G2
5
PR54
10K
PR55
100K
84
+
1
-
PU13A
3
2
LM393
PC39
0.1u/50V_0805
3
PQ28
VL
REFP
PR56
100K
REF5V
PR57
137K_1%
2
PU13B
5
+
6
4
5
7
-
LM393
6
2N7002E
1
Size Document Number Rev
B
Date: Sheet of
BATTERY SELECTOR
7
PROJECT : RT2.0
Quanta Computer Inc.
50 57Tuesday, September 11, 2001
8
1A
5
E E
D D
C C
B B
AD[0..31][11,25,28,30,41]
PIRQB#[11,18,30,41]
PIRQD#[11,30,41]
REQ4#[11]
GNT4#[11]
PCIRST#[6,11,16,18,25,28,30,31,41]
C/BE0#[11,25,28,30,41]
C/BE1#[11,25,28,30,41]
C/BE2#[11,25,28,30,41]
C/BE3#[11,25,28,30,41]
FRAME#[11,25,28,30,41]
IRDY#[11,25,28,30,41]
TRDY#[11,25,28,30,41]
DEVSEL#[11,25,28,30,41]
STOP#[11,25,28,30,41]
PAR[11,25,28,30,41]
SERR#[11,28,30,41]
PERR#[11,28,30,41]
CLKRUN#[11,25,28,30,31,41]
PME#[11,25,28,30,41]
1988AC_RESET#[25,30,41]
1988AC_SYNC[25,30,41]
1988AC_SCLK[25,30,41]
1988MC_DATAI1[25,30]
1988AC_DATAO[25,30,41]
-MODEM_RI[30,38]
MODEMSPK[30,39]
PCLK_MINI2[3]
AD[0..31]
PIRQB#
PIRQD#
REQ4#
GNT4#
PCIRST#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
SERR#
PERR#
CLKRUN#
Q77
2N7002E
3
2
3.3VAUX
1988AC_RESET#
1988AC_SYNC
1988AC_SCLK
1988MC_DATAI1
1988AC_DATAO
-MODEM_RI
MODEMSPK
PCLK_MINI2
R473
33
3.3VAUX
1
R464
10K
MINIPCI2_PME#
4
AGND_MINI2
L114
BK1608HS241-T
3
CON27
1
+3V
PIRQD#
PCLK_MINI2
REQ4#
AD31
AD29
AD27
AD25
C/BE3#
AD23
AD21
AD19
AD17
C/BE2#
IRDY#
CLKRUN#
SERR#
PERR#
C/BE1#
AD14
AD12
AD10
AD8
AD7
AD5
AD3
+5V
AD1
1988AC_SYNC
1988MC_DATAI1
1988AC_SCLK
MODEMSPK
-MODEM_RI
+5V
AGND_MINI2 AGND_MINI2
TIP
3
LAN1
5
LAN3
7 8
LAN5 LAN6
9 10
LAN7 LAN8
11 12
LED_GP LED_YP
13 14
LED_GN LED_YN
15
NC1
17 18
-INTB +5V_1
19 20
+3V_0 -INTA
21 22
R(IRQ3) R(IRQ4)
23 24
GND_1 +3VAUX_1
25 26
PCICLK -RST
27 28
GND_2 +3V_3
29 30
-REQ -GNT
31 32
+3V_1 GND_9
33 34
AD31 -PME
35 36
AD29 (V)_3
37 38
GND_3 AD30
39 40
AD27 +3V_4
43
(V)_1
45 46
-CBE3 AD24
47 48
AD23 IDSEL
49 50
GND_4 GND_10
51 52
AD21 AD22
53 54
AD19 AD20
55 56
GND PAR
57 58
AD17 AD18
59 60
-CBE2 AD16
61 62
-IRDY GND_11
63 64
+3V -FRAME
65 66
-CLKRUN -TRDY
67 68
-SERR -STOP
69 70
GND_5 +3V_5
71 72
-PERR -DEVSEL
73 74
-CBE1 GND_12
75 76
AD14 AD15
77 78
GND_6 AD13
79 80
AD12 AD11
81 82
AD10 GND_13
83 84
GND_7 AD9
85 86
AD8 -CBE0
87 88
AD7 +3V_6
89 90
+3V_2 AD6
91 92
AD5 AD4
93 94
(V)_2 AD2
95 96
AD3 AD0
97 98
+5V_0 (V)_4
99 100
AD1 SERIRQ
101 102
GND_8 GND_14
103 104
SYNC M66EN
105 106
SDIN0 SDOUT
107 108
BITCLK SDIN1
109 110
-AC_PRIMARY -RESET
111 112
BEEP -MPCICACK
113 114
AGND_1 AGND_3
115 116
+MIC +SPK
117 118
-MIC -SPK
119 120
AGND_2 AGND_4
121 122
-RI NC4
123 124
+5VA +3VAUX_2
GND_15
125
126
RING
LAN2
LAN4
AD28AD25
AD26
GND_16
MINIPCI_4.0
NC2
2
4
6
16
4241
44
2
+3V
+5V
PIRQB#
3.3VAUX
PCIRST#
GNT4#
MINIPCI2_PME#
AD30
AD28
AD26
AD24
MINIPCI2ID
R505 100
AD22
AD20
PAR
AD18
AD16
FRAME#
TRDY#
STOP#
DEVSEL#
AD15
AD13
AD11
AD9
C/BE0#
AD6
AD4
AD2
AD0
1988AC_DATAO
1988AC_RESET#
3.3VAUX
1
AD18
Device ID is AD18
PIRQD#
PIRQB#
GNT4#
REQ4#
C822
22P
C852
0.1u_0402
A A
5
C872
0.1u_0402
4
+3V+5V 3.3VAUX
C873
4.7u/10V_0805
C815
0.1u_0402
C832
0.1u_0402
C824
0.1u_0402
3
C845
0.1u_0402
1u/6.3V_0603
C843
C818
0.1u
C813
0.1u_0402
2
C810
1u/6.3V_0603
Size Document Number Rev
B
Date: Sheet of
PROJECT : RT2.0
Quanta Computer Inc.
MINI PCI second interface
51 57Tuesday, September 11, 2001
1
1A
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