© 1999 Fairchild Semiconductor Corporation DS500246 www.fairchildsemi.com
June 1999
Revised August 1999
GTLP6C817 Low Drive GTLP-to-LVTTL 1:6 Clock Driver
GTLP6C817
Low Drive GTLP-to-LVTTL 1:6 Clock Driver
General Description
The GTLP6C817 is a l ow drive clock driver tha t provides
TTL to GTLP signal lev el trans lation (and vice ver sa). The
device provides a high speed interface between cards
operating at TTL l ogic le vels and a backp lane o perat ing at
GTLP logic levels. H igh speed backplane operation is a
direct result of GTLP’s reduced output swing (<1V),
reduced input threshold leve ls and output edge rate control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconduct or derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has intern al edge -rate cont rol and is process, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GT L but with different outp ut
levels and receiver threshold. GTLP output LOW level is
typically less than 0. 5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
■ Interface between TTL and GTLP logic levels
■ Edge Rate Control to minimize noise on the GTLP port
■ Power up/down high impedance for live insertion
■ 1:6 fanout clock driver for LVTTL port
■ 1:2 fanout clock driver for GTLP port
■ LVTTL compatible driver and control inputs
■ 5V over voltage tolerance on LVTTL ports
■ Flow through pinout optimizes PCB layout
■ Open drain on GTLP to support wired-or connection
■ Recommended Operating Temperature −40°C to +85°C
Ordering Code:
Pin Descriptions Connection Diagram
Order Number Package Number Package Description
GTLP6C817M TC MTC24 24-Lead Thin Shrink S m all Ou t li n e Pac ka ge ( TSSOP), JEDE C MO - 15 3 , 4. 4 mm W id e
Pin Names Description
TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively)
OEB
Output Enable (Active LOW)
GTLP Port (TTL Levels)
OEA
Output Enable (Active LOW)
TTL Port (TTL Levels)
V
CCT
.GNDT LVTTL Output Supplies (3V)
V
CC
Internal Circuitry VCC (5V)
GNDG OBn GTLP Output Grounds
V
REF
Voltage Reference Input
OA0–OA5 TTL Buffered Clock Outputs
OB0–OB1 GTLP Buffered Clock Outputs