Fairchild Semiconductor CD4043BCSJX, CD4043BCSJ, CD4043BCN, CD4043BCMX, CD4043BCM Datasheet

October 1987 Revised January 1999
CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches
© 1999 Fairchild Semiconductor Corporation DS005967.prf www.fairchildsemi.com
CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches •
Quad 3-STATE NAND R/S Latches
General Description
logic “1” on the ENABLE inpu t conne cts the latch sta tes to the Q outputs. A logic “0” on the ENABLE input discon­nects the latch states from the Q outputs resulting in an open circuit condition on the Q output. The 3-S TATE fea­ture allows common bussing of the outputs.
Features
Wide supply voltage range: 3V to 15V
Low power: 100 nW (typ.)
High noise immunity: 0.45 V
DD
(typ.)
Separate SET and RESET inputs for each latch
NOR and NAND configuration
3-ST ATE output with common output enable
Applications
• Multiple bus storage
• Strobed register
• Four bits of independent storage with output enable
• General digital logic
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4043BC
Top View
Pin Assignments for DIP and SOIC
CD4044BC
Top V iew
Order Number Package Number Package Description
CD4043BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body CD4043BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4044BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD4044BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4044BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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CD4043BC • CD4044BC
Block Diagrams
CD4043BC CD4044BC
Truth Tables
CD4043BC
CD4044BC
OC = 3-STATE NC = No change X = Don’t care
∆ = Dominated by S = 1 input ∆∆ = Dominated by R = 0 input
SREQ
XX0OC 001NC 1011 0110 111
SREQ
XX0OC 111NC 0111 1010 001∆∆
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