Fairchild Semiconductor 100355QIX, 100355QI, 100355QCX, 100355QC, 100355PC Datasheet
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© 2000 Fairchild Semiconductor Corporation DS010147 www.fairchildsemi.com
July 1989
Revised August 2000
100355 Low Power Quad Multiplexer/Latch
100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of
which can accept an d store data from two sou rces. When
both Enable (E
n
) inputs are LOW, the data that appears at
an output is controlled by the Sel ect (S
n
) inputs, as shown
in the Operating Mod e table. In addition to routing data
from either D
0
or D1, the Select inputs can force the ou t-
puts LOW for the case wh er e th e latc h i s tr ansp ar ent (bo th
Enables are LOW) and can steer a HIGH signal from either
D
0
or D1 to an output. The Select inputs can be tied
together for applications requiring only that data be steered
from either D
0
or D1. A positive-going signal on either
Enable input latches the outputs. A HIGH signal on the
Master Reset (MR) input over rides all the ot her inputs and
forces the Q outputs LOW. All inputs have 50 k
Ω pull-down
resistors.
Features
■ Greater than 40% power reduction of the 100155
■ 2000V ESD protection
■ Pin/function compatible with 100155
■ Voltage compensated operating range
= −4.2V to −5.7V
■ Available to industrial grade temperature range
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Order Number Package Number Package Description
100355PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100355QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100355QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
−40°C to +85°C)
Pin Names Description
E
1
, E
2
Enable Inputs (Active LOW)
S
0
, S
1
Select Inputs
MR Master Reset
D
na–Dnd
Data Inputs
Q
a–Qd
Data Outputs
Q
a–Qd
Complementary Data Outputs
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100355
Operating Mode Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Note 1: Stores data present before E
went HIGH
Tr uth Table
Logic Diagram
Controls Outputs
E
1E2S1S0
Q
n
H X X X Latched (Note 1)
X H X X Latched (Note 1)
LLLL D
0x
LLHL D0x + D
1x
LLLH L
LLHH D
1x
Inputs Outputs
MR E
1E2S1S0D1xD0xQx
Q
x
HXXXXXX H L
LLLHHHX L H
LLLHHLX H L
LLLLLXH L H
LLLLLXL H L
LLLLHXX H L
LLLHLHX L H
LLLHLXH L H
LLLHLLL H L
L H X X X X X Latched (Note 1)
L X H X X X X Latched (Note 1)
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100355
Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions
Note 2: The “Absolute Maximum Ratings” are those value s beyond which
the safety of the dev ice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 4)
V
EE
= −4.2V to −5.7V, VCC = V
CCA
= GND, T
C
= 0°C to +85°C
Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guard banding ca n be a chie ve d by decr easi ng the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
Storage Temperature (T
STG
) −65°C to +150°C
Maximum Junction Temperature (T
J
) +150°C
V
EE
Pin Potential to Ground Pin −7.0V to +0.5V
Input Voltage (DC) V
EE
to +0.5V
Output Current (DC Output HIGH)
−50 mA
ESD (Note 3)
≥2000V
Case Temperature (T
C
)
Commercial 0
°C to +85°C
Industrial
−40°C to +85°C
Supply Voltage (V
EE
) −5.7V to −4.2V
Symbol Parameter Min Typ Max Units Conditions
V
OH
Output HIGH Voltage −1025 −955 −870 mV VIN = V
IH (Max)
Loading with
V
OL
Output LOW Voltage −1830 −1705 −1620 mV or V
IL (Min)
50Ω to −2.0V
V
OHC
Output HIGH Voltage −1035 mV VIN = V
IH (Min)
Loading with
V
OLC
Output LOW Voltage −1610 mV or V
IL (Max)
50Ω to −2.0V
V
IH
Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal
for ALL Inputs
V
IL
Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal
for ALL Inputs
I
IL
Input LOW Current 0.50 µAVIN = V
IL (Min)
I
IH
Input HIGH Current
S
0
, S
1
220
E
1
, E
2
350 µAVIN = V
IH (Max)
Dna–D
nd
340
MR 430
I
EE
Power Supply Current −87 −40 mA Inputs Open
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