Fairchild Semiconductor 100331SCX, 100331SC, 100331DC, 100331QIX, 100331QI Datasheet
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© 2000 Fairchild Semiconductor Corporation DS010262 www.fairchildsemi.com
February 1990
Revised August 2000
100331 Low Power Tri p le D-Type Flip-Flop
100331
Low Power Triple D-Type Flip-Flop
General Description
The 100331 contains three D-type, edge- triggered master/
slave flip-flops with true and complement outputs, a Common Clock (CP
C
), and Master Set (MS) an d Master Reset
(MR) inputs. Each flip-flop has individual Clock (CP
n
),
Direct Set (SD
n
) and Direct Clear (CDn) inputs. Data enters
a master when bot h CP
n
and CPC are LOW and tra nsfers
to a slave when CP
n
or CPC (or both) go HIGH. The Master
Set, Master Reset and individual CD
n
and SDn inputs over-
ride the Clock inputs. All inputs have 50 k
Ω pull-down
resistors.
Features
■ 35% power reduction of the 100131
■ 2000V ESD protection
■ Pin/function compatible with 100131
■ Voltage compensated operating range
= −4.2V to −5.7V
■ Available to industrial grade temperature range
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Order Number Package Number Package Description
100331SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100331PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100331QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100331QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
−40°C to +85°C)
Pin Names Description
CP
0
–CP
2
Individual Clock Inputs
CP
C
Common Clock Input
D
0–D2
Data Inputs
CD
0
–CD
2
Individual Direct Clear Inputs
SD
n
Individual Direct Set Inputs
MR Master Reset Input
MS Master Set Input
Q
0-Q2
Data Outputs
Q
0–Q2
Complementary Data Outputs
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100331
Truth Tables
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
U = Undefined
t = Time before CP Positive Transition
t + 1 = Time after CP Positive Tr ansition
= LOW-to-HIGH Transiti on
Logic Diagram
Synchronous Operation (Each Flip-Flop)
Inputs Outputs
D
n
CPnCP
C
MS MR
Q
n
(t + 1)
SD
n
CD
n
L
LLLL
H
LLLH
LL
LLL
HL
LLH
XLLLLQ
n
(t)
XHXLLQ
n
(t)
XXHLLQ
n
(t)
Asynchronous Operation (Each Flip-Flop)
Inputs Outputs
D
n
CPnCP
C
MS MR
Q
n
(t + 1)
SD
n
CD
n
XXXHLH
XXXLH L
XXXHHU
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100331
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: The “Absolute Maximum Ratings” are those value s beyond which
the safety of the dev ice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 3)
V
EE
= −4.2V to −5.7V, VCC = V
CCA
= GND, T
C
= 0°C to +85°C
Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are chosen to guarantee operation under “worst case” conditions.
Storage Temperature (T
STG
) −65°C to +150°C
Maximum Junction Temperature (T
J
) +150°C
Pin Potential to Ground Pin (V
EE
) −7.0V to +0.5V
Input Voltage (DC) V
EE
to +0.5V
Output Current
(DC Output HIGH)
−50 mA
ESD (Note 2)
≤ 2000V
Case Temperature (T
C
)
Commercial 0
°C to +85°C
Industrial
−40°C to +85°C
Supply Voltage (V
EE
) −5.7V to −4.2V
Symbol Parameter Min Typ Max Units Conditions
V
OH
Output HIGH Voltage −1025 −955 −870 mV VIN = VIH (Max) Loading with
V
OL
Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V
V
OHC
Output HIGH Voltage −1035 mV VIN = VIH (Min) Loading with
V
OLC
Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V
V
IH
Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal
for All Inputs
V
IL
Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal
for All Inputs
I
IL
Input LOW Current 0.5 µAVIN = VIL (Min)
I
IH
Input HIGH Current 240 µAVIN = VIH (Max)
I
EE
Power Supply Current −122 −65 mA Inputs OPEN
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