Datasheet FDB13AN06A0, FDP13AN06A0 Datasheet (Fairchild)

FDB13AN06A0 / FDP13AN06A0

N-Channel PowerTrench® MOSFET 60V, 62A, 13.5mΩ

FDB13AN06A0 / FDP13AN06A0

July 2003

Features

•r

•Q

• Low Miller Charge

•Low Q

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

Formerly developmental type 82555

DRAIN

(FLANGE)

MOSFET Maximum Ratings T

= 11.5mΩ (Typ.), V

DS(ON)

(tot) = 22nC (Typ.), V

g

Body Diode

RR

FDP SERIES

GS

TO-220AB

= 10V, ID = 62A

GS

= 10V

GATE

SOURCE

DRAIN

C

GATE

SOURCE

= 25°C unless otherwise noted

Applications

• Motor / Body Load Control

• ABS Systems

• Powertrain Management

• Injection Syste m s

• DC-DC converter s and Off-line UPS

• Distributed P ower Arc hitectures and VRMs

• Primary Switch for 12V and 24V systems

G

TO-263AB

FDB SERIES

DRAIN

(FLANGE)

D

S

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Sou r c e Voltage 60 V Gate to Source Voltage ±20 V Drain Curr e nt Continuous (T

I

D

Continuous (T Continuous (T

= 25oC, VGS = 10V)

C

= 100oC, VGS = 10V) 44 A

C

= 25oC, VGS = 10V, R

A

= 43oC/W) 10.9 A

θJA

62 A

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse Avalanche Energy (Note 1) 56 mJ Power dissipation 115 W

o

Derate above 25

C0.77W/

Operating and Storage Temperature -5 5 to 175

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

This product ha s been des igned to me et the e xtr eme test c ondit ions and envir onment deman ded by the automot ive indus t ry. For a

All Fairchild Semiconductor prod ucts are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

Thermal Resistance Junction to Case TO-220,TO-263 1.3 Thermal Resistance Junction to Ambient TO-220, TO-263 ( Note 2) 62 Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad ar ea 43

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

certification.

FDB13AN06A0 / FDP1 3AN06A0 Rev. A1

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDB13AN06A0 FDB13AN06A0 TO-263AB 330mm 24mm 800 units FDP13AN06A0 FDP13AN06A0 TO-220AB Tube N/A 50 units

FDB13AN06A0 / FDP13AN06A0

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Con ditions Min Typ Max Units

Off Characteristics

B I

DSS

I

GSS

VDSS

Drain to Sou r c e Br ea k down Voltag e ID = 250µA, VGS = 0V 60 - - V

V

= 50V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- -250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

I

= 62A, VGS = 10V - 0.0115 0.0135

D

I

= 31A, VGS = 6V - 0.022 0.034

Drain to S ou r c e On Re si st ance

D

= 62A, VGS = 10V,

I

D

T

= 175oC

J

- 0.026 0.030

Dynamic Characteristics

C C C Q Q Q Q Q

ISS OSS RSS

g(TOT) g(TH) gs gs2 gd

Input Capacitance Output Capacitance - 260 - pF Reverse Transfer Capacitance - 90 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total Gate Charge at 10V VGS = 0V to 10V Threshold Gate Charge VGS = 0V to 2V - 2.6 3.4 nC Gate to Source Gate Charg e - 8.5 - nC Gate Charge Threshold to Plateau - 5.9 - nC

V

DD

I

= 62A

D

I

= 1.0m A

g

= 30V

Gate to Drain “Miller” Charge - 6.4 - nC

- 1350 - pF

22 29 nC

µA

Ω

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time Turn-On Delay Time - 9 - ns Rise Time - 96 - ns Turn-Off D elay Time - 24 - ns Fall Time - 26 - ns Turn-Off Time - - 74 ns

(VGS = 10V)

V

= 30V, ID = 62A

DD

V

= 10V, RGS = 12Ω

GS

--158ns

Drain-Source Diode Characteristics

I

= 62A - - 1.2 5 V

V

SD

t

rr

Q

RR

Notes: 1: Starting T 2: Pulse width = 100s.

Source to Drain Diode Voltage Reverse Recovery Time ISD = 62A, dISD/dt = 100A/µs- -25ns

Reverse Recovered Charge ISD = 62A, dISD/dt = 100A/µs- -17nC

= 25°C, L = 45µH, IAS = 50A.

J

SD

I

= 31A - - 1.0 V

SD

FDB13AN06A0 / FDP13AN06A0

Typical Characteristics T

= 25°C unless otherwise noted

C

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

80

60

40

, DRAIN CURRENT (A)

D

I

20

150

0

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

10

TC, CASE TEMPERATURE (oC)

Case Temperature

P

DM

NOTES: DUTY FACTOR: D = t PEAK TJ = PDM x Z

-1

10

θJC

10

1/t2

0

x R

θJC

t

+ T

1

t

2

C

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

800

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

VGS = 10V

100

, PEAK CURRENT (A)

DM

I

30

-5

10

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

TC = 25oC FOR TEMPERATURES

o

ABOVE 25

C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

10

C

150

0

1

10

Figure 4. Peak Current Capability

FDB13AN06A0 / FDP13AN06A0

Typical Characteristics T

1000

100

OPERATION IN THIS

10

AREA MAY BE

LIMITED BY r

, DRAIN CURRENT (A)

D

I

1

SINGLE PULSE TJ = MAX RATED

T

= 25oC

C

0.1 1 10 100

DS(ON)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

= 25°C unless otherwise noted

C

10µs

100µs

1ms

DC

Figure 5. Forward Bias Safe Operating Area

100

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX V

= 15V

DD

80

10ms

100

10

, AVALANCHE CURRENT (A)

AS

I

1

0.01 0.1 1 10 100

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R

≠

0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

STARTING TJ = 150oC

tAV, TIME IN AVALANCHE (ms)

DSS

STARTING TJ = 25oC

- VDD)

- VDD) +1]

DSS

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

100

TC = 25oC

80

VGS = 20V

VGS = 10V

60

40

, DRAIN CURRENT (A)

D

I

20

0

TJ = 25oC

34567

VGS, GATE TO SOURCE VOLTAGE (V)

TJ = 175oC

TJ = -55oC

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

30

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

25

VGS = 6V

20

15

VGS = 10V

DRAIN TO SOURCE ON RESISTANCE(mΩ)

10

0 10203040506070

I

, DRAIN CURRENT (A)

D

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

60

VGS = 6V

40

, DRAIN CURRENT (A)

D

I

20

0

0 0.5 1.0 1.5 2.0

VDS, DRAIN TO SOURCE VOLTAGE (V)

2.5

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

VGS = 5V

VGS = 10V, ID =62A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDB13AN06A0 / FDP13AN06A0

Typical Characteristics T

1.4

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

C

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

3000

C

1000

C

≅ C

+ C

OSS

DS

GD

= CGS + C

ISS

GD

1.2 ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 30V

8

6

C

= C

RSS

GD

C, CAPACITANCE (pF)

100

V

= 0V, f = 1MHz

GS

40

0.1 1 10 60 VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Sour ce

Voltage

4

WAVEFORMS IN

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 5 10 15 20 25

Qg, GATE CHARGE (nC)

DESCENDING ORDER:

ID = 62A

= 31A

I

D

Figure 14. Gat e Charge Waveforms for Constant

Gate Current

Test Circuits and Waveforms

V

DS

L

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

I

AS

DUT

t

0V

P

I

AS

0.01Ω

0

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Wavef orm s

V

DS

V

DD

V

Q

I

g(REF)

L

V

GS

DUT

+

V

DD

-

V

0

I

g(REF)

GS

= 2V

Q

gs2

Q

g(TH)

Q

gs

0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

BV

DSS

t

P

t

AV

Q

g(TOT)

DS

gd

V

GS

FDB13AN06A0 / FDP13AN06A0

V

DS

V

DD

V

= 10V

GS

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

90%

PULSE WIDTH

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

Thermal Resistance vs. Mounting Pad Area

80

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maxi mum al lowab le de vice p ower di ssip ation, P application. Therefore the application’s ambient temperature, T must be reviewed to ensure that T Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

serve s as the basis for establ ishing the rating of the part.

TJMTA–()

----------------- ------------=

P

DM

R

θJA

DM

(oC/W)

θJA

(EQ. 1)

, in an

60

C/W)

o

(

θJA

R

40

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

FDB13AN06A0 / FDP13AN06A0

In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power d issipati on rating s. Precise d etermin ation of P comple x and influenced by many factors:

DM

is

1. Mou nting pad area ont o which the device is attached and whet her the re is copp er on one s ide or both side s of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the duty cycle and the transient thermal response of the part, the boa rd and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 board w ith 1oz co pp er af t er 1 0 0 0 se c onds of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides the necessary inf ormation for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice t hermal model or manu ally utilizing the no rmalized maximum transient thermal impedance curve.

20

1100.1

(0.645) (6.45) (64.5)

AREA, TOP COPPER AREA in2 (cm2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

Therma l resi stances correspondi ng to other copper are as can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inch es squ are and equ ation 3 is for area in cent imeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads.

19.84

26.51

=

R

θJA

26.51

=

R

θJA

-------------------------------------+

0.262 Area+()

Area in Inches Squared

128

----------------------------------+

1.69 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

PSPICE Electrical Model

.SUBCKT FDB13AN06A0 2 1 3 ; rev August 2002 Ca 12 8 5.1e-10 Cb 15 14 5.1e-10 Cin 6 8 1.3e-9

Dbod y 7 5 DbodyMOD Dbreak 5 11 Db reakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 65.40 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1 Lgat e 1 9 6.9e-9

Ldrain 2 5 1.0e -9 Lsource 3 7 2.91e-9

RLgate 1 9 69 RLdr ai n 2 5 10 RLsource 3 7 29.1

Mmed 16 6 8 8 M m edMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 3.0e-3 Rgate 9 20 3.77 RSLC1 5 51 RSL CM OD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 5.5e-3 Rvthres 22 8 RvthresMO D 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BM OD S2a 6 15 14 13 S2AM OD S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

-

18 22

20

S1A

12

13

8

S1B

EGS EDS

6

8

13

10

RSLC2

6

14 13

+

6 8

-

DPLCAP

EVTHRES

+

19

8

S2A

S2B

15

CIN

CB

-

+

-

5

51

5

51

21

MSTRO

14

5 8

RSLC1

+

ESLC

50

RDRAIN

16

8

MMED

8

DBREAK

11

+

17

EBREAK

IT

18

-

MWEAK

RSOURCE

RBREAK

17 18

RVTHRES

7

+

RVTEMP 19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB13AN06A0 / FDP13AN06A0

ESLC 51 50 VALUE = {(V(5,51)/ ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*160), 6))} .MODEL DbodyMOD D (IS=1.5E-11 N=1.08 RS=3.3e-3 TRS1=2.2e-3 TRS2=2.5e-9

+ CJO=0.9e-9 M= 5.1e-1 TT=1e-9 XTI=3.9) .MODEL DbreakMOD D (RS= 1.5e-1 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=4.1e-10 IS=1e-30 N=10 M=0.45)

.MODEL MmedMOD NMOS (VTO=3.5 KP=6 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.77) .MODEL MstroMOD NMOS (VTO=4.3 KP=50 IS=1e-30 N=10 TOX=1 L= 1u W=1u) .MODEL Mwe akMOD NMOS (VTO=2.88 KP=0. 05 I S=1e-30 N=10 TOX = 1 L=1u W=1u RG=3. 77e+1 RS=0.1)

.MODEL Rb reakMOD RES (T C1=9e-4 TC2=-5e-7) .MODEL Rd rai nMOD RES (TC 1=1.5e-2 TC2=4e-5) .MODEL RSLCMOD RES (TC1=1.8e-3 TC2=1.7e-5) .MODEL RsourceMOD RES (TC 1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (T C1=-5.3e-3 TC 2=-1.0e-5) .MODEL RvtempMOD RES (T C1=-2.5e-3 TC 2=1e-6)

.MODEL S1AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 5 VOFF =-2 ) .MODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 2 VOFF =-5 ) .MODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1.5 VO FF=0.5) .MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= 0 .5 VOFF= -1.5)

.ENDS *Not e: For fu rthe r dis cu ssi on of t he PS P IC E mod el , co ns ul t A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Powe r Electronic s S pecialist Conf erence Recor ds, 1991, written by Wi l liam J. Hepp and C. F rank Wheatley.

SABER Electrical Model

rev August 2002 template FDB 13AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.5e-11,nl=1.08,rs=3.3e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=0.9e-9,m=5.1e-1,tt=1e-9,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=4.1e-10,isl=10e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=3.5,kp=6,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.3,kp=50,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.88,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0.1, von=-5,voff=-2) sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0.1, von=-2,voff=-5) sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0.1, von=-1.5,voff =0.5) sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0.1, von=0.5,voff= -1.5) c.ca n12 n8 = 5.1e -10 c.cb n15 n14 = 5.1e-10 c.cin n6 n8 = 1.3e -9

dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplca pm od

spe.ebreak n11 n7 n17 n18 = 65.40 spe.eds n14 n8 n5 n8 = 1

GATE

spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1

LGATE

1

RLGATE

9

RGATE

ESG

EVTEMP +

20

spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1 l.lgate n1 n9 = 6.9e-9

l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.91e-9

res.rlgate n1 n9 = 69

CA

S1A

12

S1B

res.rldrai n n2 n5 = 10 res.rlsource n3 n7 = 29.1

m.mmed n16 n6 n8 n8 = m odel=mmedm od, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=ms trongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mwea kmod, l=1u, w=1u

18 22

DPLCAP

10

RSLC2

6

8

EVTHRES

+

19

6

-

S2A

13

14

8

13

S2B

13

+

6

EGS EDS

8

-

5

RSLC1

51

ISCL

MMED

8

DBREAK

11

MWEAK

EBREAK

+

-

RSOURCE

RBREAK

17 18

IT

RVTHRES

17 18

7

RVTEMP 19

-

+

22

50 RDRAIN

16

21

-

8

MSTRO

CIN

15

CB

8

14

+

5 8

-

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB13AN06A0 / FDP13AN06A0

res.rbreak n17 n18 = 1, tc1=9e-4,tc 2=-5e-7 res.rdrain n50 n16 = 3.0e-3, tc1=1.5e-2,tc2= 4e-5 res.rgate n9 n20 = 3.77 res.rslc1 n5 n51 = 1e-6, tc1=1.8e-3,tc2=1.7e-5 res.rslc2 n5 n50 = 1e3 res.rsour ce n8 n7 = 5.5e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.0e-5 res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=1e-6 sw_vcsp.s1 a n6 n12 n13 n8 = model= s1amod sw_vcsp.s1 b n13 n12 n13 n8 = model =s1bmod sw_vcsp.s2 a n6 n15 n14 n13 = model =s2amod sw_vcsp.s2 b n13 n15 n14 n13 = model =s2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n 51))))*((abs(v(n5,n51)* 1e6/160))** 6)) }

FDB13AN06A0 / FDP13AN06A0

PSPICE Thermal Model

REV 23 March 2002 FDB13AN06A0T

CTHERM1 TH 6 9.7e-4 CTHERM2 6 5 6. 2e-3 CTHERM3 5 4 4. 6e-3 CTHERM4 4 3 4. 9e-3 CTHERM5 3 2 8e-3 CTHERM6 2 TL 4.2e-2

RTHERM1 TH 6 5.24e-2 RTHERM2 6 5 10.08e-2 RTHERM3 5 4 4. 28e-1 RTHERM4 4 3 1. 8e-1 RTHERM5 3 2 1. 9e-1 RTHERM6 2 TL 2.1e-1

SABER Thermal Model

SABER thermal model FDB14AN06A0T template thermal_model th tl thermal_ c th , tl { ctherm.c th erm 1 th 6 =9.7e-4 ctherm.ctherm2 6 5 =6.2e-3 ctherm.ctherm3 5 4 =4.6e-3 ctherm.ctherm4 4 3 =4.9e-3 ctherm.ctherm5 3 2 =8e-3 ctherm.ctherm6 2 tl =4.2e-2

rtherm.rth erm1 th 6 =5.24e- 2 rtherm.rtherm2 6 5 =10.08e-2 rtherm.rt herm3 5 4 =4.28e-1 rtherm.rt herm4 4 3 =1.8e-1 rtherm.rt herm5 3 2 =1.9e-1 rthe r m.rtherm6 2 tl =2.1 e-1 }

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

RTHERM6

2

CTHERM6

CASE

tl

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1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or In Design

First Production

Full Production

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

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This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. I3

Datasheet FDB13AN06A0, FDP13AN06A0 Datasheet (Fairchild)

Specifications and Main Features

Frequently Asked Questions

User Manual