Denon AVR-2801, AVR-981 Service Manual

SERVICE MANUAL

Hi-Fi Component

MODEL

AVR-2801/981

AV SURROUND RECEIVER

SYSTEM

SURROUND

SETUP

PARAMETER

TUNING

TITLE

MENU/GUIDE

BAND

CH SELECT

ENTER

MODE

SELECT

ON SCREEN

STATUS

MEMORY

USE/LEARN T.TONE MULTI OUTPUT SET UP

RETURN

DISPLAY







Some illustrations using in this service manual are slightly different from the actual set.





AVR-2801/981

SAFETY PRECAUTIONS

The following check should be performed for the continued protection of the customer and service technician.

LEAKAGE CURRENT CHECK

Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis
resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the
power cord is less than 460 kohms, the unit is defective.

SPECIFICATIONS

AUDIO SECTION

(Power Amplifier)

Rated output: Front: 90 W + 90 W (8 Ω/ohms, 20 Hz ~ 20 kHz with 0.05 % T.H.D.)

Center: 90 W (8 Ω/ohms, 20 Hz ~ 20 kHz with 0.05 % T.H.D.)
Surround: 90 W + 90 W (8 Ω/ohms, 20 Hz ~ 20 kHz with 0.05 % T.H.D.)

Dynamic power: 120 W × 2 ch (8 Ω/ohms)

Output terminals: Front: A or B 6 ∼ 16 Ω/ohms

170 W × 2 ch (4 Ω/ohms)
200 W × 2 ch (2 Ω/ohms)

Surround/Center: 6 ∼ 16 Ω/ohms

(Analog)

Input sensitivity/input impedance: 200 mV/47 kΩ/kohms
Frequency response: 10 Hz ~ 100 kHz: +0, −3 dB (DIRECT mode)
S/N: 102 dB (DIRECT mode)
Distortion: 0.008 % (20 Hz ~ 20 kHz) (DIRECT mode)
Rated output: 1.2 V

(Digital)

D/A output: Rated output − 2 V (at 0 dB playback)

Digital input: Format − Digital audio interface

Total harmonic distortion - 0.008% (1 kHz, at 0 dB)
S/N ratio − 102 dB
Dynamic range - 96 dB

(Phono equalizer (PHONO input-REC OUT))

Input sensitivity: 2.5 mV
RIAA deviation: ±1 dB (20 Hz to 20 kHz)
Signal-to-noise ratio: 74 dB (A weighting, with 5 mV input)
Rated output/Maximum output: 150 mV/7 V
Distortion factor: 0.03% (1 kHz, 3 V)

VIDEO SECTION

(Standard Video Jacks)

Input/output level and impedance: 1 Vp-p, 75 Ω/ohms
Frequency response: 5 Hz ~ 10 MHz − +0, −3 dB

(S-video jacks)

Input/output level and impedance: Y (brightness) signal − 1 Vp-p, 75Ω/ohms
Frequency response: 5 Hz ~ 10 MHz − +0, −3 dB

C (color) signal − 0.286 Vp-p, 75Ω/ohms

TUNER SECTION

Receiving range: 87.50 MHz ~ 107.90 MHz 520 kHz ~ 1710 kHz

Usable sensitivity: 1.0 µV (11.2 dBf) 18 µV
50 dB quieting sensitivity: MONO 1.6 µV (15.3 dBf)

S/N ratio: MONO 80 dB

Total harmonic distortion: MONO 0.15 %

[FM] (Note: µV at 75 Ω/ohms, 0 dBf = 1 × 10

(for North America model) (for North America model)

87.50 MHz ~ 108.00 MHz 522 kHz ~ 1611 kHz
(for Europe, China, Hong Kong, (for Europe, China, Hong Kong,
Taiwan R.O.C. and Multiple voltage models

STEREO 23 µV (38.5 dBf)

STEREO 75 dB

STEREO 0.3 %

GENERAL

Power supply: AC120 V, 60 Hz (for North America and Taiwan R.O.C. models)

Power consumption: 5.0 A (for North America model)
Maximum external dimensions: 434 (W) × 171 (H) × 416 (D) mm (17-3/32″ × 6-11/32″ × 16-3/8″)

Weight: 11.5 kg (25 lbs. 6 oz.)

AC230 V, 50 Hz (Europe model)
AC220 V, 50 Hz (for China model)
AC115/230 V, 50/60 Hz (for Hong Kong and Multiple voltage)

270 W (for Europe, China, Hong Kong, Taiwan R.O.C. and Multiple voltage models

REMOTE CONTROL UNIT (RC-881: for North America, China, Hong Kong, Taiwan R.O.C. and Multiple voltage models)

(RC-882: for Europe model)

Batteries: R6P/AA Type (two batteries)
External dimensions: 70 (W) × 215 (H) × 24 (D) mm (2-3/4″× 8-15/32″ × 15/16″)
Weight: 200 g (Approx. 7 oz.) (including batteries)

2

135 W + 135 W (6 Ω/ohms, 1 kHz with 0.7 % T.H.D.)
135 W (6 Ω/ohms, 1 kHz with 0.7 % T.H.D.)
135 W + 135 W (6 Ω/ohms, 1 kHz with 0.7 % T.H.D.)

A+B 8 ∼ 16 Ω/ohms

-15

W) [AM]

)

Taiwan R.O.C. and Multiple voltage models

)

)

AVR-2801/981

WIRE ARRANGEMENT

If wire bundles are untied or moved to perform adjustment or parts replacement etc.,be sure to rearrange them neatly as they
were originally bundled or placed afterward.
Otherwise, incorrect arrangement can be a cause of noise generation.

Wire arrangement viewed from the top

3

AVR-2801/981

DISASSEMBLY

(Follow the procedure below in reverse order when reassembling)

1. Top Cover

Remove 3 screws on the rear and 6 screws on both
sides to detach the Top Cover as shown in the arrow
direction.

1

2

Top Cover

1

2

2

2. Front Panel

(1) Remove 7 screws from the top and bottom edges of

the Front Panel.

(2) Release 4 top and bottom hooks, then detach the Front

Panel as shown in the arrow direction.

3

3. Inner Panel

Pull out the Inner Panel in the arrow direction after removing
3 screws .

4

Front panel

Hook

Hook

3

3

Hook

3

4

Hook

4

Inner panel

4

4. Inner Panel Ass'y

(1) Remove 3 round and 1 square knobs, and unscrew 4

nuts.

(2) Remove 19 screws fixing each P.W.B.

5

AVR-2801/981

5

5

Round knob

5. Amp Unit

(1) Remove 2 screw to detach Pre-out Unit .
(2) Take off the Amp Unit as shown in the arrow direction

after removing 1 screw .

6 7

8

9

Nut

Square knob

8

Round knob

9

5

Nut

7

6

6. Regulator Unit

Take off the Regulator Unit as shown in the arrow
direction after removing 8 screws .

10

11

11

10

5

AVR-2801/981

7. S-Video / C-video / Audio-in & DSP /
Ext-in & VR / Digital-in / Tuner Unit

(1) Remove 38 screws to detach the Rear Panel.
(2) Take off the objective P.W.B. upward.

12

Rear Panel

12

12

12

8. How to Check Power Amp /

µµ

µ-com Unit

µµ

with Power-on

(1) Remove 12 screws , 1 screw , and 4 screws

15

fixing to the Chassis.

(2) Pull up the Unit to separate from the Chassis.

13

14

13

13

14

13

15

13

15

13

6

LEVEL DIAGRAM

AVR-2801/981

FRONT

1 4

BUFF.

+

A/D IN AMP

PHONO-IN

EQ.AMP

+

−

32 5

−

RIAA

ADC DSP DAC

LINE-IN

EXT.-IN

(dBV) (dB)

30

40

20

30

−10

−14

−20

−50

10

20

0

10

LINE-IN 200mV
EXT.IN 200mV

0dB

~

~

−30

~

~

PHONO 2.5mV (−52dBV)

−

38dB

−9dB

A/D IN

A/D

0dBfs

−10dBfs

−20dBfs

−30dBfs

D/A

+

−

−

+

D/A OUT AMP

TO

ADDER.

FROM.

(S.W.ch.)

0dBfs

−10dBfs

−20dBfs

D/A OUT(DOLBYDIGITAL: DIALNORM

−30dBfs

H.P.F.

+

−

−27dB)

VR

PRE AMP

+

−

LPF

10kHz: −4dB

CINEMA EQ

1.2V (1.58dBV) (DIRECT)

15.5dB

TONE

+

−

16.5dB

(TONE)

POWER AMP

+

42.6dB→27V, 28.6dBV

876

SP-OUT

H/P-OUT

PRE-OUT

SP-OUT

PRE-OUT

A

B

C

CENTER
SURROUND

EXT.-IN

(dBV) (dB)

30

20

10

0

−10

−14

−20

40

30

20

10

0dB

200mV/EXT.IN

FROM
DSP

DAC

+

−

+

−

D/A OUT AMP

D/A

0dBfs

−10dBfs

−20dBfs

D/A OUT(DOLBYDIGITAL: DIALNORM

−30dBfs

−27dB)

VR

PRE AMP

+

−

LPF

10kHz: −4dB

CINEMA EQ

CENTER CH ONLY

1.2V (1.58dBV)

15.5dB

POWER AMP

+

LEVEL: Same as Front ch

SP-OUT

PRE-OUT

D

SP-OUT

PRE-OUT

E

7

AVR-2801/981

A

B

C

1

SUBWOOFER

EXT.-IN

(dBV)

30

20

10

0

−10

−14

−20

(dB)

40

30

20

10

200mV/EXT.IN

0dB

32

4

8765

(FRONT CH)

(FRONT CH)

FROM

R ch

FROM

FRONT L/R ADD.

L ch

LPF

TO

+−

DAC

Config2

Config1

+

+

−

−

D/A OUT AMP

D/A

0dBfs

−10dBfs

−20dBfs

−30dBfs

−40dBfs

D/A OUT(DOLBYDIGITAL: DIALNORM

11dB

11dB

− − +

ADDER

1.5dB

1.5dB

ATTN.

INV

3dB

TO FRONT CH

2.5dB

−27dB)

PRE AMP

20.5dB

2.15V (6.65dBV)

1.2V (1.58dBV)

20.5dB

PRE-OUT

PRE-OUT

D

E

8

CLOCK FLOW & WAVE FORM IN DIGITAL BLOCK

Wave Form

AVR-2801/981

1

CH1: D-DATA

(IC705 (5) )

2

CH1: DATA

CH2: fs

CH3: 64fs

3

CH1: DATA

CH2: fs

CH3: 64fs

4

CH1: DATA

CH2: fs

CH3: 64fs

CH4: 256fs

9

AVR-2801/981

A

B

C

1

INPUT

SELECTOR1

IC705

TC74HC

151AF

COAX1

OPT1

OPT2
OPT3

*fs is a sampling frequency of input digital signal.
e.g.:sampling frequency 48kHz →fs=48kHz
*64fs and 256fs are 64 or 256 times the sampling
frequency respectively.
e.g.: sampling frequency 48kHz
64fs: 48kHzX64=3.072MHz
256fs: 48kHzX256=12.288MHz
*The samoling frequency for analog input is fixed
to 48kHz internally.
*(No.) indicates the pin unmber of individual
*The arrow indicates the direction of signal
as the input terminal pointed by the arrow
and the output terminal by the opposite.

(13)
(15)
(3)
(2)

(5)

12.287MHz
IC802

SG-8002

2 3

(5)DIN2

(3)

AIN

A/D CONVERTER

DIR

IC800

LC89055W

CKOUT(13)

BCK(14)

LRCK(15)

DATAD(16)

XIN(22)

IC606

(7)

(10)

(13)

SN74LV4040APW

IC604

AK5353

MCLK(11)

SCLK(12)
LRCK(10)

SDATA(9)

A/D SELECTOR

SN74AHC157PW

256fs

DATA

IC804

64fs

4

5

6

256fs

64fs

7 8

D/A CONVERTER

IC701

AD1854

4

21

MCLK

DA SCK

fs

DA LRCK
SD IN

9624 SELECTOR

IC805

TC74HCT157AF

fs

FRONT

CENTER/SW

(2)256fs
(26)64fs

(25)fs

(27)DATA

IC702

AD1854

(2)256fs

(26)64fs
(25)fs
(27)DATA

Fch

C&SWch

3

IC703

AD1854

(2)256fs

(44) (22) (25) (26)

MCLK

(30)CLKIN

SCLKN1LRCKN1SDATAN1

(27) (43) (42)

SCLK LRCLKCMPDAT

AUDATA0(41)

AUDATA1(40)

AUDATA2(39)

IC814

CS492604

DSP1

SURROUND

(26)64fs Sch
(25)fs
(27)DATA

10

D

E

ADJUSTMENTADJUSTMENT

Step

Frequency

Input Level

Modulation

Connect to

1

Tuning Center

Function : FM

Mode : Auto

2

Separation

Stereo (L)

1KHz 100%

Terminal (R)

Separation

3

Signal Level

Step

Connect to

1

(Input level is not over to work A.G.C.)

Oscilloscope

IC502 12Pin

Maximum height and best

symmetry curve

Tuner SectionTuner Section

CONNECTION DIAGRAM OF MEASURING INSTRUMENTSCONNECTION DIAGRAM OF MEASURING INSTRUMENTS

''

FM FM

''

AVR-2801/981AVR-2801/981

AM AM

STEREO
MODULATOR

FMSSG

DIGITAL
VOLTMETER

FM/MPX ALIGNMENT

Alignment

Item

Frequency

98.1 MHz FM SSG 98.1 MHz 60 dBµ None

98.1 MHz FM SSG 98.1 MHz 60 dBµ

Tuning

Setting

75Ω

Type

1U-3235-5TUNERUNIT

VR502

1kHz1kHz

IC502

1

T502

VR501

Coupling Type

Antenna
Terminal

Antenna
Terminal

Digital

Voltmeter

AC

Voltmeter

TP102 T502 ± 50mV

AUDIO

OUT

TP102

Input Output Adjust

Points Adjust to

VR502

Maximum

Remarks



OSCILLOSCOPE

OUT

AMIF

GND

AM

1U-3235-5TUNERUNIT

T503

1

12

IC502

Pin

AM ALIGNMENT

Alignment

Item

IF 

98.1 MHz FM SSG 98.1 MHz 20 dBµ Off

Frequency Input

IF SWEEP

Type

Antenna
Terminal

Output Adjustment

  VR501

Points Adjust to

T503

Light

“TUNED”

FLD

Character



Remarks

1111

AVR-2801/981

Audio Section

Idling Current (1U-3232-1)

Required measurement equipment : DC Voltmeter

Preparation

(1) Avoid direct blow from an air conditioner or an electric fan, and adjust the unit at normal room tempereture 15 °C ~ 30 °C

(59 °F ~ 86 °F).

(2) Presetting

l POWER (Power sourse switch) → OFF
l SPEAKER (Speaker terminal) → No load (Do not connect speaker, dummy resistor, etc.)

Adjustment

(1) Remove top cover and set VR501, VR502, VR503, VR504, VR505, on 1U-3232-1 (Power Unit) at counterclockwise

(

) fully.

(2) Connect DC Voltmeter to test points (FRONT-Lch: TP501, FRONT-Rch: TP502, CENTER ch: TP505, SURROUND-Lch:

TP503, SURROUND-Rch: TP504).

(3) Connect power cord to AC Line, and turn power switch "ON".

(4) Presetting. MASTER VOLUME : "---" counterclockwise (

min.)

MODE : 5CH STEREO
FUNCTION : CD

(5) Allow 2 minutes, and turn VR501 clockwise ( ) and adjust the TEST POINT voltage to 1.5 mV ±0.5 mV DC.
(6) After 10 minutes from preset, turn VR501 to set the voltage to 3 mV ±0.5 mV DC.

(7) Adjust the Variable Resistors of other channels in the same way.
(8) After 5 minutes from (6), turn VR501 to set the voltage to 3 mV ±0.5 mV DC.
(9) Adjust the Variable Resistors of other channels in the same way.

VR504

S Rch

F Rch

Cch

DC Voltmeter

F Lch

TP504

VR502

TP502

VR505

TP505

VR501

TP501

12

S Lch

VR503

TP503

1

24

AVR-2801/981AVR-2801/981

SEMICONDUCTORSSEMICONDUCTORS

&&

IC’sIC’s

Note:Note: Abbreviation ahead of IC No. indicates the name of P.W.B.Abbreviation ahead of IC No. indicates the name of P.W.B.

PO:PO: Power P.W.B.Power P.W.B. RE:RE: Requlator P.W.B.Requlator P.W.B.
EX:EX: Exit in P.W.B.Exit in P.W.B. AU:AU: Audio/DSP P.W.B.Audio/DSP P.W.B.
CO:CO: Control P.W.B.Control P.W.B.

TMP88CU74FTMP88CU74F (CO: IC303)(CO: IC303)

64

65

80

TMP88CU74F Terminal FunctionTMP88CU74F Terminal Function

PinPin

NameName

No.No.

11 P02/S01P02/S01 RDS RESETRDS RESET OO CC   ZZ LL RDS reset output (LC7074)RDS reset output (LC7074)
22 P03P03 OSD RSTOSD RST OO CC   ZZ HH OSD control output (M35015)OSD control output (M35015)
33 P04P04 ST/MONOST/MONO OO CC   ZZ LL STEREO/MONO control signal, L: STEREOSTEREO/MONO control signal, L: STEREO
44 P05P05 PLFL DATAPLFL DATA OO CC   ZZ LL PLL, FL control terminal (LC72131 & LC75721NE)PLL, FL control terminal (LC72131 & LC75721NE)
55 P06P06 PLL STBPLL STB OO CC   ZZ LL PLL control terminal (LC72131)PLL control terminal (LC72131)
66 P07P07 PLFL CLKPLFL CLK OO CC   ZZ LL PLL, FL control terminal (LC72131 & LC75721NE)PLL, FL control terminal (LC72131 & LC75721NE)
77 VssVss VssVss II  GNDGND   LL GNDGND
88 XoutXout XoutXout OO      XTALXTAL

99 XinXin XinXin II      XTALXTAL
1010 RESET_RESET_ RESET_RESET_ II  EuEu LvLv LL  Reset inputReset input
1111 P22/XTOUTP22/XTOUT TUNED_TUNED_ II  EuEu LvLv ZZ  Tuning detect, L: TunedTuning detect, L: Tuned
1212 P21/XTINP21/XTIN STEREO_STEREO_ II  EuEu LvLv ZZ  L: At stereo receiveL: At stereo receive
1313 TESTTEST TESTTEST II  GNDGND SS   Connect to GNDConnect to GND
1414 P20/INT5_P20/INT5_ B.DOWN_B.DOWN_ II  EuEu LvLv ZZ  Power down detect, L: Power downPower down detect, L: Power down
1515 P10/INT0_P10/INT0_ PROTECT_PROTECT_ II  EdEd E&LE&L ZZ  PROTECTION detect input, H: DetectPROTECTION detect input, H: Detect
1616 P11/INT1P11/INT1 RDS STARTRDS START II    ZZ LL RDS data input (LC7074)RDS data input (LC7074)
1717 P12P12 OSD CLKOSD CLK OO CC   ZZ HH OSD control output (M35015)OSD control output (M35015)
1818 P13P13 OSD CSOSD CS OO CC   ZZ HH OSD control output (M35015)OSD control output (M35015)
1919 P14P14 OSD DATAOSD DATA OO CC   ZZ LL OSD control output (M35015)OSD control output (M35015)
2020 P15/INT3P15/INT3 REMOCONREMOCON II  EdEd E&LE&L ZZ  Remote control signal inputRemote control signal input
2121 P16/INT2P16/INT2 ACKACK OO CC   ZZ LL MAIN-SUB CPU comm. control terminalMAIN-SUB CPU comm. control terminal
2222 P17/INT4P17/INT4 REQREQ II  EuEu  ZZ LL MAIN-SUB CPU comm. control terminalMAIN-SUB CPU comm. control terminal
2323 P30/SCLP30/SCL SISI II MAIN-SUB CPU comm. control terminalMAIN-SUB CPU comm. control terminal
2424 P31/SDAP31/SDA SOSO OO CC MAIN-SUB CPU comm. control terminalMAIN-SUB CPU comm. control terminal
2525 P32/SCK0_P32/SCK0_ CLKCLK OO CC MAIN-SUB CPU comm. control terminalMAIN-SUB CPU comm. control terminal
2626 P40/AIN0P40/AIN0 MODEMODE II  EuEu LvLv ZZ  Destination switching inputDestination switching input
2727 P41/AIN1P41/AIN1 KEY1KEY1 II  EuEu LvLv ZZ  Button input 1Button input 1
2828 P42/AIN2P42/AIN2 KEY2KEY2 II  EuEu LvLv ZZ  Button input 2Button input 2
2929 P43/AIN3P43/AIN3 KEY3KEY3 II  EuEu LvLv ZZ  Button input 3Button input 3
3030 P44/AIN4P44/AIN4 FUNC STB1FUNC STB1 OO CC   ZZ  Function control output (TC9274N), INPUTFunction control output (TC9274N), INPUT
3131 P45/AIN5P45/AIN5 FUNC/T. CON CLKFUNC/T. CON CLK OO CC   ZZ LL
3232 P46/AIN6P46/AIN6 FUNC/T. CON DATAFUNC/T. CON DATA OO CC   ZZ LL
3333 P47/AIN7P47/AIN7 FUNC STB2FUNC STB2 OO CC   ZZ LL Function control output (NJU7313), 6CH EXT. INFunction control output (NJU7313), 6CH EXT. IN
3434 P50/AIN8P50/AIN8 E.VOL STBE.VOL STB OO CC   LL LL Elect. volume control output (TC9459)Elect. volume control output (TC9459)
3535 P51/AIN9P51/AIN9 TONE STBTONE STB OO CC   LL LL TONE control output (TC9184P)TONE control output (TC9184P)
3636 P52/AIN10P52/AIN10 E.VOL DATAE.VOL DATA OO CC   LL HH Elect. volume control output (TC9459)Elect. volume control output (TC9459)
3737 P53/AIN11P53/AIN11 E.VOL CLKE.VOL CLK OO CC   LL HH Elect. volume control output (TC9459)Elect. volume control output (TC9459)

SymbolSymbol

I/OI/O TypeType OpOp DetDet ResRes InitInit

41

40

25

FunctionFunction

Function control output (TC9274N, TC9273), TONE control output (TC9184P)Function control output (TC9274N, TC9273), TONE control output (TC9184P)
Function control output (TC9274N, TC9273), TONE control output (TC9184P)Function control output (TC9274N, TC9273), TONE control output (TC9184P)

PinPin
No.No.

NameName

SymbolSymbol

I/OI/O TypeType OpOp DetDet ResRes InitInit

FunctionFunction

3838 VASSVASS VASSVASS II Ref. volt (GND)Ref. volt (GND)
3939 VAREFVAREF VAREFVAREF II Ref. volt (VDD)Ref. volt (VDD)
4040 VDDVDD VDDVDD II Power supplyPower supply
4141 P60P60 FL CEFL CE OO PP EdEd SS LL HH FL display control output (LC75712NE)FL display control output (LC75712NE)
4242 P61P61 FL RESFL RES OO PP EdEd SS LL HH FL display control output (LC75712NE)FL display control output (LC75712NE)
4343 P62P62 FUNC STB3FUNC STB3 OO PP EdEd  ZZ LL Function control output (TC9273), REC OUTFunction control output (TC9273), REC OUT
4444 P63P63 FA-RELAYFA-RELAY OO PP IdId  LL LL Front SP relay A control terminal, L: MuteFront SP relay A control terminal, L: Mute
4545 P64P64 FB-RELAYFB-RELAY OO PP IdId  LL LL Front SP relay B control terminal, L: MuteFront SP relay B control terminal, L: Mute
4646 P65P65 C-RELAYC-RELAY OO PP IdId  LL LL Center SP relay control terminal, L: MuteCenter SP relay control terminal, L: Mute
4747 P66P66 S-RELAYS-RELAY OO PP IdId  LL HH Surround SP relay control terminal, L: MuteSurround SP relay control terminal, L: Mute
4848 P67P67 PRE F MUTEPRE F MUTE OO PP EdEd  LL HH Front PRE OUT mute control terminal, L: MuteFront PRE OUT mute control terminal, L: Mute
4949 P70P70 PRE C MUTEPRE C MUTE OO PP EdEd  LL LL Center PRE OUT mute control terminal, L: MuteCenter PRE OUT mute control terminal, L: Mute
5050 P71P71 PRE S MUTEPRE S MUTE OO PP EdEd  LL LL Surround PRE OUT mute control terminal, L: MuteSurround PRE OUT mute control terminal, L: Mute
5151 P72P72

SUB WOOFER MUTESUB WOOFER MUTE

OO PP EdEd  LL HH Sub-woofer PRE OUT mute control terminal, L: MuteSub-woofer PRE OUT mute control terminal, L: Mute
5252 P73P73 H/P RELAYH/P RELAY OO PP IdId  LL HH H/P OUT relay control terminal, L: MuteH/P OUT relay control terminal, L: Mute
5353 P74P74 EXP OEEXP OE OO PP EdEd  LL HH Port expander control terminal (BU4094B)Port expander control terminal (BU4094B)
5454 P75P75 EXP CLKEXP CLK OO PP EdEd  LL LL Port expander control terminal (BU4094B)Port expander control terminal (BU4094B)
5555 P76P76 EXP DATAEXP DATA OO PP EdEd  LL LL Port expander control terminal (BU4094B)Port expander control terminal (BU4094B)
5656 P77P77 EXP STBEXP STB OO PP EdEd  LL LL Port expander control terminal (BU4094B)Port expander control terminal (BU4094B)
5757 P80P80 POWERPOWER OO PP IdId  LL HH Power relay control output, H: ONPower relay control output, H: ON
5858 P81P81 RESET2RESET2 OO PP IdId  LL LL Reset signal output to sub-CPU, H: ResetReset signal output to sub-CPU, H: Reset
5959 P82P82 SUB-CPU-B-DOWNSUB-CPU-B-DOWN OO PP IdId  LL LL B-DOWN signal output to sub-CPUB-DOWN signal output to sub-CPU
6060 P83P83 TAPE MON. LEDTAPE MON. LED OO PP IdId  LL LL TAPE MONITOR LED indicator control, H: MONITORTAPE MONITOR LED indicator control, H: MONITOR
6161 P84P84 STANDBYSTANDBY OO PP IdId  LL HH Standby LED drive output H: LightStandby LED drive output H: Light
6262 P85P85 DIRECTDIRECT OO PP IdId  LL LL DIRECT relay control, H: DIRECTDIRECT relay control, H: DIRECT
6363 P86P86 S1S1 OO PP IdId  LL  Video signal switching control outputVideo signal switching control output
6464 P87P87 S2S2 OO PP IdId  LL  Video signal switching control outputVideo signal switching control output
6565 P90P90 TUNER MUTETUNER MUTE OO PP EdEd  LL HH TUNER mute control terminal, H: MuteTUNER mute control terminal, H: Mute
6666 P91P91 OO PP IdId  LL HH Not UsedNot Used
6767 P92P92 S MONI DETS MONI DET II  EuEu LvLv ZZ  S monitor connection detect input, L: ConnectedS monitor connection detect input, L: Connected
6868 P93P93 S SIG DETS SIG DET II  EuEu LvLv ZZ  S signal detect input, H: DetectedS signal detect input, H: Detected
6969 P94P94 SYNC DET.SYNC DET. II  EuEu LvLv ZZ  Sync detect input, H: Ext. syncSync detect input, H: Ext. sync
7070 P95P95 SEL A (M)SEL A (M) II  EuEu LvLv ZZ  Master volume rotation detect input (rotary encoder)Master volume rotation detect input (rotary encoder)
7171 P96P96 SEL B (M)SEL B (M) II  EuEu LvLv ZZ  Master volume rotation detect input (rotary encoder)Master volume rotation detect input (rotary encoder)
7272 P97P97 CINEMA EQCINEMA EQ OO PP EuEu LvLv ZZ LL CINEMA EQ control output, H: ONCINEMA EQ control output, H: ON
7373 PD0PD0 VOL MUTEVOL MUTE OO PP EdEd  LL LL Master volume minimum control, L: Min.Master volume minimum control, L: Min.
7474 PD1PD1 SEL C (S)SEL C (S) II  EuEu LvLv ZZ  Surround mode rotation detect input (rotary encoder)Surround mode rotation detect input (rotary encoder)
7575 PD2PD2 SEL D (S)SEL D (S) II  EuEu LvLv ZZ  Surround mode rotation detect input (rotary encoder)Surround mode rotation detect input (rotary encoder)
7676 PD3PD3 SEL E (F)SEL E (F) II  EuEu LvLv ZZ  Input selector switch rotation detect input (rotary encoder)Input selector switch rotation detect input (rotary encoder)
7777 PD4PD4 SEL F (F)SEL F (F) II  EuEu LvLv ZZ  Input selector switch rotation detect input (rotary encoder)Input selector switch rotation detect input (rotary encoder)
7878 VkkVkk VkkVkk       GND fixedGND fixed
7979 P00/SCK1_P00/SCK1_ RDS CLKRDS CLK II   SS ZZ  RDS clock input (LC7074)RDS clock input (LC7074)
8080 P01/SI1P01/SI1 RDS DATARDS DATA II   SS ZZ  RDS data input (LC7074)RDS data input (LC7074)

NOTE:

Pin No. : Terminal number of microcomputer.
Port Name : The name entered in the data sheet of microcomputer.
Symbol : Symbolized interface function.
I/O : Input or out of part.

Type : Composition of port in case of output port.

Op : Pull up/Pull down selection information.

Det : Indicates judging state of input port. Level detection is “LV”; Edge detection is “Ed”; Detection by both shifting is “E&L”;

Res : State at reset.

Ini : Initial output state.
Function : Function and logical level explanation of signals to be interface.

Serial data detection is “S” (Serial data output is also “S”).

“I” = Input port
“O” = Output port

“C” = CMOS output
“N” = NMOS open drain output
“P” = PMOS open drain output

“Iu” = Inner microcomputer pull up
“Id” = Inner microcomputer pull down
“Eu”= External microcomputer pull up
“Ed”= External microcomputer pull down

“H” = Outputs High Level at reset
“L” = Outputs Low Level at reset
“Z” = Becomes High impedance mode at reset

1313

AVR-2801/981AVR-2801/981

TMP93CS41F (AU: IC301)TMP93CS41F (AU: IC301)

76

100

75

1

51

50

26

25

TMP93CS41F Terminal FunctionTMP93CS41F Terminal Function

PinPin
No.No.

11 V REFLV REFL       A/D ref. GNDA/D ref. GND
22 A VssA Vss ←←       A/D GNDA/D GND
33 A VccA Vcc ←←       AD +5VAD +5V
44 _NMI_NMI II      Not used (fixed to H)Not used (fixed to H)
55 P70/TI0P70/TI0 C15C15 OO CC   LL LL Fixed to L (DSP ROM address cont. out bit 15, not used)Fixed to L (DSP ROM address cont. out bit 15, not used)
66 P71/TO1P71/TO1 C16C16 OO CC   LL LL DSP program ROM address cont. output bit 16DSP program ROM address cont. output bit 16
77 P72/TO2P72/TO2 C17C17 OO CC   LL LL DSP program ROM address cont. output bit 17DSP program ROM address cont. output bit 17
88 P73/TO3P73/TO3 OO CC   LL LL

99 P80/INT4/TI4P80/INT4/TI4 _INTREQ_INTREQ I/OI/O CC EuEu EE↓↓&L&L ZZ  DSP request input and cont. output (L: Rq & cont.)DSP request input and cont. output (L: Rq & cont.)
1010 P81/INT5/TI5P81/INT5/TI5 B. DOWN_B. DOWN_ II  EuEu EE↑↑&L&L ZZ  Power down detect (H: Detected)Power down detect (H: Detected)
1111 P82/TO4P82/TO4 DSP SSDSP SS OO CC   ZZ LL

1212 P83/TO5P83/TO5 _REQ_REQ OO CC EuEu  HH LL
1313 P84/INT6/TI6P84/INT6/TI6 _ACK_ACK II  EuEu EE↓↓&L&L   MAIN-SUB CPU comm. control input (L: Ack. return from main)MAIN-SUB CPU comm. control input (L: Ack. return from main)

1414 P85/INT7/TI7P85/INT7/TI7 ERRERR II   EE↑↑&L&L   DIR control input terminal (LC89055Q)( H: ERR)DIR control input terminal (LC89055Q)( H: ERR)
1515 P86/TO6P86/TO6 _DSP RESET_DSP RESET OO CC   LL LL DSP reset output terminal (L: Reset)DSP reset output terminal (L: Reset)

1616 P87/INT0P87/INT0 _CS_CS II   EE↑↑&L&L  

1717 P90/TXD0P90/TXD0 SISI OO CC MAIN-SUB CPU comm. control terminal (data output)MAIN-SUB CPU comm. control terminal (data output)
1818 P91/RXD0P91/RXD0 SOSO II  MAIN-SUB CPU comm. control terminal (data input)MAIN-SUB CPU comm. control terminal (data input)
1919
2020 P93/TXD1P93/TXD1 DSP DATADSP DATA OO CC   ZZ LL
2121 P94/RXD1P94/RXD1 DSP SODSP SO OO CC  LvLv ZZ LL
2222 P95/SCLK1P95/SCLK1 DSP CLKDSP CLK OO CC   ZZ LL
2323 AM8/_16AM8/_16 ←←       Fixed to +5VFixed to +5V
2424 CLKCLK OO CC EuEu   
2525 VccVcc ←←       +5V+5V
2626 VssVss I/O1I/O1       GNDGND
2727 X1X1 XinXin II      XX′′tal connectiontal connection
2828 X2X2 XoutXout OO      XX′′tal connectiontal connection
2929 _EA_EA ←←       Fixed to GNDFixed to GND
3030 _RESET_RESET RESET2_RESET2_ II  EuEu LvLv LL  Reset input (controlled by main CPU)Reset input (controlled by main CPU)
3131 P96/XT1P96/XT1 A/D RESETA/D RESET OO NN EuEu  HH HH A/D control terminal (L: Reset)A/D control terminal (L: Reset)
3232 P97/XT2P97/XT2 OO CC EdEd  LL LL
3333 TEST1TEST1 ←← ΙΙ      Connected to TEST2Connected to TEST2
3434 TEST2TEST2 ←← ΙΙ      Connected to TEST1Connected to TEST1
3535 PA0PA0 DINADINA OO CC EdEd  LL LL Digital input switching control outputDigital input switching control output
3636 PA1PA1 DINBDINB OO CC EdEd  LL LL Digital input switching control outputDigital input switching control output
3737 PA2PA2 DINCDINC OO CC EdEd  LL LL Digital input switching control outputDigital input switching control output
3838 PA3PA3 OO CC EdEd  LL LL
3939 PA4PA4 DIRECTDIRECT OO CC EdEd  LL LL Digital direct data switch cont. terminal (H: Direct)Digital direct data switch cont. terminal (H: Direct)
4040 PA5PA5 OO CC EdEd  LL LL

NameName FunctionFunction

P92/_CTS0/SCLK0P92/_CTS0/SCLK0

SymbolSymbol

CLKCLK II CC MAIN-SUB CPU comm. control terminal MAIN-SUB CPU comm. control terminal (I2C clock in/output)(I2C clock in/output)

I/OI/O TypeType OpOp DetDet ResRes InitInit

MAIN-SUB CPU comm. control output (L: Comm. request fromMAIN-SUB CPU comm. control output (L: Comm. request from
sub)sub)

DIR control input terminal (LC89055Q), when CH status changeDIR control input terminal (LC89055Q), when CH status change
LL→→HH

PinPin
No.No.

4141 PA6PA6 DEEMPDEEMP OO CC EdEd  LL LL DAC de-emphasis filter cont. out terminal (H: ON)DAC de-emphasis filter cont. out terminal (H: ON)
4242 PA7/SCOUTPA7/SCOUT 96k-DAC96k-DAC OO CC   ZZ LL DAC control terminal (H: Sample frequency 96kHz)DAC control terminal (H: Sample frequency 96kHz)
4343 ALEALE ←← OO CC   LL LL Address latch enableAddress latch enable
4444 VccVcc       +5V+5V

4545 P00/AD0P00/AD0 AD0AD0 II     
4646 P01/AD1P01/AD1 AD1AD1 II     
4747 P02/AD2P02/AD2 AD2AD2 II     
4848 P03/AD3P03/AD3 AD3AD3 II     
4949 P04/AD4P04/AD4 AD4AD4 II     
5050 P05/AD5P05/AD5 AD5AD5 II     
5151 P06/AD6P06/AD6 AD6AD6 II     
5252 P07/AD7P07/AD7 AD7AD7 II     
5353 P10/AD8/A8P10/AD8/A8 A8A8 II     
5454 P11/AD9/A9P11/AD9/A9 A9A9 II     
5555 P12/AD10/A10P12/AD10/A10 A10A10 II     
5656 P13/AD11/A11P13/AD11/A11 A11A11 II     
5757 P14/AD12/A12P14/AD12/A12 A12A12 II     
5858 P15/AD13/A13P15/AD13/A13 A13A13 II     
5959 P16/AD14/A14P16/AD14/A14 A14A14 II     
6060 P17/AD15/A15P17/AD15/A15 A15A15 II     

6161 _WDTOUT_WDTOUT ←← OO CC   ZZ HH
6262 VssVss ←←       GNDGND
6363 VccVcc ←←       +5V+5V

6464 P20/A0/A16P20/A0/A16 A16A16 II     
6565 P21/A1/A17P21/A1/A17 DIR CLKDIR CLK OO CC   ZZ LL DIR control terminal (LC89055Q) control clock outputDIR control terminal (LC89055Q) control clock output
6666 P22/A2/A18P22/A2/A18 DIR CEDIR CE OO CC   ZZ LL DIR control terminal (LC89055Q) control chip enable outputDIR control terminal (LC89055Q) control chip enable output
6767 P23/A3/A19P23/A3/A19 DIR MOSIDIR MOSI OO CC   ZZ LL DIR control terminal (LC89055Q) control data outputDIR control terminal (LC89055Q) control data output
6868 P24/A4/A20P24/A4/A20 DIR MISODIR MISO II   LvLv   DIR control terminal (LC89055Q) control data inputDIR control terminal (LC89055Q) control data input
6969 P25/A5/A21P25/A5/A21 SW-SUMSW-SUM OO CC   LL LL Subwoofer output summation cont. outputSubwoofer output summation cont. output

7070 P26/A6/A22P26/A6/A22 DAC-RESETDAC-RESET OO CC   LL HH
7171 P27/A7/A23P27/A7/A23 SEL CKSEL CK OO CC   ZZ LL ADC/DIR data clock switching control terminal (L: ADC)ADC/DIR data clock switching control terminal (L: ADC)

7272 P30/_RDP30/_RD _RD_RD OO CC   ZZ LL

7373 P31/_WRP31/_WR _WR_WR OO CC   ZZ LL
7474 P32/_HWRP32/_HWR CSICSI II   LvLv   DIR control input terminal (L: PCM)DIR control input terminal (L: PCM)
7575 P33/_WAITP33/_WAIT ERR MUTE_ERR MUTE_ OO CC   LL LL Pop noise preventive mute control output (L: Mute)Pop noise preventive mute control output (L: Mute)

7676 P34/_BUSRQP34/_BUSRQ II     
7777 P35/_BUSRQP35/_BUSRQ DIG. (AC3) MUTEDIG. (AC3) MUTE OO CC   ZZ LL Digital mute control output (L: AC-3 or DTS decode enable)Digital mute control output (L: AC-3 or DTS decode enable)

7878 P36/_R/WP36/_R/W II     
7979 P37/_RASP37/_RAS DIR RESETDIR RESET OO CC   ZZ LL DIR control output (LC89055Q) (L: Reset)DIR control output (LC89055Q) (L: Reset)
8080 P40/_CS0/_CAS0P40/_CS0/_CAS0 OO CC   ZZ LL
8181
8282
8383 P60/PG00P60/PG00 DSP C. RESETDSP C. RESET OO CC   ZZ LL DSP reset output terminal (L: Reset)DSP reset output terminal (L: Reset)
8484 P61/PG01P61/PG01 SCDOUTSCDOUT II   LvLv   DSP status data input terminalDSP status data input terminal
8585 P62/PG02P62/PG02 DSP_C. CSDSP_C. CS OO CC   ZZ LL DSP chip select cont. output (L: Data out)DSP chip select cont. output (L: Data out)
8686 P63/PG03P63/PG03 DSP C. CLKDSP C. CLK OO CC   ZZ LL DSP data clock output terminalDSP data clock output terminal
8787 P64/PG10P64/PG10 SCDINSCDIN OO CC   ZZ LL DSP data output terminalDSP data output terminal
8888 P65/PG11P65/PG11 OO CC   ZZ LL
8989 P66/PG12P66/PG12 OO CC   ZZ LL
9090 P67/PG13P67/PG13 OO CC   ZZ LL
9191 VssVss ←←       GNDGND

9292 P50/AN0P50/AN0 II     

9393 P51/AN1P51/AN1 II     
9494 P52/AN2P52/AN2 EMPEMP II   LvLv   H: EMP onH: EMP on
9595 P53/AN3P53/AN3 96K DET96K DET II   LvLv   96k signal detect input, H: 96k96k signal detect input, H: 96k

9696 P54/AN4P54/AN4 II     

9797 P55/AN5P55/AN5 II     

9898 P56/AN6P56/AN6 II     

9999 P57/AN7P57/AN7 II     

100100 V REFHV REFH ←←       AD ref. +5VAD ref. +5V

NameName

P41/_CS1/_CAS1P41/_CS1/_CAS1
P42/_CS2/_CAS2P42/_CS2/_CAS2

SymbolSymbol

_CS0_CS0 OO CC   ZZ LL Flash memory control terminalFlash memory control terminal

I/OI/O TypeType OpOp DetDet ResRes InitInit

DAC control terminal (L: Power down mode, DAC control terminal (L: Power down mode, →→(rising edge) Reset)(rising edge) Reset)

OO CC   ZZ LL

FunctionFunction

1414

LC89055W (AU: IC800)

DIDOERROR

BPSYNC

AUTO

DGND

DVDD

VF/P3/C3

F2/P2/C2

F1/P1/C1

F0/P0/C0

CSFLAG

AVDD

AGND

Function

AUDIO

EMPHA

XIN

XOUT

XMCK

DVDD

DGND

XSTATE

DATA0

LRCK

BCK

CKOUT

CE

CL

XSEL

MODE0

MODE1

DGND

DVDD

DOSEL0

DOSEL1

CKSEL0

CKSEL1

XMODE

R

VIN

LPF

DVDD

LC89055W Terminal Function

Pin
No.

Pin Name

I/O

DISEL

DIN0

DIN1

DIN2

DOUT

DGND

1 DISEL I Data input terminal (select input pin of DIN0, DIN1)
2 DOUT O Input bi-phase data through output terminal
3 DIN0 I Amp built-in coaxial/optical input correspond data input terminal
4 DIN1 I Amp built-in coaxial/optical input correspond data input terminal
5 DIN2 I Optical input correspond data input terminal
6 DGND Digital GND
7 DVDD Digital power supply
8 R I VCO gain control input terminal

9 VIN I VCO free-run frequency setting input terminal
10 LPF O PLL loop filter setting terminal
11 AVDD Analog power supply
12 AGND Analog GND
13 CKOUT O Clock output terminal (256fs, 384fs, 512fs, X′tal osc., VCO free-run osc.)
14 BCK O 64fs clock output terminal
15 LRCK O fs clock output terminal (L: Rch, H: Lch, I2S: Reverse)
16 DATAO O Data o utput ter minal
17 XSTATE O Input data detecting result output terminal
18 DGND Digital GND
19 DVDD Digital power supply
20 XMCK O X′tal osc. clock output terminal (24.576MHz or 12.288MHz)
21 XOUT O X′tal osc. connection output terminal
22 XIN I X′tal osc. connection output terminal
23 EMPHA O Emphasis information output terminal of channel status
24 AUDIO O Bit1 output terminal of channel status
25 CSFLAG O Top 40bit revise flag output terminal of channel status
26 F0/P0/C0 O Input fs cal. sig. out / data type out / input word inf. output terminal
27 F1/P1/C1 O Input fs cal. sig. out / data type out / input word inf. output terminal
28 F2/P2/C2 O Input fs cal. sig. out / data type out / input word inf. output terminal
29 VF/P3/C3 O Validity flag out / data type out / input word inf. output terminal
30 DVDD Digital power supply
31 DGND Digital GND
32 AUTO O Non PCM burst data transfer detect sig. output terminal
33 BPSYNC O Non PCM burst data preamble Pa, Pb, Pc, Pd sync sig. output terminal
34 ERROR O PLL lock error, data error flag output terminal
35 DO O CPU I/F read data output terminal
36 DI I CPU I/F write data input terminal
37 CE I CPU I/F chip enable input terminal
38 CL I CPU I/F clock input terminal
39 XSEL I Frequency select input pin of XIN X′tal osc. (24.576MHz or 12.288MHz)
40 MODE0 I Mode setting input terminal
41 MODE1 I Mode setting input terminal
42 DGND Digital GND
43 DVDD Digital power supply
44 DOSEL0 I Data output format select input terminal
45 DOSEL1 I Data output format select input terminal
46 CKSEL0 I Output clock select input terminal
47 CKSEL1 I Output clock select input terminal
48 XMODE I Reset input terminal

* For latch-up countermeasure, set digital (DVDD) and analog (AVDD) power on/off in the same timing.

AVR-2801/981

15

AVR-2801/981

M35015-204SP (RE: IC308)

1 2 19 18

HOR*VERT*OSC2OSC1

SYNC SIGNAL DIS-

CRIMINATING CIRCUIT

OSC CIRCUIT

FOR SYNC SIGNAL

GENERATION

TIMING

GENERATOR

NTSC

VIDEO OUTPUT

CIRCUIT

20

OSC1

OSC2

SCK

V

CVIDEO

LECHA

CVIN

3

CS

SCK

SIN

10

1

1
2

3

CS

4

SIN

5
6

AC

DD2

7
8

9

10

20
19
18
17

16
15
14

13

12
11

DD1

V
VERT*
HOR*

OSCIN

OSCOUT
P3
P2

P1
P0

Vss

V

DD1

AC

Vss

DD2

V

INPUT

4

CONTROL

CIRCUIT

5

DATA

CONTROL

CIRCUIT

20

6

11

7

ADDRESS
CONTROL

CIRCUIT

INDICATION

CONTROL

REGISTER

INDICATION RAM

INDICATION CHARACTER ROM

INDICATION

OSCILLATOR

TIMING

GENERATOR

BLINKING CIRCUIT

H COUNTER

IINDICATION LOCATION

DETECTION CIRCUIT

READ OUT ADDRESS

CONTROL CIRCUIT

INDICATION

CONTROL CIRCUIT

SHIFT REGISTER

SYNC SIGNAL

SWITCHING CIRCUIT

M35015-204SP Terminal Function

Pin No. Symbol Name I/O Function

1 OSC1 Osc. circuit ext. I External terminal for indication oscillator circuit. Standard OSC. freq. is approx. 7MHz.
2 OSC2 terminal. O With this OSC. freq., decides horizontal indicatin and character width.

3 CS Chip select input I

4 SCK Serial clock input I

5 SIN Serial data input I

6 AC Auto-clear input I

7V

DD2

8CVIDEO

9 LECHA

10 CVIN

Power supply
Combined

video output
Character level
input
Combined video
input

11 Vss Ground  Ground terminal. Connect to GND.

12 P0 Output port p0 O

13 P1 Output port P1 O

14 P2 Output port P2 O

15 P3 Output port P3 O

16 OSCOUT O Terminal for external use of sync signal OSC. circuit. Use the freq.: 14.32MHz at NTSC
17 OSCIN I system, 17.73MHz at PAL. system, 14.30MHz at MPAL system.

18 HOR*

19 VERT*

20 V

DD1

Ext. terminal
for sync sig.
OSC. Circuit

Horizontal sync
signal
Vertical sync
signal
Power supply I Power supply terminal of digital system. Connect to +5V.

Chip select terminal and turns to “L” when transfer serial data.
Hysteresis input. Pull up resistor is built-in.
Takes in serial data of SIN at SCK rise when CS terminal is in “L”.
Hysteresis input. Pull up rersist is built-in.
Serial input of register for indication control and data, and address for indication data
memory. Hysteresis input. Pull up rersistor is built-in.
Resets internal circuit of IC at “L” mode.
Hysteresi input. Pull up resistor is built-in.
Power supply terminal of analog system. Connect to +5V.



Output terminal of combined video signal. Outputs 2Vp-p combined signal. Character

O

output, etc. Overlap CVIN signal and outputs at superimpose.
Input terminal deciding character output level in combined video signal. color of character

I

is white.
Input terminal of external combined video signal.

I

Character output etc. overlap this external combined video signal.

General output or character background signal BL NK1* output is switchable.
Polarity can be selected at ROM mask.
General output or character background signal CO1* output is switchable.
Polarity can be selected at ROM mask.
General output or character background signal BLNK2* output is switchable.
Polarity can be selected at ROM mask.
General output or character background signal CO2* output is switchable.
Polarity can be selected at ROM mask.

Inputs horizontal sync signal.

I

Hysteresis input.

Input vertical sync signal. Hysteresis input. Polarity can be selected at ROM mask.



17

16

8

9

10

12

13

14

15

OSCIN

OSCOUT

CVIDEO

LECHA

CVIN

P0

P1

P2

P3

16

CS492604-CLR
(AU: IC814)

A0,SCCLK
DATA7,EMAD7,GPIO7
DATA6,EMAD6,GPIO6
DATA5,EMAD5,GPIO5
DATA4,EMAD4,GPIO4

DATA3,EMAD3,GPIO3
DATA2,EMAD2,GPIO2
DATA1,EMAD1,GPIO1
DATA0,EMAD0,GPIO0

VD2

DGND2

A1,SCDIN

7

8

9

10

11

12

13

14

15

16

17

18 19 20 21 22

CS

AVR-2801/981

RD,R/W,EMOE,GPIO11

WR,DS,EMWR,GPIO10

XMT958

DGND1

VD1

MCLK

SCLK

LRCLK

AUDATA0

AUDATA1

41

ABOOT,INTREQ

44

1234

VD3

SDATAN1

EXTMEM,GPIO8

40

42

43

39

AUDATA2

38

DC

37

DD
RESET

36

AGND

35

34

VA
FILT1

33

FILT2

32

CLKSEL

31

CLKIN

30

CMPREQ,LRCLKN2

29

282726252423

DGND3

LRCLKN1

CMPCLK,SCLKN2

SCLKN1,STCCLK2

CMPDAT,SDATAN2

56

CS492604-CLR Terminal Function

Pin
No.

Pin Name

SCDIO,SCDOUT,PSEL,GPIO9

Function

1 VD1 Digital positive supply
2 DGND1 Digital supply ground
3 XMT958 SPDIF transmitter output
4 WR, DS, EMWR, GPIO10

Host write strobe or host data strobe or external memory write enable or general purpose input & output number10

5 RD, R/W, EMOE, GPIO11 Host parallel output enable or host parallel R/W or external memory outout enable or general

purpose input & output number11
6 A1, SCDIN Host adddress bit one or SPI serial control data input
7 A0, SCCLK Host parallel address bit zero or serial control port clock
8 DATA7, EMAD7, GPIO7
9 DATA6, EMAD6, GPIO6

10 DATA5, EMAD5, GPIO5
11 DATA4, EMAD4, GPIO4
12 VD2 Digital positive supply
13 DGND2 Digital supply ground
14 DATA3, EMAD3, GPIO3
15 DATA2, EMAD2, GPIO2
16 DATA1, EMAD1, GPIO1
17 DATA0, EMAD0, GPIO0
18 CS Host parallel chip select, host serial SPI chip select
19

SCDIO, SCDOUT, PSEL, GPIO9

Serial control port data input and output, parallel port type select

20 INTREQ, ABOOT Control port interrupt request, automatic boot enable
21 EXTMEM, GPIO8 External memory chip select or general purpose input & output number 8
22 SDATAN1 PCM audio data input number one
23 VD3 Digital positive supply
24 DGND3 Digital supply ground
25 SCLKN1, STCCLK2 PCM audio input bit clock
26 LRCLKN1 PCM audio input sample rate clock
27 CMPDAT, SDATAN2 PCM audio data input number two
28 CMPCLK, SCLKN2 PCM audio input bit clock
29 CMPREQ, LRCLKN2 PCM audio input sample rate clock
30 CLKIN Master clock input
31 CLKSEL DSP clock select
32 FILT2 Phase locked loop filter
33 FILT1 Phase-locked loop filter
34 VA Analog positive supply
35 AGND Analog supply ground
36 RESET Master reset input
37 DD Reserved
38 DC Reserved
39 AUDATA2 Digital audio output 2
40 AUDATA1 Digital audio output 1
41 AUDATA0 Digital audio output 0
42 LRCLK Audio output sample rate clock
43 SCLK Audio output bit clock
44 MCLK Audio master clock

17

AVR-2801/981

LC75721E (EX: IC101)

RES

V

OSCI

OSCO

Vss

TEST

G7 G8G9

G10

G11

AA8/G12

48 33

49

DI
CL
CE

DD

FL

V

G1
G2
G3
G4
G5
G6

64

AM 1

AM 2

AM 3

AM 4

AM 5

AM 6

AA7/G13

AM 7

AA6/G14

AM 8

AA5/G15

AM 9

AA4/G16

AA3

AM 10

AA2

AM 11

AM 12

AA1

AM35

AM 13

AM 14

AM34

AM33

161

AM 15

AM 16

32

17

AM 17
AM 18
AM 19
AM 20
AM 21
AM 22
AM 23
AM 24
AM 25
AM 26
AM 27
AM 28
AM 29
AM 30
AM 31
AM 32

Symbol

V

DD

Vss

FL

V

DI
CL
CE

OSCI
OSCO

RES
AM1~AM35

AA1~AA3

Power terminal +5V
Power terminal GND
Power terminal FL drive
Serial data transfer terminal

DI: Data
CL: Clock
CE: Chip enable

External CR connecting terminal

System reset terminal

Anode output terminal

Function

AA4/G16
AA5/G15
AA6/G14

Anode/Grid output terminal
AA7/G13
AA8/G12

G1~G11 Grid output terminal
TEST LSI test terminal

AD1854 (AU: IC701, 702, 703)

CCLK

96/48

1

2

3

4

5

6

7

AD1854

8

9

10

11

12

-

13

14

DGND

MCLK

CLATCH

CDATA

384/256

X2MCLK

ZEROR

DEEMP

AGND

OUTR+

OUTR

FILTR

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DVDD

SDATA

BCLK

L/RCLK

PD/RST

MUTE

ZEROL

IDPM0

IDPM1

FILTB

AVDD

OUTL+

-

OUTL

AGND

Pin

Name I/O Description

No.

1 DGND Digital Ground.
2 MCLK Master Clock Input.
3 CLATCH Latch input for control data.
4 CCLK Control clock input for control data.
5 CDATA Serial control input.
6 384/256 Selects the master clock mode.
7 X2MCLK Selects internal clock doubler (LO) or internal clock=MCLK (HI).
8 ZEROR Right Channel Zero Flag Output.
9 DEEMP De-Emphasis.

10 96/48 Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.

11,15 AGND Analog Ground.

12 OUTR+ Right Channel Positive line level analog output.
13 OUTR- Right Channel Negative line level analog output.
14 FILTR Voltage Reference Filter Capacitor Connection.
16 OUTL- Left Channel Negative line level analog output.
17 OUTL+ Left Channel Positive line level analog output.
18 AVDD Analog Power supply.
19 FILTB Filter Capacitor connection.
20 IDPM1 Input serial data port mode control one.
21 IDPM0 Input serial data port mode control zero.
22 ZEROL Left Channel Zero Flag output.
23 MUTE Mute. Assert HI to mute both stereo analog outputs.
24 PD/RST Power-Down/Reset.
25 L/RCLK Left/Right clock input for input data.
26 BCLK Bit clock input for input data.
27 SDATA Serial input.
28 DVDD Digital Power Supply.

I
I
I

I
I
I
I

O

I
I
I

O
O
O
O
O

I

O

I
I

O

I
I
I

I
I
I

18

AK5353 (AU: IC813)

AINR

AINL

VREF

VCOM

AGND

DGND

VA

VD

1
2
3
4
5
6
7
8

TST

16

TTL

15

DIF

14

13

PDN

SCLK

12

MCLK

11

10

LRCK

9

SDTO

TC9274N-011 (AU: IC107)

Terminal Function

No. Name I/O Function

1 AINR I Rch analog input pin
2 AINL I Lch analog input pin
3 VREF O Ref. V out pin
4 VCOM O Common V out pin
5 AGND  Analog GND pin
6VA  Analog power pin, +2.7~+5.5
7VD  Digital power pin, +2.7~+5.5V
8 DGND  Digital GND pin

9 SDTO O Serial data out pin, 2’s complement, MSB first out, at power down: L
10 LRCK I L/Rch clock pin
11 MCLK I Master clock input pin
12 SCLK I Serial data clock input pin, A/D data out at SCLK falling edge
13 PDN I Power down pin, L: Power down mode
14 DIF I Serial interface format pin (L: Firward, H: I2S)
15 TTL I Digital input level select pin, L: CMOS level, H: TTL level
16 TST I Test pin (internal pull-down)

AVR-2801/981

42

1

Europe model only
SAA6579T (CO: IC301)

16

1

1

QUAL

2

RDDA

3

REF

V

4

MUX

5

V

DD A

6

V

SS A

7

CIN

8

SCOUT

S1S2S3S4S5S6S7S8S9

41

21

DD

V

42

SS

V

1

2

S1S2S3S4S5S6S7S8S9

3839

40

4

3

56

35

34

36

37

18 bit Latch Circuit (Rch)

(Lch) Same as Rch

89

7

33

10 11

S10

32

12 13 14

S10

S11

S11

S12

S13

S14

S15

S16

S17

S13

26

28

27

16

17 18 19

15

S14

S15

29

3031

S12

S16

S18

24

25

23

STB

22

DATA

21

CK

Level Shift + Shift Register Circuit

20

GND

S17

S18

SAA6579T Terminal Function

Pin No. Symbol Function

QUAL

1

RDDA

10
11
12
13
14
15
16

2
3

V

4

MUX

5

V

6

V

7

CIN

8

SCOUT

9

MODE
TEST
V
V
OSCI
OSCO
T57
RDCL

8

16

RDCL

15

T57

14

OSCO

13

OSCI

12

DD D

V

11

SS D

V

10

TEST

9

MODE

Quality indication output.
RDS data output.
Reference voltage output (0.5 V

REF

Multiplex signal input.

DD A

+5V power supply for analog part.

SS A

Ground for analog part (0V).
Subcarrier input to comparator.
Subcarrier ouput of reconstruction filter.
Oscillation mode/test control input.
Test enable input.

SS D

Ground for digital part (0V).

DD D

+5V power supply for digital part.
Oscillator input.
Oscillator output.
57kHz clock signal output.
RDS clock output.

DD A

).

19

AVR-2801/981

BU4094BF (CO: IC304, EX: IC103)

8

16

VDD

15

OE

14

Q5

13

Q6

12

Q7

Q8

11

10

Q'

S

Q

S

9

STROBE

DATA

CLOCK

Q1

Q2

Q3

Q4

V

16

1

1

2

3

4

5

6

7

8

SS

CO: IC304

Port Symbol Function

Q1
Q2
Q3

Q4
Q5
Q6
Q7
Q8

A
B
C

D
E
F
G
Not Used

Video input switching
Video input switching
Video input switching

Video output switching
Video output switching
Video output switching (DVD/TV)
Video output switching (DVD/TV)

EX: IC103

Port Symbol Function

Q1 LOCK LED
Q2

DOLBY DIGITAL LED

Q3

dts LED

Q4

AUTO LED

Q5

DTS LED
PCM LED

Q6
Q7 FRONT SP-A LED
Q8

FRONT SP-B LED

"LOCK" LED drive output (H: Lock)
"DOLBY DIGITAL" LED drive output (H: D.Digital)
"dts" LED drive output (H: dts)

"AUTO" LED drive output (H: input mode "AUTO")
"DTS" LED drive output (H: input mode "DTS")
"PCM" LED drive output (H: input mode "PCM")
"FRONT SPEAKER A" LED drive output
"FRONT SPEAKER B" LED drive output

TC9273N-004 (AU: IC108)

1

Vss

S1

2

S2

3

4

S3

S4

5

6

S5

7

14

28

1

S6

8

S7

9

S8

10

S9

11

S10

12

13

GND

14

CK

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

STB

DATA

DD

V

28

27

26

25

24

23

22

21

20

19

18

17

16

15

TC9273N Terminal Function

Pin No. Symbol Name Function Note

1Vss-Power Terminal
13 GND Digital Ground
28 VDD +Power Terminal

2~12

S1~11 I/O Terminal Input terminal of analog switch.

17~27

14 CK Clock Input Clock input for data transfer.
15 DATA Data Input Serial input for switch setting.
16 STB Strobe Input Strobe input for data writing.

Dual Power Use: VDD = 8.0~17 V Single Power Use: VDD = 8.0~18V

GND = 0V Vss = GND = 0V
Vss = -8.0~17V

Low level

Border Input

Terminal

¾

¾

20

TC9184AP (CO: IC102)

AVR-2801/981

16

1

LA1265 (S)
(RE: IC502)

22

1

BASS+

VSS

1

2

VDD

16

GND

78

DATA

CK

9

Level shift

STB

10

BASS+

15

8

BASS-

TREBLE-

TREBLE+

11

COM

3

4

5

6

17

19

18

RF Amp Mix.

Ladder resister

Ladder resister

Analog switch

Analog switch

15

Level
Det.

1

FM IF

13 bit latch circuit

13 bit latch circuit

23

Level
Det.

AM IF

20 bit Shift register circuit

Code
detect
circuit

6

5

Q Det

Det.

Analog switch

Analog switch

Post

Amp

S Curve

7

Vcc

Ladder resister

Ladder resister

LED
Driver

14

13

12

11

10

12

BASS-

COM

TREBLE-

TREBLE+

9

8

Osc.

21

Buffer

22

Reg.

20

4

AGC S meter

GND

SD Adj

13

16

11

14

21

AVR-2801/981

SN74AHC157PW
(AU: IC804)
TC74VHC123AFT
(AU: IC801, 806)
TC74HC151AF
(CO: IC705)
TC74HCT157AF
(AU: IC805)

SN74AHC157PW

TC74VHC123AFT TC74HC151AF

16

INPUTS

OUTPUT

INPUTS

OUTPUT

1

TC74HCT157AF

1

SELECT

2

1A

3

1B

4

1Y

5

2A

6

2B

2Y

7
8

GND

LECT

1A
1B

1Y
2A
2B
2Y

GND

1
2
3
4
5

5
6
7
8

SE

8

SEL

16

Vcc

15

ST

14

4A

13

4B

12

4Y

11

3A

10

3B

9

3Y

1A
1B

1CLR

1Q
2Q

2Cex1

2Rext/Cext

GND

1
2

CLR

3

QQ

4
5

5

QQ

6
7
8

CLR

16
15
14
13
12
11
10

9

Vcc
1Rex/Cext

1Cext
1Q
2Q
2CLR
2B
2A

Data

Inputs

Outputs

Strobe

GND

3

1

2

2

D2

1

3

D1

0

D0

4
5

5

Y

Y

W

6

W

7

S

8

16

Vcc
4

15

D4
D5
D6
D7

C

5

14

Data
Inputs

6

13
12

7
A

A

11

Data

B

10

B

Select

C

9

W29C020P-90 (AU: IC817)

A12

A15

4

14 15

A16NCVDDWENC

23

1

16

19 20

17 18

303132

A14

29

A13

28

A8

27

A9

26

A11

25
24

OE
A10

23
22

CE

21

DQ7

Vcc

16

S

1A

G

1B

4A

4B

1Y

4Y

2A

3A

2B

3B

2Y

3Y

STROBE

15

4A

14

INPUTS

4B

13

OUTPUT

4Y

12
11

3A

INPUTS

3B

10

OUTPUT

9

3Y

DQ0

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10
11

A1

12

A0

13

Terminal Function

Name Function

A0 - A16

DQ0 - DQ7

CE
OE

WE

V

DD

GND

NC

Address input
Data in/output
Chip enable
Output enable
Write enable
Power terminal
GND
No connection

LA3401
(TU: IC503)

22

1

11

22

VOL
REG

SYMMETRICAL
REOCTANCE
CIRCUIT

MUTING

FM AM CHANGE

2

1

OSC

21

FF

3

DQ1

DQ2

GND

20

PHASE
COMPARATOR

FF

Ro

4

DQ3

DQ4

19

FF

38kHz

DECODER

5

DQ5

DQ6

18

VCO STOP

FF

38kHz 90°FF19kHz 90°

Rb

Rc

Rc

6

17

PILOT DET

Rb

7

16

15

MUTING CONTROL
FM AM CHANGE OVER

Vcc ON
MUTING

8

9

14

10

13

LAMP
DRIVER

TRIGGER

STEREO
SWITCH

MUTING
OUTPUT

11

12

22

AVR-2801/981

16

1

8

1
2

V

H

C

X

B

L
L
H
H

X

A

L

X

3
4
5
6
7
8

9

10

11

16
15
14
13
12

MC74HC4053N
(RE: IC304)

Y1
Y0
Z1

Z

Z0

Enable

EE

GND

Vcc
Y
X1

X
X0

C
A
B

Control Inputs

Enable

Select

ON Switches
L
L

L
L

L
L
L
L

L
L
L
L

H
H
H
H

L
L

H
H

L
H
L
H

Z0
Z0
Z0
Z0

Z1
Z1
Z1

Z1

Y0
Y0
Y1
Y1

X0
X1

X0
X1

X0
X1
X0
X1

None

X = Don't Care

3

2

4

6

7

8

9

10

11

12

13

14

1

15

16

5

NJM2229S (RE: IC305)

1

16

Sync Sepa

Sync Det

Phase

Det

Vsync Sepa

32fH

VCO

1/32

LC7074M (CO: IC302)
(Europe model only)

Y0
Y0
Y1

Y1

H
L
H

18

1

9

OSC1

GND
GND

RES

CLOCK-IN

DATA-IN

CORR. SEL

CLED. SEL

+5V

OSC2
GND

CLOCK-OUT
DATA-OUT
DATA START
ERROR
CORRECTION
D S CONTROL
RECEIVE

18

17

16

15

14

13

12

11

10

1

2

3

4

5

6

7

8

9

SN74LV4040APW (AU: IC812)

16

1

8

Outputs

OL

OF

OE

OG

OD

OC

OB

GND

1
2
3
4
5
6
7
8

16

15

14

13

12

11

10

9

Vcc

OK

OJ

OH

OI

CLR

CLK

Outputs

Outputs
OA

OL

OA

OF

OE

OG

OD

OC

OB

OK

OJ

OH

OI

CLR

CLK

23

AVR-2801/981

SN74LV14APW (AU: IC809)
SN74LV00APW (AU: IC807, 808)
TC74HCU04AF (CO: IC704)

SN74LV14APW SN74LV00APW

TC74HCU04AF

14

7

1

SN74AHC574APW
(AU: IC815, 816)

1

OE

2

1D
2D

3
4

3D

5

4D
5D

6

6D

7
8

7D
8D

9

10

GND

GND

1

1A

2

1Y

2A

3

4

2Y

5

3A

3Y

6

7

Vcc

14

13

6A

6Y

12

5A

11

5Y

10

9

4A

4Y

8

GND

1

1A

1B

2

1Y

3

2A

4

2B

5

6

2Y

7

Vcc

14

4B

13

4A

12

4Y

11

3B

10

9

3A

3Y

8

1Y

2Y

3A

3Y

GND

1A

2A

1

2

3

4

5

6

7

14

Vcc

13

6A

6Y

12

11

5A

5Y

10

4A

9

8

4Y

Function Table

logic symbol

1

20

Vcc

19

1Q

18

2Q

17

3Q

16

4Q

15

5Q

14

6Q
7Q

13
12

8Q

11

CK

CE

CLK

1D
2D
3D 3Q
4D
5D 5Q
6D 6Q
7D
8D 8Q

EN

11

C1

2

1D

3
417
5
615
714
8
912

19

1Q

18

2Q

16

4Q

13

7Q

(each flip-flop)

IN PU TS O UTPU T

OE

CLK

L
LLL
LXQ0

H or L

HXZX

DQ

HH

BA7625
(PO: IC402, 450)
(RE: IC302, 377)
BA7626
(RE: IC301, 376)

16

1

ABE

8

MONITOR OUT

Monitor OUT

CTL E

CTL D

C D E V O U T 1 C D E V O U T 2
LL* IN 1 LL*
H L * IN 2 H L * IN 2 H L *
L H * IN 3 L H * IN 3 L H * IN 3
H H L IN 4 H H L IN 4 H H L IN 4
H H H IN 5 H H H IN 5 H H H IN 5

N ote 1: * m ark m eans that feasible for either H or L.
N o te 2 : E a c h in p u t te rm in a l is p ro v id e d w ith s in k c h ip c la m p (B A 7 6 2 5 ).

E a c h in p u t te rm in a l ta k e s 2 0 k o h m a t th e e n d (B A 7 6 2 6 ).

GND

IN5

GND

IN4

IN3

1

2

3

6dB

LO G IC

4

5

6

7

6dB

LO G IC

8

¾

16

IN1

CTL A

15

V OUT1

14

13

Vcc

12

IN2

CTL B

11

10

V OUT2

CTL C

9

LL* IN 1

¾

24

BA4510F (AU: IC811)
UPC4570G2 (EX: IC302,308~310,701,801~803)
(CO: IC103,104)
(AU: IC106,109,731~733)

8

1

LC72131M (RE: IC507)

XOUT

20

10

1

AVR-2801/981

V

AM IN

13

8

B OUTPUT

7
6

B –INPUT
B +INPUT

5

IO 2

12

IF IN

A OUTPUT

A –INPUT

4

Vss

AOUT

19

AIN

18

17

A+INPUT

PD

16

1

2
3

V

4

DD

FM IN

V

14

NJU7313AL (EX: IC311)

28

VEE

L1
L2
L3

L-C O M 1

L4
L5

L6

L-C O M 2

L7
L8

L-C O M 3

ST

Vss

1

1
2
3
4
5
6
7
8

9
10
11
12
13
14 15

120

2

CE

XIN

14

28

VDD

27

R1

26

R2

25

R3

24

R-COM1

23

R4

22

R5

21

R6

20

R-COM2

19

R7

18

R8

17

R-COM3

16

DATA
CK

3

DI

L-C O M 1

L-C O M 2

L-C O M 3

ST

VDD

VEE

7

4

CL

L1

L2

L3

L4

L5

L6

L7

L8

5

DO

615

BO1

LATC H

LEVEL SH IFTER

CONTROL

8

BO2

BO3

LATC H

9

BO4

LEVEL SH IFTER

10 11

IO 1

R1

R2

R3

R-COM1

R4

R5

R6

R-COM2

R7

R8

R-COM3

DATA

CK

Vss

25

AVR-2801/981

Z

TC9459N (EX: IC805~807)

28

1

BU4052BC (PO: IC401)
(RE: IC371, 375)

16

15

14

13

10

12
11

8

9

V

DD

X2
X1
X-COM
X0
X3
A
B

16

Y-COM

INH

V

Vss

1

1

Y0

2

Y2

3

4

Y3

5

Y1

6
7

EE

8

14

V
INH 6

A 10

B 9
V
V
X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4

SS

V

1

NC

2

L-OUT

3

W

/

50k

TEP

91S

NC

4

L-IN

L-LD1

L-LD2

L-A-GND

CS1

GND

16

DD

LEVEL
CONVER

-TER

SS

8
7

EE

VR

5

6

7

8

9

NC

10

11

12

NC

13

14

CK

BINARY TO 1 of 4
DECODER WITH INHIBIT

L-ch7 to 91decoder

L-ch latch circuit

Shift register (24Bit)

Level shift circuit

DD

V

28

Same

R-ch7 to 91decoder

R-ch latch circuit

13 X

3 Y

27

NC

R-OUT

26

NC

25

as L-ch

24

23

22

21

20

19

18

17

16

15

R-IN

R-LD1

R-LD2

R-A-GND

NC

CS2

NC

NC

STB

DATA

TRUTH TABLE

INHIBIT A B ON SW ITCH

LL L X0 Y0
HL L X1 Y1
LL H X2 Y2
HL H X3 Y3
XHXNONE

X : d o n 't C a re

BU4053BC (PO: IC403)

V

16

DD

16

-COM

INH

Vss

INH6

A11

8

1

1

Y1

2

Y0

3

Z1

4

5

Z0

6
7

V

EE

8

16
15

14

13

12
11

10

9

V

DD

Y-COM
X-COM
X1
X0
A
B
C

B10

Vss8
V

X0 12
X1 13
Y0 2
Y1 1
Z0 5
Z1 3

C9

EE

LEVEL
CONVER

-TER

7

BINARY TO 1 of 2
DECODER WITH INHIBIT

TRUTH TABLE

INHIBIT A B ON SW ITCH

LL L X0 Y0
HLL
LLH
HLH

14 X

15 Y

4 Z

LLL
HLL
LLH
HLH
XHX NONE

C
L

X1 Y0 Z0

L

X0 Y1 Z0

L

X1 Y1 Z0

L
H

X0 Y0 Z1

H

X1 Y0 Z1
X0 Y1 Z1

H
H

X1 Y1 Z1

X

Z0

X : d o n 't C a re

26

AVR-2801/981



OTHERS

GP1U271X (Remote Control Sensor)
(EX: IC102)

GND

Vcc

Vout

H ead
Am p

Lim iter
Am p

BPF

D e te c to r &
C om parator

Integrator

H ysteresis
C om parator

Output
GND
Input

NJM7912FA (RE: IC907)

Output
Input
GND

4

V

DD

1

2

OE

Vss

OUT

1

2

4

3



IC PROTECTOR

ICP-N15 (PO: IC501)



OPTICAL

INPUT
GP1F37R1 (CO: IC701~703)

1

2

3

1
3
2

1. Vcc

2. GND

3. Vout

NJM7805FA (S) (RE: IC902, 903)
NJM7806FA (S)
(PO: IC502)
(RE: IC904)
NJM7812FA (S) (RE: IC906)
BA033T (AU: 819)

NJM7912FA (RE: IC907)

SG-8002DCPT (12.287MHz)
(AU: XL802)

V

1

2

4

3

3

1. Vcc

2. GND

3. Vout

GND

V

OUT

Vcc

SN74AHCT1G08DBV (AU: IC821)

1

2

3

4

5

1: A
2: B
3: GND
4: Y
5: Vcc

1
2

4

27

AVR-2801/981

TRANSISTORS



2SA970 (BL)
2PA1015GR
2SA988 (E/F)
2PC1815 (BL)
2SC3200 (BL)
KTC2874B

2SC2705 (O) / (Y)

2SA1491
2SC3855

2SB1186A
2SD1763A

DTA114TK
DTA114EK
DTA144EK
DTC114EK
DTC144EK
DTC323TK
KRA102S

E (Emitter)
C (Collector)
B (Base)

B (Base)
C (Collector)
E (Emitter)

2SA1670 (O/P/Y)

E (Emitter)
C (Collector)
B (Base)

DTA114TK
DTA114EK
DTA144EK
KRA102S

PNP Type

B (Base)
C (Collector)
E (Emitter)

2SC4495

E (Emitter)
C (Collector)
B (Base)

E (Emitter)
C (Collector)
B (Base)

DTC114EK
DTC144EK
DTC323TK

NPN Type

28

2SA933S (S)
2SC3311A
2SC1645S (B)

B (Base )
C (Collector)
E (Emitter)

1: GND/Emitter
2: Out/Collector
3: In/Base

2SK771

DTA114TK

DTA114EK
DTA144EK

KRA102S

1: Drain
2: Source
3: Gate

R1

10kohm

10kohm
47kohm

10kohm

R2

-

10kohm
47kohm
10kohm

2SA1505Y
2SC2996 (Y)
2SC3326 (A/B)
2SD601A

R1
DTC114EK

DTC144EK
DTC323TK 2.2kohm

10kohm
47kohm

1: Emitter
2: Collector
3: Base

R2
10kohm
47kohm

-

DIODES (included LED)



1SS270A



Naby Blue

MTZJ3.3A
MTZJ5.6A
MTZJ6.2A

MTZJ7.5A
MTZJ9.1A
MTZJ36A

1SR35-400A

Green

Orange

AVR-2801/981

DSM1D2(Type 3)

White

Black



S4VB20

Black

SEL1210S (Red)
SEL4214S

Short

(Cathode)

Long
(Anode)

DAN202K DAP202K

1

2

1: Anode
2: Anode
3: Cathode

3

1: Cathode
2: Cathode
3: Anode

1

2

3

29

AVR-2801/981

FL DISPLAY CM1690 (VI : FL101)



1

STEREO

TUNED

RDS

CH

G16

TUNED

RDS

CH

G15

STEREO

AUTO

Pin Assignment

PIN NO.

CONNECTION

PIN NO.

CONNECTION

PIN NO.

CONNECTION

58

S15

S11

S12

S9

S10

G1

S5

S4

S6

S1

S7

AUTO

REC

MULTI

PHONO

VCR

CD

AUX

V.AUX

DVDMDVDP

TAPE

TUNER

-

1

-

2 -3

TV

-

1

-

DBS

2

PRO LOGIC
DIGITAL

DIGITAL ANALOG

S38

S14

S13

F2F1

G2~G16

S3

G10

CD

-

1

G9

TUNER

-

2 -3

G13

REC

MULTI

G14 G11 G8

G12

PHONO

VCR

12345

F1 F1 S1 S2 S3
21 22

23 24 25

S4
26

S1

G7

AUX

V.AUX

78910111213141516171819

6

G5 G2 G1

G6

DVD

MD

G4

VDP

TAPE

G3
TV

-

DBS

-

2

1

PRO LOGIC
DIGITAL

DIGITAL ANALOG

S6

S11

S16

S21

S26

S31

S2

S7

S12

S17

S22

S27

S32

S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
27 28 29 30 31 32 33 34

35 36 37 38 39 40

S4

S9

S8

S14

S13

S19

S18

S23

S24

S29

S28

S33

S34

S16 S17

S5

S10

S15

S20

S25

S30

S35

20

S18

S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38

41 42 43 44 45

47 48 49 50 51 52 53 54 55 56 57

46

58

G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 F2 F2

F1,F2 : Filament
G1~G16 : Grid

S1~S38 : Anode

S2

S3

30

Anode & Grid Assignment

G1

G2~G16

S36
S37
S38

S1
S2
S3
S4
S5
S6
S7

S1
S2
S3
S4
S5
S6

S7
S8
S9

S9

G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16

/

-

2

S38

DBS

TV

-

S1
S2

S3
S4
S5
S6
S7
S8
S9

VDP

1

TAPE

S10
S11

S12
S13
S14

S15
S16
S17

S18

/(DVD)

/(MD)

G1
S10
S11

S12

S13
S14
S15

DIGITAL

PRO LOGIC

AUX

DVD

MD

V.AUX

G2~G16

S10

S11

S12
S13
S14
S15
S16
S17
S18

S19
S20
S21
S22
S23
S24
S25
S26

S27

TUNER

2

-

3

-

CD

-

G1

G2~G16

S19
S20
S21
S22
S23
S24

S25
S26

S28
S29
S30
S31
S32
S33
S34
S35

G1

G2~G16

S28
S29
S30
S31

S32
S33

S34
S35

S27

PHONO

1

VCR

REC

MULTI

STEREO

AUTO

TUNED

RDS

CH