Denon AVR-2800 Service Manual

AVR-2800

NEW MODEL INFORMATION

Outstanding surround sound an affor dable price,with Dolby Digital and DTS decoding.

Featuring the latest in Dolby Digital and DTS decoding technology, theAVR-2800 provides outstanding home theater surround
sound performance. The heart of the AVR-2800 is Denon’s Dynamic Discrete Surround Circuit-Digital technology, incorporating
high performance dual DSP chips and superior A/D and D/A conversion devices. This provides superb listening results, with virtually any
home theater or music source. Prepared for the future, the AVR-2800 features 6-Channel external input, for connection to future
multi-channel surround formats. A high quality, discrete power output section provides a total system power of 425 watts RMS into
8 ohms. Full 24 bit, 96 kHz digital-to-analog D/A converters on all 6 channels (3 stereo pairs) provide transparent reproduction of
multi-channel music and motion picture soundtracks with outstanding dynamic range and superb low level resolution. Outstanding
surround sound an affordable price, with Dolby Digital and DTS decoding. The AVR-2800’s remote controller features an easy-to­use layout where most frequently used buttons are provided in different colors and shapes for easy recognition, even while keeping
your eyes on the screen. The buttons also feature “Self-illuminated GLO-KEY” for easy operation in the dark.

Dolby Digital and DTS A/V Receiver

■ Equal Power Discrete Power Amplifier

Front 85 W + 85 W (8 ohms, 20Hz - 20kHz, 0.05% THD)
Center 85 W (8 ohms, 20Hz - 20kHz, 0.05% THD)
Surround 85 W + 85 W (8 ohms, 20Hz - 20kHz, 0.05% THD)

All five power amplifier channels feature discrete power out­put devices, and all five amplifier channels provide equal
power with lowest distortion. Each channel is rated at 85 watts,
into 8 ohms, from 20 Hz - 20 kHz, with no more than 0.05%
THD. A hallmark of Denon A/V component design, the equal
power amplifier provides outstandingly accurate reproduction of
motion picture soundtracks and multi-channel music programs.

■ DDSC-Digital (Dynamic Discrete Surround

Circuit-Digital)

Since surround signals are all processed in the digital domain,
the AVR-2800 is equipped with a newly-developed, sophisticat­ed, high-performance dual DSP circuit for the Dolby Digital, Dolby
Pro Logic, dts decoders, and Surround Simulator.The D/Acon­verters feature high resolution designs for all the Front L/R,
Center, Surround L/R, and Subwoofer channels.This combina­tion of DSP and D/A converters works to bring out the tremen­dous potential of Dolby Digital and dts sound. In addition, high
resolution A/D converters have been incorporated for the Dolby
Pro Logic decoder.The high sound quality of New DDSC-Digital
is due in part to the high-grade signal processing of the 24-bit,
96-kHz Digital Interface Receiver (DIR). The AVR-2800 not only
allows digital signals input from DVD and other advanced media
to pass directly to the DIR, it also processes them while preserv­ing their integrity so that even the most delicate nuances of the
music, reflecting the emotions of the artists, are passed unfet­tered to the dual digital signal processors (DSP).

Dynamic Discrete Surround Circuit-Digital Block Diagram

■ Dolby Digital

Dolby Digital and Dolby Pro Logic decoding functions are per­formed in the digital domain for excellent dynamic range and
crystal clear reproduction.

■ DTS

Digital Theater Systems decoding provides thrilling movie and
music multi-channel surround sound.

■ 96kHz, 24-bit Audio D/A Converters

■ 6-Channel External Input For Future Multi-Channel Formats

■ Separate Current Supplies for Circuits

The AVR-2800 is equipped with a main transformer featuring
independent 5-winding outputs, and a dedicated transformer for
the microprocessor, to completely separate the power amplifier,
audio, digital, video, and display circuits. This construction
reduces noise interference among the circuits and ensures a
clean, transparent sound.

■ Hefty Power Transformer for Stable Supply of Power

A power transformer has been connected in the power sec­tion where it is combined with a rectifier diode and a large block
capacitor to ensure a large, stable supply of electrical current.
Accordingly, the AVR-2800 boasts high output power of 85 W for
each of the 5 channels.

■ Stable Speaker Drive

In the AVR-2800, the circuitry through which current flows
to drive the speakers has been incorporated onto a single
board between the rectifier circuit of the power source and the
speaker terminals. Anew phase correction circuit has also
been adopted, eliminating the need for an output coil. Since
this configuration allows the power transistor to drive the
speakers directly, there is no loss of power to any of the
channels. The sound that you hear is thus extremely stable
as well as powerful.

■ Pre Outputs for System Upgrading

The pre-out terminals on the AVR-2800 is offered for Front L/R,
Center and Mono (Subwoofer) channels. Aseparate power amp
can be connected to these terminals to upgrade your system.

■ Video Select Switch

This function lets you select video sources independently of
the audio sources.

■ All-channel Level Control

■ Binding Post Speaker Terminals for All Channels

■ Icon-based On-Screen Display

The AVR-2800 provides an On-Screen Display (OSD) fea­turing icons (pictorial representations) to let you easily monitor
the current operating status.

■ Personal Memory Plus

The handy Personal Memory Plus function allows you to
store the surround mode, the level settings for all speakers,
as well as the delay time, to further customize the sound
source. Simply push any source button and it will instantly
display the settings stored for that source.

■ Multi-function Remote Controller

● Self-illuminated GLO-KEY Remote Controller with Easy

Recognition Layout

● System Call Function to execute up to 10 successive pre-assigned

commands at the single touch of a button

● Pre-Memory and Programming Function for non-DENON components

■ Frequency Synthesis Tuning

● 40-Station AM/FM Random Preset Memory Tuning

● Auto Preset Memory

■ Other Features

● Cinema Equalizer

● Music Surround Modes Including 5-channel Stereo

● “S”and Composite Video Switching

● Front A/B Speaker Switching

Connect another pair of stereo speakers in another room.

● Tone Control

● 2 Switched AC Outlets

■ Input/Output Terminals For Every A/V System

● Audio Inputs

3 Digital (Optical) Input ....... OPTICAL x 3

1 Digital (Coaxial) Input ...... COAXIAL x 1

9 Analog Inputs ................... PHONO, CD, TUNER, DVD, VDP,

TV/DBS, VCR-1, VCR-2/V-AUX,
MD/TAPE

6 Analog EXT. Inputs ........... FRONT L/R, CENTER,

SURROUND L/R, SUBWOOFER

● Audio Outputs

4 Analog Pre Outputs ......... FRONT L/R, CENTER, SUBWOOFER

3 Analog Rec Outputs ........ VCR-1, VCR-2/V-AUX, MD/TAPE

● Video Inputs

5 S-Video Inputs ................. DVD, VDP, TV/DBS, VCR-1,

VCR-2/V-AUX

5 Composite Inputs ............. DVD, VDP, TV/DBS, VCR-1,

VCR-2/V-AUX

● Video Outputs

3 S-Video Outputs .............. VCR-1, VCR-2/V-AUX, MONITOR

3 Composite Outputs .......... VCR-1, VCR-2/V-AUX, MONITOR

Specifications

■ Power Amplifier Section
Rated output *THD figures are power amp stage values.

Front...........................................85 W + 85 W (8 ohms, 20Hz - 20kHz, 0.05% THD)

Center........................................ 85 W (8 ohms, 20Hz - 20kHz, 0.05% THD)

Surround................................... 85 W + 85 W (8 ohms, 20Hz - 20kHz, 0.05% THD)

■ Preamplifier Section
Input sensitivity/Impedance

PHONO(MM)............... 2.5 mV/47 kohms

CD, DVD, VDP, TV/DBS, VCR-1 VCR-2/V-AUX, MD/TAPE,
FRONT L/R, CENTER, SURROUND L/R,

SUBWOOFER............. 200 mV/47 kohms

Output level/Load Impedance

FRONT L/R, CENTER,

SUBWOOFER............. 1.2 V/10 kohms

VCR, MD/TAPE,

MONITOR .................... 200 mV/47 kohms

RIAA deviation................. ±1 dB (20 Hz - 20 kHz)

Tone control..................... Treble: ±10 dB at 10 kHz

Bass: ±10 dB at 100 Hz

■ FM Section
Tuning frequency range... 87.50 - 107.90 MHz

Usable sensitivity............. 1.0 µV (11.2 dBf)

■ AM Section
Tuning frequency range... 520 - 1710 kHz

Usable sensitivity............. 18 µV

■ General

Power supply................... AC 120 V, 60 Hz

Power consumption......... 5.0 A

Dimensions...................... 434 (W) x 171 (H) x 416 (D) mm

17.1” (W) x 6.7”(H) x 16.4”(D)

Weight.............................. 11.5 kg, 25.4 lbs

*Design and specifications are subject to change without notice.
*”Dolby”, “Dolby Digital”, “Pro Logic”, and the double-D device are registered trademarks of

Dolby Laboratories Licensing Corporation.

*DTS is registered trademarks of DTS Technology.

DENON ELECTRONICS. NIPPON COLUMBIA CO., LTD.
DIVISION OF DENON CORPORATION (USA) 14-14, AKASAKA4-CHOME, MINATO-KU, TOKYO 107-8011, JAPAN

222 NEW ROAD, PARSIPPANY, NEW JERSEY 07054, USA Denon Home Page Address: http://www.denon.co.jp
TEL: [phone] www.del.denon.com

DENON CANADA INC.

17 DENISON STREET, MARKHAM ONTARIO, CANADAL3R 1B5
TEL: [phone] 11790699 A Printed in Japan

SAFETY PRECAUTIONS

The following check should be performed for the continued protection of the customer and service technician.

LEAKAGE CURRENT CHECK

Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis
resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the
power cord is less than 460 kohms, the unit is defective.

SPECIFICATIONS



 AUDIO SECTION





 Power Amplifier



Rated output: Front: 90W + 90W (8Ω/ohms, 20Hz ~ 20kHz with 0.05% T.H.D.)

Center: 90W (8Ω/ohms, 20Hz ~ 20kHz with 0.05% T.H.D.)

Surround: 90W + 90W (8Ω/ohms, 20Hz ~ 20kHz with 0.05% T.H.D.)

Surround Back: 90W (8Ω/ohms, 20 Hz ~ 20kHz with 0.05% T.H.D.)

Dynamic power: 120W × 2ch (8Ω/ohms)

Output terminals: Front: A or B 6 ~ 16Ω/ohms



 Analog



Input sensitivity/input impedance: 200mV/47kΩ/kohms
Frequency response: 10Hz ~ 100kHz: +0, −3dB (DIRECT mode)
S/N: 102dB (DIRECT mode)
Distortion: 0.005% (20Hz ~ 20kHz) (DIRECT mode)
Rated output: 1.2V



 Digital



D/A output: Rated output ⎯ 2V (at 0dB playback)

Digital input: Format ⎯ Digital audio interface



 Phono equalizer (PHONO input



Input sensitivity: 2.5mV
RIAA deviation: ±1dB (20Hz to 20kHz)
Signal-to-noise ratio: 74dB (A weighting, with 5mV input)
Rated output/Maximum output: 150mV/7V
Distortion factor: 0.03% (1kHz, 3V)



 VIDEO SECTION





 Standard video jacks



Input/output level and impedance: 1Vp-p, 75Ω/ohms
Frequency response: 5Hz ~ 10MHz ⎯ +0, −3dB



 S-video jacks



Input/output level and impedance: Y (brightness) signal ⎯ 1Vp-p, 75Ω/ohms

Frequency response: 5Hz ~ 10MHz ⎯ +0, −3dB



 Color component video jacks



Input/output level and impedance: Y (brightness) signal ⎯ 1Vp-p, 75Ω/ohms

Frequency response: 5Hz ~27MHz ⎯ +0, −3dB



 TUNER SECTION



Receiving Range: 87.50MHz ~ 107.90MHz 520kHz ~ 1710kHz

Usable Sensitivity: 1.0μV (11.2dBf) 18μV
50dB Quieting Sensitivity: MONO: 1.6μV (15.3dBf)

S/N (IHF-A): MONO: 77dB

Total Har monic Distortion (at 1kHz): MONO: 0.15%



 GENERAL



Power supply: AC120V, 60Hz (for U.S.A., Canada and Taiwan R.O.C. models)

Power consumption: 5.0A (for U.S.A.& Canada model)

Maximum external dimensions: 434 (W) × 171 (H) × 416 (D)mm (17-3/32″× 6-11/32″× 16-3/8″)
Weight: 11.5kg (25 lbs 6 oz)



 REMOTE CONTROL UNIT



Batteries: R6P/AA Type (three batteries)
External dimensions: 70 (W) × 215 (H) × 24 (D)mm (2-3/4″× 8-15/32″× 15/16″)
Weight: 200g (Approx. 7 oz) (including batteries)

* For purposes of improvement, specifications and design are subject to change without notice.

170W × 2ch (4Ω/ohms)
200W × 2ch (2Ω/ohms)

Center, Surround, Surr.Back: 6 ~ 16Ω/ohms

Total har monic distortion ⎯ 0.008% (1 kHz, at 0 dB)
S/N ratio ⎯ 102dB
Dynamic range ⎯ 96dB

⎯⎯

⎯ REC OUT)

⎯⎯

C (color) signal ⎯ 0.286Vp-p, 75Ω/ohms

P

B/CB (blue) signal ⎯ 0.7Vp-p, 75Ω/ohms

P

R/CR (red) signal ⎯ 0.7Vp-p, 75Ω/ohms

[FM] (note: μV at 75Ω/ohms, 0dBf=1 × 10

(for U.S.A., Canada and multiple voltage models) (for U.S.A., Canada and Multiple voltage models)

87.50MHz ~ 108.00MHz 522kHz ~ 1611kHz
(for Europe, Asia, China, Hong Kong, Taiwan R.O.C. and Multiple voltage models) (for Europe, Asia, China, Hong Kong, Taiwan R.O.C. and multiple voltage models)

STEREO: 23μV (38.5dBf)

STEREO: 72dB

STEREO: 0.3%

AC230V, 50Hz (for Europe model)
AC220V, 50Hz (for China model)
AC115V/230V, 50/60Hz (for Asia, Hong Kong and Multiple voltage models)

270W (for Europe, Asia, China, Hong Kong and Multiple voltage models)
650W (for Taiwan R.O.C. model)

2.0W Max (Standby)

(RC-903: for U.S.A., Canada, Asia, China, Hong Kong, Taiwan R.O.C. and Multiple voltage models)
(RC-904: for Europe model)

135W + 135W (6Ω/ohms, 1kHz with 0.7% T.H.D.)
150W + 150W (6Ω/ohms, EIAJ)

135W (6Ω/ohms, 1kHz with 0.7% T.H.D.)
150W (6Ω/ohms, EIAJ)

135W + 135W (6Ω/ohms, 1kHz with 0.7% T.H.D.)
150W + 150W (6Ω/ohms, EIAJ)

135W (6Ω/ohms, 1kHz with 0.7% T.H.D.)
150W (6Ω/ohms, EIAJ)

A + B 8 ~ 16Ω/ohms

-15

W) [AM]

2

WIRE ARRANGEMENT

If wire bundles are untied or moved to perform adjustment or parts replacement etc.,be sure to rearrange them neatly as they
were originally bundled or placed afterward.
Otherwise, incorrect arrangement can be a cause of noise generation.

Wire arrangement viewed from the top

3

DISASSEMBLY

(Follow the procedure below in reverse order when reassembling)

1. Top Cover

Remove 3 screws 1 on the rear and 6 screws 2 on both
sides to detach the Top Cover as shown in the arrow
direction.

2

2. Front Panel

(1) Remove 7 screws 3 from the top and bottom edges of

the Front Panel.

(2) Release 4 top and bottom hooks, then detach the Front

Panel as shown in the arrow direction.

Top Cover

1

2

3

Hook

3. Inner Panel

Pull out the Inner Panel in the arrow direction after removing
3 screws

.

4

Front Panel

Inner Panel

Hook

3

Hook

3

4

4

Hook

4

4. Inner Panel Ass'y

(1) Remove 3 round and 1 square knobs, and unscrew 4

nuts.

(2) Remove 15 screws

fixing each P.W.B.

5

5

5

5. Amp Connect Unit

(1) Remove 3 screw to detach Pre-out Unit .

(2) Take off the Amp Connect Unit as shown in the

arrow direction after removing 1 screw .

6

8

9

7

Round Knob

Square Knob

Nut

Round Knob

Nut

5

9

7

8

6

6. Regulator Unit

Take off the Regulator Unit as shown in the arrow
direction after removing 9 screws .

 

 

 

 

5

7. Component-Video/S-Video / C-video /
Audio & DSP / Ext-in VR / Digital-in / AM
FM Tuner Unit

(1) Remove 44 screws to detach the Rear Panel.

(2) Take off the objective P.W.B. upward.



Rear Panel







8. How to Check Power / Control Unit with
Power-on

(1) Remove 13 screws ,and 4 screws fixing to the

Chassis.

(2) Pull up the Unit to separate from the Chassis.

 !

 "

 !

 !

 !

 !

 "

 !

 "

 !

6

CLOCK FLOW & WAVE FORM IN DIGITAL BLOCK

Wave Form

1

CH1: D-DATA

AVR-2802/982

(IC505 (5) )

2

CH1: DATA

CH2: DA-LRCK(fs)

CH3: DA-SCK(64fs)

3

CH1: DATA

CH2: fs

CH3: 64fs

CH4: 256fs

7

Clock Flow

AVR-2802/982

COAXIAL
OPTICAL-1
OPTICAL-2
OPTICAL-3

OPTICAL
OUTPUT

INPUT

SELECTOR

IC505

SN74HC

151NS

(15)
(14)

(5)
(13)
(12)

(3)
(2)
(1)

12.288MHz

IC506

SN74HC

151NS

1

X801

(5)

DIR

IC800

LC89055W

(5)DIN2

XIN(22)

XMCK(20)

SN74LV4040APW

CKOUT(13)

BCK

(14)

LRCK(15)

(16)

DATA

IC813

(10)

(13)

(7)

A/D SELECTOR

IC804

74LVX157

256fs

64fs

fs

DATA

2

MCLK
DA SCK
DA LRCK
SD IN

(44) (22) (25) (26)

MCLK

SDATAN1

(27) (43) (42)

(30)CLKIN

CS493292

* fs is a sampling frequency of input digital signal.

e.g.:sampling frequency 48kHz fs=48kHz

* 64fs and 256fs are 64 or 256 times the sampling frequency respectively.

e.g.: sampling frequency 48kHz
64fs: 48kHz x 64=3.072MHz

256fs: 48kHz x 256=12.288MHz
* The sampling frequency for analog input is fixed to 48kHz internally.
* (No.) indicates the pin number of individual.
* The arrow indicates the direction of signal as the input terminal pointed by

the arrow and the output terminal by the opposite.

SCLKN1 LRCKN1

SCLK LRCLKCMPDAT

AUDATA0 (41)

AUDATA2 (39)

AUDATA1 (40)

XMT958 (3)

IC814

DSP

3

256fs
64fs

fs

FRONT

CENTER/SW

SURROUND

SURROUND BACK

D/A CONVERTER

IC801

AD1854

(2)256fs
(26)64fs
(25)fs
(27)DATA

CODEC

IC602

AK4527

(6)SDTI1

(7)SDTI2

(8)SDTI3

(39)MCLK

(4)BICK

(5)LRCK

(9)SDTO

8

BLOCK DIAGRAM

1

2

3

4

5

76

8

A

B

C

D

E

9

LEVEL DIAGRAMS (1/3)

1

2

3

4

5

76

8

A

B

C

D

E

10

LEVEL DIAGRAMS (2/3)

1

2

3

4

5

76

8

A

B

C

D

E

11

LEVEL DIAGRAMS (3/3)

1

2

3

4

5

76

8

A

B

C

D

E

12

AVR-2802/982

CAUTION IN SERVICING



 Initializing AV SURROUND RECEIVER



AV SURROUND RECEIVER initialization should be performed when the μcom, peripheral parts of μcom, and DSP
P.W.B. are replaced.

1. Switch off the unit and remove the AC cord from the
wall outlet.

2. Hold the following A button and B button, and plug
the AC cord into the outlet.

3. Check that the entire display is flashing with an
interval of about 1 second, and release your fingers
from the 2 buttons and the microprocessor will be
initialized.

Note:  If step 3 does not work, start over from step 1.

 All user settings will be lost and its factory setting will be recovered when this initialization mode.

So make sure to memorize your setting for restoring after the initialization.

REMOTE

SIGNAL

SENSOR

LOCK

DIGITAL

INPUT

STAND BY

AUTO

PCM

DIGITAL

2

VOLUME LEVEL

13

ADJUSTMENT

Idling Current (1U-3368-1)

Required measurement equipment : DC Voltmeter

Preparation

(1) Avoid direct blow from an air conditioner or an electric fan, and adjust the unit at normal room tempereture 15 °C ~ 30 °C

(59 °F ~ 86 °F).

(2) Presetting

 POWER (Power sourse switch) → OFF
 SPEAKER (Speaker terminal) → No load (Do not connect speaker, dummy resistor, etc.)

Adjustment

(1) Remove top cover and set VR101, VR102, VR201, VR202, VR301, VR401, on 1U-3368-1 (Power Unit) at fully

counterclockwise (

(2) Connect DC Voltmeter to test points (FRONT-Lch: TP101, FRONT-Rch: TP102, CENTER ch: TP103, SURROUND-Lch:

TP101, SURROUND-Rch: TP103, SURROUND BACK-ch: TP102).

(3) Connect power cord to AC Line, and turn power switch "ON".

).

(4) Presetting. MASTER VOLUME : "---" counterclockwise (

min.)

MODE : 6CH STEREO
FUNCTION : CD

(5) Allow 2 minutes, and turn VR101 clockwise (

) to adjust the TEST POINT voltage to 6.5 mV ±0.5 mV DC.

(6) After 10 minutes from preset, turn VR101 to set the voltage to 8 mV ±0.5 mV DC.
(7) Adjust the Variable Resistors of other channels in the same way.
(8) After 5 minutes from (6), turn VR101 to set the voltage to 8 mV ±0.5 mV DC.
(9) Adjust the Variable Resistors of other channels in the same way.

VR301

VR102

VR401

VR202

DC Voltmeter

SBch

TP102

FRch

Cch

TP103

SRch

TP101

FLch

SLch

VR101

VR201

14

SEMICONDUCTORS



 IC’s



Note: Abbreviation ahead of IC No. indicates the name of P.W.B.

PO: Power P.W.B. RE: Regulator P.W.B.
EX: Exit in P.W.B. AU: Audio/DSP P.W.B.
CO: Control P.W.B.

TMP88CU74F
(CO: IC303)

64

65

80

124

TMP88CU74F Terminal Function

Pin

Name

No.

1 P02/S01 RDS RESET O C ⎯⎯ Z L RDS reset output (LC72720)
2 P03 OSD RST O C ⎯⎯ Z H OSD control output (M35015)
3 P04 PLL DATA I ⎯⎯⎯⎯⎯PLL Serial data input terminal (LC72131)
4 P05 PLFLRDS DATA O C ⎯⎯ ZL
5 P06 PLL STB O C ⎯⎯ Z L PLL control terminal (LC72131)
6 P07 PLFLRDS CLK O C ⎯⎯ ZL
7 Vss Vss I ⎯ GND ⎯⎯ L GND
8 Xout Xout O ⎯⎯⎯⎯⎯XTAL

9 Xin Xin I ⎯⎯⎯⎯⎯XTAL
10 RESET_ RESET_ I ⎯ Eu Lv L ⎯ Reset input
11 P22/XTOUT TUNED_ I ⎯ Eu Lv Z ⎯ Tuning detect, L: Tuned
12 P21/XTIN STEREO_ I ⎯ Eu Lv Z ⎯ L: At stereo receive
13 TEST TEST I ⎯ GND S ⎯⎯Connect to GND
14 P20/INT5_ B.DOWN_ I ⎯ Eu Lv Z ⎯ Power down detect, L: Power down
15 P10/INT0_ PROTECT_ I ⎯ Ed E&L Z ⎯ PROTECTION detect input, H: Detect
16 P11/INT1 RDS DATA I ⎯⎯⎯ Z L RDS data input (LC72720)
17 P12 OSD CLK O C ⎯⎯ Z H OSD control output (M35015)
18 P13 OSD CS O C ⎯⎯ Z H OSD control output (M35015)
19 P1 4 OSD DATA O C ⎯⎯ Z L OSD control output (M35015)
20 P15/INT3 REMOCON I ⎯ Ed E&L Z ⎯ Remote control signal input
21 P16/INT2 ACK O C ⎯⎯ Z L MAIN-SUB CPU comm. control terminal
22 P17/INT4 REQ I ⎯ Eu ⎯ Z L MAIN-SUB CPU comm. control terminal
23 P30/SCL SI I MAIN-SUB CPU comm. control terminal
24 P31/SDA SO O C MAIN-SUB CPU comm. control terminal
25 P32/SCK0_ CLK O C MAIN-SUB CPU comm. control terminal
26 P40/AIN0 MODE I ⎯ Eu Lv Z ⎯ Destination switching input
27 P41/AIN1 KEY1 I ⎯ Eu Lv Z ⎯ Button input 1
28 P42/AIN2 KEY2 I ⎯ Eu Lv Z ⎯ Button input 2
29 P43/AIN3 KEY3 I ⎯ Eu Lv Z ⎯ Button input 3
30 P44/AIN4 FUNC STB1 O C ⎯⎯ ZL
31 P45/AIN5 FUNC/T. CON CLK O C ⎯⎯ ZL
32 P46/AIN6 FUNC/T. CON DATA O C ⎯⎯ ZL
33 P47/AIN7 E.VOL STB4 O C ⎯⎯ Z L Elect. volume control output (TC9482)
34 P50/AIN8 E.VOL STB1 O C ⎯⎯ L L Elect. volume control output (TC9459)
35 P51/AIN9 TONE STB O C ⎯⎯ L L TONE control output (TC9184P)
36 P52/AIN10 E.VOL DATA O C ⎯⎯ L H Elect. volume control output (TC9459, TC9482)
37 P53/AIN11 E.VOL CLK O C ⎯⎯ L H Elect. volume control output (TC9459, TC9482)

Symbol

I/O Type Op Det Res Init

41

40

25

Function

PLL, FL, RDS control terminal (LC72131 & LC75721, LC72720)

PLL, FL, RDS control terminal (LC72131 & LC75721, LC72720)

Function control output, REC OUT (TC9274-011), EXT/SOURCE (TC9274-017)
Function control output (TC9274N, TC9273), TONE control output (TC9184P)
Function control output (TC9274N, TC9273), TONE control output (TC9184P)

Pin

Name

No.

38 VASS VASS I Ref. volt (GND)
39 VAREF VAREF I Ref. volt (VDD)
40 VDD VDD I Power supply
41 P60 FL CE O P Ed S L H FL display control output (LC75721NE)
42 P61 FL RES O P Ed S L H FL display control output (LC75721NE)
43 P62 FUNC STB2 O P Ed ⎯ Z L Function control output (TC9273), INPUT (TC9273)
44 P6 3 FA-RELAY O P Id ⎯ L L Front SP relay A control terminal, L: Mute
45 P64 FB-RELAY O P Id ⎯ L L Front SP relay B control terminal, L: Mute
46 P65 C-RELAY O P Id ⎯ L L Center SP relay control terminal, L: Mute
47 P66 S-RELAY O P Id ⎯ L H Surround SP relay control terminal, L: Mute
48 P67 PRE F MUTE O P Ed ⎯ L H Front PRE OUT mute control terminal, L: Mute
49 P70 PRE C MUTE O P Ed ⎯ L L Center PRE OUT mute control terminal, L: Mute
50 P71 PRE S MUTE O P Ed ⎯ L L Surround PRE OUT mute control terminal, L: Mute
51 P72
52 P73 H/P RELAY O P Id ⎯ L H H/P OUT relay control terminal, L: Mute
53 P74 EXP OE O P Ed ⎯ L H Port expander control terminal (BU4094)
54 P75 EXP CLK O P Ed ⎯ L L Port expander control terminal (BU4094)
55 P76 EXP DATA O P Ed ⎯ L L Port expander control terminal (BU4094)
56 P77 EXP STB O P Ed ⎯ L L Port expander control terminal (BU4094)
57 P80 POWER O P Id ⎯ L H Power relay control output, H: ON
58 P81 RESET2 O P Id ⎯ L L Reset signal output to sub-CPU, H: Reset
59 P82 PRE S.BACK MUTE O P Id ⎯ L L Surround Back PRE PUT mute control terminal, L: Mute
60 P83 S.BACK VOL MUTE O P Id ⎯ L L Surround Back volume mute, L: Mute
61 P84 STANDBY O P Id ⎯ L H Standby LED drive output H: Light
62 P85 S.BACK RELAY O P Id ⎯ L L Surround Back SP relay control terminal, L: Mute
63 P86 LED CK O P Id ⎯ L L LED control terminal (BU2090F)
64 P8 7 LED DATA O P I d ⎯ L L LED control terminal (BU2090F)
65 P90 TUNER MUTE O P Ed ⎯ L H TUNER mute control terminal, L: Mute
66 P91 MULTI MUTE O P Id ⎯ L H MULTI PREOUT mute control terminal, L: Mute
67 P92 S MONI DET I ⎯ Eu Lv Z ⎯ S monitor connection detect input, L: Connected
68 P93 S SIG DET I ⎯ Eu Lv Z ⎯ S signal detect input, H: Detected
69 P94 SYNC DET. I ⎯ Eu Lv Z ⎯ Sync detect input, H: Ext. sync
70 P95 SEL A (M) I ⎯ Eu Lv Z ⎯ Master volume rotation detect input (rotary encoder)
71 P96 SEL B (M) I ⎯ Eu Lv Z ⎯ Master volume rotation detect input (rotary encoder)
72 P97 CINEMA EQ O P Eu Lv Z L CINEMA EQ control output, H: ON
73 PD0 VOL MUTE O P Ed ⎯ L L Master volume minimum control, L: Min.
74 PD1 SEL C (S) I ⎯ Eu Lv Z ⎯ Surround mode rotation detect input (rotary encoder)
75 PD2 SEL D (S) I ⎯ Eu Lv Z ⎯ Surround mode rotation detect input (rotary encoder)
76 PD3 SEL E (F) I ⎯ Eu Lv Z ⎯
77 PD4 SEL F (F) I ⎯ Eu Lv Z ⎯
78 Vkk Vkk ⎯⎯⎯⎯⎯⎯GND fixed
79 P00/SCK1_ O C ⎯⎯ ZL
80 P01/SI1 RDS CE O C ⎯⎯ Z L RDS data output (LC72720)

NOTE:

Pin No. :Terminal number of microcomputer.
Port Name : The name entered in the data sheet of microcomputer.
Symbol :Symbolized interface function.
I/O : Input or out of part.

Type :Composition of port in case of output por t.

Op : Pull up/Pull down selection information.

Det : Indicates judging state of input port. Level detection is “LV”; Edge detection is “Ed”;

Res :State at reset.

Ini : Initial output state.
Function :Function and logical level explanation of signals to be interface.

Detection by both shifting is “E&L”; Serial data detection is “S” (Serial data output is also “S”).

Symbol

SUB WOOFER MUTE

“I” = Input por t
“O” = Output port

“C” = CMOS output
“N” = NMOS open drain output
“P” = PMOS open drain output

“Iu” = Inner microcomputer pull up
“Id” = Inner microcomputer pull down
“Eu” = Exter nal microcomputer pull up
“Ed” = Exter nal microcomputer pull down

“H” = Outputs High Level at reset
“L” = Outputs Low Level at reset
“Z” = Becomes High impedance mode at reset

I/O Type Op Det Res Init

OPEd⎯ L H Sub-woofer PRE OUT mute control terminal, L: Mute

Input selector switch rotation detect input (rotary encoder)
Input selector switch rotation detect input (rotary encoder)

Function

15

TMP93CS40F (AU: IC301)

7 5

7 6

1 0 0

1

5 1

5 0

2 6

2 5

TMP93CS40F Terminal Function

Pin

Name

No.

1 V REFL ⎯⎯⎯⎯⎯⎯A/D ref. GND

2 A Vss ← ⎯⎯⎯⎯⎯⎯A/D GND

3 A Vcc ← ⎯⎯⎯⎯⎯⎯AD +5V

4 _NMI I ⎯⎯⎯⎯⎯Not used (fixed to H)

5 P70/TI0 C15 O C Ed ⎯ L L Fixed to L (DSP ROM address cont. out bit 15, not used)

6 P71/TO1 C16 O C Ed ⎯ L L DSP program ROM address cont. out bit 16

7 P72/TO2 C17 O C Ed ⎯ L L DSP program ROM address cont. out bit 17

8 P73/TO3 ROM/RAM O C Ed ⎯ L L ROM/RAM switching control terminal (L:ROM)

9 P80/INT4/TI4 _INTREQ OUT I/O C Eu E↓&L Z ⎯ DSP request input and cont. output (L:Rq & cont.)
10 P81/INT5/TI5 B.DOWN I ⎯ Eu E↑&L Z ⎯ Power down detect (H: Detected)
11 P82/TO4 O C ⎯⎯ LL

12 P83/TO5 _REQ O C Eu ⎯ HL

13 P84/INT6/TI6 _ACK I ⎯ Eu E↓&L ⎯⎯MAIN-SUB CPU comm. control input (L: Ack. return from main)
14 P85/INT7/TI7 ERR I ⎯⎯E↑&L ⎯⎯DIR control input terminal (LC89055Q)( H: ERR)
15 P86/TO6 I ⎯⎯Lv Z ⎯ (GND)

16 P97/INT0 _CS I ⎯ Ed E↑&L ⎯⎯

17 P90/TXD0 S I O C MAIN-SUB CPU comm. control terminal (data output)
18 P91/RXD0 SO I ⎯ MAIN-SUB CPU comm. control terminal (data input)

19

P92/_CTS0/SCLK0

20 P93/TXD1 O C ⎯⎯ ZL
21 P94/RXD1 O C ⎯⎯ ZL
22 P95/SCLK1 O C ⎯⎯ ZL
23 AM8/_16 ← ⎯⎯⎯⎯⎯⎯Fixed to +5V
24 CLK O C Eu ⎯⎯⎯
25 Vcc ← ⎯⎯⎯⎯⎯⎯+5V
26 Vss I/O1 ⎯⎯⎯⎯⎯⎯GND
27 X1 Xin I ⎯⎯⎯⎯ ⎯X′tal connection
28 X2 Xout O ⎯⎯⎯⎯⎯X′tal connection
29 _EA ← ⎯⎯⎯⎯⎯⎯Fixed to +5V
30 _RESET RESET2_ I ⎯ Eu Lv L ⎯ Reset input (controlled by main CPU)
31 P96/XT1 A/D RESET O N Eu ⎯ H H A/D control terminal (L: Reset)
32 P97/XT2 O C Ed ⎯ LL
33 TEST1 ← I ⎯⎯⎯⎯⎯Connected to TEST2
34 TEST2 ← I ⎯⎯⎯⎯⎯Connected to TEST1
35 PA0 DINA O C Ed ⎯ L L Digital input switching control output
36 PA1 DINB O C Ed ⎯ L L Digital input switching control output
37 PA2 O C ⎯⎯ LL
38 PA3 DINC O C Ed ⎯ L L Digital input switching control output
39 PA4 DOUTA O C Ed ⎯ L L Digital output switching control output
40 PA5 DOUTB O C Ed ⎯ L L Digital output switching control output

Symbol

CLK I/O C MAIN-SUB CPU comm. control terminal (I2C clock in/output)

I/O Type Op Det Res Init

MAIN-SUB CPU comm. control output (L: Comm. request from

sub)

DIR control input terminal (LC89055Q), when CH status change

L→H

Function

Pin

Name

No.

41 PA6 DEEMP O C Ed ⎯ L L DAC de-emphasis filter cont. out terminal (H:ON)
42 PA7/SCOUT 96k-DAC O C ⎯⎯ L L DAC control terminal (H: Sample frequency 96kHz)
43 ALE O C ⎯⎯ L L (Address latch enable)
44 Vcc ⎯⎯⎯⎯⎯⎯+5V
45 P00/AD0 (AD0) I/O C ⎯⎯ Z L (EPROM data in D0 / address out A0)
46 P01/AD1 (AD1)) I/O C ⎯⎯ Z L (EPROM data in D1 / address out A1)
47 P02/AD2 (AD2) I/O C ⎯⎯ Z L (EPROM data in D2 / address out A2)
48 P03/AD3 (AD3) I/O C ⎯⎯ Z L (EPROM data in D3 / address out A3)
49 P04/AD4 (AD4) I/O C ⎯⎯ Z L (EPROM data in D4 / address out A4)
50 P05/AD5 (AD5) I/O C ⎯⎯ Z L (EPROM data in D5 / address out A5)
51 P06/AD6 (AD6) I/O C ⎯⎯ Z L (EPROM data in D6 / address out A6)
52 P07/AD7 (AD7) I/O C ⎯⎯ Z L (EPROM data in D7 / address out A7)
53 P10/AD8/A8 (A8) O C ⎯⎯ Z L (EPROM address out A8)
54 P11/AD9/A9 (A9) O C ⎯⎯ Z L (EPROM address out A9)
55 P12/AD10/A10 (A10) O C ⎯⎯ Z L (EPROM address out A10)
56 P13/AD11/A11 (A11) O C ⎯⎯ Z L (EPROM address out A11)
57 P14/AD12/A12 (A12) O C ⎯⎯ Z L (EPROM address out A12)
58 P15/AD13/A13 (A13) O C ⎯⎯ Z L (EPROM address out A13)
59 P16/AD14/A14 (A14) O C ⎯⎯ Z L (EPROM address out A14)
60 P17/AD15/A15 (A15) O C ⎯⎯ Z L (EPROM address out A15)
61 _WDTOUT ← OC⎯⎯Z H Watch dog output
62 Vss ← ⎯⎯⎯⎯⎯⎯GND
63 Vcc ← ⎯⎯⎯⎯⎯⎯+5V
64 P20/A0/A16 (A16) O C ⎯⎯ Z L (EPROM address out A16)
65 P21/A1/A17 DIR CLK O C ⎯⎯ Z L DIR control terminal (LC89055Q) control clock output
66 P22/A2/A18 DIR CE O C ⎯⎯ Z L DIR control terminal (LC89055Q) control chip enable output
67 P23/A3/A19 DIR MOSI O C ⎯⎯ Z L DIR control terminal (LC89055Q) control data output
68 P24/A4/A20 DIR MOSO I ⎯⎯Lv ⎯⎯DIR control terminal (LC89055Q) control data input
69 P25/A5/A21 FGAIN O C Ed ⎯ L L FRONT ch GAIN switching control output (H: SW=NO)
70 P26/A6/A22 DAC-RESET O C Ed ⎯ LH
71 P27/A7/A23 SEL CK O C ⎯⎯ Z L ADC/DIR data clock switching control terminal (L: ADC)
72 P30/_RD (_RD) O C ⎯⎯ Z L (Flash memory control terminal)
73 P31/_WR (_WR) O C ⎯⎯ Z L (Flash memory control terminal)
74 P32/_HWR CSI I ⎯⎯Lv ⎯⎯DIR control input terminal (L: PCM)
75 P33/_WAIT ERR MUTE_ O C Ed ⎯ L L Pop noise preventive mute control output (L: Mute)
76 P34/_BUSRQ I ⎯⎯Lv Z ⎯ GND
77 P35/_BUSRQ DIG.(AC3) MUTE O C Ed ⎯ Z L Digital mute control output (L: AC-3 or DTS decode enable)
78 P36/_R/W I ⎯⎯Lv Z ⎯ GND
79 P37/_RAS DIR RESET O C ⎯⎯ Z L DIR control output (LC89055Q) (L: Reset)

80

P40/_CS0/_CAS0

81

P41/_CS1/_CAS1

82

P42/_CS2/_CAS2

83 P60/PG00 DSP. RESET O C ⎯⎯ Z L DSP reset output terminal (L:Reset)
84 P61/PG01 I/02 SCD OUT I C ⎯ Lv Z ⎯ DSP status data input terminal
85 P62/PG02 I/03 DSP. CS O ⎯⎯⎯ Z L DSP chip select cont.output (L:Data out)
86 P63/PG03 I/04 DSP. CLK O C ⎯⎯ Z L DSP data clock output terminal
87 P64/PG10 I/05 SCD IN O C ⎯⎯ Z L DSP data output terminal
88 P65/PG11 I/06 4527_CE O C ⎯⎯ Z L AD control terminal (AK4527), Chip enable output
89 P66/PG12 I/07 4527_CLK O C ⎯⎯ Z L AD control terminal (AK4527), Data clock output
90 P67/PG13 I/08 4527_DIN O C ⎯⎯ Z L AD control terminal (AK4527), Data output
91 Vss ← ⎯⎯⎯⎯⎯⎯GND
92 P50/AN0 INTTREQ IN I ⎯ Eu Lv Z ⎯
93 P51/AN1 I ⎯ Eu Lv Z ⎯
94 P52/AN2 EMP I ⎯⎯Lv ⎯⎯H: EMP on
95 P53/AN3 96K DET I ⎯⎯Lv ⎯⎯96k signal detect input, H: 96k
96 P54/AN4 I ⎯ Eu Lv ⎯ Z
97 P55/AN5 I ⎯ Eu Lv ⎯ Z
98 P56/AN6 ACC ON/OFF I ⎯ Eu Lv ⎯ Z
99 P57/AN7 I ⎯ Eu Lv ⎯ Z

100 V REFH ← ⎯⎯⎯⎯⎯⎯AD ref. +5V

Symbol

(_CS0) O C ⎯⎯ Z L (Flash memory control terminal)

I/O Type Op Det Res Init

OC⎯⎯ZL
OC⎯⎯ZL

DAC control terminal (L: Power down mode, ↑(rising edge) Reset)

Function

16

CS493292-CL (AU: IC814)

A0, SCCLK 7

DATA7, EMAD7, GPIO7 8

DATA6, EMAD6, GPIO6 9

DATA5, EMAD5, GPIO5 10

DATA4, EMAD4, GPIO4 11

VD2 12

DGND2 13

DATA3, EMAD3, GPIO3 14

DATA2, EMAD2, GPIO2 15

DATA1, EMAD1, GPIO1 16

DATA0, EMAD0, GPIO0

A1, SCDIN

RD, R/W, EMOE, GPIO11

WR/DS/EMWR, GPIO10

AUDATA3, XMT958

6

5

4

3

DGND1

2

Top View

VD1

1

MCLK

44

SCLK

43

LRCLK

42

AU DATA 0

AU DATA 1

41

40

AU DATA 2

39

DC

38

37

DD

36

RESET

35

AGND

34

VA

33

FILT1

32

FILT2

31

CLKSEL

30

CLKIN

29

CMPREQ, LRCLKN217



 CS493292-CL Terminal Funtion



CS 18

SCDIO, SCDOUT,PSEL, GPIO9 19

VD3 23

DGND3 24

SDATAN1 22

ABOOT, INTREQ 20

EXTMEM, GPIO8 21

LRCLKN1 26

CMPCLK, SCLKN2 28

SCLKN1, STCCLK2 25

CMPDAT,SDATAN2, RCV958 27

Port Name FunctionPin No.

1,12,23 VD1,2,3 Digital power supply (+)
2,13,24 DGND1,2,3 Digital GND

3 AUDATA3, XMT958 SPDIF transmitter output, Digital audio output 3

4 WR, DS, EMWR, GPIO10

5 RD, R/W, EMOE,GPIO11

Host write strobe, Host data strobe, External memory write enable,
General purpose in/output 10
Host parallel output enable, Host parallel R/W, External memory write enable,

General purpose in/output 11
6 A1,SCDIN Host address bit 1, SPI serial control data input
7 A0,SCCLK Host address bit 0, Serial control port clock
8 DATA7, EMAD7, GPIO7 Bidirectional data bus 7, External memory address 7, General purpose in/output 7
9 DATA6, EMAD6, GPIO6 Bidirectional data bus 6, External memory address 6, General purpose in/output 6

10 DATA5, EMAD5, GPIO5 Bidirectional data bus 5, External memory address 5, General purpose in/output 5
11 DATA4, EMAD4, GPIO4 Bidirectional data bus 4, External memory address 4, General purpose in/output 4
14 DATA3, EMAD3, GPIO3 Bidirectional data bus 3, External memory address 3, General purpose in/output 3
15 DATA2, EMAD2, GPIO2 Bidirectional data bus 2, External memory address 2, General purpose in/output 2
16 DATA1, EMAD1, GPIO1 Bidirectional data bus 1, External memory address 1, General purpose in/output 1
17 DATA0, EMAD0, GPIO0 Bidirectional data bus 0, External memory address 0, General purpose in/output 0
18 CS Host parallel chip select, Host serial SPI chip select
19 SCDIO, SCDOUT, PSEL,GPIO9 Serial control port data in/output, Parallel port type select, General purpose in/output 9
20 INTREQ, ABOOT Control port interrupt request, Automatic boot enable
21 EXTMEM, GPIO8 External memory chip select, General purpose in/output 8
22 SDATAN1 PCM audio data input 1
25 SCLKN1, STCCLK2 PCM audio input bit clock
26 LRCLKN1 PCM audio input sample rate clock
27 CMPDAT, SDATAN2 PCM audio data input 2
28 CMPCLK, SCLKN2 PCM audio input bit clock
29 CMPREQ, LRCLKN2 PCM audio input sample rate clock
30 CLKIN Master clock input
31 CLKSEL DSP clock select
32 FILT2 PLL filter
33 FILT1 PLL filter
34 VA Analog power supply (+)
35 AGND Analog GND
36 RESET Master reset input
37 DD Reserved
38 DC Reserved
39 AUDATA2 Digital audio output 2
40 AUDATA1 Digital audio output 1
41 AUDATA0 Digital audio output 0
42 LRCLK Audio output sample rate clock
43 SCLK Audio output bit clock
44 MCLK Audio master clock

17

LC89055W (AU: IC800)

D I

D O

E R R O R

B P S Y N C

A U T O

D G N D

D V D D

V F / P 3 / C 3

F 2 / P 2 / C 2

F 1 / P 1 / C 1

F 0 / P 0 / C 0

C S F L A G

A U D I O

E M P H A

X I N

X O U T

X M C K

D V D D

D G N D

X S T A T E

D A T A 0

L R C K

B C K

C K O U T

A V D D

A G N D

X S E L

M O D E 0

M O D E 1

D G N D

D V D D

D O S E L 0

D O S E L 1

C K S E L 0

C K S E L

X M O D E

C E

C L

1

R

V I N

D I N 0

D I N 1

D I N 2

D O U T

D I S E L

D G N D

L P F

D V D D

LC89055W Terminal Function

Pin
No.

Pin Name

I/O

1 DISEL I Data input terminal (select input pin of DIN0, DIN1)
2 DOUT O Input bi-phase data through output terminal
3 DIN0 I Amp built-in coaxial/optical input correspond data input terminal
4 DIN1 I Amp built-in coaxial/optical input correspond data input terminal
5 DIN2 I Optical input correspond data input terminal
6 DGND Digital GND
7 DVDD Digital power supply
8 R I VCO gain control input terminal

9 VIN I VCO free-run frequency setting input terminal
10 LPF O PLL loop filter setting terminal
11 AVDD Analog power supply
12 AGND Analog GND
13 CKOUT O Clock output terminal (256fs, 384fs, 512fs, X′tal osc., VCO free-run osc.)
14 BCK O 64fs clock output terminal
15 LRCK O fs clock output terminal (L: Rch, H: Lch, I2S: Reverse)
16 DATAO O Data o utput te rmi na l
17 XSTATE O Input data detecting result output terminal
18 DGND Digital GND
19 DVDD Digital power supply
20 XMCK O X′tal osc. clock output terminal (24.576MHz or 12.288MHz)
21 XOUT O X′tal osc. connection output terminal
22 XIN I X′tal osc. connection input terminal, external signal input possible (24.576MHz or 12.288MHz)
23 EMPHA O Emphasis information output terminal of channel status
24 AUDIO O Bit1 output terminal of channel status
25 CSFLAG O Top 40bit revise flag output terminal of channel status
26 F0/P0/C0 O Input fs cal. sig. out / data type out / input word inf. output terminal
27 F1/P1/C1 O Input fs cal. sig. out / data type out / input word inf. output terminal
28 F2/P2/C2 O Input fs cal. sig. out / data type out / input word inf. output terminal
29 VF/P3/C3 O Validity flag out / data type out / input word inf. output terminal
30 DVDD Digital power supply
31 DGND Digital GND
32 AUTO O Non PCM burst data transfer detect sig. output terminal
33 BPSYNC O Non PCM burst data preamble Pa, Pb, Pc, Pd sync sig. output terminal
34 ERROR O PLL lock error, data error flag output terminal
35 DO O CPU I/F read data output terminal
36 DI I CPU I/F write data input terminal
37 CE I CPU I/F chip enable input terminal
38 CL I CPU I/F clock input terminal
39 XSEL I Frequency select input pin of XIN X′tal osc. (24.576MHz or 12.288MHz)
40 MODE0 I Mode setting input terminal
41 MODE1 I Mode setting input terminal
42 DGND Digital GND
43 DVDD Digital power supply
44 DOSEL0 I Data output format select input terminal
45 DOSEL1 I Data output format select input terminal
46 CKSEL0 I Output clock select input terminal
47 CKSEL1 I Output clock select input terminal
48 XMODE I Reset input terminal

* For latch-up countermeasure, set digital (DVDD) and analog (AVDD) power on/off in the same timing.

Function

18

M35015-210SP (AU: IC453)

O S C 1

O S C 2

C V I D E O

L E C H A

C V I N

1

2

3

C S

4

S C K

S I N

5
6

A C

V

D D 2

7

8

9

1 0

2 0

V

D D 1

1 9

V E R T *

1 8

H O R *

1 7

O S C I N

1 6

O S C O U T

1 5

P 3

1 4

P 2

1 3

P 1

1 2

P 0

1 1

V s s

C S

S C K

S I N

S Y N C S I G N A L

H O R *V E R T *O S C 2O S C 1

S Y N C S I G N A L D I S -

C R I M I N A T I N G C I R C U I T

O S C C I R C U I T

F O R S Y N C S I G N A L

G E N E R A T I O N

T I M I N G

G E N E R A T O R

1 7

1 6

O S C I N

O S C O U T

1 2 1 9 1 8

3

I N P U T

4

C O N T R O L

C I R C U I T

5

U I T

I N D I C A T I O N

C O N T R O L
R E G I S T E R

A D D R E S S
C O N T R O L

C I R C U I T

D A T A

C O N T R O L

C I R C

I N D I C A T I O N

O S C I L L A T O R

T I M I N G

G E N E R A T O R

I I N D I C A T I O N L O C A T I O N

D E T E C T I O N C I R C U I T

R E A D O U T A D D R E S S

C O N T R O L C I R C U I T

S W I T C H I N G C I R C U I T

H C O U N T E R

V

D D 1

2 0

6

A C

1 1

V s s

7

V

D D 2

I N D I C A T I O N R A M

I N D I C A T I O N C H A R A C T E R R O

M

B L I N K I N G C I R C U I T

I N D I C A T I O N

C O N T R O L C I R C U I T

S H I F T R E G I S T E R

N T S C

V I D E O O U T P U T

C I R C U I T

M35015-210SP Terminal Function

Pin No. Symbol Name I/O Function

1 OSC1 Osc. circuit ext. I External terminal for indication oscillator circuit. Standard OSC. freq. is approx. 7MHz.

2 OSC2 terminal. O With this OSC. freq., decides horizontal indicatin and character width.

3 CS Chip select input I

4 SCK Serial clock input I

5 SIN Serial data input I

6 AC Auto-clear input I

DD2

7V

8CVIDEO

9 LECHA

10 CVIN

Power supply

Combined
video output
Character level
input
Combined video
input

11 Vss Ground

12 P0 Output port p0 O

13 P1 Output port P1 O

14 P2 Output port P2 O

15 P3 Output port P3 O

16 OSCOUT O Terminal for external use of sync signal OSC. circuit. Use the freq.: 14.32MHz at NTSC

17 OSCIN I system, 17.73MHz at PAL. system, 14.30MHz at MPAL system.

18 HOR*

19 VERT*

DD1

20 V

Ext. terminal
for sync sig.
OSC. Circuit

Horizontal sync
signal
Vertical sync
signal
Power supply I Power supply terminal of digital system. Connect to +5V.

Chip select terminal and turns to “L” when transfer serial data.
Hysteresis input. Pull up resistor is built-in.
Takes in serial data of SIN at SCK rise when CS terminal is in “L”.
Hysteresis input. Pull up rersist is built-in.
Serial input of register for indication control and data, and address for indication data
memory. Hysteresis input. Pull up rersistor is built-in.
Resets internal circuit of IC at “L” mode.
Hysteresi input. Pull up resistor is built-in.



Power supply terminal of analog system. Connect to +5V.

Output terminal of combined video signal. Outputs 2Vp-p combined signal. Character

O

output, etc. Overlap CVIN signal and outputs at superimpose.
Input terminal deciding character output level in combined video signal. color of character

I

is white.
Input terminal of external combined video signal.

I

Character output etc. overlap this external combined video signal.



Ground terminal. Connect to GND.

General output or character background signal BL NK1* output is switchable.
Polarity can be selected at ROM mask.
General output or character background signal CO1* output is switchable.
Polarity can be selected at ROM mask.
General output or character background signal BLNK2* output is switchable.
Polarity can be selected at ROM mask.
General output or character background signal CO2* output is switchable.
Polarity can be selected at ROM mask.

Inputs horizontal sync signal.

I

Hysteresis input.



Input vertical sync signal. Hysteresis input. Polarity can be selected at ROM mask.

8

C V I D E O

9

L E C H A

1 0

C V I N

P 0

1 2

1 3

P 1

1 4

P 2

1 5

P 3

19

AK4527BVQ (AU:IC602)

SDOS

I2C

SMUTE

BICK

LRCK

SDTI1

SDTI2

SDTI3

SDTO

DAUX

DFS

L0OP1

L0OP0/SDA/CDTI

DIF0/CSL

P/S

MCLK

DIF1/SCL/CCLK

39

13 14

DEM1

DEM0

41

15

TVDD

40

Top View

16 17 18

DVDD

DVSS

PDN

444342

1
2
3
4
5
6
7
8
9

10

11

12

38

ICKS2

DZF1

AVSS

37

192021

ICKS1

36

AVDD

35

ICKS0

VREFH

VCOM

34

22

CAD1

CAD0

33

DZF2

32

RIN+

31

RIN–

30

LIN+

29

LIN–

28

ROUT1

27

LOUT1

26

ROUT2

25

LOUT2

24

ROUT3

23

LOUT3

AK4527BVQ Terminal Function

Pin

Pin Name I/O Function

No.

1 SDOS I SDTO source select pin, L: Internal ADC output, H: DAUX input

2 I2C I Serial control mode select pin, L: 3-core serial, H: I2C bus

3 SMUTE I Soft mute pin, H: Soft mute start, L: Release

4 BICK I Audio serial data clock pin

5 LRCK I Input channel clock pin

6 SDTI1 I DAC1 audio serial data input pin

7 SDTI2 I DAC2 audio serial data input pin

8 SDTI3 I DAC3 audio serial data input pin

9 SDTO O Audio serial data output pin

10 DAUX I Auxiliary audio serial data input pin
11 DFS I Double speed sampling mode pin, L: Normal, H: Double
12 NC  No Connect, No internal bonding
13 DZFE I Zero input detect enable pin
14 TVDD  Power pin for output buffer, 2.7V~5.5V
15 DVDD  Digital power pin, 4.5V~5.5V
16 DVss  Digital GND pin, 0V
17 PDN I Power down & reset pin, L: Powered-down and register initialized, Reset with PDN when switching CAD0-1
18 TST I Test pin, connected to DVSS
19 NC  No Connect, No internal bonding
20 ADIF I Analog Input Format Select pin
21 CAD1 I Chip address-1 pin
22 CAD0 I Chip address-0 pin
23 LOUT3 O DAC3L channel analog out pin
24 ROUT3 O DAC3R channel analog out pin
25 LOUT2 O DAC2L channel analog out pin
26 ROUT2 O DAC2R channel analog out pin
27 LOUT1 O DAC1L channel analog out pin
28 ROUT1 O DAC1R channel analog out pin
29 LIN- I L-ch analog inverted input pin
30 LIN+ I L-ch analog non-inverted input pin
31 RIN- I R-ch analog inverted input pin
32 RIN+ I R-ch analog non-inverted input pin
33 DZF2/OVF O 0 input detect 2 pin/Analog input overflow detect pin
34 VCOM O Common V-out pin, AVDD/2, connect large capacitor to avoid noise
35 VREFH I Ref. V input pin, AVDD
36 AVDD  Analog GND pin, 4.5V~5.5V
37 AVss  Analog GND pin, 0V
38 DZF1 O 0 input detect pin, H: Input data of G1 is 8192 times “0” in a raw or RSTN bit “0”, L: When P/S= “0”
39 MCLK I Master clock input pin
40 P/S I Parallel/Serial select pin, L: Serial control

DIF0 I Audio data I/F format 0 pin (parallel control)

41

CSN I Chip select pin (3-wire serial control), connect to DVDD when I
DIFI I Audio data I/F format 1 pin (parallel control)

42

SCL/CCLK I Control data clock pin (serial control), I
LOOP0 I Loop back mode 0 pin (parallel control), effects digital loop back ADC to all DAC

43

SDA/CDTI I/O Control data input pin (serial control), I

2

C=”L”: CCLK (3-wire serial), I2C=”H”: SCL (I2C bus)

2

C=”L”: CCTI (3-wire serial), I2C=”H” SDA (I2C bus)

44 LOOP1 I Loop back mode 1 pin, from SDT1 to all DAC

2

C bus control

20

BU4094BCF (CO: IC304,305)

STROBE

DATA

CLOCK

V

1

2

3

4

Q1

5

Q2

6

Q3

7

Q4

8

SS

16

VDD

15

OE

14

Q5

13

Q6

12

Q7

Q8

11

10

Q'

S

Q

S

9

CO: IC304

Port

Q1 A Video input switching
Q2 B Video input switching
Q3 C Video input switching
Q4 D Video output switching
Q5 E Video output switching
Q6 F Video output switching
Q7 H Video output switching
Q8 G Video output switching

Symbol Function

CO: IC305

Port

Q1
Q2 S1 Video signal switching control output
Q3 S2 Video signal switching control output
Q4 EXT. IN
Q5 D Video output switching
Q6 G Video output switching
Q7 NC
Q8 FRONT A+B Current limiter control terminal (H:Front SP A+B)

Symbol Function

DIRECT/TONE DEFEAT

DIRECT & TONE DEFEAT relay control (H:DIRECT,TONE DEFEAT)

Sub woofer channel gain control terminal (L:EXT. IN)

LC75721E (CO: IC101)

G7 G8G9

G10

G11

AA8/G12

AA7/G13

AA6/G14

AA5/G15

AA4/G16

48 33

49

DI
CL
CE

RES

DD

V

OSCI

OSCO

Vss

TEST

FL

V

G1
G2
G3
G4
G5
G6

64

AM 1

AM 2

AM 3

AM 4

AM 5

AM 6

AM 7

AM 8

AM 9

AM 10

AA3

AM 11

AA2

AM 12

AA1

AM 13

AM35

AM 14

AM34

AM 15

AM33

161

AM 16

32

17

LC75721E Terminal Function

Symbol

V

DD

Vss

FL

V

AM 17
AM 18

DI

AM 19
AM 20

CL

AM 21

CE

AM 22
AM 23
AM 24

OSCI

AM 25

OSCO

AM 26
AM 27

RES

AM 28
AM 29

AM1~AM35

AM 30

AA1~AA3

AM 31
AM 32

AA4/G16
AA5/G15
AA6/G14
AA7/G13
AA8/G12

G1~G11 Grid output terminal
TEST LSI test terminal

Function
Power terminal +5V
Power terminal GND
Power terminal FL drive
Serial data transfer terminal

DI: Data
CL: Clock
CE: Chip enable

External CR connecting terminal

System reset terminal

Anode output terminal

Anode/Grid output terminal

BU2090F (CO: IC103)

1Vss

2DATA

3CLOCK

4LCK

5Q0

6Q1

7Q2

8Q3

9Q4

TC9274N-011 (AU: IC107) TC9274N-017 (EX: IC312)

S1S2S3S4S5S6S7S8S9

41

40

V

DD

42

36

3839

37

S10

35

18 bit Latch Circuit (Rch)

(Lch) Same as Rch

S11

32

34

33

S12

S13

S14

S15

S16

S17

S18

26

29

28

3031

24

25

27

23

STB

22

DATA

S1S2S3S4S5S6S7S8S9

41

40

V

DD

42

36

3839

37

S10

35

18 bit Latch Circuit (Rch)

(Lch) Same as Rch

S11

32

34

33

CONTROL CIRCUIT

12-bit SHIFT RESISTER

12-bit STRAGE RESISTER

OUTPUT BUFFER (OPEN DRAIN)

S12

S13

S14

S15

S16

26

29

28

27

3031

DD

18

V

OE

17

Q11

16

Q10

15

Q9

14

Q8

13

Q7

12

Q6

11

Q5

10

S17

S18

24

25

23

STB

22

DATA

V

SS

1

2

345678 9 10 111213 14

S1S2S3S4S5S6S7S8S9

21

CK

Level Shift + Shift Register Circuit

20

GND

16 171819

15

S10

S11

S12

S13

S14

S15

S16

S17

S18

V

SS

1

2

34567891011

S1S2S3S4S5S6S7S8S9

12

S10

16 171819

14

15

13

S11

S12

S13

S14

S15

S16

S17

21

CK

Level Shift + Shift Register Circuit

20

GND

S18

21

TC9273N-004 (AU: IC108)

Vss

1

S1

2

S2

3

4

S3

S4

5

6

S5

7

S6

S7

8

9

S8

10

S9

11

S10

12

V

DD

28

S1

27

S2

26

25

S3

S4

24

23

S5

22

S6

S7

21

20

S8

19

S9

18

S10

17

TC9273N Terminal Function

Symbol Name

Pin No

1

13

28

2~12

12~27

14

15

16

Vss

GND

V

DD

S1~S10

CK

DATA

STB

+Power Terminal

Digital Ground

+Power Terminal

I/O Terminal

Clock Input

Data Input

Dual Power Use:VDD = 8.0~17 V Single Power Use:VDD = 8.0~18V

Input terminal of analog switch.

Clock input for data transfer.

Serial input for switch setting.

Strobe InputStrobe input for data writing.Strobe Input

Function

GND=0V

Vss=-8.0~-17V

GND=0V

Low level

Border Input

Terminal

13

GND

14

CK

STB

DATA

16

15

NJM2229S (AU: IC452)

AD1854 (AU: IC601)

1

DGND

2

MCLK

3

CLATCH

4

CCLK

5

CDATA

6

384/256

7

X2MCLK

8

ZEROR

9

DEEMP

10

96/48

11

AGND

12

OUTR+

13

OUTR−

14

FILTR

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

DVDD

SDATA

BCLK

L/RCLK

PD/RST

MUTE

ZEROL

IDPM0

IDPM1

FILTB

AVDD

OUTL+

OUTL−

AGND

7

15

6

Sync Sepa

Vsync Sepa

FRONT VIEW

16

14

13

Sync Det

11

12

8

Phase

Det

4

32fH

VCO

3

2

Terminal Function

No.

11,15 AGND I Analog Ground

Name Function

I/O

1 DGND I Digital Ground.

2 MCLK I Master Clock Input

3 CLATCH I Latch input for control data

4 CCLK I Control clock input for control data

5 CDATA I Serial control input

6 384/256 I Selects the master clock mode

7 X2MCLK I Selects internal clock doubler (LO) or internal clock=MCLK (HI)

8 ZEROR O Right Channel Zero Flag Output

9 DEEMP I De-Emphasis

10 96/48 I Selects 48kHz (LO) or 96kHz Sample Frequency Control

12 OUTR+ O Right Channel Positive line level analog output

13 OUTR- O Right Channel Negative line level analog output

14 FILTR O Voltage Reference Filter Capacitor Connection

16 OUTL- O Left Channel Negative line level analog output

17 OUTL+ O Left Channel Positive line level analog output

18 AVDD I Analog Power supply

19 FILTB O Filter Capacitor connection

20 IDPM1 I Input serial data port mode control one

21 IDPM0 I Input serial data port mode control zero

22 ZEROL O Left Channel Zero Flag output

23 MUTE I Mute. Assert HI to mute both stereo analog output

24 PD/RST I Power-Down/Reset

25 L/R CLK I Left/Right clock input for input data

26 BCLK I Bit clock input for input data

27 SDATA I Serial input

28 DVDD I Digital Power Supply

9

1

10

1/32

5

16

22

SN74LV244APW (AU: IC818, 825)

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

1
2

3
4

5

6

7
8

9

10

TOP VIEW

Vcc

20

2OE

19

1Y1

18

2A4

17

1Y2

16

2A3

15

1Y3

14

2A2

13

12

1Y4

11

2A1

FUNCTION TABLE

(each buffer)

INPUT

OE A Y

LH H

LL L

HX Z

OUTPUT

BU4053BCF (AU:IC256)

MM74HC4053SJ (AU: IC451)

Z-COM

INH

V
Vss

Y1
Y0

Z1

Z0

EE

TOP VIEW

1

2

3

4

5

6

7

8

 $

 #

 "

 !

12

11

 

9

DD

V

Y-COM

X-COM

X1

X0
A

B

C

V

INH6

Vss8

V

X0 12
X1 13
Y0 2

Y1 1
Z0 5

Z1 3

DD

A11
B10

16

C9

EE

7

LEVEL
CONVER

-TER

BINARY TO 1 of 2
DECODER WITH INHIBIT

14 X

15 Y

4 Z

TC9459N
(EX: IC805)

TOP VIEW TOP VIEW

Vss

L-OUT

L-IN

L-LD1

L-LD2

L-A-GND

CS1

GND

1

2

NC

3

4

NC

5

6

7

8

9

NC

10

NC

11

NC

12

13

14

CK

28

27

26

25

24

23

22

21

20

19

18

17

16

15

TC9184AP (EX: IC102)

TOP VIEW

Vss

BASS+

BASS-

COM

TREBLE-

TREBLE+

GND

CK

1

2

3

4

5

5

6

7

8

16

15

14

13

12

11

10

9

V

DD

NC

R-OUT

NC

R-IN

R-LD1

R-LD2

R-A-GND

NC

CS2

NC

NC

STB

DATA

V

DD

BASS+

BASS-

COM

TREBLE-

TREBLE+

STB

DATA

L-OUT

NC

L-IN

L-LD1

L-LD2

L-A-GND

CS1

GND

NC

NC

NC

NC

CK

BASS+

BASS-

TC9482N
(EX: IC809)

SS

V

1

2

3

Ω

/

50k

TEP

91S

4

VR

5

6

7

8

9

L-ch7 to 91decoder

L-ch latch circuit

10

11

12

13

14

Shift register (24Bit)

Level shift circuit

VSS

1

2

3

Ladder resister

DD

V

28

Same

R-ch7 to 91decoder

R-ch latch circuit

VDD

16

Analog switch

as L-ch

GND

7

13 bit latch circuit

27

26

25

24

23

22

21

20

19

18

17

16

15

NC

R-OUT

NC

R-IN

R-LD1

R-LD2

R-A-GND

NC

CS2

NC

NC

STB

DATA

DATA

CK

9

8

Level shift

L-OUTA

L-INA

L-A-GNDA

L-OUTB

L-INB

L-A-GNDB

L-OUTC

L-INC

L-A-GNDC

GND

STB

10

Vss

NC

CS1

CK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Analog switch

Ladder resister

28

27

26

25

24

23

22

21

20

19

18

17

16

15

15

14

V

DD

TEST

R-OUTA

R-INA

R-A-GNDA

R-OUTB

R-INB

R-A-GNDB

R-OUTC

R-INC

R-A-GNDC

CS2

STB

DATA

BASS+

BASS-

COM

TREBLE-

TREBLE+

4

5

13

12

COM

TREBLE-

20 bit Shift register circuit

Analog switch

6

Ladder resister

13 bit latch circuit

Code
detect
circuit

Analog switch

Ladder resister

11

TREBLE+

23

BU4052BCF (AU:IC255,509,510)

AT49LV002T (AU:IC817)

TOP VIEW

Y

4

1

Y

0

X

2

Y

Y

2

2

2

Common

Y

3

Y

Y

3

4

5

Y

1

6

INH

7

EE

V

8

Vss

OUT/IN

Y

3

Y

1

INH

V

EE

OUT/IN

B

X

1

X

X

0

X

3

A

SN74AHC574PW
(AU: IC815, 816)

1

OE

2

1D

2D

3

4

3D

5

4D

5D

6

6D

7

8

7D

8D

9

10

GND

16

15

14

13

12

11

10

9

V

DD

X

2

X

1

Common

X

X

0

X

3

A

B

20

19

18

17

16

15

14

13

12

11

Vcc

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

CK

INH

L
L
L
L

H

X:Don't Care

FUNCTION TABLE

A B ON SWITCH

LLX

HL

LH
HH
XX

Y

00

XY

11

XY

22

XY

33

NONE

RESET

A16

A15
A12

A7
A6
A5
A4
A3
A2
A1
A0

I/O 0
I/O 1
I/O 2
GND

SN74HC151NS (EX:IC505,506)

logic symbol

1

CE

CLK

1D

2D

3D 3Q

4D

5D 5Q

6D 6Q

7D

8D 8Q

EN

11

C1

2

1D

3

417

5

615

714

8

912

19

1Q

18

2Q

16

13

Outputs

4Q

7Q

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Data

Inputs

Strobe

TOP VIEW

3

1

2

2

1

3

0

4

5

5

Y

W

6

7

GND

8

D2

D1

D0

Y

W

S

FUNCTION TABLE

C

VCC
WE

A17
A14

A13
A8
A9
A11
OE
A10
CE
I/O 7
I/O 6
I/O 5

I/O 4
I/O 3

D4

D5

D6

D7

A

B

Pin Name

A0 - A17

CE
OE

WE

RESET

I/O0 -I/O7

DC

16

Vcc

4

15

5

14

6

13

12

7

A

11

B

10

C

9

Data
Inputs

Data
Select

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Function

Addresses

Chip Enable

Output Enable

Write Enable

RESET

Data Inputs/Outputs

Don't Connect

BU4051BCF
(AU:IC251,252,504~507)

X

Channel

Common
OUT/IN

INHIBIT

4

1

X

6

IN/OUT

X

X

7

X

5

V

EE

Vss

4

2

6

3

OUT/IN

4

7

5

5

6

INH

7

V

EE

C

8

V

DD

16

X

2

15

2

X

1

14

1

13

X

0

0

X

3

12

3

A

11

A

10

B

B

9

C

SN74LV00APW
(AU: IC807)

1

GND

1A

1B

2

1Y

3

2A

4

2B

5

6

2Y

7

Vcc

14

4B

13

4A

12

4Y

11

3B

10

9

3A

3Y

8

TC74VHC123AF
(AU: IC801)

1A

1

1B

2

1CLR

3

Channel

IN/OUT

1Q

4

5

5

2Q

2Cex1

6

GND

7

8

2Rext/Cext

SN74LV14APW
(AU: IC809)

1

1A

2

1Y

2A

3

4

2Y

5

3A

3Y

6

GND

7

QQ

CLR
QQ

CLR

74LVX157
(AU: IC804)

16

15

14

13

12

11

10

9

Vcc

1Rex/Cext

1Cext

1Q

2Q

2CLR

2B

2A

SE

LECT

GND

1

1A

2

3

1B

1Y

4

5

5

2A

2B

6

7

2Y

8

SEL

16

15

14

13

12

11

10

Vcc

ST

4A

4B

4Y

3A

3B

9

3Y

SN74LV4040APW
(AU: IC813)

OL

Outputs

OG

GND

1

OF

OE

OD

OC

OB

OL

2

OF

3

OE

4

OG

5

OD

6

OC

7

8

CLR

OB

CLK

OA

Vcc

14

13

6A

6Y

12

5A

11

5Y

10

9

4A

4Y

8

Vcc

16

OK

15

OK

OJ

14

OJ

13

OH

OH

OI

Outputs

OI

12

CLR

11

10

CLK

Outputs

9

OA

TC74HCU04AF
(EX:IC504)

1

1A

2

1Y

3

2A

4

2Y

5

3A

6

3Y

GND

7

TC74HCT7007AF
(AU:IC823)

1A

1

1Y

2

2A

3

2Y

4

3A

5

3Y

6

7

GND

14

Vcc

13

6A

6Y

12

11

5A

5Y

10

4A

9

8

4Y

14

Vcc

13

6A

6Y

12

11

5A

5Y

10

4A

9

8

4Y

24

BA033T (AU: IC819)

)

KIA7805API (RE: IC901, 902, 907)
KIA7806API (PO: IC501)
KIA7812API (RE: IC905)

FRONT

VIEW

KIA7905PI (RE: IC909)
KIA7912PI (RE: IC906)

FRONT

VIEW

BA15218F (AU: IC112)
BA4510F (AU: IC811, 812)
NJM2068MD (EX: IC103, 301, 302,
308~310, 701, 801~804)
(AU: IC109, 701, 721, 741, 761
TK15420MTL (AU: IC253, 254, 257,
501~503, 508, 511)

GND

Input

Output

NJM2391DL1 (AU: IC824)

TOP VIEW

GND

IN OUT



OPTICAL

INPUT
GP1FA551RZ (EX:IC501~503)

FRONT VIEW

GND

Input

Output

LC72720NM (CO: IC105)
Europe Model Only

TOP VIEW

V

REF

1

MPXIN

2

3

V

dda

V

ssa

4

5

FLOUT

CIN

6

T1

7

T2

8

XOUT

9

10

11

12

T3(RDCL)

T4(RDDA)

T5(RSFT)

OUTPUT
GP1FA551TZ(EX:IC707)

FRONT VIEW

24

SYR

23

CE

DI

22

CL

21

DO

20

RDS-ID

19

SYNC

18

T7(OORREC/ARI-ID/BEO)

17

16

T6(ERROR/57K/BEI)

15

V

ssd

14

V

ddd

XIN

13

A OUTPUT

A –INPUT

A +INPUT

1

1

2

3

V

4

V

8

B OUTPUT

7

2

B –INPUT

6

B +INPUT

5



IC PROTECTOR

ICP-N15 (PO: IC502)

FRONT VIEW

Vcc

Vout

GND



OTHERS

GP1U27X (Remote Control Sensor)
(CO: IC102)

TOP VIEW

Head
Amp

Vcc

Vout

GND

V

CC

V

OUT

GND

Limiter
Amp

BPF

Vin

Vcc

GND

Detector &
Comparator

LED

Integrator

DRIVE

GND

IC

Hysteresis
Comparator

Vcc

Vout

V

CC

Vin

GND

25



TRANSISTORS

B

2SA1505Y
2SC2412K (S)
2SD601A
KTC2875B

B

E

2SA970 (BL)
2SA988 (E/F)
2SA933S (S)
2SA1145 (O/Y)
2SC1740S (S)
2SC2705 (O/Y)

FRONT

VIEW

C

E

2SC3311A
2SD2144STPU
KTA1266 (GR)
KTC2874B
2SC/KTC3200(BL)

DTA114EK

DTC114ES
DTA114TK
DTA144EK
DTC114EK

FRONT

VIEW

DTC143EK
DTC144EK
DTC323TK

B

TOP

C

VIEW

E

MP15P MN15N

FRONT

VIEW

D

C

E

R:70W Typ.

B

E

DTA114TK
DTA114EK
DTA144EK

DTA114EK

DTA114TK

DTA144EK

RE:0.22W Typ.

S

PNP Type

R1

10kohm

10kohm

47kohm

FRONT

10kohm

47kohm

VIEW

R2

-

TOP

VIEW

2SB/KTB778 (R/O) 2SK771

C

FRONT

VIEW

BCE

S

TOP

G

VIEW

D

DTC114EK
DTC114ES
DTC143EK
DTC144EK
DTC323TK

C

B

NPN Type

R1

DTC114EK

DTC114ES

DTC143EK

DTC144EK

DTC323TK 2.2kohm

10kohm

10kohm

4.7kohm

47kohm

R2

10kohm

10kohm

4.7kohm

47kohm

-

ES CDB



DIODES (included LED)

1SR35-400A
1SS270A
RB721Q-40

B

HZS3C-2
HZS5C-1
HZS6A-1
HZS6A-2
HZS7B-2
HZS9B-1
HZS33-2
MTZJ18A

C

DAN202K

2

1

TOP

VIEW

3

1: Anode
2: Anode
3: Cathode

BDCSE

1

3

DAP202K

2

D

2

1

TOP

VIEW

3

1: Cathode
2: Cathode
3: Anode

R:70W Typ.

1

3

2

RE:0.22W Typ.

E

S4VB20
S4VB20F

S

TOP VIEW

SEL1210S (Red)
SEL1410E (Green)

TOP VIEW

26



FL DISPLAY

CM1690C (CO: FL101)

1

STEREO

TUNED

RDS

CH

G16

TUNED

RDS

CH

G15

STEREO

AUTO

Pin Assignment

PIN NO.

CONNECTION

PIN NO.

CONNECTION

PIN NO.

CONNECTION

58

S15

S12

S10

S11

S9

G1

S5

S4

S6

S7

S1

S2

S3

AUTO

REC

MULTI

PHONO

VCR

CD

AUX

3

V.AUX

DVDMDVDP

TAPE

TUNER

−

1

−2−

TV

−

1

DBS

−

2

PRO LOGIC
DIGITAL

DIGITAL ANALOG

S38

S14

S13

F2F1

G2~G16

G12

G10

G13

REC

PHONO

MULTI

VCR

G14 G11 G8

CD

−

1

G9

TUNER

−2−

12345

F1 F1 S1 S2 S3

21 22

23 24 25

S4
26

G7

AUX

V.AUX

3

78910111213141516171819

6

G5 G2 G1

G6

DVD

MD

G4

VDP

TAPE

G3
TV

−

DBS

−

2

1

PRO LOGIC
DIGITAL

DIGITAL ANALOG

S1

S6

S11

S16

S21

S26

S31

S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15

27 28 29 30 31 32 33 34

35 36 37 38 39 40

S7

S8

S12

S13

S18

S17

S22

S23

S28

S27

S32

S33

S16 S17

S9

S14

S19

S24

S29

S34

S5

S10

S15

S20

S25

S30

S35

20

S18

S4

S2

S3

S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38

41 42 43 44 45

47 48 49 50 51 52 53 54 55 56 57

46

58

G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 F2 F2

F1,F2 : Filament
G1~G16 : Grid

S1~S38 : Anode

Anode & Grid Assignment

G1

G2~G16

S36
S37
S38

S1
S2
S3
S4
S5
S6
S7

S1
S2
S3
S4
S5
S6

S7
S8
S9

S9

G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15

/

−2

S38

DBS

TV

−1

S1
S2

S3
S4
S5
S6
S7
S8
S9

VDP

TAPE

S10
S11

S12
S13
S14

S15
S16
S17

S18

/(DVD)

/(MD)

G1
S10
S11

S12

S13
S14

S15

DIGITAL

PRO LOGIC

DVD

MD

V.AUX

G2~G16

AUX

S10

S11

S12
S13
S14
S15
S16
S17
S18

S19
S20

S21
S22
S23
S24
S25

S26

S27

TUNER

−2

−3

CD

−1

G1

G2~G16

S19
S20
S21
S22
S23
S24

S25
S26
S27

PHONO

VCR

S28
S29
S30
S31
S32
S33
S34
S35

REC

MULTI

G1

STEREO

AUTO

G2~G16

S28
S29
S30
S31

S32
S33

S34
S35

G16

TUNED

RDS

CH

27

PRINTED WIRING BOARDS

1

1U-3368 POWER P.W.B. Ass'y

2

3

4

5

76

8

13

7

4

3

1

1

113

12

13

12

12

12

A

B

3

1

110

17191515151515

C

COMPONENT SIDE

D

E

28

1

1U-3369 EXT IN P.W.B. Ass'y

2

11

3

4

5

76

8

A

1

13

1

1

16 9

18

12

1

11

1

10

1

1

12

1

4

1

15

1

9

14 1

15 28

10

B

C

D

42 22

14 1

COMPONENT SIDE

121

15 28

E

29