Dell LATITUDE 3550 ZAL50, LATITUDE 3550 ZAL60 Schematics

5

4

3

2

1

MODEL NAME : Marble Falls/ Discrete PROJECT CODE : ZAL50, ZAL60 PCB NO : LA-B072P

D D

ZZZ

R1@ZZZ

R1@

UC1

UV17

VRAM

X76_HYX@

UV17

UV18

VRAM

X76_HYX@

UV18

UV19

VRAM

X76_HYX@

UV19

UV20

VRAM

X76_HYX@

UV20

RV59

20K

X76_HYX@

RV59

ZZZ

X7653531L01

X76_HYX_R@

ZZZ

X7653531L51

PCB 14B LA-B072P REV0 M/B

CPU

VRAM

X76_MIC@

UV17

VRAM

X76_SAM@

VRAM

X76_MIC@

UV18

VRAM

X76_SAM@

VRAM

X76_MIC@

UV19

VRAM

X76_SAM@

VRAM

X76_MIC@

UV20

VRAM

X76_SAM@

24.9K

X76_MIC@

RV59

30.1K

X76_SAM@

X7653531L51

X76_MIC_R@

ZZZ

X7653531L02

X76_SAM_R@

For Post RTS

C C

Dell / Compal Confidential

Schematic Document

Intel Broadwell ULT

B B

Marble Falls 14"/15" Value DIS

2013-10-03 Rev: 0.1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

4019RU

1

of

154Monday, April 07, 2014

of

154Monday, April 07, 2014

of

154Monday, April 07, 2014

A

5

4

3

2

1

D D

eDP Conn.

Page 21

HDMI Conn.

Page 19

DDR3L 256MX16 2GB

Page 51,52

CRT Conn.

Page 20

n

VIDIA

N15S-GM GB2B-64

DP to CRT IT6513FN

PCI-E X4

Page 20

BGA 595

C C

Page 46~50

PCI-E

x1 x1

NGFF 2230 WiFi/BT4.0 RTL8111GUS-CG

SATA HDD Conn.

B B

Port 4 Port 3

Ethernet

Port 0

Page 26

SATA Rediver

Page 22Page 25

Page 26

eDP

DDI

SATA3.0

Intel Broadwell ULT-U Processor BGA 1168

Memory Bus (DDR3L)

Dual Channel

1.35V DDR3L 1600 MHz

USB 3.0

USB2.0

Port 3

Port 4

Port 7

Port 5

Port 6

DDRIIIL-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

8GB Max

Fingerprint

NGFF WiFi/BT4.0

Digital Camera (With Digital MIC)

Touch Screen

Card Reader RTS5176E

Page 17, 18

Port 1

Port 0

Port 2

Port 1

Port 2

Page 26

Page 25

Page 21

Page 27

USB 3.0 Conn. 1

USB 3.0 Conn. 2

USB 2.0 Conn. 3

Digital Mic.

Page 24

Page 27

LS-B071P

IOR/B

USB2.0 Conn

USB2.0 Port 2

Card Reader

USB2.0 Port 6

SPI ROM

8MB

Page 9

HD Audio

SPI

Page 6~16

LPC Bus

Audio Codec ALC3234

Page 23

Headphone Jack / Mic. Jack combo

Int. Speaker R / L

Page 23

33MHz

LS-B072P

A A

LED/B

LED *2

Lid Switch

5

SMSC SIO ECE1099

4

BC Bus

Page 28 Page 29

SMSC KBC MEC5085

BC Bus

PS/2

Touch Pad

Page 27

KB control ECE1117

Page 30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/08/01 2014/07/31

KBD

Page 30

KB BKL

Page 30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

245Monday, April 07, 2014

of

A

5

4

3

2

1

D D

IOR /B

C C

JUSB3

JREAD

16pin

3in1

B B

JIO1

pin 1

FFC

JIO

pin 1

LidSwitch

LED2

JLED1

LED1

pin 1

JLED

8pin

pin 1

M

/

B

LED /B

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

of

354Monday, April 07, 2014

A

5

Board ID Table

Phase ID

RE79 CE54

240K 4700p X00 130K 4700p

D D

4700p 4700p

33K

4700p

8.2K 4700p

4.3K

2K

4700p

1K

4700p

BOARD_IDrisetimeismeasuredfrom5%~68%.

Config ID

RE89 RE90 Config

Pop

De-Pop Pop

De-Pop

REV

X01 X0262K X03 A00

Discrete UMA

4

3

2

1

USB3.0 Port1 Port2

USB connector 1

USB connector 2 Port3 Port4

USB2.0 Port0 Port1 Port2 Port3

USB connector 1 USB connector 2 USB connector 3 (IO/B) Finger print

SMBUS Control Table

Touch

C C

CHARGER_SMBCLK CHARGER_SMBDAT

PBAT_SMBCLK PBAT_SMBDAT

GPU_SMBDAT SML1_SMBCLK

SML1_SMBDATA SMBCLK

SMBDATA SML0CLK

SML0DATA SML1CLK

SML1DATA

B B

SOURCE

MEC5085

MEC5085GPU_SMBCLK

MEC5085

ULT

BATT

V

Charger

DDR3L

V

XDP

V

WLAN NGFF

pad

VV

VGA

ULT

V

Link

Port4 Port5 Port6 Port7

Lane 1 Lane 2 Lane 3 Lane 4 Lane 5

NGFF (BT + WLAN) Touch Screen Panel Card Reader Camera

PCI EXPRESS

10/100/1000 LAN NGFF (BT + WLAN) PEG (N15S)

Lane 6

CLOCK SIGNAL

SATA

CLKOUT_PCIE0

HDDSATA0

CLKOUT_PCIE1

SATA1

CLKOUT_PCIE2 CLKOUT_PCIE3 CLKOUT_PCIE4

10/100/1000 LAN NGFF (BT + WLAN)

Symbol Note :

: means Digital Ground

SATA2 SATA3

DDI

CLKOUT_PCIE5

A A

5

: means Analog Ground

4

DDI1 DDI2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

HDMI DP to CRT

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

A

of

454Monday, April 07, 2014

5

4

3

2

1

D D

SMBUS Address [0x9a]

AP2 AH1

MEM_SMBCLK MEM_SMBDATA

SML0CLK

MCP

C C

AN1 AK1

SML0DATA

SML1_SMBCLK SML1_SMBDATA

79

SML1_SMBCLK

80

SML1_SMBDATA

2.2K

1K

2.2K

+3.3V_ALW_PCH

N-MOS N-MOS

+3.3V_ALW_PCH

2.2K

DDR_XDP_WLAN_TP_SMBCLK DDR_XDP_WLAN_TP_SMBDAT

+3VS

0 ohm 0 ohm

DDR_XDP_SMBCLK_R1 DDR_XDP_SMBDAT_R1

202

DIMMA

200

202

DIMMB

200

53 51

JXDP1

SMBUS Address [A0]

SMBUS Address [A4]

SMBUS Address [TBD]

2.2K

77

B B

MEC 5085

CHARGER_SMBCLK

78

CHARGER_SMBDAT

+3VALW_5085

0 ohm 0 ohm

SCL SDA

11 10

POWERPU700 Charger

SMBUS Address [0x12]

2.2K

+3VALW_5085

100 ohm 100 ohm

3 1

4

PD1

Z4304

65

Z4305

3

PBATT1

SMBUS Address [0x16]

BATT CONN

PBAT_SMBCLK PBAT_SMBDAT

2.2K

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

554Monday, April 07, 2014

of

A

5

4

3

2

1

H_VCCST_PWRGD[13]

SIO_PWRBTN#[10,29]

CPU_PWR_DEBUG#[13]

SYS_PWROK[10,29]

DDR_XDP_WLAN_TP_SMBCLK[9,17,18]

HASWELL_MCP_E

+1.05VS

1

2

Place near JXDP1

+3VALW_PCH

1 OF 19

JTAG

2 OF 19

0.1U_0402_10V7K

1

CC14

@

CC14

@

CC15

@

CC15

@

2

RC5needtoclosetoJCPU1

1 2

RC114 1K_0402_5%XDP@RC114 1K_0402_5%XDP@

H_CPUPWRGD H_VCCST_PWRGD_XDP

SYS_PWROK

XDP@

RC64

RC64 1K_0402_5%

1K_0402_5%

1 2

SYS_PWROK_XDP

1

@

CC16

0.1U_0402_10V7K

2

Place near JXDP1.47

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

PROC_TRST

3

Rev1p2

PRDY PREQ

PROC_TCK

PROC_TMS

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

Rev1p2

1 2

RC48 1K_0402_5%@RC48 1K_0402_5%@

1 2

RC49 0_0402_1%@RC49 0_0402_1%@

1 2

RC50 0_0402_1%@RC50 0_0402_1%@

1 2

RC52 0_0402_1%@RC52 0_0402_1%@

1 2

RC53 0_0402_1%@RC53 0_0402_1%@

1 2

RC54 0_0402_1%@RC54 0_0402_1%@

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20

EDP_COMP

A43

EDP_DISP_UTIL

RC72 0_0402_5%@RC72 0_0402_5%@

J62

XDP_PRDY#

K62

XDP_PREQ#

E60

XDP_TCLK

E61

XDP_TMS

E59

XDP_TRST#

F63

XDP_TDI

F62

XDP_TDO XDP_TDI

J60

XDP_OBS0_R

H60

XDP_OBS1_R

H61 H62 K59 H63 K60 J61

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CFG0[16] CFG1[16]

CFG2[16] CFG3[16]

CFG4[16] CFG5[16]

CFG6[16] CFG7[16]

1 2

EDP_TX0# [21] EDP_TX0 [21] EDP_TX1# [21] EDP_TX1 [21]

T111@ T111@ T112@ T112@ T113@ T113@ T114@ T114@ T115@ T115@ T116@ T116@

XDP_PREQ# XDP_PRDY#

XDP_OBS0_R XDP_OBS1_R

CFD_PWRBTN#_XDP CPU_PWR_DEBUG#_R

SYS_PWROK_XDP DDR_XDP_SMBDAT_R1

DDR_XDP_SMBCLK_R1

PCH_JTAG_TCK XDP_TCLK

EDP_AUX# [21] EDP_AUX [21]

2013/08/01 2014/07/31

CFG3

JXDP

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

CONN@

COMPENSATION PU FOR eDP

EDP_BIA_PWM [10,21]

CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.

Compal Secret Data

Deciphered Date

+1.05VS+1.05VS

2

GND1

4

OBSFN_C0

6

OBSFN_C1

8

GND3

10

OBSDATA_C0

12

OBSDATA_C1

14

GND5

16

OBSDATA_C2

18

OBSDATA_C3

20

GND7

22

OBSFN_D0

24

OBSFN_D1

26

GND9

28

OBSDATA_D0

30

OBSDATA_D1

32

GND11

34

OBSDATA_D2

36

OBSDATA_D3

38

GND13

VCC_OBS_CD DBR#/HOOK7

GND15 TRST#

TMS

GND17

40 42 44 46

XDP_RST#_R

48

XDP_DBRESET#

50 52

TDO_XDP

TD0

54

TRST#_XDP

56

TDI_XDP

TDI

58

TMS_XDP

60

CFG3_R

XDP_DBRESET#

+VCCIOA_OUT

12

RC7124.9_0402_1% RC7124.9_0402_1%

ITPCLK/HOOK4

ITPCLK#/HOOK5 RESET#/HOOK6

2

CFG17 [16] CFG16 [16]

CFG8 [16] CFG9 [16]

CFG10 [16] CFG11 [16]

CFG19 [16] CFG18 [16]

CFG12 [16] CFG13 [16]

CFG14 [16] CFG15 [16]

12

XDP@

RC51

RC51 1K_0402_5%

1K_0402_5%

1 2

XDP@

RC56 1K_0402_5%

CFG3

XDP_DBRESET# [10]

PU/PD for JTAG signals

XDP_TMS XDP_PREQ#

TDO_XDP

XDP_TDO XDP_TCLK

XDP_TRST#

51_0402_5%

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

RC362

RC362 1K_0402_1%

1K_0402_1%

1 2

1 8 2 7 3 6 4 5

RP44 51_8P4R_5%

51_8P4R_5%

1 8 2 7 3 6 4 5

RP45

RP45 51_8P4R_5%

51_8P4R_5%

1

12

XDP@

CC17

0.1U_0402_10V7K

@RP44

@

12

PCH_PLTRST#_EC [10,22,25,29]

+3VS

+1.05VS

RC129@

654Monday, April 07, 2014

A

of

+3VS

CC13

12

XDP@

PCH_JTAG_TDO[8]

D D

PCH_JTAG_TDI[8]

C C

B B

A A

1 2

@

RC44

X02.08

PCH_JTAG_TMS[8]

TDI_XDP TDI_XDP_R

0_0402_5%RC44

0_0402_5%

RUNPWROK[29]

PCH_JTAG_RST#[8]

+1.05VS

RC58 49.9_0402_1%@RC58 49.9_0402_1%@ RC60 62_0402_5%RC60 62_0402_5%

H_PROCHOT#[29,38,41]

22P_0402_50V8J

DDR3 COMPENSATION SIGNALS

CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil

5

XDP@

0.1U_0402_10V7K

1 2

@

RC43

RC45

RC46

0.1U_0402_10V7K

1 2 1 2

TDO_XDP

0_0402_5%RC43

0_0402_5%

RUNPWROK

1 2

@

0_0402_5%RC45

0_0402_5%

RUNPWROK

1 2

@

TMS_XDP

0_0402_5%RC46

0_0402_5%

RUNPWROK TRST#_XDP XDP_TRST#

RUNPWROK

1

CC29

ESD@CC29

ESD@

2

Place CC29 close to UC4

PCH_JTAG_JTAGX[8]

PCH_JTAG_TCK[8]

H_CATERR# H_PROCHOT#

H_PROCHOT# H_PROCHOT#_R

1

EMI@

12

CA26

2

12

RC68200_0402_1% RC68200_0402_1%

12

RC69121_0402_1% RC69121_0402_1%

12

RC70100_0402_1% RC70100_0402_1%

UC4

XDP@UC4

XDP@

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

74CBTLV3126BQ_DHVQFN14_2P5X3

reference Shark Bay ULT Validation Customer Debug Port Implementation Requirement Rev 1.0

GND PAD

3

1B

6

2B

8

3B

11

4B

7

GND

15

X02.08

12

@

PCH_JTAG_RST#

0_0402_5% RC57

0_0402_5%

0_0402_5% RC59

0_0402_5%

PCH_JTAG_TDO TDI_XDP_R

RC66

RC66 10K_0402_5%

10K_0402_5%

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

@

DDI1_LANE_N0[19] DDI1_LANE_P0[19] DDI1_LANE_N1[19] DDI1_LANE_P1[19] DDI1_LANE_N2[19] DDI1_LANE_P2[19] DDI1_LANE_N3[19] DDI1_LANE_P3[19]

DDI2_LANE_N0[20] DDI2_LANE_P0[20] DDI2_LANE_N1[20] DDI2_LANE_P1[20]

PECI_EC[29]

1 2

RC67 56_0402_5%RC67 56_0402_5%

1

CC27

CC27 100P_0402_50V8J

100P_0402_50V8J

ESD@

2

ESD solution

DDR3_DRAMRST#_CPU[17]

DDR_PG_CTRL[17]

XDP_TRST#

RC57

12

XDP_TCLK

RC59

12

TDO_XDP

RC620_0402_5% @ RC620_0402_5% @

12

RC630_0402_5% @ RC630_0402_5% @

12

XDP_TCLK

RC650_0402_5% @ RC650_0402_5% @

CC35

0.047U_0402_16V4Z

Place CC35 on BOT

4

DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3

DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1

H_CATERR#

H_CPUPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

1

2

@

XDP_TDOPCH_JTAG_TDO

XDP_TDI

XDP_TMS

C54 C55 B58 C58 B55 A55 A57 B57

C51 C50 C53 B54 C49 B50 A53 B53

D61 K61 N62

K63

C61

AU60 AV60 AU61 AV15 AV61

UC1A

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

@

UC1B

PROC_DETECT CATERR PECI

PROCHOT

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

@

DDR_XDP_WLAN_TP_SMBDAT[9,17,18]

DDI EDP

MISC

THERMAL

PWR

DDR3

5

4

3

2

1

InterleavedMemory

HASWELL_MCP_E

UC1D

AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29

AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25

AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22

AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18

AL18 AK20 AM20 AR18 AP18

UC1D

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

HASWELL_MCP_E

UC1C

AH63 AH62

AK63

AK62 AH61 AH60

AK61

AK60 AM63 AM62

AP63

AP62 AM61 AM60

AP61

AP60

AP58 AR58 AM57

AK57

AL58

AK58 AR57 AN57

AP55 AR55 AM54

AK54

AL55

AK55 AR54 AN54

AY58 AW58

AY56 AW56

AV58 AU58

AV56 AU56

AY54 AW54

AY52 AW52

AV54 AU54

AV52 AU52

AK40

AK42 AM43 AM45

AK45

AK43 AM40 AM42 AM46

AK46 AM49

AK49 AM48

AK48 AM51

AK51

UC1C

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

D D

DDR_A_D[0..15][17]

DDR_B_D[0..15][18]

DDR_A_D[16..31][17]

C C

DDR_B_D[16..31][18]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

HASWELL_MCP_E

DDR CHANNEL A

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1 SA_CKE0

SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS SA_BA0

SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32 AY34

AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

DDR_A_RAS# DDR_A_WE# DDR_A_CAS#

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_B_DQS#0 DDR_B_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_B_DQS#2 DDR_B_DQS#3

DDR_A_DQS0 DDR_A_DQS1 DDR_B_DQS0 DDR_B_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_B_DQS2 DDR_B_DQS3

M_CLK_DDR#0 [17] M_CLK_DDR0 [17] M_CLK_DDR#1 [17] M_CLK_DDR1 [17]

DDR_CKE0_DIMMA [17] DDR_CKE1_DIMMA [17]

DDR_CS0_DIMMA# [17] DDR_CS1_DIMMA# [17]

DDR_A_RAS# [17] DDR_A_WE# [17] DDR_A_CAS# [17]

DDR_A_BS0 [17] DDR_A_BS1 [17] DDR_A_BS2 [17]

DDR_A_MA[0..15] [17]

DDR_A_DQS#[0..1] [17] DDR_B_DQS#[0..1] [18] DDR_A_DQS#[2..3] [17] DDR_B_DQS#[2..3] [18]

DDR_A_DQS[0..1] [17] DDR_B_DQS[0..1] [18] DDR_A_DQS[2..3] [17] DDR_B_DQS[2..3] [18]

+SM_VREF_CA +SM_VREF_DQ0 +SM_VREF_DQ1

DDR_A_D[32..47][17]

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46

DDR_B_D[32..47][18]

DDR_A_D[48..63][17]

DDR_B_D[48..63][18]

DDR_A_D47 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

HASWELL_MCP_E

DDR CHANNEL B

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32 AM35

AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3

DDR_CKE2_DIMMB DDR_CKE3_DIMMB

DDR_CS2_DIMMB# DDR_CS3_DIMMB#

DDR_B_RAS# DDR_B_WE# DDR_B_CAS#

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_A_DQS#4 DDR_A_DQS#5 DDR_B_DQS#4 DDR_B_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_B_DQS#6 DDR_B_DQS#7

DDR_A_DQS4 DDR_A_DQS5 DDR_B_DQS4 DDR_B_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_B_DQS6 DDR_B_DQS7

M_CLK_DDR#2 [18] M_CLK_DDR2 [18] M_CLK_DDR#3 [18] M_CLK_DDR3 [18]

DDR_CKE2_DIMMB [18] DDR_CKE3_DIMMB [18]

DDR_CS2_DIMMB# [18] DDR_CS3_DIMMB# [18]

DDR_B_RAS# [18] DDR_B_WE# [18] DDR_B_CAS# [18]

DDR_B_BS0 [18] DDR_B_BS1 [18] DDR_B_BS2 [18]

DDR_B_MA[0..15] [18]

DDR_A_DQS#[4..5] [17] DDR_B_DQS#[4..5] [18] DDR_A_DQS#[6..7] [17] DDR_B_DQS#[6..7] [18]

DDR_A_DQS[4..5] [17] DDR_B_DQS[4..5] [18] DDR_A_DQS[6..7] [17] DDR_B_DQS[6..7] [18]

B B

Rev1p2

3 OF 19

+1.35V

3 OF 19

12

RC14

1.82K_0402_1%

12

RC20

1.82K_0402_1%

1 2

RC17

2.2_0402_1%

@

A A

Rev1p2

+1.35V

12

RC15

1.82K_0402_1%

+SM_VREF_CA +SM_VREF_DQ1

1

CC8

0.022U_0402_16V7K

2

change 22nF

12

RC23

24.9_0402_1%

1.82K_0402_1%

12

RC21

1.82K_0402_1%

1 2

RC18

2.2_0402_1%

1

2

12

confirm by intel request PDG P141

@

+1.35V

12

RC16

1.82K_0402_1%

+SM_VREF_DQ0_DIMM1+SM_VREF_CA_DIMM +SM_VREF_DQ1_DIMM2

CC9

0.022U_0402_16V7K

change 22nF change 22nF

RC24

24.9_0402_1%

1.82K_0402_1%

12

RC22

1.82K_0402_1%

1 2

RC19

2.2_0402_1%

+SM_VREF_DQ0

1

2

12

4 OF 19

CC10

0.022U_0402_16V7K

RC25

24.9_0402_1%

Rev1p2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

754Monday, April 07, 2014

of

A

5

4

3

2

1

ServiceModeSwitch: AddaswitchtoME_FWPsignaltounlocktheMEregionand allowtheentireregionoftheSPIflashtobeupdatedusingFPT.

+3VALW_PCH

12

RC9

RC9 1K_0402_5%

1K_0402_5%

ME_FWP_EC[29]

ME_FWPPCHhasinternal20KPD.

FLASHDESCRIPTORSECURITYOVERRIDE

HIGH→DISABLEME(MEcanupdate)‐‐>Pin1&Pin2short LOW→ENABLEME(DEFAULT)‐‐>Pin2&Pin3short

HASWELL_MCP_E

RTC

JTAG

5 OF 19

ME_EN

SATAAUDIO

SW3

1 2 3

4

G

5

G

SATA_RN0/PERN6_L3

SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2

SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1

SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

RSVD RSVD

SATA_RCOMP

SATALED

Rev1p2

SSAL120100_3P

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1 U1 V6 AC1

A12 L11 K10 C12 U3

PCH_GPIO34 HDD_DET# PCH_GPIO36 PCH_GPIO37

SATA_IREF

SATA_RCOMP SATA_ACT#

X02.13

SATA_PRX_DTX_N0_C [26]

SATA_PRX_DTX_P0_C [26] SATA_PTX_DRX_N0_C [26] SATA_PTX_DRX_P0_C [26]

PCH_GPIO36 [10]

RC126 0_0603_5%@RC126 0_0603_5%@

RC131 3.01K_0402_1%RC131 3.01K_0402_1%

HDD_DET# [26]

1 2

+1.05VS_ASATA3PLL

X02.08

within 500 mils

SATA HDD

X02.04

1 8

HDD_DET#

2 7

SATA_ACT#

3 6

PCH_GPIO37

4 5

PCH_GPIO34

RP37

RP37 10K_8P4R_5%

10K_8P4R_5%

SATA Impedance Compensation

CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins. reference FFRD sch 0.5

+3VS

+CHGRTC

CC1

15P_0402_50V8J

1 2

ESR MAX=50k ohm

CC2

15P_0402_50V8J

1 2

2

PCH_JTAG_JTAGXPCH_JTAG_TDI

PCH_JTAG_TCK

+RTCBATT

3

1

CC26

CC26 1U_0603_10V6K

1U_0603_10V6K

2

RC10

RC10 1K_0402_5%

1K_0402_5%

1 2

W=20mils

2

DC1

DC1 BAT54CW_SOT323-3

BAT54CW_SOT323-3

12

YC1

32.768KHZ_12.5PF_9H03220008

+RTCVCC

X02.03

PCH_RTCRST#[10]

PCH_AZ_CODEC_SDIN0[23]

+RTCBATT

+CHGRTC

1 2

RC8 1K_0402_5%RC8 1K_0402_5%

PCH_JTAG_RST#[6]

PCH_JTAG_TCK[6] PCH_JTAG_TDI[6] PCH_JTAG_TDO[6] PCH_JTAG_TMS[6]

PCH_JTAG_JTAGX[6]

1 2 3 4

ACES_50271-0020N-001

PJP12

2

JUMP_43X39

@

PCH_RTCX1

12

RC4

RC4 10M_0402_5%

10M_0402_5%

PCH_RTCX2 INTRUDER# PCH_INTVRMEN SRTCRST# PCH_RTCRST#

PCH_AZ_BITCLK PCH_AZ_SYNC PCH_AZ_RST#

PCH_AZ_SDOUTME_EN

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_JTAG_JTAGX

112

JRTC

1 2 GND GND

CONN@

+3VLP

UC1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

@

+RTCVCC

12

RC1

D D

INTVRMEN‐INTEGRATEDSUS1.05VVRM ENABLE High‐EnableInternalVRs Low‐EnableExternalVRs

C C

+1.05VS

B B

RC1 330K_0402_1%

330K_0402_1%

PCH_INTVRMEN

12

@

RC2

RC2 330K_0402_1%

330K_0402_1%

+RTCVCC

CMOS1

Shunt ClearCMOS

Open

CMOSsetting

KeepCMOS

1 2

CC3 1U_0402_6.3V6KCC3 1U_0402_6.3V6K

1 8 2 7

PCH_JTAG_TDO

3 6

PCH_JTAG_TMS

4 5

RP48

RP48 51_8P4R_5%

51_8P4R_5%

RTC Battery

W=20mils

1 2

RC7 1M_0402_5%RC7 1M_0402_5%

1 2 1 2

RC5 20K_0402_5%RC5 20K_0402_5% RC6 20K_0402_5%RC6 20K_0402_5%

1

2

@

CMOS1 SHORT PADS~D

1 2

1U_0402_6.3V6K

CC4

CMOS place near DIMM

+1.05VS

12

@

RC130 1K_0402_1%

RC135 51_0402_1%

12

@

HDA for Codec

1 2

EMI@

1

CC5

CC5 27P_0402_50V8J

27P_0402_50V8J

2

R2356 33_0402_5%EMI@ R2356 33_0402_5%EMI@

1 2

R2357 33_0402_5%EMI@ R2357 33_0402_5%EMI@

1 2

R2358 33_0402_5%EMI@ R2358 33_0402_5%EMI@

1 2

R2359 33_0402_5%EMI@ R2359 33_0402_5%EMI@

PCH_AZ_CODEC_SDOUT[23] PCH_AZ_CODEC_SYNC[23]

PCH_AZ_CODEC_RST#[23]

PCH_AZ_CODEC_BITCLK[23]

A A

PCH_AZ_SDOUT PCH_AZ_SYNC PCH_AZ_RST# PCH_AZ_BITCLK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

854Monday, April 07, 2014

of

A

5

4

3

2

1

D D

UC1G

EMI@

C2326

C2326 68P_0402_50V8J

68P_0402_50V8J

1

2

+3VS

R2334 1K_0402_1%R2334 1K_0402_1% R2335 1K_0402_1%R2335 1K_0402_1%

PCH_SPI_MOSI_1 PCH_SPI_MISO_1 PCH_SPI_WP1# PCH_SPI_HOLD1#

1 2 1 2

LPC_LAD0[29] LPC_LAD1[29] LPC_LAD2[29] LPC_LAD3[29]

LPC_LFRAME#[29]

1 2

R2333 15_0402_1%R2333 15_0402_1%

RP39

1 8 2 7 3 6 4 5

15_0804_8P4R_5%

PCH_SPI_CLKPCH_SPI_CLK_R PCH_SPI_CS0#

PCH_SPI_MOSI PCH_SPI_MISO PCH_SPI_WP# PCH_SPI_HOLD#

AU14

AW12

AY12

AW11

AV12

LAD0 LAD1 LAD2 LAD3 LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

@

HASWELL_MCP_E

LPC

SPI C-LINK

7 OF 19

SMBUS

SMBALERT/GPIO11

SMBCLK

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML1ALERT/PCHHOT/GPIO73

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST

Rev1p2

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

PCH_SMB_ALERT# MEM_SMBCLK MEM_SMBDATA

SML0CLK SML0DATA

SML1_SMBCLK SML1_SMBDATA

10K_0402_5%

T97@ T97@ T98@ T98@ T99@ T99@

+3VALW_PCH

12

R2329

SML1_SMBCLK [29]

SML1_SMBDATA [29]

12

R2330

R2330 10K_0402_5%

10K_0402_5%

MEM_SMBCLK MEM_SMBDATA SML1_SMBCLK SML1_SMBDATAPCH_GPIO73

SML0CLK

R2527 1K_0402_1%R2527 1K_0402_1%

SML0DATA

R2528 1K_0402_1%R2528 1K_0402_1%

RP40

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

1 2 1 2

+3VALW_PCH

MEM Bus : DDR/XDP/WLAN/TP

R2331

2.2K_0402_5%

+3VS

12

R2332

2.2K_0402_5%

DDR_XDP_WLAN_TP_SMBCLK [6,17,18]

DDR_XDP_WLAN_TP_SMBDAT [6,17,18]

C C

SPI ROM ( 8MByte )

U2302

PCH_SPI_CS0# PCH_SPI_MISO_1 PCH_SPI_WP1#

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64FVSSIQ_SO8

/HOLD(IO3)

DI(IO0)

8

VCC

7 6

CLK

5

PN : SA000039A30 ,W25Q64FVSSIQ

+3VS

PCH_SPI_HOLD1# PCH_SPI_CLK_R PCH_SPI_MOSI_1

C2327

0.1U_0402_10V7K

1 2

MEM_SMBCLK

MEM_SMBDATA

+3VS

2

G

6 1

D

5

DMN66D0LDW-7_SOT363-6

3 4

SGD

QC1A

DMN66D0LDW-7_SOT363-6

S

QC1B

CC6

15P_0402_50V8J

CC7

15P_0402_50V8J

+PCH_VCCACLKPLL

12 12

12

CLK_PCI_MEC [29] CLK_PCI_LPDEBUG [29]

1M_0402_5%

RC12

B B

1 2

R2341 10K_0402_5%R2341 10K_0402_5%

+3VS

1 2

R2343 10K_0402_5%R2343 10K_0402_5%

+3VS

CLK_PCIE_GFX# CLK_PCIE_GFX GFXCLK_REQ#

+3VS

1 2

R2340 10K_0402_5%R2340 10K_0402_5%

1 2

R2342 10K_0402_5%R2342 10K_0402_5%

1 2

R2345 10K_0402_5%R2345 10K_0402_5%

1 2

R2344 10K_0402_5%R2344 10K_0402_5%

LAN ------->

WLAN(Mini Card)--->

A A

CLK_PCIE_LAN#[22] CLK_PCIE_LAN[22]

LAN_CLKREQ#[22] CLK_PCIE_WLAN#[25]

CLK_PCIE_WLAN[25] WLAN_CLKREQ#[25]

CLK_PCIE_GFX#[45] CLK_PCIE_GFX[45]

GFXCLK_REQ#[45]

UC1F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

@

HASWELL_MCP_E

CLOCK

SIGNALS

6 OF 19

XTAL24_IN

XTAL24_OUT

RSVD RSVD

DIFFCLK_BIASREF

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

Rev1p2

A25

XTAL24_IN

B25

XTAL24_OUT

K21 M21 C26

CLK_BIASREF

C35 C34 AK8 AL8

AN15 AP15

B35 A35

1 2

R2523 10K_0402_5%R2523 10K_0402_5%

1 2

R2524 10K_0402_5%R2524 10K_0402_5%

1 2

R2525 10K_0402_5%R2525 10K_0402_5%

1 2

R2526 10K_0402_5%R2526 10K_0402_5%

CLKOUT_LPC0 CLKOUT_LPC1

RC12

3

4

YC2

YC2 24MHZ_12PF_X3G024000DC1H

24MHZ_12PF_X3G024000DC1H

1

2

1 2

RC13

3.01K_0402_1%

1 2

R2336 22_0402_5%EMI@R2336 22_0402_5%EMI@ R2339 22_0402_5%

R2339 22_0402_5%

EMI@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

954Monday, April 07, 2014

of

A

5

4

3

2

1

JAPS

+3VALW_PCH

+3V_DSW

PCH_RTCRST#[8]

POWER_SW#_MB[27,29]

DSWODVREN‐ONDIEDSWVRENABLE

HIGH=ENABLED(DEFAULT)

LOW=DISABLED

PCH_DPWROK [29]

1

IN1

2

IN2

+3VS

5

VCC

GND

3

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

CC11

@CC11

@

1 2

0.1U_0402_10V7K

4

OUT

UC3

MC74VHC1G08DFT2G_SC70-5

AW7

DSWVRMEN

AV5

DPWROK

AJ5

WAKE

V5 AG4 AE6

SLP_S4 SLP_S3

SLP_A SLP_SUS SLP_LAN

Rev1p2

AP5

AJ6 AT4 AL5 AP4 AJ7

SLP_S5/GPIO63

12

R159

100K_0402_5%

DSWODVREN

PCH_PCIE_WAKE#_R

CLKRUN# SUS_STAT#/LPCPD# SUSCLK_R SIO_SLP_S5#

SIO_SLP_S4# SIO_SLP_S3# SIO_SLP_A# SIO_SLP_SUS#

PCH_PLTRST#_EC [6,22,25,29]

1 2

@

RC367 0_0402_1%

1 2

R2337 330K_0402_5%R2337 330K_0402_5%

1 2

R2338 330K_0402_5%@R2338 330K_0402_5%@

X02.08

1 2

RC97@0_0402_5%RC97@0_0402_5%

CLKRUN# [29]

1 2

RC107 @ 0_0402_5%RC107 @ 0_0402_5%

SIO_SLP_S5# [29]

SIO_SLP_S4# [29] SIO_SLP_S3# [29]

SIO_SLP_SUS# [29]

PLTRST_GPU# [45]

+RTCVCC

PCH_PCIE_WAKE# [28,29]

SUSCLK [25]

D D

1 2 1 2

1 2 1 2 1 2

1 2

@

1

2

CLKRUN#

ME_SUS_PWR_ACK SUSACK# SUS_STAT#/LPCPD#

PCH_BATLOW# AC_PRESENT

PCH_PCIE_WAKE#_R

PCH_RSMRST#_R

SYS_PWROK

CC31

0.047U_0402_16V4Z

Place CC31 on BOT

XDP_DBRESET#[6]

RC80@ 8.2K_0402_5%RC80@ 8.2K_0402_5%

SUSACK#[29] SYS_PWROK[6,29]

RESET_OUT#[13,29]

1

@CC31

@

2

PCH_RSMRST#[29] ME_SUS_PWR_ACK[29]

AC_PRESENT[29]

PCH_BATLOW# Need pull high to VCCDSW3_3 (If no deep Sx , connect to VCCSUS3_3)

12

SUSACK# SUSACK#_R

RC36 10K_0402_5%RC36 10K_0402_5% RC95@ 8.2K_0402_5%RC95@ 8.2K_0402_5%

+3VALW_PCH

RC27 10K_0402_5%RC27 10K_0402_5% RC28 10K_0402_5%RC28 10K_0402_5% RC29 10K_0402_5%@RC29 10K_0402_5%@

+3V_DSW

RC39 10K_0402_5%RC39 10K_0402_5% RC32 10K_0402_5%RC32 10K_0402_5%

C C

RC34 10K_0402_5%RC34 10K_0402_5%

RC92 10K_0402_5%

RESET_OUT#

CC34

@CC34

@

0.047U_0402_16V4Z

Place CC34 close to RP50.2&RP50.3

X02.08

1 2

RC78 @ 0_0402_5%RC78 @ 0_0402_5%

+3VS+3VS

1

B

2

ME_RESET#

A

X02.08

1 2

RC37 @ 0_0402_5%RC37 @ 0_0402_5%

1 2

RC40 @ 0_0402_5%RC40 @ 0_0402_5%

1 2

RC47 @ 0_0402_5%RC47 @ 0_0402_5%

1 2

RC55 @ 0_0402_5%RC55 @ 0_0402_5%

1 2

RC41 @ 0_0402_5%RC41 @ 0_0402_5%

1 2

RC42 @ 0_0402_5%RC42 @ 0_0402_5%

SIO_PWRBTN#[6,29]

SIO_SLP_WLAN#[28]

5

P

4

O

G

UC5@

74AHC1G09GW_TSSOP5

3

SYS_RESET#ME_RESET#

SYS_RESET# SYS_PWROK_R RESET_OUT#_R PM_APWROK_R PCH_PLTRST#

PCH_RSMRST#_R ME_SUS_PWR_ACK_R

AC_PRESENT PCH_BATLOW# SIO_SLP_S0#

Place CC33 close to UC3.1 & UC3.2

UC1H

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPWRDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

@

PCH_PLTRST#

CC33

ESD@CC33

ESD@

0.047U_0402_16V4Z

HASWELL_MCP_E

SYSTEM POWER MANAGEMENT

1

2

8 OF 19

SIO_SLP_S3# SIO_SLP_S5#

SIO_SLP_S4# SIO_SLP_A#

SYS_RESET# SIO_SLP_S0#

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

GND

20

GND

CONN@

ACES_50506-01841-P01

B B

+3VS

RP43

1

8

SIO_RCIN#

2

7

PCH_GPIO36

3

6

DGPU_PWROK

4 5

PCH_GPIO80

10K_8P4R_5%

1 2

@

1 2

@

1 2

@

1 2

EDP_BIA_PWM

DGPU_PWR_EN

DGPU_PWR_EN DGPU_CORE_EN

ENVDD_PCH

RC75 10K_0402_5%

RC370 10K_0402_5%RC370 10K_0402_5%

RC368 10K_0402_5%

RC368 10K_0402_5% RC369 10K_0402_5%

RC369 10K_0402_5%

A A

RC87 100K_0402_5%@RC87 100K_0402_5%@

SIO_RCIN# [11,29] PCH_GPIO36 [8]

EDP_BIA_PWM[6,21]

PANEL_BKLEN[21]

X02.08

1 2

RC81@0_0402_5%RC81@0_0402_5%

ENVDD_PCH[21,29]

PCH_GPIO77[11]

DGPU_PWROK[28,44,45]

PCH_GPIO79[11]

DGPU_PWR_EN[49]

EDP_BKLCTLEDP_BIA_PWM

ENVDD_PCH

PCH_GPIO77 DGPU_PWROK

PCH_GPIO80

T117 @T117 @

DGPU_PWR_EN DGPU_CORE_EN

B8 A9

C6

U6

P4 N4 N2

AD4

U7

L1

L3 R5

L4

UC1I

EDP_BKLCTL EDP_BKLEN EDP_VDDEN

PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

@

eDP SIDEBAND

GPIO

HASWELL_MCP_E

9 OF 19

DISPLAY

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

EDP_HPD

Rev1p2

B9 C9 D9 D11

C5 B6 B5 A6

C8 A8 D6

CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT

CPU_DPB_AUX# CPU_DPC_AUX# CPU_DPB_AUX CPU_DPC_AUX

DPC_HPD CPU_EDP_HPD

CPU_DPB_CTRLCLK [19]

CPU_DPB_CTRLDAT [19]

CPU_DPC_AUX# [20] CPU_DPC_AUX [20]

DPB_HPD [19] DPC_HPD [20] CPU_EDP_HPD [21]

CPU_DPB_CTRLDAT CPU_DPB_CTRLCLK CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT

CPU_DPB_AUX# CPU_DPB_AUX CPU_DPC_AUX CPU_DPC_AUX#

DPC_HPD

RC84 100K_0402_5%@RC84 100K_0402_5%@

CPU_EDP_HPD

RC89 100K_0402_5%RC89 100K_0402_5%

1 8 2 7 3 6 4 5

1 2

+3VS

RP52

2.2K_0804_8P4R_5%

2.2K_0804_8P4R_5% RP51

RP51

100K_0804_8P4R_5%

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

10 54Monday, April 07, 2014

of

A

5

4

3

2

1

D D

+1.05VS

Close to R2353

1

CC28

CC28 100P_0402_50V8J

100P_0402_50V8J

@

HASWELL_MCP_E

UC1J

+3V_DSW

1 2

RC153 10K_0402_5%RC153 10K_0402_5%

+3VS

1 2

RC98 100K_0402_5%RC98 100K_0402_5% RC116 10K_0402_5%RC116 10K_0402_5%

C C

+3VALW_PCH

RC109 10K_0402_5%RC109 10K_0402_5% RC105 10K_0402_5%RC105 10K_0402_5% RC103 10K_0402_5%RC103 10K_0402_5% RC117 10K_0402_5%RC117 10K_0402_5%

LAN_WAKE#

12

12 12 12 12

SIO_EXT_SCI# PCH_GPIO76

SIO_EXT_WAKE#

SIO_EXT_SMI# KB_DET# PCH_GPIO12

SIO_EXT_WAKE#[29]

LAN_WAKE#[22,29]

DGPU_HOLD_RST#[45]

KB_DET#[30]

SIO_EXT_SMI#[29]

HDD_DEVSLP[26] SIO_EXT_SCI#[29] HDA_SPKR[23]

T182 PAD~D@ T182 PAD~D@

T174 PAD~D@ T174 PAD~D@ T124 PAD~D@ T124 PAD~D@

T126 PAD~D@ T126 PAD~D@ T127 PAD~D@ T127 PAD~D@

T27@ PAD~DT27@ PAD~D

PCH_GPIO76 SIO_EXT_WAKE# PCH_GPIO12 HOST_ALERT1_R_N

LAN_WAKE#

PCH_GPIO47 DGPU_HOLD_RST#

KB_DET# PCH_GPIO14 PCH_GPIO25 SIO_EXT_SMI#

PCH_GPIO10

SIO_EXT_SCI# HDA_SPKR

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

@

HASWELL_MCP_E

GPIO

10 OF 19

CPU/

CPU/ MISC

MISC

LPIO

THERMTRIP

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD RSVD

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92 UART0_RTS/GPIO93 UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1

UART1_RST/GPIO2

UART1_CTS/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

Rev1p2

D60

H_THERMTRIP#_R

V4 T4

IRQ_SERIRQ

AW15

PCH_OPI_COMP

AF20 AB21

R6

GC6_EVENT#

L6

GPU_GC6_FB_EN

N6

PCH_GPIO85

L8

BBS_BIT

R7

PCH_GPIO87

L5 N7

TS_EN

K2

PCH_GPIO90

J1

CPPE#

K3

CPUSB#

J2

PCH_GPIO93

G1

PCH_GPIO94

K4 G2 J3

LCD_CBL_DET#

J4 F2

I2C0_SDA

F3

I2C0_SCL

G4

I2C1_SDA_TCH_PAD

F1

I2C1_SCL_TCH_PAD

E3 F4

CAM_MIC_CBL_DET#

D3

PCH_GPIO66

E4 C3 E2

X02.08

1 2

R2355 @ 0_0402_5%R2355 @ 0_0402_5%

1 2

RC101

49.9_0402_1%

T177PAD~D @T177PAD~D @ T176PAD~D @T176PAD~D @ T175PAD~D @T175PAD~D @

T4931PAD~D @T4931PAD~D @

TS_EN [21]

T179PAD~D @T179PAD~D @

T180PAD~D @T180PAD~D @ T181PAD~D @T181PAD~D @

LCD_CBL_DET# [21]

CAM_MIC_CBL_DET# [21]

H_THERMTRIP#

SIO_RCIN# [10,29]

IRQ_SERIRQ [29]

@

2

ESD solution

H_THERMTRIP# [29]

PCH_GPIO77[10] PCH_GPIO79[10]

IRQ_SERIRQ LCD_CBL_DET# CPPE# CPUSB#PCH_GPIO48

I2C1_SDA_TCH_PAD I2C1_SCL_TCH_PAD I2C0_SDA I2C0_SCL

PCH_GPIO77 TS_EN PCH_GPIO79 CAM_MIC_CBL_DET#

@

@ @

@

1 8 2 7 3 6 4 5

+1.05VS

H_THERMTRIP#

12

RC10210K_0402_5% RC10210K_0402_5%

12

RC10610K_0402_5% RC10610K_0402_5%

12

RC108100K_0402_5%

12

RC11110K_0402_5%

RP53

2.2K_0804_8P4R_5%

2.2K_0804_8P4R_5% RP60

RP60

18 27 36 45

10K_8P4R_5%

+3VS

12

R2353

R2353 1K_0402_5%

1K_0402_5%

B B

+3VS +3VS

12

@

RC118

RC118 1K_0402_5%

1K_0402_5%

PCH_GPIO66hasinternalpulldown20k PCH_GPIO86hasinternalpulldown20k

PCH_GPIO66

12

@

RC119

RC119 10K_0402_5%

10K_0402_5%

BBS_BIT

+3VALW_PCH

12

RC120

RC120 1K_0402_5%

1K_0402_5%

HOST_ALERT1_R_N

+3VS

12

@

RC121

RC121 1K_0402_5%

1K_0402_5%

HDA_SPKR

GPIO66 GPIO86 GPIO15 GPIO81

TOP‐BLOCKSWAPOVERRIDE

HIGHdepopRC118(DEFAULT) LOWpopRC122

A A

BOOTBIOSSTRAPBITBBS

HIGH LOW(DEFAULT)

LPC SPI

TLSCONFIDENTIALITY

HIGH LOW(DEFAULT)

NOREBOOTSTRAP

HIGH LOW(DEFAULT)

disable enable

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

11 54Monday, April 07, 2014

of

A

5

4

3

2

1

PEG_CTX_GRX_P[0..3][45]

D D

PEG_CTX_GRX_N[0..3][45]

PEG_CRX_GTX_P[0..3][45] PEG_CRX_GTX_N[0..3][45]

PEG_CTX_GRX_P[0..3] PEG_CTX_GRX_N[0..3] PEG_CRX_GTX_P[0..3] PEG_CRX_GTX_N[0..3]

HASWELL_MCP_E

PCIe

HASWELL_MCP_E

11 OF 19

AN8

USB2N0

AM8

USB2P0

AR7

USB2N1

AT7

USB2P1

AR8

USB2N2

AP8

USB2P2

AR10

USB2N3

AT10

USB2P3

AM15

USB2N4

AL15

USB2P4

AM13

USB2N5

AN13

USB2P5

AP11

USB2N6

AN11

USB2P6

AR13

USB2N7

AP13

USB2P7

G20

USB3RN1

H20

USB3RP1

USB

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS USBRBIAS

RSVD RSVD

OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43

Rev1p2

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

USBRBIAS

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USB20_JUSB1_N0 [24] USB20_JUSB1_P0 [24]

USB20_JUSB2_N1 [24] USB20_JUSB2_P1 [24]

USB20_JUSB3_N2 [27] USB20_JUSB3_P2 [27]

USB20_BIO_N3 [26] USB20_BIO_P3 [26]

USB20_MINI1_N4 [25] USB20_MINI1_P4 [25]

USB20_TOUCH_N5 [21] USB20_TOUCH_P5 [21]

USB20_CR_N6 [27] USB20_CR_P6 [27]

USB20_CAM_N7 [21] USB20_CAM_P7 [21]

USB3RN1_JUSB1 [24] USB3RP1_JUSB1 [24]

USB3TN1_JUSB1 [24] USB3TP1_JUSB1 [24]

USB3RN2_JUSB2 [24] USB3RP2_JUSB2 [24]

USB3TN2_JUSB2 [24] USB3TP2_JUSB2 [24]

T118PAD~D @T118PAD~D @ T119PAD~D @T119PAD~D @

USB_OC0# [24] USB_OC1# [24] USB_OC2# [27]

22.6_0402_1%

RC90

USB Conn JUSB1

USB Conn JUSB2

USB Conn JUSB3

Finger print

Mini Card (WLAN)

Touch screen panel

Card Reader

Camera

USB Conn JUSB1

USB_OC0# USB_OC1# USB_OC2#

USB Conn JUSB2

CAD NOTE:

12

Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils.

USB_OC3#

1 8 2 7 3 6 4 5

RP55

RP55 10K_8P4R_5%

10K_8P4R_5%

+3VALW_PCH

UC1K

PEG_CRX_GTX_N0 PEG_CRX_GTX_P0

PEG_CTX_GRX_N0 PEG_CTX_GRX_N0_C PEG_CTX_GRX_P0

PEG_CRX_GTX_N1 PEG_CRX_GTX_P1

PEG_CRX_GTX_N2 PEG_CRX_GTX_P2

PEG_CRX_GTX_N3 PEG_CRX_GTX_P3

C C

LAN

NGFF WLAN

B B

PCIE_PRX_LANTX_N3[22] PCIE_PRX_LANTX_P3[22]

PCIE_PTX_LANRX_N3[22] PCIE_PTX_LANRX_P3[22]

PCIE_PRX_WLANTX_N4[25] PCIE_PRX_WLANTX_P4[25]

PCIE_PTX_WLANRX_N4[25] PCIE_PTX_WLANRX_P4[25]

+1.05VS_AUSB3PLL

12

CC18 0.22U_0402_16V7KCC18 0.22U_0402_16V7K

12

CC19 0.22U_0402_16V7KCC19 0.22U_0402_16V7K

12

CC20 0.22U_0402_16V7KCC20 0.22U_0402_16V7K

12

CC21 0.22U_0402_16V7KCC21 0.22U_0402_16V7K

12

CC22 0.22U_0402_16V7KCC22 0.22U_0402_16V7K

12

CC23 0.22U_0402_16V7KCC23 0.22U_0402_16V7K

12

CC24 0.22U_0402_16V7KCC24 0.22U_0402_16V7K

12

CC25 0.22U_0402_16V7KCC25 0.22U_0402_16V7K

1 2

CC32 0.1U_0402_10V7KCC32 0.1U_0402_10V7K

1 2

CC40 0.1U_0402_10V7KCC40 0.1U_0402_10V7K

RC91

3.01K_0402_1%

1 2

PCH_PCIE_RCOMP

PEG_CTX_GRX_P0_C

PEG_CTX_GRX_N1_CPEG_CTX_GRX_N1 PEG_CTX_GRX_P1_CPEG_CTX_GRX_P1

PEG_CTX_GRX_N2_CPEG_CTX_GRX_N2 PEG_CTX_GRX_P2_CPEG_CTX_GRX_P2

PEG_CTX_GRX_N3_CPEG_CTX_GRX_N3 PEG_CTX_GRX_P3_CPEG_CTX_GRX_P3

PCIE_PTX_LANRX_N3_C PCIE_PTX_LANRX_P3_C

T120PAD~D@T120PAD~D@ T121PAD~D@T121PAD~D@

F10 E10

C23 C22

F8 E8

B23 A23

H10

G10 B21

C21

E6 F6

B22 A21

G11

F11 C29

B30 F13

G13 B29

A29 G17

F17

C30

C31 F15

G15 B31

A31

E15 E13

A27 B27

@

PERN5_L0 PERP5_L0

PETN5_L0 PETP5_L0

PERN5_L1 PERP5_L1

PETN5_L1 PETP5_L1

PERN5_L2 PERP5_L2

PETN5_L2 PETP5_L2

PERN5_L3 PERP5_L3

PETN5_L3 PETP5_L3

PERN3 PERP3

PETN3 PETP3

PERN4 PERP4

PETN4 PETP4

PERN1/USB3RN3 PERP1/USB3RP3

PETN1/USB3TN3 PETP1/USB3TP3

PERN2/USB3RN4 PERP2/USB3RP4

PETN2/USB3TN4 PETP2/USB3TP4

RSVD RSVD PCIE_RCOMP PCIE_IREF

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

12 54Monday, April 07, 2014

of

A

5

4

3

2

1

C40

1 2

22U_0603_6.3V6M

ESD@

ESD solution

+CPU_CORE

X02.08

1 2

@

0_0402_5%R248

0_0402_5%

1 2

@

1 2

@

0_0402_5%R250

0_0402_5% 0_0402_5%R251

0_0402_5%

+CPU_CORE

+1.35V

2.2U_0402_6.3V6M

1

2

+1.35V

VCCSENSE

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDATA H_VCCST_PWRGD VR12.5_VR_ON_R VR_READY_R

CPU_PWR_DEBUG#

+1.05VS

VDDQ DECOUPLING

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M C36

C36

C35

1

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M C37

C37

T38 @T38 @

T39 @T39 @ T40 @T40 @ T41 @T41 @ T42 @T42 @ T43 @T43 @ T44 @T44 @ T45 @T45 @ T46 @T46 @ T47 @T47 @ T48 @T48 @ T49 @T49 @ T50 @T50 @ T51 @T51 @

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M C38

C38

1

2

HASWELL_MCP_E

UC1L

L59

RSVD

J58

RSVD

AH26

VDDQ

AJ31

VDDQ

AJ33

VDDQ

AJ37

VDDQ

AN33

VDDQ

AP43

VDDQ

AR48

VDDQ

AY35

VDDQ

AY40

VDDQ

AY44

VDDQ

AY50

VDDQ

F59

VCC

N58

RSVD

AC58

RSVD

E63

VCC_SENSE

AB23

RSVD

A59

VCCIO_OUT

E20

VCCIOA_OUT

AD23

RSVD

AA23

RSVD

AE59

RSVD

L62

VIDALERT

N63

VIDSCLK

L63

VIDSOUT

B59

VCCST_PWRGD

F60

VR_EN

C59

VR_READY

D63

VSS

H59

PWR_DEBUG

P62

VSS

P60

RSVD_TP

P61

RSVD_TP

N59

RSVD_TP

N61

RSVD_TP

T59

RSVD

AD60

RSVD

AD59

RSVD

AA59

RSVD

AE60

RSVD

AC59

RSVD

AG58

RSVD

U59

RSVD

V59

RSVD

AC22

VCCST

AE22

VCCST

AE23

VCCST

AB57

VCC

AD57

VCC

AG57

VCC

C24

VCC

C28

VCC

C32

VCC

@

10U_0603_6.3V6M

1

C39

2

1

C41

2

HASWELL_MCP_E

12 OF 19

HSW ULT POWER

10U_0603_6.3V6M

C72

10U_0603_6.3V6M

1

C45

C42

2

+1.35V : 470UF/2V/7343 *2 (PWR)

10U_0603_6.3V6M

1

10UF/6.3V/0603 * 6

C74

2.2UF/6.3V/0402 * 4

2

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Rev1p2

+CPU_CORE

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

+VCCIO_OUT

+VCCIOA_OUT

R248

R250 R251

H_CPU_SVIDCLK

1

@C5212

@

2

+CPU_CORE

1 2

@

+VCCIO_OUT

VR_SVID_CLK[38]

H_VCCST_PWRGD[6]

H_VR_READY[38]

CPU_PWR_DEBUG#[6]

VR_ON[38]

C5212 68P_0402_50V8J

68P_0402_50V8J

D D

C C

B B

RESET_OUT#[10,29]

VCCSENSE[38]

VR_ON

0.1U_0402_10V7K

Place C80 close to R250.1

C80

1

@C80

@

2

UC6

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

X02.23

SVID ALERT

VR_SVID_ALRT#[38]

SVID DATA

SVID_DAT need to pull-up double side ( PWR_VR & CPU )

VR_SVID_DAT[38]

VCCSENSE

+1.05VS

R253

R253 150_0402_1%

150_0402_1%

1 2

CPU_PWR_DEBUG#

@

R255

R255 10K_0402_5%

10K_0402_5%

1 2

+CPU_CORE

12

R1

R1 100_0402_1%

100_0402_1%

+1.05VS

12

RC363

RC363 10K_0402_5%@

10K_0402_5%@

12

H_VR_READY

RC3641.5K_0402_5% RC3641.5K_0402_5%

+3VALW

5

1 2

CC41@ 0.1U_0402_25V6CC41@ 0.1U_0402_25V6

4

H_VCCST_PWRGD

Y

+1.05VS

12

Place the PU

R252

resistors close to CPU

75_0402_5%

R254

R254 43_0402_1%

43_0402_1%

12

+1.05VS

12

X02.08

R257

R257 0_0402_5%

0_0402_5%

12

@

CAD Note: PU resistor on HW side close to process

R253 INTEL Check list , XDP use only

+1.05VS

RC365

RC365 1K_0402_5%

1K_0402_5%

1 2

1

2

H_CPU_SVIDALRT#

Place the PU resistors close to CPU

R256

R256 130_0402_1%

130_0402_1%

H_CPU_SVIDDATA

EMI@

CC42

CC42 100P_0402_50V8J

100P_0402_50V8J

+1.05VS

R245 0_0603_5%

RESISTORSTUFFINGOPTIONSARE PROVIDEDFORTESTINGPURPOSES

R245 0_0603_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

13 54Monday, April 07, 2014

of

A

5

4

3

2

1

D D

+1.05VS

L1

2.2UH_LQM2MPN2R2NG0L_30%

L2

2.2UH_LQM2MPN2R2NG0L_30%

L3

2.2UH_LQM2MPN2R2NG0L_30%

L4

2.2UH_LQM2MPN2R2NG0L_30%

C C

B B

2.2UH_LQM2MPN2R2NG0L_30%

L5

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS_AUSB3PLL

1 2

+1.05VS_ASATA3PLL

1 2

+1.05VS_APLLOPI

R267

R267 0_0805_5%

0_0805_5%

1 2 1 2

@L3

@

+PCH_VCC1P05

1 2

+PCH_VCCACLKPLL

1 2

C1313 0.47U_0402_10V4

RC127 0_0402_5%RC127 0_0402_5%

+VCCHDA

Reserve for HDA issue, C77 close to AH14

+1.05VS

+3VALW_PCH

1 2

C58 1U_0402_6.3V6KC58 1U_0402_6.3V6K

1 2

C59 100U_1206_6.3V6MC59 100U_1206_6.3V6M

1 2

C63 1U_0402_6.3V6KC63 1U_0402_6.3V6K

1 2

C65 100U_1206_6.3V6MC65 100U_1206_6.3V6M

1 2

C69 1U_0402_6.3V6KC69 1U_0402_6.3V6K

1 2

C70 100U_1206_6.3V6M@C70 100U_1206_6.3V6M@

1 2

C83 1U_0402_6.3V6KC83 1U_0402_6.3V6K

1 2

C84 100U_1206_6.3V6MC84 100U_1206_6.3V6M

1 2

C85 1U_0402_6.3V6KC85 1U_0402_6.3V6K

1 2

C86 100U_1206_6.3V6MC86 100U_1206_6.3V6M

1 2

@

1 2 1 2

1 2

+VCCHDA+3VALW_PCH

@

1 2

C77 0.1U_0402_10V7KC77 0.1U_0402_10V7K

C50 1U_0402_6.3V6KC50 1U_0402_6.3V6K C53 1U_0402_6.3V6KC53 1U_0402_6.3V6K

C81 0.1U_0402_10V7K

C78 22U_0603_6.3V6MC78 22U_0603_6.3V6M

+PCH_VCCDSW+3V_DSW

+1.05VS

+1.05VS_AUSB3PLL

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

+3VALW_PCH

+PCH_VCC1P05

+PCH_VCCACLKPLL

+3VALW_PCH

Close to K9,M9

Close to AH10

Close to AC9/AA9/AE20/AE21

+3V_DSW

+1.05VS +1.05VS

T53 @T53 @

+VCCHDA

T55 @T55 @

+3VS

AA21

AH14

AH13

AH10

AE20 AE21

L10

B18 B11

Y20

W21

J13

AC9 AA9

J18 K19 A20 J17

R21

T21 K18

M20

V21

K9

M9 N8

P9

V8

W9

UC1M

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3

@

mPHY

OPI

USB3

AXALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

LPT LP POWER

HASWELL_MCP_E

13 OF 19

RTC

SPI

CORE

THERMAL SENSOR

SDIO/PLSS

SUS OSCILLATOR

USB2

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP DCPSUSBYP

VCCASW

DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO

DCPSUS4

RSVD VCC1_05 VCC1_05

Rev1p2

AH11

C51 1U_0402_6.3V6KC51 1U_0402_6.3V6K

AG10 AE7

+VCCRTCEXT

Y8

C68 0.1U_0402_10V7K@ C68 0.1U_0402_10V7K@

AG14 AG13

J11

C60 10U_0603_6.3V6MC60 10U_0603_6.3V6M

H11

C61 1U_0402_6.3V6KC61 1U_0402_6.3V6K

H15

C62 1U_0402_6.3V6KC62 1U_0402_6.3V6K

AE8 AF22 AG19 AG20 AE9 AF9

C66 22U_0603_6.3V6M@ C66 22U_0603_6.3V6M@

AG8

C67 1U_0402_6.3V6KC67 1U_0402_6.3V6K

AD10 AD8

T58 @T58 @ T59 @T59 @

J15 K14 K16

1 2

C71 0.1U_0402_10V7KC71 0.1U_0402_10V7K

U8 T9

1 2

C73 1U_0402_6.3V6KC73 1U_0402_6.3V6K

AB8

T56 @T56 @

AC20 AG16

+1.05VS

AG17

1 2

C76 1U_0402_6.3V6KC76 1U_0402_6.3V6K

12

1 2

+1.05VS +1.05VS

X02.08

1 2

@

R2640_0603_5% R2640_0603_5%

+RTCVCC

+3VS

+PCH_VCCDSW_R+PCH_VCCDSW

0_0402_5%R265

0_0402_5%

1 2

C52 0.1U_0402_10V7KC52 0.1U_0402_10V7K

1 2

1 2 1 2 1 2

R265

1 2 1 2

+1.5VS +3VS

+3VS

+3VALW_PCH

+1.05VS

+PCH_VCCDSW

C64

C64 1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

+RTCVCC

1

C54

2

1U_0402_6.3V6K

+1.05VS

22U_0603_6.3V6M

ESD solution

22U_0603_6.3V6M

ESD solution

C55

0.1U_0402_10V7K

C44

1 2

ESD@

C43

1 2

ESD@

1

C56

2

0.1U_0402_10V7K

+3VS

+1.35V+1.05VS

1 2

C82 22U_0603_6.3V6MC82 22U_0603_6.3V6M

+3VS

1 2

+1.05VS

A A

C87 1U_0402_6.3V6KC87 1U_0402_6.3V6K

1 2

C88 1U_0402_6.3V6KC88 1U_0402_6.3V6K

1 2

C57 1U_0402_6.3V6K

@

Close to V8

Close to J17

Close to R21

Close to N8

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

14 54Monday, April 07, 2014

of

A

5

4

3

2

1

D D

HASWELL_MCP_E

UC1N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

C C

B B

AB22 AC61

AD21 AD63

AE10 AE58

AF11 AF12 AF14 AF15 AF17 AF18

AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

VSS

AB7

VSS VSS VSS

AD3

VSS VSS VSS

AE5

VSS VSS VSS VSS VSS VSS VSS VSS

AG1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

14 OF 19

@

14 OF 19

Rev1p2

AJ35

VSS

AJ39

VSS

AJ41

VSS

AJ43

VSS

AJ45

VSS

AJ47

VSS

AJ50

VSS

AJ52

VSS

AJ54

VSS

AJ56

VSS

AJ58

VSS

AJ60

VSS

AJ63

VSS

AK23

VSS

AK3

VSS

AK52

VSS

AL10

VSS

AL13

VSS

AL17

VSS

AL20

VSS

AL22

VSS

AL23

VSS

AL26

VSS

AL29

VSS

AL31

VSS

AL33

VSS

AL36

VSS

AL39

VSS

AL40

VSS

AL45

VSS

AL46

VSS

AL51

VSS

AL52

VSS

AL54

VSS

AL57

VSS

AL60

VSS

AL61

VSS

AM1

VSS

AM17

VSS

AM23

VSS

AM31

VSS

AM52

VSS

AN17

VSS

AN23

VSS

AN31

VSS

AN32

VSS

AN35

VSS

AN36

VSS

AN39

VSS

AN40

VSS

AN42

VSS

AN43

VSS

AN45

VSS

AN46

VSS

AN48

VSS

AN49

VSS

AN51

VSS

AN52

VSS

AN60

VSS

AN63

VSS

AN7

VSS

AP10

VSS

AP17

VSS

AP20

VSS

AP22 AP23 AP26 AP29

AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

AR5

AU1

HASWELL_MCP_E

UC1O

VSS VSS VSS VSS

AP3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

15 OF 19

@

15 OF 19

Rev1p2

AV59

VSS

AV8

VSS

AW16

VSS

AW24

VSS

AW33

VSS

AW35

VSS

AW37

VSS

AW4

VSS

AW40

VSS

AW42

VSS

AW44

VSS

AW47

VSS

AW50

VSS

AW51

VSS

AW59

VSS

AW60

VSS

AY11

VSS

AY16

VSS

AY18

VSS

AY22

VSS

AY24

VSS

AY26

VSS

AY30

VSS

AY33

VSS

AY4

VSS

AY51

VSS

AY53

VSS

AY57

VSS

AY59

VSS

AY6

VSS

B20

VSS

B24

VSS

B26

VSS

B28

VSS

B32

VSS

B36

VSS

B4

VSS

B40

VSS

B44

VSS

B48

VSS

B52

VSS

B56

VSS

B60

VSS

C11

VSS

C14

VSS

C18

VSS

C20

VSS

C25

VSS

C27

VSS

C38

VSS

C39

VSS

C57

VSS

D12

VSS

D14

VSS

D18

VSS

D2

VSS

D21

VSS

D23

VSS

D25

VSS

D26

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

UC1P

HASWELL_MCP_E

D33

VSS

D34

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D5

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

D8

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS

H13

VSS

16 OF 19

@

16 OF 19

VSS_SENSE

Rev1p2

H17

VSS

H57

VSS

J10

VSS

J22

VSS

J59

VSS

J63

VSS

K1

VSS

K12

VSS

L13

VSS

L15

VSS

L17

VSS

L18

VSS

L20

VSS

L58

VSS

L61

VSS

L7

VSS

M22

VSS

N10

VSS

N3

VSS

P59

VSS

P63

VSS

R10

VSS

R22

VSS

R8

VSS

T1

VSS

T58

VSS

U20

VSS

U22

VSS

U61

VSS

U9

VSS

V10

VSS

V3

VSS

V7

VSS

W20

VSS

W22

VSS

Y10

VSS

Y59

VSS

Y63

VSS

V58

VSS

AH46

VSS

V23

VSS

E62 AH16

VSS

12

R2

R2 100_0402_1%

100_0402_1%

VSSSENSE [38]

close to process

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

15 54Monday, April 07, 2014

of

A

5

4

3

2

1

D D

HASWELL_MCP_E

UC1R

AU44 AV44

UC1R

AT2

RSVD RSVD RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

@

HASWELL_MCP_E

UC1Q

DC_TEST_AY2_AW2 DC_TEST_AY3_AW3

T166PAD~D@T166PAD~D@

T167PAD~D@T167PAD~D@

DC_TEST_AY60 DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 TP_DC_TEST_B2 DC_TEST_A3_B3 DC_TEST_A61_B61

DC_TEST_B62_B63 DC_TEST_C1_C2 DC_TEST_AY62_AW62

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

@

HASWELL_MCP_E

17 OF 19

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

Rev1p2

A3

DC_TEST_A3_B3

A4

DC_TEST_A4

A60

DC_TEST_A60

A61

DC_TEST_A61_B61

A62

DC_TEST_A62

AV1

DC_TEST_AV1

AW1

DC_TEST_AW1

AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW61

AW62 AW63

DC_TEST_AW63

T168PAD~D @T168PAD~D @ T169PAD~D @T169PAD~D @ T170PAD~D @T170PAD~D @

T171PAD~D @T171PAD~D @ T172PAD~D @T172PAD~D @

T173PAD~D @T173PAD~D @

@

T128 PAD~D

@

T132 PAD~D

@

T134 PAD~D

@

T135 PAD~D

@

T138 PAD~D

@

T140 PAD~D

@

T143 PAD~D

RSVD_AT2 RSVD_AU44 RSVD_AV44 RSVD_D15

RSVD_F22 RSVD_H22 RSVD_J21

HASWELL_MCP_E

18 OF 19

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Rev1p2

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

RSVD_N23 RSVD_R23 RSVD_T23 RSVD_U10

RSVD_AL1 RSVD_AM11 RSVD_AP7 RSVD_AU10 RSVD_AU15 RSVD_AW14 RSVD_AY14

@

T129PAD~D@T129PAD~D

@

T130PAD~D@T130PAD~D

@

T131PAD~D@T131PAD~D

@

T133PAD~D@T133PAD~D

@

T136PAD~D@T136PAD~D

@

T137PAD~D@T137PAD~D

@

T139PAD~D@T139PAD~D

@

T141PAD~D@T141PAD~D

@

T142PAD~D@T142PAD~D

@

T144PAD~D@T144PAD~D

@

T145PAD~D@T145PAD~D

C C

CFG0[6] CFG1[6] CFG2[6] CFG3[6] CFG4[6] CFG5[6] CFG6[6] CFG7[6] CFG8[6] CFG9[6] CFG10[6] CFG11[6] CFG12[6] CFG13[6] CFG14[6] CFG15[6]

CFG16[6] CFG18[6] CFG17[6]

RC132 49.9_0402_1%RC132 49.9_0402_1%

B B

RC133 8.2K_0402_1%RC133 8.2K_0402_1%

12

1 2

CFG19[6]

T159PAD~D@T159PAD~D@ T161PAD~D@T161PAD~D@

T163PAD~D@T163PAD~D@ T164PAD~D@T164PAD~D@ T165PAD~D@T165PAD~D@

CFG0

CFG4

CFG_RCOMP

TDI_IREF

AC60 AC62 AC63 AA63 AA60

AA62 AA61

Y62 Y61 Y60 V62 V61 V60

U60

T63 T62 T61 T60

U63 U62

V63

D1

J20

H18

B12

A5 E1

UC1S

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP RSVD RSVD

RSVD RSVD RSVD TD_IREF

@

HASWELL_MCP_E

RESERVED

19 OF 19

RSVD_TP RSVD_TP

RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD RSVD

RSVD

PROC_OPI_RCOMP

RSVD RSVD

Rev1p2

AV63 AU63

C63 C62 B43

A51 B51

L60 N60 W23

Y22 AY15

PROC_OPI_RCOMP

AV62 D58

P22

VSS

N21

VSS

P20 R20

T146PAD~D @T146PAD~D @ T147PAD~D @T147PAD~D @

T148PAD~D @T148PAD~D @ T149PAD~D @T149PAD~D @ T150PAD~D @T150PAD~D @

T151PAD~D @T151PAD~D @ T152PAD~D @T152PAD~D @

T153PAD~D @T153PAD~D @ T154PAD~D @T154PAD~D @ T155PAD~D @T155PAD~D @

T156PAD~D @T156PAD~D @

T157PAD~D @T157PAD~D @ T158PAD~D @T158PAD~D @

1 2

RC13449.9_0402_1% RC13449.9_0402_1%

CFGSTRAPSforCPU

DisplayPortPresenceStrap

1:Disabled;NoPhysicalDisplayPort

CFG4

attachedtoEmbeddedDisplayPort 0:Enabled;AnexternalDisplayPortdeviceis connectedtotheEmbeddedDisplayPort

CFG4

CFG0

1K_0402_5%

12

RC191

1K_0402_1%

12

RC183@

EAR‐STALL/NOTSTALLRESETSEQUENCEAFTERPCUPLLISLOCKED

1:(Default)NormalOperation;Nostall

CFG0

0:LaneReversed

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEAMTICS,MB AB072

SCHEAMTICS,MB AB072 4019RU

4019RU

1

16 54Monday, April 07, 2014

of

A

5

4

3

2

1

D D

C C

B B

A A

Populate RD1, De-Populate RD7 for Intel DDR3 VREFDQ multiple methods M1 Populate RD7, De-Populate RD1 for Intel DDR3 VREFDQ multiple methods M3

DDR_A_DQS#[0..7][7] DDR_A_D[0..63][7] DDR_A_DQS[0..7][7]

DDR_A_MA[0..15][7]

Layout Note: Place near JDIMM1

+1.35V

1U_0402_6.3V6K

1

CD4

2

+1.35V

10U_0603_6.3V6M

CD16

1

2

Layout Note: Place near JDIMM1.203,204

+0.675VS

0.1U_0402_10V7K

0.1U_0402_10V7K CD24

CD24

1

2

1U_0402_6.3V6K

1

2

CD25

CD12

1

CD6

2

10U_0603_6.3V6M

CD18

1

2

0.1U_0402_10V7K

0.1U_0402_10V7K CD26

CD26

1

2

CD5

2

10U_0603_6.3V6M

@

CD17

1

2

0.1U_0402_10V7K

1

2

+SM_VREF_DQ0_DIMM1

All VREF traces should have 10 mil trace width

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

1U_0402_6.3V6K

1

CD8

CD7

2

10U_0603_6.3V6M

@

CD20

CD19

1

2

0.1U_0402_10V7K

10U_0603_6.3V6M

CD27

CD28

1

2

1U_0402_6.3V6K

1

CD9

2

10U_0603_6.3V6M

CD13

1

2

10U_0603_6.3V6M

CD29

1

2

1

CD10

2

330U_D3_2.5VY_R6M

1

CD15

CD14

1

+

2

1U_0402_6.3V6K

CD11

RD6 10K_0402_5%RD6 10K_0402_5%

RD7 10K_0402_5%RD7 10K_0402_5%

1 2

RD1

RD1 0_0402_5%

0_0402_5%

1 2 1 2

+3VS

+DIMM1_VREF_DQ

+3VS

CD62

1 2

22U_0603_6.3V6M

ESD@

DDR_CKE0_DIMMA[7]

M_CLK_DDR0[7] M_CLK_DDR#0[7]

DDR_CS1_DIMMA#[7]

+1.35V

2.2U_0402_6.3V6M

0.1U_0402_10V7K

DDR_A_D0

CD1

1

2

DDR_A_BS2[7]

DDR_A_BS0[7] DDR_A_WE#[7]

DDR_A_CAS#[7]

1

2

DDR_A_D1

CD2

1

DDR_A_D2

2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25

DDR_A_D26

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

2.2U_0402_6.3V6M

0.1U_0402_10V7K

1

@

CD30

CD31

+0.675VS

2

ESD solution

5

4

H=4mm

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9 VSS925VSS10

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17 VSS1849DQ22

51

DQ18 DQ1953VSS19 VSS2055DQ28

57

DQ24 DQ2559VSS21 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A621-U4R6-7H

CONN@

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

DQ14 DQ15

DQ20 DQ21

DQ23

DQ29

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30 VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42 VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

+1.35V

2 4

DQ4

6

DQ5

8 10 12 14 16

DQ6

18

DQ7

20 22 24 26 28

DM1

30 32 34 36 38 40 42 44 46

DM2

48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102

CK1

104 106 108

BA1

110 112 114

S0#

116 118 120 122

NC2

124 126 128 130 132 134 136

DM4

138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170

DM6

172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

SDA

202

SCL

204 206

G2

3

2-3A to 1 DIMMs/channel

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0

DDR_A_DQS0 DDR_A_D6

DDR_A_D7 DDR_A_D12

DDR_A_D13

DDR3_DRAMRST# DDR_A_D14

DDR_A_D15 DDR_A_D20

DDR_A_D21

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31DDR_A_D27

DDR_CKE1_DIMMA DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 M_CLK_DDR1

M_CLK_DDR#1 DDR_A_BS1

DDR_A_RAS# DDR_CS0_DIMMA#

M_ODT0 M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

+0.675VS

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

1

CD3

0.1U_0402_10V7K

2

CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN

DDR_CKE1_DIMMA [7]

M_CLK_DDR1 [7] M_CLK_DDR#1 [7]

DDR_A_BS1 [7] DDR_A_RAS# [7]

DDR_CS0_DIMMA# [7]

0.1U_0402_10V7K

CD22

CD21

1

2

2013/08/01 2014/07/31

Issued Date

2.2U_0402_6.3V6M

+SM_VREF_CA_DIMM

1 2

RD4

RD4 0_0402_5%

0_0402_5%

DDR_PG_CTRL[6]

DDR_XDP_WLAN_TP_SMBDAT [6,9,18]

DDR_XDP_WLAN_TP_SMBCLK [6,9,18]

Compal Secret Data

Deciphered Date

2

DDR3L SODIMM ODT GENERATION

+5VALW +1.35V

12

R2347

R2347 220K_0402_5%

220K_0402_5%

@

R2351

R2351 2M_0402_5%

2M_0402_5%

1 2

RD5

RD5 0_0402_5%

0_0402_5%

QD2

L2N7002WT1G_SC-70-3

1 3

D

2

U2303

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

X02.23

+1.35V

12

RD3

RD3 470_0402_5%

470_0402_5%

DDR3_DRAMRST#_CPU [6]DDR3_DRAMRST#[18]

M_ODT

CD64

0.1U_0402_10V7K

Place CC31 between QD2 and R2349

S

M_ODT

G

0.675V_DDR_VTT_ON

5

4

Y

1 2

R2348 66.5_0402_1%R2348 66.5_0402_1%

1 2

R2349 66.5_0402_1%R2349 66.5_0402_1%

1 2

R2350 66.5_0402_1%R2350 66.5_0402_1%

1 2

R2352 66.5_0402_1%R2352 66.5_0402_1%

+1.35V

@

CD23

0.1U_0402_10V7K

1 2

0.675V_DDR_VTT_ON

Title

SCHEAMTICS,MB AB072

Size Document Number Rev

4019RU

Date: Sheet

M_ODT0 M_ODT1

0.675V_DDR_VTT_ON [37]

Compal Electronics, Inc.

1

ESD@CD64

ESD@

2

M_ODT2 [18] M_ODT3 [18]

17 54Monday, April 07, 2014

A

of

Dell LATITUDE 3550 ZAL50, LATITUDE 3550 ZAL60 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual