Datasheet S6A0090 Datasheet (Samsung)

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

S6A0090

written permission of LCD Driver IC Team.

June. 2000.

Prepared by: Weon-seek, Kang

Ver. 0.2

Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express

k2w2@samsung.co.kr

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

S6A0090 Specification Revision History

Version Content Date

0.0 Original Jun.1998

0.1 KS0090 à KS0090B, add ILB key Apr.1999

0.2 Add power ON / OFF sequence Apr.1999 Inspection Jun.2000

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

CONTENTS

INTRODUCTION ................................................................................................................................................. 1

FEATURES.........................................................................................................................................................1

BLOCK DIAGRAM..............................................................................................................................................3

PAD CONFIGURATION ...................................................................................................................................... 4

PAD CENTER COORDINATES ........................................................................................................................... 5

PIN DESCRIPTION ............................................................................................................................................. 7

POWER SUPPLY ..........................................................................................................................................7

LCD DRIVER SUPPLY..................................................................................................................................7

SYSTEM CONTROL .....................................................................................................................................8

MPU INTERFACE.........................................................................................................................................8

LCD DRIVER OUTPUTS (DYNAMIC)............................................................................................................9

LCD DRIVER OUTPUTS (STATIC) ...............................................................................................................9

FUNCTION DESCRIPTION ............................................................................................................................... 10

SYSTEM INTERFACE.................................................................................................................................10

ADDRESS COUNTER (AC).........................................................................................................................14

DISPLAY DATA RAM (DDRAM)..................................................................................................................14

CHARACTER GENERATOR ROM (CGROM) .............................................................................................15

CHARACTER GENERATOR RAM (CGRAM)..............................................................................................16

SEGMENT ICON RAM (ICONRAM) ............................................................................................................17

STATIC ICON RAM (SI) .............................................................................................................................. 18

SEGMENTS FOR SIGNAL DISPLAY (FS)................................................................................................... 18

LOW POWER CONSUMPTION MODE.......................................................................................................19

LCD DRIVER CIRCUIT ...............................................................................................................................19

INSTRUCTION DESCRIPTION.......................................................................................................................... 20

INITIALIZING & POWER SAVE MODE SETUP................................................................................................. 26

HARDWARE RESET ...................................................................................................................................26

INITIALIZING AND POWER SAVE MODE SETUP......................................................................................27

LCD DRIVING POWER SUPPLY CIRCUIT ....................................................................................................... 30

VOLTAGE CONVERTER ............................................................................................................................31

VOLTAGE REGULATOR.............................................................................................................................32

VOLTAGE GENERATOR CIRCUIT.............................................................................................................35

REFERENCE APPLICATIONS.......................................................................................................................... 36

MPU INTERFACE.......................................................................................................................................36

APPLICATION INFORMATION FOR LCD PANEL.......................................................................................38

FRAME FREQUENCY.................................................................................................................................42

MAXIMUM ABSOLUTE RATINGS .................................................................................................................... 43

ELECTRICAL CHARACTERISTICS.................................................................................................................. 44

DC CHARACTERISTICS .............................................................................................................................44

AC CHARACTERISTICS.............................................................................................................................47

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

INTRODUCTION

The S6A0090 is an LCD driver and controller LSI for liquid crystal dot matrix character display systems. It can display 2 or 3 lines of 12 characters with 5 x 8 dots format. It is capable of interfacing with various microprocessors, supporting the 4-bit and 8-bit parallel mode and the clock synchronized serial mode. Voltage converter (2 or 3 times), voltage regulator, divider resistor and voltage follower OP AMP are built in the IC and a low operation current of 50µA is achieved. The slim shape of the chip makes it suitable for the COG module application and TCP. The S6A0090 is an ideal solution for display on portable equipment such as cellular phones.

FEATURES

Driver Outputs

- Common outputs: 26 common

- Segment outputs: 64 segment

- Icons: 128 horizontal icons, 24 x 4 vertical icons, 5 static icons

Applicable Panel Size

Display size Duty Contents of outputs

2-line x 12 characters 1/18 (12 characters + 4 segments for signal) x 2 + 128 icons + 5 static icons 3-line x 12 characters 1/26 (12 characters + 4 segments for signal) x 3 + 128 icons + 5 static icons

Internal Memory

- Character Generator ROM (CGROM): 10,240 bits (256 characters x 5 x 8 dots)

- Character Generator RAM (CGRAM): 160 bits (4 characters x 5 x 8 dots)

- Display Data RAM (DDRAM): 288 bits (12 characters x 3 lines x 8 bits)

- Segment Icon RAM (ICONRAM): 224 bits (12 x 2 x 5 bits + 2 x 4 bits + 24 x 4 bits)

MPU Interface

- No busy MPU interface (no busy check or no execution waiting time)

- 8-bit parallel interface mode: 68-series and 80-series are available

- 4-bit parallel interface mode: 68-series and 80-series are available

- Serial interface mode: 4 pins clock synchronized serial interface

Function Set

- Various instructions set: display control, power save, power control, function set, etc.

- COM / SEG bi-directional function (4 types of LCD application available)

- Hardware reset (RES pin)

Built-in Analog Circuit

- On-chip oscillator with an internal resistor or external clock input

- Electronic volume for contrast control (32 or 64 steps)

- Voltage converter (2 or 3 times) / voltage regulator / voltage follower and bias circuit

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

Low Power Consumption

- 80 µA Max. : in normal mode for normal display operation

- 10 µA Max. : in standby mode for displaying static icon

- 5 µA Max. : in sleep mode when display is turned OFF

Operating Voltage Range

- Power supply voltage (VDD): 2.4 to 5.5 V

- LCD driving voltage (VLCD = V0 - VSS): 11.0 V (positive process)

Package Type

- Gold bumped chip or TCP

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

BLOCK DIAGRAM

RES

CSB

DB7

(SI)

DB6

(SCL) DB5~

DB4

DB3~

DB0

Parallel

Interface

4-bit/8-bit

Serial

Interface

Input Buffer

Instruction

Icon RAM

(ICONRAM)

224 bits

(IR)

Data

(DR)

Character Generator

(CGRAM)

Address

Counter

RAM

32 bytes

Instruction

Decoder

Character Generator

ROM (CGROM) 10240 bits

Display

Data RAM

(DDRAM)

36x8 bits

Timing GeneratorOscillator

Cursor &

Blink

Controller

64 bits

Shift

26 bits

Shift

64 bits

Latch

Circuit

Static

Driver

Common

Driver

Segment

Driver

LCD

Driver

Voltage

Selector

COMSA SEGSA~E

COM1~ COM24

COM S1 COM S2

SEG1~ SEG60

SEGS1,2

4,5

VDD

GND

(VSS)

5 5

Segment Data Conversion

LCD Driving Power Circuit

Voltage Converter Voltage Regulator Voltage Follower &

Bias Resistor

CAP1+ CAP1- CAP2+ CAP2- VOUT V0 VR V0 V1 V2 V3 V4 BID

Figure 1. Block Diagram

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

.....

188

.....

108

PAD CONFIGURATION

...........................

(0,0)

...........................

Figure 2. Pad Configuration

Table 1. S6A0090 Pad Dimensions

Item

Pad No.

(location)

Chip size - 7410 2470

Pad size 1 to 188 60 118

Bumped pad size 1 to 188 56 114

Bumped pad height 1 to 188

Left, right top 150 150

Left bottom 90 90Align key size

Right bottom 90 90

Size

X Y

17 ± 1.5

DUMMY PAD

PAD

Unit

µm

COG Align Key Coordinate ILB Align Key Coordinate

30µm 30µm 30µm

(-3479, -1110)

30µm 30µm 30µm

(+3479, -1125)

42µm 108µm

(-3535, +1119)

42µm108µm

(+3535, +1119)

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: µm]

Pad

No.

1 DUMMY -3540 880 31 DB5 -2430 -1111 61 CAP2- 270 -1111 2 DUMMY -3540 790 32 DB4 -2340 -1111 62 CAP2- 360 -1111 3 COM21 -3540 700 33 DB3 -2250 -1111 63 CAP2- 450 -1111 4 COM20 -3540 610 34 DB2 -2160 -1111 64 CAP2- 540 -1111 5 COM19 -3540 520 35 DB1 -2070 -1111 65 CAP2+ 630 -1111 6 COM18 -3540 430 36 DB0 -1980 -1111 66 CAP2+ 720 -1111 7 COM17 -3540 340 37 VDD -1890 -1111 67 CAP2+ 810 -1111 8 COM16 -3540 250 38 VDD -1800 -1111 68 CAP2+ 900 -1111

9 COM15 -3540 160 39 VDD -1710 -1111 69 CAP1- 990 -1111 10 COM14 -3540 70 40 VSS -1620 -1111 70 CAP1- 1080 -1111 11 COM13 -3540 -20 41 VSS -1530 -1111 71 CAP1- 1170 -1111 12 COM12 -3540 -110 42 VSS -1440 -1111 72 CAP1- 1260 -1111 13 COM11 -3540 -200 43 V4 -1350 -1111 73 CAP1+ 1350 -1111 14 COM10 -3540 -290 44 V4 -1260 -1111 74 CAP1+ 1440 -1111 15 COM9 -3540 -380 45 V3 -1170 -1111 75 CAP1+ 1530 -1111 16 COMS2 -3540 -470 46 V3 -1080 -1111 76 CAP1+ 1620 -1111 17 SEGSA -3540 -560 47 V2 -990 -1111 77 VSS 1710 -1111 18 SEGSB -3540 -650 48 V2 -900 -1111 78 VSS 1800 -1111 19 SEGSC -3540 -740 49 V1 -810 -1111 79 VSS 1890 -1111 20 SEGSD -3540 -830 50 V1 -720 -1111 80 BID 1980 -1111 21 SEGSE -3540 -920 51 V0 -630 -1111 81 VDD 2070 -1111 22 DUMMY -3240 -1111 52 V0 -540 -1111 82 VDD 2160 -1111 23 DUMMY -3150 -1111 53 V0 -450 -1111 83 VDD 2250 -1111 24 DUMMY -3060 -1111 54 V0 -360 -1111 84 CK 2340 -1111 25 DUMMY -2970 -1111 55 VR -270 -1111 85 VDD 2430 -1111 26 RS -2880 -1111 56 VR -180 -1111 86 PS 2520 -1111 27 E -2790 -1111 57 VOUT -90 -1111 87 IF 2610 -1111 28 CSB -2700 -1111 58 VOUT 0 -1111 88 RES 2700 -1111 29 DB7 -2610 -1111 59 VOUT 90 -1111 89 VDD 2790 -1111 30 DB6 -2520 -1111 60 VOUT 180 -1111 90 VDD 2880 -1111

Pad

Name

Coordinate Coordinate Coordinate

X Y

Pad

No.

Pad

Name

X Y

Pad

No.

Pad

Name

X Y

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

Table 2. Pad Center Coordinates (Continued)

[Unit: um]

Pad

No.

Pad

Name

Coordinate Coordinate Coordinate

X Y

Pad

No.

Pad

Name

X Y

Pad

No.

Pad

Name

X Y

91 DUMMY 2970 -1111 124 SEG4 2520 1070 157 SEG37 -450 1070 92 DUMMY 3060 -1111 125 SEG5 2430 1070 158 SEG38 -540 1070 93 DUMMY 3150 -1111 126 SEG6 2340 1070 159 SEG39 -630 1070 94 DUMMY 3240 -1111 127 SEG7 2250 1070 160 SEG40 -720 1070 95 DUMMY 3540 -920 128 SEG8 2160 1070 161 SEG41 -810 1070 96 DUMMY 3540 -830 129 SEG9 2070 1070 162 SEG42 -900 1070 97 DUMMY 3540 -740 130 SEG10 1980 1070 163 SEG43 -990 1070 98 DUMMY 3540 -650 131 SEG11 1890 1070 164 SEG44 -1080 1070

99 DUMMY 3540 -560 132 SEG12 1800 1070 165 SEG45 -1170 1070 100 COMSA 3540 -470 133 SEG13 1710 1070 166 SEG46 -1260 1070 101 COMS1 3540 -380 134 SEG14 1620 1070 167 SEG47 -1350 1070 102 COM1 3540 -290 135 SEG15 1530 1070 168 SEG48 -1440 1070 103 COM2 3540 -200 136 SEG16 1440 1070 169 SEG49 -1530 1070 104 COM3 3540 -110 137 SEG17 1350 1070 170 SEG50 -1620 1070 105 COM4 3540 -20 138 SEG18 1260 1070 171 SEG51 -1710 1070 106 COM5 3540 70 139 SEG19 1170 1070 172 SEG52 -1800 1070 107 COM6 3540 160 140 SEG20 1080 1070 173 SEG53 -1890 1070 108 COM7 3540 250 141 SEG21 990 1070 174 SEG54 -1980 1070 109 COM8 3540 340 142 SEG22 900 1070 175 SEG55 -2070 1070 110 COMS1 3540 430 143 SEG23 810 1070 176 SEG56 -2160 1070 111 DUMMY 3540 520 144 SEG24 720 1070 177 SEG57 -2250 1070 112 DUMMY 3540 610 145 SEG25 630 1070 178 SEG58 -2340 1070 113 DUMMY 3540 700 146 SEG26 540 1070 179 SEG59 -2430 1070 114 DUMMY 3540 790 147 SEG27 450 1070 180 SEG60 -2520 1070 115 DUMMY 3540 880 148 SEG28 360 1070 181 SEGS4 -2610 1070 116 DUMMY 3240 1070 149 SEG29 270 1070 182 SEGS5 -2700 1070 117 DUMMY 3150 1070 150 SEG30 180 1070 183 COM24 -2790 1070 118 DUMMY 3060 1070 151 SEG31 90 1070 184 COM23 -2880 1070 119 SEGS1 2970 1070 152 SEG32 0 1070 185 COM22 -2970 1070 120 SEGS2 2880 1070 153 SEG33 -90 1070 186 DUMMY -3060 1070 121 SEG1 2790 1070 154 SEG34 -180 1070 187 DUMMY -3150 1070 122 SEG2 2700 1070 155 SEG35 -270 1070 188 DUMMY -3240 1070 123 SEG3 2610 1070 156 SEG36 -360 1070

* NOTE: The COMS1 has two terminals (#101, #110), and these two COMS1 are the same signal at the same time

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

PIN DESCRIPTION

POWER SUPPLY

Table 3. Pin Description

Name I/O Description

VDD

VSS

V0 V1 V2 V3 V4

Power

I/O

LCD DRIVER SUPPLY

Name I/O Description

CAP1+ O

CAP1- O

CAP2+ O

CAP2– O

VOUT I/O

VR I

Power supply Connect to MPU power supply pin 0V (GND)

Bias voltage level for LCD driving Voltages should have the following relationship; V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS When the built-in power circuit is on, the following voltages are given to pins V1 to V4 by internal 1/5 bias resistors are used.

LCD bias V1 V2 V3 V4

(1/5) bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0

Table 3. Pin Description (continued)

Capacitor 1+ connecting pin for the internal voltage converter This pin connects the capacitor with CAP1-. Capacitor1- connecting pin for the internal voltage converter This pin connects the capacitor with CAP1+. Capacitor 2+ connecting pin for the internal voltage converter When VOUT is 2 times boosting, this pin connects the capacitor with VDD, when 3 times boosting, this pin connects the capacitor with CAP2Capacitor2- connecting pin for the internal voltage converter When VOUT is 2 times boosting, this pin is not used, when 3 times boosting, this pin connects the capacitor with CAP2+ 2 or 3 times DC/DC voltage converter output This pin connects a capacitor with VDD pin. Voltage adjust pin This pin gives a voltage between V0 and VSS by resistance-division of voltage.

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

SYSTEM CONTROL

Table 3. Pin Description (continued)

Name I/O Description

External clock input pin

CK I

PS I

IF I

BID I

It must be fixed to "High" when the internal oscillation circuit is used. In the external clock mode, it is used as external clock input pin. Parallel / serial selection pin When PS = "Low": serial mode When PS = "High": 4-bit/8-bit bus mode Interface data length selection pin for parallel data input When PS = "Low" IF = "Low " or "High": serial interface mode When PS = “High” IF = "Low": 4-bit bus mode IF = "High": 8-bit bus mode SEG direction selection pin When BID = "Low";

SEGS1 → SEGS2 → SEG1 → ...... → SEG60 → SEGS4 → SEGS5

When BID = "High";

SEGS5 → SEGS4 → SEG60 → ...... → SEG1 → SEGS2 → SEGS1

MPU INTERFACE

Name I/O Description

RES I

CSB I

RS I

Table 3. Pin Description (continued)

Initialization is performed by edge sensing of the RES signal. An interface type for the 68/80 series MPU is selected by input level after initialization. When RES = "Low": 68 series MPU When RES = "High": 80 series MPU Chip selection pin When CSB = "Low": selected When CSB = "High": not selected Register selection pin When RS = "Low": instruction register When RS = "High": data register

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

Table 3. Pin Description (Continued)

Name I/O Description

In 80 series MPU interface mode, active "Low". This pin connects the WR pin of the 80 series MPU.

E I

DB0 to DB3 DB4 to DB5

DB6 (SCL)

DB7 (SI)

The signal on the data bus is fetched at the rise of the WR signal. In 68 series MPU interface mode, active "High". This pin becomes an enable clock input of the 68 series MPU. When in 8-bit interface mode, DB0 to DB7 are used as input data bus pin In the 4-bit bus mode, only DB4 to DB7 are used as data input pin and DB0 to DB3 are not used. In the serial mode, DB6 (SCL) is used as serial clock input pin, DB7 (SI) is used as serial data input pin and the others are not used.

LCD DRIVER OUTPUTS (DYNAMIC)

Table 3. Pin Description

Name I/O Description

COM1 to COM24 O

COMS1, COMS2 O

SEG1 to SEG60 O SEGS1, SEGS2 SEGS4, SEGS5

Common signal output for character display Common signal output for icon display

The COMS1 has two terminals and these two COMS1 are the same signal at the same time.

Segment signal output for character display Segment signal output for vertical icon display

LCD DRIVER OUTPUTS (STATIC)

Table 3. Pin Description (continued)

Name I/O Description

COMSA O Static common signal output for static icon display

SEGSA, B, C, D, E O Static segment signal output for static icon display

* NOTE: DUMMY - These pins should be opened (floated).

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

FUNCTION DESCRIPTION

SYSTEM INTERFACE

S6A0090 has two kinds of interface type with MPU: bus mode and serial mode. Bus mode or serial mode is selected by PS pin. In bus mode, 4-bit bus or 8-bit bus is selected by IF pin, and 68 series MPU or 80 series MPU is selected by RES pin.

Table 4. Various kinds of MPU interface according to PS, RES and IF

PS RES IF CSB RS E DB0 to 3 DB4 to 5 DB6 DB7

80 series

Bus

mode (H)

Serial

mode (L)

"*": Don't care ("High", "Low" or "Open"), (H)/(L): fixed "High"(VDD) or "Low"(VSS)

PS: "High" = bus mode, "Low" = serial mode RES: "High" = 80-series MPU, "Low" = 68-series MPU IF: "High" = 8-bit mode, "Low" = 4-bit mode (PS: "High") CSB: "High" = chip is not selected, "Low" = chip is selected RS: "High" = data register, “Low" = instruction register E: 80-series active "Low", 68-series active "High" SCL (DB6): serial clock input SI (DB7): serial data input

Interface with MPU in Parallel Mode (PS = "High")

During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM / ICONRAM, and one of these RAMs is selected by RAM address setting instruction. The Instruction register (IR) is used only to store instruction code transferred from MPU. To select DR or IR register, RS input pin is used in bus mode or serial mode. In 4-bit bus mode, it is needed to transfer 4-bit data (DB4 to DB7) by two times. The high order bits (for 8-bit mode DB4 to DB7) are transferred before the low order bits (for 8-bit mode DB0 to DB3). The DB0 to DB3 pins are floated in this 4-bit bus mode. After RES resets, S6A0090 considers first 4-bit data from MPU as the high order bits.

(H)

68 series

(L)

(H)/(L) (H)/(L) CSB RS (H)/(L) * * SCL SI

8 bit (H) CSB RS WR DB0 to 3 DB4 to 5 DB6 DB7

4 bit (L) CSB RS WR * DB4 to 5 DB6 DB7

8 bit (H) CSB RS E DB0 to 3 DB4 to 5 DB6 DB7

4 bit (L) CSB RS E * DB4 to 5 DB6 DB7

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

Write

RES

CSBRSE

DB0 to DB7

4-bit

4-bi

4-bit

RES CSB

DB0 to DB7

Instruction

Write

Data

Write

Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)

RES CSB

to DB7

Instruction

Data

Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)

upper

lower

upper

lower

Instruction Write Data Write

Figure 5. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

RES

CSB

DB0 to DB7

4-bit

upper

lower

upper

lower

Instruction Write Data Write

Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

D7D6D5D4D3D2D1D0D7

123456789

Interface with MPU in Serial Mode (PS = "Low")

When PS input pin is "Low", clock synchronized serial interface mode is selected. At this time, five ports, SCL (DB6, synchronizing transfer clock), SI (DB7, serial input data), RS (register selection input) and CSB (chip selection input) are used. By setting CSB to "Low", S6A0090 can receive SCL input. If CSB is set to "High", S6A0090 resets the internal 8-bit shift register and 3-bit counter. Serial data is input in the order of "D7, D6, D5, D4, D3, D2, D1, D0" from the serial data input pin (SI = DB7) at the rising edge of serial clock (SCL = DB6). At the rising edge of the 8th serial clock, the serial data (D7–D0) is converted into 8-bit bus mode data. The RS input of the DR / IR selection is latched at the rising edge of the 8th serial clock (SCL).

CSB

SI (DB7)

SCL (DB6)

Figure 7. Timing Diagram of Serial Data Transfer

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

(2)3linemodeDDRAMAddres

ADDRESS COUNTER (AC)

Address Counter (AC) in S6A0090 stores CGRAM / DDRAM / ICONRAM address, transferred from IR. After writing into CGRAM / DDRAM / ICONRAM, AC is automatically increased by 1.

DISPLAY DATA RAM (DDRAM)

DDRAM stores display data of maximum 36 x 8-bits (Max. 36 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number.

1st ch. 12th ch.

COM1

30 31 32 33 34 35 36 37 38 39 3A 3B 3C

COM8

COM9

COM16

40 41 42 43 44 45 46 47 48 49 4A 4B 4C

SEG1

(1) 2 line mode DDRAM Address

1st ch. 12th ch.

COM1

30 31 32 33 34 35 36 37 38 39 3A 3B 3C

COM8

COM9

40 41 42 43 44 45 46 47 48 49 4A 4B 4C

SEG60

SEGS1,2 SEGS4,5

COM17 COM24

50 51 52 53 54 55 56 57 58 59 5A 5B 5C

SEG1

SEG60

Figure 8. DDRAM Address

SEGS1,2 SEGS4,5

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

CHARACTER GENERATOR ROM (CGROM)

S6A0090 has the Character Generator ROM (CGROM) consisted of up to 256 types of characters. Character size is 5 x 8 dots. The CG bit of the instruction table selects the 4 characters (00h to 03h) of CGROM or CGRAM. S6A0090 CGROM is contact mask option ROM and compatible with customized ROM font.

Table 5. CGROM Character Code Table (00)

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

CHARACTER GENERATOR RAM (CGRAM)

CGRAM contained in S6A0090 enables user to program of character pattern for display signal. When using CGRAM, the CG bit should be selected to “High”. CGRAM has up to four 5 x 8-dot characters. By writing font data to CGRAM, user defined character can be used.

Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)

Character code

(DDRAM data)

CGRAM address

CGRAM data

(character pattern)

D7 D6 D5 D4 D3 D2 D1 D0 A6 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0

0 0 0 0 0 0 0 0

(00h)

0 0 0 0 0 0 0 1

(01h)

0 0 0 0 0 0 1 0

(02h)

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1

0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1

0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 0 1 0 1 1 1

– – – 0 1 0 1 0 – – – 1 0 1 0 1 – – – 0 1 0 1 0 – – – 1 0 1 0 1 – – – 0 1 0 1 0 – – – 1 0 1 0 1 – – – 0 1 0 1 0 – – – 1 0 1 0 1

– – – 0 0 0 0 0 – – – 1 1 1 1 1 – – – 0 0 0 0 0 – – – 1 1 1 1 1 – – – 0 0 0 0 0 – – – 1 1 1 1 1 – – – 0 0 0 0 0 – – – 1 1 1 1 1

– – – 0 1 0 1 0 – – – 0 1 0 1 0 – – – 0 1 0 1 0 – – – 0 1 0 1 0 – – – 0 1 0 1 0 – – – 0 1 0 1 0 – – – 0 1 0 1 0 – – – 0 1 0 1 0

Pattern

number

Pattern 1

Pattern 2

Pattern 3

0 0 0 0 0 0 1 1

(03h)

0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1

– – – 0 1 0 1 0 – – – 0 1 0 1 0 – – – 1 0 1 0 1 – – – 1 0 1 0 1 – – – 0 1 0 1 0 – – – 0 1 0 1 0 – – – 1 0 1 0 1 – – – 1 0 1 0 1

Pattern 4

("–": Don't care)

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

SEGMENT ICON RAM (ICONRAM)

ICONRAM has Segment Control Data and Segment Pattern Data

…… ……

COMS1

COMS2

S61

S E G S 1

S E G S 2

S E G 4

S5 S65

S E G 5

S6 S10 S1

S66 S70

……

S116

1 0

Figure 9. Relationship between ICONRAM and Icon Display

Table 7. Relationship between ICONRAM Address and Display Pattern

ICONRAM address ICONRAM bits

High order

Low

order

D7 D6 D5 D4 D3 D2 D1 D0

0 - - - S1 S2 S3 S4 S5 1 - - - S6 S7 S8 S9 S10

: : :

: :

A - - - S51 S52 S53 S54 S55

S56 S60 S11 S15

S120 S71 S75

: :

B - - - S56 S57 S58 S59 S60

C - - - SEGS1 SEGS2 - SEGS4 SEGS5

0 - - - S61 S62 S63 S64 S65 1 - - - S66 S67 S68 S69 S70

: :

: A - - - S111 S112 S113 S114 S115 B - - - S116 S117 S118 S119 S120 C - - - SEGS1 SEGS2 - SEGS4 SEGS5

("–": Don't care)

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

Example) RAM Address = 3Ch, Data = 41h (CGROM Font = "A")

∅∆∇

⊗

STATIC ICON RAM (SI)

S6A0090 contains the Static Icon RAM for displaying the static icons in addition to the dynamic icons. Capacity of static icon RAM is 10 bits and is capable of displaying up to 5 icons. The following table shows relationship between the static icon functions, Static Icon RAM address and written data. (blink frequency: 1 to 2 Hz)

Table 8. Relationship between Static Icon RAM Address and Display Pattern

Static icon data Static icon

(A)D3(B)D2(C)D1(D)D0(E)

Function

Display

ON / OFF

Blink

ON / OFF

RAM

address

D7 D6 D5

20h - - - 0 1 0 1 0 21h - - - 1 1 1 0 0

20h = "0": static icon OFF "1": static icon ON

21h = "0": blink OFF "1": blink ON (20h data are inverted)

SEGMENTS FOR SIGNAL DISPLAY (FS)

When DDRAM address is 3Ch: COM1 to COM8, 1-line 4Ch: COM9 to COM16, 2-line 5Ch: COM17 to COM24, 3-line

SEGS1: font 1st bit display SEGS2: font 2nd bit display SEGS4: font 4th bit display SEGS5: font 5th bit display (Font 3rd bit is not displayed.)

SEGS-A B C D E

COMSA

S E G S 1

S E G S E

SEGS1 SEGS2

COM1

: : :

COM8

Figure 10. Segment for Signal Display

SEGS4 SEGS5

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

LOW POWER CONSUMPTION MODE

S6A0090 provides with standby mode and sleep mode for saving power consumption during standby period.

Standby Mode (Power Save Bit ON, Oscillation Bit ON)

The Standby mode can be switched according to the power save command. In the Standby mode, only static icon is displayed.

1. Liquid Crystal Display Output COM1 to COM24, COMS1, COMS2: VSS level SEG1 to SEG60, SEGS1, 2, 4, 5: VSS level SEGSA, B, C, D, E, COMSA: VDD or VSS level (can be turned on/off by static drivers) Use the static icon RAM for controlling the static icon display done with SEGSA, B, C, D, E, COMSA.

2. Written data in DDRAM, CGRAM, ICONRAM and registers remain at its previous value.

3. Operation mode is retained the same as it was prior to execution of the standby mode. The internal circuit for the dynamic display output is stopped.

4. The oscillation circuit for the static display must remain ON.

Sleep Mode (Power Save ON, Oscillation OFF)

To enter the Sleep Mode, the power circuit and oscillation circuit should be turned off by power save command and power control command. This mode helps to save power consumption by reducing current to reset level.

1. Liquid Crystal Display Output COM1 to COM24, COMS1, COMS2: VSS level SEG1 to SEG60, SEGS1, 2, 4, 5: VSS level SEGSA, B, C, D, E, COMSA: VSS level

2. Written data in DDRAM, CGRAM, ICONRAM and registers remain at its previous value.

3. Operation mode is retained the same as it was prior to execution of the sleep mode. All internal circuits are stopped.

4. Power Circuit and Oscillation Circuit The built-in power supply circuit and oscillation circuit are turned off by power save command and power control command.

LCD DRIVER CIRCUIT

LCD driver circuit has 26 common and 64 segment signals for driving LCD. Data from ICONRAM / CGRAM / CGROM are transferred to 64-bit segment register serially, and then they are stored to 64-bit latch. For 2-line display mode, COM1 to COM16, COMS1, COMS2 have 1/18 duty, and in 3-line mode, COM1 to COM24, COMS1, COMS2 have 1/26 duty ratio. SEG bi-directional function is selected by BID input pin, and COM shift direction is selected by function set instruction "S" bit.

Table 9. SEG Data Shift Direction

BID pin SEG data shift direction

Low

SEGS1 → SEGS2 → SEG1 → ...... → SEG60 → SEGS4 → SEGS5

High

SEGS5 → SEGS4 → SEG60 → ...... → SEG1 → SEGS2 → SEGS1

Page 24

S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

INSTRUCTION DESCRIPTION

Table 10. Instruction Table

Instruction

Description

RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction code

Return

home

0 0 0 0 1 – – – –

DDRAM address is set to "30h" from AC and cursor returns to “30h” position if shifted. The contents of DDRAM are not changed.

Cursor / blink / display ON / OFF

Display

control

0 0 0 1 1 C B – D

C = 0: cursor OFF (default), C = 1: cursor ON B = 0: blink OFF (default), B = 1: blink ON D = 0: display OFF (default), D = 1: display ON

Power save / oscillation circuit

Power

save

0 0 1 0 0 – – OS PS

OS=0: oscillator OFF (default), OS=1: oscillator ON PS=0: power save OFF (default),

PS=1: power save ON LCD power control

VR = 0: voltage regulator OFF (default),

Power

control

0 0 1 0 1 0 VR VF VC

1: voltage regulator ON VF = 0 : voltage follower OFF (default), 1: voltage follower ON VC = 0: voltage converter OFF (default), 1: voltage converter ON

Display line mode N2, N1 = 0, 0: 2-line display mode (default), 0, 1: 3-line display mode

Function

set

0 0 1 1 0 N2 N1 S

Set shifting direction of COM S = 0: COM left shift (COM1 → COM24) (default),

1: COM right shift (COM24 → COM1) Select CGRAM or CGROM CG = 0: use CGROM (default), 1: use CGRAM

RAM

address

0 1

AC6 AC5 AC4 AC3 AC2 AC1 AC0

DDRAM / CGRAM / ICONRAM or register address

set

Write

data

mode

Test

mode

* NOTE1: For the NOP instruction, when EV mode is "0" (32 contrast-step), the NOP instruction set is (000000000), when EV mode is "1" (64 contrast-step), the NOP instruction set is (000000001). * NOTE2: Instruction execution time depends on the internal process time of S6A0090, therefore it is necessary to provide a time larger than one MPU interface cycle time (tc) between execution of two successive instructions.

1 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 EV

0 0 0 0 0 * * * *

("–": Don’t care, "*": Don’t use)

Write DDRAM / CGRAM / ICONRAM or register data

Electronic volume step EV = 0: 32 contrast-step (default), 1: 64 contrast-step

Instruction for IC chip test Don't use this instruction.

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

Return Home

Return Home instruction field makes cursor return home. DDRAM address is set to "30h" into the address counter. Return cursor to first digit of the first line. Contents of DDRAM are not changed.

RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 – – – –

("–": Don't care)

Display Control

Display Control instruction field controls cursor / blink / display ON / OFF.

RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 1 C B – D

("–": Don't care)

C: Cursor ON / OFF control bit When C = "High", cursor is turned ON. When C = "Low", cursor is disappeared in current display, and can't blink (default).

B: Cursor blink ON / OFF control bit When C = "High" and B = "High", S6A0090 makes LCD alternate between inverting display character and normal display character at the cursor position with about a half second. On the contrary, if C = "Low", only a normal character is displayed regardless of "B" flag. When B = "Low", blink is OFF (default).

D: Display ON / OFF control bit When D = "High", entire display is turned ON When D = "Low", display is turned OFF, but display data remain in DDRAM (default).

* NOTE: Static icons driven by COMSA and SEGSA / B / C / D / E must be controlled by the static icon RAM.

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

Power Save

Power Save instruction field is used to control the oscillator and to control Power Save mode.

RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 0 – – OS PS

("–": Don't care) OS: Oscillator ON / OFF control bit When OS = "High", oscillator circuit is turned ON. When OS = "Low", oscillator is turned OFF (default).

PS: Power save ON / OFF control bit When PS = "High", power save mode is turned ON. When PS = "Low", power save mode is turned OFF (default).

Power Control

Power Control instruction field sets voltage regulator / follower / converter ON / OFF.

RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 VR VF VC

VR: Voltage regulator circuit control bit When VR = "High", voltage regulator is turned ON. When VR = "Low", voltage regulator is turned OFF (default).

VF: Voltage follower circuit control bit When VF = "High", voltage follower is turned ON. When VF = "Low", voltage follower is turned OFF (default).

VC: Voltage converter circuit control bit When VC = "High", voltage converter is turned ON. When VC = "Low", voltage converter is turned OFF (default).

* NOTE: The oscillator circuit must be turned on for the voltage converter circuit to be active.

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

Function Set

RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 0 N2 N1 S CG

N2, N1: Display line mode instruction field select 2-line or 3-line display mode. When N2, N1 = "Low, Low", 2-line display mode (default) When N2, N1 = "Low, High", 3-line display mode S: Data shift direction of common. When S = "High", COM right shift (default) When S = "Low", COM left shift

Line

mode

2-line mode

3-line mode

S COM data shift direction

0 (left)

1 (right)

0 (left)

1 (right)

COM1 → ......→ COM15 → COM16 → COMS1 → COMS2 → COM1

COM16 → COM15 →......→ COM1 → COMS1 → COMS2 → COM16

COM1 → ......→ COM23 → COM24 → COMS1 → COMS2 → COM1

COM24 → COM23 →......→ COM1 → COMS1 → COMS2 → COM24

CG: CGRAM enable bit When CG = "High", CGRAM can be accessed and you can use this RAM as a four special character area. (00h to 03h = CGRAM font display). When CG = "Low", CGRAM is disabled. CGROM (00h to 03h) can be accessed and additional current consumption is saved by using this mode (default), (00h to 03h = CGROM font display).

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

RAM Address Set

RAM Address set instruction field sets CGRAM / DDRAM / ICONRAM or register address. Each RAM is distinguished by a RAM address. Before writing data into the RAM, set the address by RAM address set instruction. Next, when data are written in succession, the address is automatically increased by 1.

RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

Address 0 1 2 3 4 5 6 7 8 9 A B C D E F

00h CGRAM (00h) CGRAM (01h) 10h CGRAM (02h) CGRAM (03h) 20h SI Unused EV TE Unused 30h DD RAM 1-line (30h to 3Bh) FS 40h DD RAM 2-line (40h to 4Bh) FS 50h DD RAM 3-line (50h to 5Bh) FS 60h ICONRAM COMS1 icon (60h to 6Ch) 70h ICONRAM COMS2 icon (70h to 7Ch)

SI: static icon register (20h, 21h)

It is used for SEGS / B / C / D / E. EV: electronic volume register (28h) TE: test register (29h) (Do not use) FS: for signals - 1-line (3Ch), 2-line (4Ch), 3-line (5Ch). It is used for SEGS1 / 2 / 4 / 5

Unused

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

Write Data

This instruction field makes S6A0090 write binary 8-bit data to DDRAM/CGRAM/ICONRAM or register. The RAM address to be written into is determined by the previous RAM Address Set Instruction. After writing operation, the address is automatically increased by 1.

RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 D7 D6 D5 D4 D3 D2 D1 D0

EV Mode

This instruction field selects between 2 electronic volume steps: 32 and 64 contrast-steps.

RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 EV

When EV = “Low", S6A0090 selects 32 contrast-step (default) Electronic volume register (28h) =

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

– – – C4 C3 C2 C1 C0

When EV = "High", S6A0090 selects 64 contrast-step. Electronic volume register (28h) =

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

– – C5 C4 C3 C2 C1 C0

("–": Don't care)

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

INITIALIZING & POWER SAVE MODE SETUP

HARDWARE RESET

After reset by RES pin, S6A0090 can be initialized the following state.

Control Display ON / OFF Instruction

C = 0: cursor OFF B = 0: blink OFF D = 0: display OFF

Power Save Set Instruction

OS = 0: oscillator OFF PS = 0: power save OFF

Power Control Set Instruction

VR = 0: voltage regulator OFF VF = 0: voltage follower OFF VC = 0: voltage converter OFF

Function Set Instruction

N2 = 0, N1 = 0: 2-line display mode S = 0: COM left shift CG = 0: CGRAM is not used.

Return Home

Address counter = 30h

Static icon RAM & Electronic Contrast Control Register

Static icon RAM: 20h = (0, 0, 0, 0, 0), static icon OFF 21h = (0, 0, 0, 0, 0), blink OFF EV = 0: 32 contrast-step Electronic contrast control register: 28h = ((0), 0, 0, 0, 0, 0), contrast high

In Case of 4-bit Interface Mode, S6A0090 considers the First 4-bit Data from MPU as the High Order Bits.

*NOTE: If initialization is not done by the RES pin at application, an unknown condition may result. Then you can initialize by instruction.

VDD

RE S

Reset time tR 1us

Reset p ulse width tRW 10us

Re set start time t

2.4V t

RES

tR W tR

RES

50ns

Figure 11. Reset Timing

* NOTE: tR (reset time) indicates the internal circuit reset completion time from the edge of the RES signal Accordingly, the S6A0090 usually enters the operating state after tR. Specifies the minimum pulse width of the RES signal. It is reset when a signal having the pulse width greater than TRW is entered.

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

INITIALIZING AND POWER SAVE MODE SETUP

Initializing by Instruction

Power ON

Waiting for Stabilizing the Power

Input of Reset Signal (RES Pin)

Command Status Initializing by Hardware Reset Input Status Others are undefined.

Waiting for 10us or more

Command Input: (Asterisk indicates any command sequence.)

1. Function Setup Command (N2, N1, S, CG)

2. Electronic Volume Register Setup (28h) . Data: ((*), *, *, *, *, *)

3. Power Save Set Command . PS: OFF (Power Save) . OS: ON (Oscillation)

4. Power Control Set Command . VR, VF, VC: ON

5. RAM Address Set Command

6. Data Writing (RAM Clear) (DDRAM = 20h, CGRAM / ICONRAM = 00h)

Waiting for 20ms or more

Command Input

7. Display Control Commands . D: ON

* Note: At command (5) and (6), the internal RAM should be cleared. To clear DDRAM and FS (segment for signal)

-Set address at 30h (first DDRAM) and then write 20h (space character code) 13 times

-Set address at 40h and write 20h for 13 times

-Set address at 50h and write 20h for 13 times

To clear CGRAM,

-Set address at 00h (first CGRAM) and then write 00h (null data) 32 times

To clear ICONRAM,

-Set address at 60h (first ICONRAM) and then write 00h (null data) 13 times

-Set address at 70h and write 00h for 13 times

Data Input

8. Static Icon Display Commands 20h: (*, *, *, *, *) 21h: (*, *, *, *, *)

End of Initialization

Figure 12. Initializing by Instruction

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

Standby Mode Set or Release by Instruction

End of Initialization

Normal Operation Status

(Power save is released (OFF) and oscillator is turned ON.)

Command Input

1. Display Control (D: OFF)

2. Power Save (PS: Power Save ON, OS: OSC ON)

3. Power Control (VR, VF, VC are all OFF)

Standby Status

1. Power Save (PS: Power Save OFF, OS: OSC ON)

2. Power Control (VR, VF, VC are all ON)

3. Display Control (D: ON)

Standby mode

Command Input

Waiting for 20ms or more

Command Input

Return to Normal Operation

Figure 13. Standby Mode Set Figure 14. Standby Mode Release

Sleep Mode Set or Release by Instruction

End of Initialization

Sleep Mode

Normal Operation

(Power save is released (OFF) and oscillator is turn ON.)

Command Input

1. Display Control (D: OFF)

2. Power Save (PS: Power Save ON, OS: OSC OFF)

3. Power Control (VR, VF, VC are all OFF)

Enter the Sleep Mode

Command Input

1. Power Save (PS: Power Save OFF, OS: OSC ON)

Command Input

3. Display Control (D: ON)

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

[VC, VR, VF = 1, 1, 1]

Recommendation of Power ON / OFF Sequence

a) Power ON Sequence

Power ON

Voltage Converter ON

Waiting for ≥ 1ms

Voltage Regulator ON

[VC, VR, VF = 1, 1, 0]

Waiting for ≥ 1ms

Voltage Follower ON

b) Power OFF Sequence

Operation Command Input

Display OFF

Voltage Regulator OFF

[VC, VR, VF = 1, 0, 1]

Waiting for ≥ 50ms

Voltage Follower OFF

[VC, VR, VF = 1, 0, 0]

Waiting for ≥ 1ms

Voltage Converter OFF

[VR, VF, VC = 0, 0, 0]

Waiting for ≥ 1ms

Operation Command Input

Page 34

S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

LCD DRIVING POWER SUPPLY CIRCUIT

The Power Supply Circuit produces LCD panel driving voltage at low power consumption. The LCD driving power supply circuit consists of voltage converter (2 times or 3 times), voltage regulator and voltage follower. It is controlled by set power control instruction. The following table shows how the LCD driving power supply circuit works by power control instruction sets.

Table 11. Power Supply Control Mode Set

VC VR VF

1 1 1 Enable Enable Enable

0 1 1 Disable Enable Enable

0 0 1 Disable Disable Enable Open Open

0 0 0 Disable Disable Disable Open Open

* NOTE: SEC recommendation is to use only the case listed above table.

Voltage

converter

Voltage

regulator

Voltage

follower

VOUT pin VR pin

Internal voltage

output

External

voltage

input

Used for

voltage

adjustment

Used for

voltage

adjustment

V0, V1, V2,

V3, V4 pin

Internal voltage output

V1 to V4: internal voltage

output

V0: external voltage input

V0 to V4: external voltage

input

Page 35

64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

-+-

VOLTAGE CONVERTER

If capacitors are connected between CAP1+ and CAP1-, CAP2+ and CAP2-, VDD and VOUT, VDD- VSS voltage is positively tripled and generated at VOUT terminal. When the voltage is doubled, open CAP2- and connect CAP2+ to VOUT terminal. This boosted voltage is used in the built-in voltage regulator circuit.

VDD

C1 C1

CAP1+ CAP1CAP2 CAP2VOUT

Figure 17. Two Times Boosting

VDD

CAP1+ CAP1-

CAP2 CAP2VOUT

VOUT

VDD

VSS

VOUT

VDD

2 × VDD

3 × VDD

VSS

Figure 18. Three Times Boosting

Page 36

S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

VOLTAGE REGULATOR

The Voltage Regulator circuit is used to obtain an appropriate LCD panel driving voltage. This voltage is obtained by adjusting resistors Ra and Rb as shown in equation (1), and by setting electronic contrast control data bits, see equation (1), (2)

The potential of V0 pin can be adjusted within VREF to VOUT. VREF is the internal constant voltage source of the chip and this value is 2.0V in the condition VDD ≥ 2.4V

Voltage regulation by adjusting resistors Ra, Rb Rb

V0 = ( 1 + ---------- ) × VREF – – – – – – – (1) Ra

The internal VREF of the voltage regulator has the temperature compensation function, and the temperature coefficient is approximately –0.05%/oC.

GND

VOUT

VREF

Inside Chip

VSS

Figure 19. Voltage Regulator Circuit

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

For example,

Electronic Contrast Control (EV = 0, 32 Steps)

For 32 contrast-step, EV flag of EV set mode instruction field should be set to "Low", and then, Electronic Contrast Control data bits 28h = (C4, C3, C2, C1, C0) can be valid. Voltage regulation is adjusted as 32-contrast step according to the value of electronic contrast control data bits. LCD drive voltage V0 has one of 32 voltage values if 5-bit data is set to the Electronic Contrast Control register (RAM address 28h).

When using the Electronic Contrast Control function, you need to turn the voltage regulator on using power control instruction. Rb V0 = ( 1 + ------------ ) × VEV – – – – – – – (2) Ra

VEV = VREF – nα (n = 0, 1, 2, ......, 30, 31)

Ra = 1 [MΩ], Rb = 2 [MΩ], n = 0 then V0 = 6V

α = VREF / 150

Table 12. Electronic Contrast Control Register (32 steps)

No. C7 C6 C5 C4 C3 C2 C1 C0

1 - - - 0 0 0 0 0 2 - - - 0 0 0 0 1 3 - - - 0 0 0 1 0 4 - - - 0 0 0 1 1

. . .

. 31 - - - 1 1 1 1 0 32 - - - 1 1 1 1 1

nαα

0α (default)

1α 2α

3α . . .

. .

. 30 α 31 α

V0 Contrast

Maximum

. . . . . . .

Minimum

("–": Don't care)

VOUT

_ +

High

. . . . . . .

Low

REF

GND

Inside Chip

Figure 20. Electronic Contrast Control Circuit

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

Electronic Contrast Control (EV=1, 64 Steps)

For 64 contrast-step, EV flag of EV set mode instruction field should be set to "High", after this, Electronic Contrast Control data bits 28h = (C5, C4, C3, C2, C1, C0) can be valid. Voltage regulation is adjusted as 64contrast step according to the value of Electronic Contrast Control data bits. LCD drive voltage V0 has one of 64 voltage values if 6-bit data is set to the Electronic Contrast Control register (RAM address 28h). When using the Electronic Contrast Control function, you need to turn the voltage regulators on using power control instruction.

Rb V0 = ( 1 + ----------- ) × VEV – – – – – – – (3) Ra

VEV = VREF – nα (n = 0, 1, 2, ....., 62, 63)

α = VREF / 300

Table 13. Electronic Contrast Control Register (64 Steps)

No. C7 C6 C5 C4 C3 C2 C1 C0

1 - - 0 0 0 0 0 0 2 - - 0 0 0 0 0 1 3 - - 0 0 0 0 1 0 4 - - 0 0 0 0 1 1

. . .

. 62 - - 1 1 1 1 1 0 63 - - 1 1 1 1 1 1

("–": Don't care)

nαα

0α (default)

1α 2α

3α . . .

. .

. 62 α 63 α

VOUT

_ +

V0 Contrast

Maximum

. . . . . . .

Minimum

High

. . . . . . .

Low

REF

GND

Inside Chip

Figure 21. Electronic Contrast Control Circuit

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

CAP1+

CAP1-

VDDCAP2+

C1C2C2

- +

GND

VOUT

CAP2-

CAP1+

CAP1-

VDDCAP2+

V3V2C1

C1C2C2

- +

GND

VOUT

CAP2-

VOLTAGE GENERATOR CIRCUIT

C1: 0.1 to 4.7uF C2: 0.1uF

Three Times BoostingTwo Times Boosting

Figure 22. When Built-in Power Supply is used (VC, VR, VF = 1, 1, 1)

VDD

External

Power

Supply

VDD CAP1+ CAP1CAP2+ CAP2VOUT

VDD

CAP1+ CAP1CAP2+ CAP2VOUT

VDD

CAP1+ CAP1CAP2+ CAP2-

VOUT

GND

C2 C2 C2 C2 C2

GND

(VC, VR, VF = 0, 1, 1)

- +

- + V0

V1 V2 V3 V4 VSS

V0 V1 V2 V3 V4 VSS

External

Power Supply

GND

(VC, VR, VF = 0, 0, 1) (VC, VR, VF = 0, 0, 0)

Figure 23. When External Power Supply is used

External

Power

Supply

GND

All capacitor is C2. C2: 0.1 to 4.7uF

V0 V1 V2 V3 V4 VSS

Page 40

S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

REFERENCE APPLICATIONS

MPU INTERFACE

A1 to A7

IORQ

Decoder

RS CSB

S6A0090

MPU

D0 to D7

GND

RES

RESETB

Figure 24. Parallel Interfacing with 8080-series Microprocessors

E DB[0:7] RESETB

A1 to A7

VMA

Decoder

RS CSB

S6A0090

MPU

D0 to D7

GND

RES

RESETB

Figure 25. Parallel Interfacing with 6800-series Microprocessors

E DB[0:7] RES

Page 41

64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

VCC

PORT4 PORT3

RS CSB

S6A0090

or V

MPU

GND

PORT1 PORT2

RES

RESETB

SCL(DB6) SI(DB7) RESETB

Figure 26. Clock Synchronized Serial Interfacing with any Microprocessor

Page 42

S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

APPLICATION INFORMATION FOR LCD PANEL

Chip Bottom & Lower View (S (COM) = "0", BID (SEG) = "0")

. . . . . . . . .

S2S

COM8

: COM1 COMS1 COMSA

. . . . . . . . .

. . . . . . . . . . .

S6A0090

BOTTOM VIEW

COM24

COM17 COM16

: COM9

COMS2

SEGSA

SEGSE

S5S

Figure 27. Chip Bottom & Lower View (S (COM) = "0", BID (SEG) = "0")

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

Chip Bottom & Upper View (S (COM) = "1", BID (SEG) = "1")

SEGSE

SEGSA

COMS2 COM9

: COM16 COM17 :

COM24

S4S

S6A0090

BOTTOM VIEW

. . . . . . . . . . .

COMSA

COMS1

COM1

S E G 5

COM8 E G 1

S1S

. . . . . . . . .

Figure 28. Chip Bottom & Upper View (S (COM) = "1", BID (SEG) = "1")

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

Chip Top & Lower View (S (COM) = "0", BID (SEG) = "1")

. . . . . . . . .

S4S

COM24 : COM17

COM16 : COM9

COMS2 SEGSA

SEGSE

. . . . . . . . .

. . . . . . . . . . .

S6A0090

TOP VIEW

S1S

COM8

COM1

COMS1

COMSA

Figure 29. Chip Bottom & Lower View (S (COM) = "0", BID (SEG) = "1")

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

Chip Top & Upper View (S (COM) = "1", BID (SEG) = "0")

SEGSE

SEGSA

COMS2

COM9

: COM16 COM17

COM24

G 6 0

S5S

COMSA COMS1 COM1

COM8

S2S

S6A0090

TOP VIEW

. . . . . . . . . . .

S E G 5 6

. . . . . . . . .

Figure 30. Chip Bottom & Upper View (S (COM) = "1", BID (SEG) = "0")

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S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

V0V1V4

1-line selection period

FRAME FREQUENCY

1/18 Duty (2-line Mode)

1-line selection period

1 2 17 18 1 2• • • • • • • 17 18 1 2• • • • • • 17 18 1 2 17 18• • • • • •

V0 V1

• • • • • •

COM1

1 Frame 1 Frame

Figure 31. 1/18 Duty (2-line Mode)

1-line Selection Period = 13 Clocks One Frame = 13 x 18 x 43.2 µs = 10.0 ms (1 Clock = 43.2 µs at fOSC = 23.4 kHz) Frame Frequency = 1 / 10.0 ms = 100 Hz

1/26 Duty (3-line Mode)

1 2

• • • • • • • • • • • •

25 26

1 2 25 26 1 2• • • • • • • • • • • • • • • •

COM1

1-line Selection Period = 13 Clocks One Frame = 13 x 26 x 29.5 µs = 10.0 ms (1 Clock = 29.5 µs at fOSC = 33.8 kHz) Frame Frequency = 1 / 10.0 ms = 100 Hz

VSS

1 Frame 1 Frame

Figure 32. 1/26 Duty (3-line Mode)

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64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

* Test Condition: Temperature (25°C & 85°C), 2-line & 3-line Mode, No Load

VDD vs. fosc

50.00

45.00

40.00 2 Line (25°C)

3 Line (25°C) 2 Line (85°C) 3 Line (85°C)

fosc

[kHz]

35.00

30.00

25.00

20.00

15.00

10.00

5.00

0.00

2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 VDD [V]

Figure 33. VDD vs. fosc

MAXIMUM ABSOLUTE RATINGS

Table 14. Maximum Absolute Ratings

Characteristic Symbol Value Unit

Power supply voltage (1) VDD -0.3 to +7.0 V Power supply voltage (2) VOUT,V0 -0.3 to +13.0 V Power supply voltage (3) V1,V2,V3,V4 -0.3 to V0 V

Operating temperature TOPR -30 to 85 °C

Storage temperature TSTG -55 to 125 °C

* NOTE1: Voltage greater than above may damage the circuit. * NOTE2: All the voltage levels are based on VSS = 0V. * NOTE3: Voltage level: VOUT ≥ V0 ≥ VDD ≥ VSS V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS

Page 48

S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS

Table 15. DC Characteristics

(VDD = 2.4V to 3.6V, Ta = –30 to +85oC)

Item Symbol Condition

Min. Typ. Max. Unit

Operating voltage VDD - 2.4 - 3.6

Display operation

IDD1

Supply current

(VDD = 3V,

Ta = 25oC)

Input voltage

Input leakage current IIL VIN = 0V to VDD -1 - 1

RON resistance

Frame frequency

(internal OSC)

External clock

frequency

IDD2

IDD3

VIH - 0.8VDD - VDD

VIL - VSS - 0.2VDD

RCOM Io = ± 50µA - - 5

RSEG Io = ± 50µA - - 10

fFR VDD = 3V, Ta = 25oC 70 100 130 Hz

fck

VLCD = 6V without load

No access from MPU

Standby operation,

without load oscillator ON,

power OFF

Sleep operation,

without load oscillator OFF,

power save ON

Display of 2-line mode - 23.4 Display of 3-line mode - 33.8 -

- - 80

- - 10

- - 5

µA

kΩ

kHz

Voltage converter

VDD 2 or 3 times

Voltage regulator reference voltage

LCD driving voltage VLCD VLCD = V0 - VSS 4.0 - 11.0

VOUT2/3

VREF Ta = 25oC 1.94 2.0 2.06

Ta = 25 oC, C1 = 1uF

without load

95 99 - %

Page 49

64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

Table 15. DC Characteristics (Continued)

(VDD = 3.6V to 5.5V, Ta = –30 to +85oC)

Item Symbol Condition

Min. Typ. Max. Unit

Operating voltage VDD - 3.6 - 5.5

Display operation

IDD1

VLCD = 6V without load

- - 100

No access from MPU

Supply current

(VDD = 5V, Ta = 25oC)

IDD2

Standby operation,

without load oscillator ON,

power OFF

- - 20

sleep operation,

IDD3

without load oscillator OFF,

- - 10

power save ON

VIH - 0.8VDD - VDD

Input voltage

VIL - VSS - 0.2VDD

Input leakage current IIL VIN = 0V to VDD -1 - 1

RCOM Io = ± 50uA - - 5

RON resistance

RSEG Io = ± 50uA - - 10

Frame frequency

(internal OSC)

External clock

frequency

fFR VDD = 5V, Ta = 25oC 70 100 130 Hz

Display of 2-line mode - 23.4 -

Fck

Display of 3-line mode - 33.8 -

µA

kΩ

kHz

Voltage converter

VDD 2 times

Voltage regulator reference voltage

LCD driving

voltage

* NOTE: When power supply (VDD) range is 3.6V to 5.5V, the boosting of voltage converter is only 2 times available.

VOUT2

VREF Ta = 25oC 1.94 2.0 2.06

VLCD VLCD = V0 - VSS 4.0 - 11.0

Ta = 25 oC,C1 = 1µF

without load

95 99 - %

Page 50

S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

3 Line (85°C)

* Test Condition: Temperature (25°C & 85°C), 3-line Mode, Three Times Boosting, Rb / Ra = 2, EV = 32

VDD vs. IDD1 (Pattern Off)

90.00

80.00

70.00

60.00

IDD1

[uA]

50.00

40.00

30.00

20.00

10.00

0.00

2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 VDD [V]

3 Line (25°C) 3 Line (85°C)

Figure 34. VDD vs. IDD1 (Pattern OFF)

DD1

I [uA]

100.00

90.00

80.00

70.00

60.00

50.00

40.00

30.00

20.00

10.00

0.00

VDD vs. I

DD1

(Checker Pattern)

2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 VDD [V]

Figure 35. VDD vs. IDD1 (Checker Pattern)

3 Line (25°C)

Page 51

64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

AC CHARACTERISTICS

Write Bus Mode (68 Mode)

RS,C SB

DB0 to DB7

SU1

w h

SU2

Va l id D a ta

w l

Figure 36. Write Bus Mode Timing Diagram (68 Mode)

(VDD = 2.4V to 3.6V, Ta = –30 to +85oC)

Mode Characteristic Symbol Min. Typ. Max. Unit

E cycle time tc 650 - -

Pulse rise / fall time tr,tf - - 25

E pulse width high twh 450 - -

Write bus

mode

E pulse width low twl 150 - -

RS and CSB setup time tsu1 60 - -

RS and CSB hold time th1 30 - -

Data setup time tsu2 100 - -

Data hold time th2 50 - -

(VDD = 3.6V to 5.5V, Ta = –30 to +85oC)

Mode Characteristic Symbol Min. Typ. Max. Unit

E cycle time tc 500 - -

Pulse rise / fall time tr,tf - - 25

E pulse width high twh 350 - -

Write bus

mode

E pulse width low twl 100 - -

RS and CSB setup time tsu1 60 - -

RS and CSB hold time th1 10 - -

Data setup time tsu2 100 - -

Data hold time th2 20 - -

Page 52

S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

Write Bus Mode (80 Mode)

RS,CSB

E (W R)

DB0 to DB7

S U 1

w l

Valid D ata

w h

S U 2

Figure 37. Write Bus Mode Timing Diagram (80 Mode)

(VDD = 2.4V to 3.6V, Ta = –30 to +85oC)

Mode Characteristic Symbol Min. Typ. Max. Unit

E cycle time tc 650 - -

Pulse rise / fall time tr,tf - - 25

E pulse width high twh 150 - -

Write bus

mode

E pulse width low twl 450 - -

RS and CSB setup time tsu1 60 - -

RS and CSB hold time th1 30 - -

Data setup time tsu2 100 - -

Data hold time th2 50 - -

(VDD = 3.6V to 5.5V, Ta = –30 to +85oC)

Mode Characteristic Symbol Min. Typ. Max. Unit

E cycle time tc 500 - -

Pulse rise / fall time tr,tf - - 25

E pulse width high twh 100 - -

Write bus

mode

E pulse width low twl 350 - -

RS and CSB setup time tsu1 60 - -

RS and CSB hold time th1 10 - -

Data setup time tsu2 100 - -

Data hold time th2 20 - -

Page 53

64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD S6A0090

Clock Synchronized Serial Mode

CSB

SU1

SCL

SU2

SU3

Figure 38. Clock Synchronized Serial Interface Mode Timing Diagram

(VDD = 2.4V to 3.6V, Ta = –30 to +85oC)

Mode Characteristic Symbol Min. Typ. Max. Unit

SCL clock cycle time tc 1000 - -

Pulse rise / fall time tr,tf - - 25

SCL clock width (high, low) tw 300 - -

Clock

synchronized

serial interface

mode

CSB setup time tsu1 150 - -

CSB hold time th1 700 - -

RS data setup time tsu2 50 - -

RS data hold time th2 300 - -

SI data setup time tsu3 50 - -

SI data hold time th3 50 - -

Page 54

S6A0090 64 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

Write Bus & Serial Mode (Typical 5V)

n 68 Bus Mode

(VDD = 3.6V to 5.5V, Ta = –30 to +85oC)

Mode Characteristic Symbol Min. Typ. Max. Unit

E cycle time tc 350 - -

Pulse rise / fall time tr,tf - - 25

E pulse width high twh 250 - -

Write bus

mode

E pulse width low twl 1000 - -

RS and CSB setup time tsu1 40 - -

RS and CSB hold time th1 10 - -

Data setup time tsu2 40 - -

Data hold time th2 10 - -

n 80 Bus Mode

(VDD = 3.6V to 5.5V, Ta = –30 to +85oC)

Mode Characteristic Symbol Min. Typ. Max. Unit

E cycle time tc 350 - -

Pulse rise / fall time tr,tf - - 25

E pulse width high twh 100 - -

Write bus

mode

E pulse width low twl 250 - -

RS and CSB setup time tsu1 40 - -

RS and CSB hold time th1 10 - -

Data setup time tsu2 40 - -

Data hold time th2 10 - -

n Serial Mode

(VDD = 3.6V to 5.5V, Ta = –30 to +85oC)

Mode Characteristic Symbol Min. Typ. Max. Unit

SCL clock cycle time tc 600 - -

Pulse rise / fall time tr,tf - - 25

SCL clock width (high, low) tw 200 - -

Clock

synchronized

serial interface

mode

CSB setup time tsu1 100 - -

CSB hold time th1 400 - -

RS data setup time tsu2 40 - -

RS data hold time th2 200 - -

SI data setup time tsu3 40 - -

SI data hold time th3 40 - -