Page 1
January 2000
FDS6912
Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET
FDS6912
General Description
These N-Channel Logic Level MOSFETs have been
designed specifically to improve the overall effici ency of
DC/DC converters using either synchronous or
conventional switching PWM controllers.
These MOSFETs feature faster switching and lower
gate charge than other MOSFETs with comparable
RDS(ON) specifications.
The result is a MOSFET that is easy and safer to drive
Features
6 A, 30 V. R
•
R
= 0.042 Ω @ VGS = 4.5 V.
DS(ON)
Optimized for use in switching DC/DC converters
•
with PWM controllers
Very fast switching.
•
Low gate charge
•
= 0.028 Ω @ VGS = 10 V
DS(ON)
(even at very high frequencies), and DC/DC power
supply designs with higher overall efficiency.
D1
D1
D2
D2
G1
S2
S1
G2
SO-8
Absolute Maximum Ratings
TA=25oC unless otherwise noted
5
Q1
6
7
Q2
8
4
3
2
1
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
TJ, T
stg
Drain-Source Voltage 30 V
Gate-Source Voltage
Drain Current – Continuous
(Note 1a)
20
±
6A
– Pulsed 20
Power Dissipation for Dual Operation 2
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
1.6
1
0.9
Operating and Storage Junction Temperature Range -55 to +150
V
W
C
°
Thermal Characteristics
R
JA
θ
R
JC
θ
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
40
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS6912 FDS6912 13’’ 12mm 2500 units
2000 Fairchild Semiconductor Corpor ation
C/W
°
C/W
°
FDS6912 Rev E (W)
Page 2
FDS6912
Electrical Characteristics
TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
BV
∆
T
∆
I
DSS
I
GSSF
I
GSSR
On Characteristics
V
GS(th)
GS(th)
V
∆
T
∆
R
DS(on)
I
D(on)
g
FS
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
DSS
Coefficient
J
V
= 0 V, ID = 250 µA
GS
= 250 µA, Referenced to 25°C
I
D
30 V
20
Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V
T
= 55°C
J
Gate–Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate–Body Leakage, Reverse VGS = –20 V VDS = 0 V –100 nA
(Note 2)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
J
Static Drain–Source
On–Resistance
V
= VGS, ID = 250 µA
DS
I
= 250 µA, Referenced to 25°C
D
VGS = 10 V, ID = 6 A
T
= 125°C
J
123 V
–5
0.024
0.034
VGS = 4.5 V, ID = 4.9 A 0.035 0.042
On–State Drain Current VGS = 10 V, VDS = 5 V 20 A
Forward Transconductance VDS = 10 V, ID = 6 A 20 S
1
10
0.028
0.048
mV/°C
A
µ
mV/°C
Ω
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance 740 pF
Output Capacitance 170 pF
Reverse Transfer Capacitance
= 15 V, V
V
DS
f = 1.0 MHz
GS
= 0 V,
75 pF
Switching Characteristics
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
g
gs
gd
Turn–On Delay Time 8 16 ns
Turn–On Rise Time 13 24 ns
Turn–Off Delay Time 18 29 ns
Turn–Off Fall Time
Total Gate Charge 7 10 nC
Gate–Source Charge 3.8 nC
Gate–Drain Charge
(Note 2)
V
= 15 V, ID = 1 A,
DD
= 10 V, R
V
GS
= 10 V, ID = 6 A,
V
DS
= 5 V
V
GS
GEN
= 6
Ω
816ns
2.5 nC
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Notes:
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
R
1.
JA
θ
the drain pins. R
Scale 1 : 1 on letter size paper
2.
Maximum Continuous Drain–Source Diode Forward Current 1.3 A
Drain–Source Diode Forward
VGS = 0 V, IS = 1.3 A
(Note 2)
0.75 1.2 V
Voltage
is guaranteed by design while R
JC
θ
a) 78°/W when
mounted on a 0.5in
pad of 2 oz copper
Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
is determined by the user's board design.
CA
θ
2
b) 125°/W when
mounted on a 0.02
in2 pad of 2 oz
copper
c) 135°/W when mounted on a
minimum mounting pad.
FDS6912 Rev E (W)
Page 3
Typical Characteristics
FDS6912
30
24
18
V = 10 V
GS
6.0V
5.0V
4.5V
4.0V
12
D
I , DRAIN- S OUR CE CURREN T (A)
6
3.5V
3.0V
0
0112233
V , D RA I N-S OUR CE VOLTAGE (V)
DS
2
1.8
1.6
1.4
1.2
VGS = 4.0V
4.5V
5.0V
6.0V
7.0V
1
0.8
0 1020304050
, DRAIN CURRENT (A)
I
D
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
1.5
I = 6.3A
D
1.4
V =10V
GS
1.3
1.2
1.1
1.0
0.9
DS(ON)
R ,NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.7
0.6
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
8
7
)
6
5
4
DS(ON)
R ,(
3
DRAIN-SOURCE ON-RESISTANCE
2
1
246810
V ,GATE-SOURCE VOLTAGE (V)
GS
T = 125 C
A
o
25 C
10V
I = 3.0A
D
o
Figure 3. On-Resistance Variation
withTemperature.
20
V = 5V
DS
15
10
D
5
I , DRAIN CURRENT (A)
0
12345
V , GATE TO SOURCE VOLTAGE (V)
GS
T = -55°C
J
25°C
125°C
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
VGS = 0V
10
1
0.1
0.01
0.001
0.0001
0 0.4 0.8 1.2 1.6
TA = 125oC
25oC
-55oC
, BODY DIODE FORWARD VOLTAGE (V)
V
SD
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDS6912 Rev E (W)
Page 4
Typical Characteristics (continued)
FDS6912
10
ID = 6.3A
8
6
VDS = 5V 10V
15V
4
2
0
0481216
Q
, GATE CHARGE (nC)
g
f = 1 MHz
V = 0V
GS
DS
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
100
20
10
RDS(ON) LIMIT
2
0.5
V = 10V
D
I , DRAIN CURRENT (A)
0.05
0.01
GS
SINGLE PULSE
R = 135 °C/W
JA
θ
T = 25°C
A
0.1 0.2 0.5 1 2 5 10 20
V , DRAIN-SOURCE VOLTAGE (V)
DS
DC
10ms
100ms
1s
10s
100us
1ms
30
25
20
15
10
5
0
0.01 0.1 1 10 100 1000
SINGLE PULSE
R = 135°C/W
θ
JA
T = 25°
A
C
C
C
iss
oss
rss
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
r(t), NORMALIZED EFFECTIVE
0.002
TRANSIENT THERMAL RESISTANCE
0.001
0.0001 0.001 0.01 0.1 1 10 100 300
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
t , TIME (sec)
1
R (t) = r(t) * R
θ
JA
R = 135°C/W
θ
JA
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t /t
θ
JA
JA
θ
1 2
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS6912 Rev E (W)
Page 5
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging
Configuration: Figure 1.0
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC
ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS
TNR DATE
PT NUMBER
PEEL STRENGTH MIN ______________gms
Customized
Label
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Reel Size
Box Dimension (mm)
Max qty per Box
Weight per unit (gm)
Weight per Reel (kg)
Note/Comments
MAX _____________ gms
ESD Label
SOIC (8lds) Packaging Information
Standard
(no flow code)
2,500 95 4,000
13" Dia
343x64x343 530x130x83 343x64x343
5,000 30,000 8,000
0.0774 0.0774 0.0774 0.0774
0.6060 - 0.9696 0.1182
TNR
L86Z F011
Rail/Tube-TNR
13" Dia
Embossed Car rier Tape
Antistatic Cover Tape
Static Dissipative
F63TNR
Label
D84Z
TNR
500
7" Dia
184x18 7x47
1,000
F
NDS
9959
852
9959
SOIC-8 Unit Orientation
343mm x 342mm x 64mm
Stand a r d In t e rm ed iate box
Packaging Description:
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 uni t s pe r 13" o r 33 0c m d ia met er reel . Th e reel s ar e
dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or
177cm di ameter reel. This and some o ther options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in di ff ere nt siz es depe nd in g on th e num be r of pa rts
shippe d.
F
NDS
9959
F
NDS
9959
F
NDS
852
852
852
F
NDS
9959
852
Pin 1
F63TNR Label sample
LOT: CBVK741B019
FSID: FDS9953A
D/C1: D9842 QTY1: SPEC REV:
D/C2: QTY2: CPN:
QTY: 2500
SPEC:
N/F: F (F63TNR)3
SOIC(8lds) Tape Leader and Trailer
Configuration: Figure 2.0
Carrier Tape
Cover Tape
Trailer Tape
640mm minimum or
80 empty pockets
F63TNLab el
ESD Label
Components
ESD Label
F63TNLabel
Leader Tape
1680mm minimum or
210 empty pockets
July 1999, Rev. B
Page 6
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0
T
K0
Wc
B0
P0
D0
E1
F
W
E2
Tc
A0
P1
D1
User Direction of Feed
Dimensions are in millimeter
Pkg type
(8lds)
SOIC
(12mm)
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
SOIC(8lds) Reel Configuration: Figure 4.0
A0 B0 W D0 D1 E1 E 2 F P1 P0 K0 T Wc Tc
6.50
5.30
12.0
1.55
1.60
1.75
10.25
+/-0.10
+/-0.10
+/-0.3
+/-0.05
+/-0.10
+/-0.10
rotational and lateral movement requirements (see sketches A, B, and C).
B0
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
5.50
min
+/-0.05
20 deg maximum
A0
Sketch B (Top View)
Component Rotation
W1 Measured at Hub
8.0
+/-0.1
Typical
component
cavity
center line
Typical
component
center line
Dim A
Max
4.0
+/-0.1
0.450
2.1
+/-0.10
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
+/-
0.150
9.2
+/-0.3
0.5mm
maximum
0.06
+/-0.02
Dim A
max
Tape Size
12mm 7" Dia
12mm 13" Dia
1998 Fairchild Semiconductor Corporation
Reel
Option
Dim N
Diameter Option
7"
See detail AA
B Min
Dim C
13" Diameter Option
See detail AA
W2 max Measured at Hub
Dim D
W3
min
DETAIL AA
Dimensions are in inches and millimeters
Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
7.00
0.059
177.8
13.00
330
1.5
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
512 +0.020/-0.008
13 +0.5/-0.2
0.795
2.165550.488 +0.078/-0.000
20.2
0.795
7.00
20.2
178
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.724
18.4
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
July 1999, Rev. B
Page 7
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1 : 1
Scale 1:1 on letter size paper
Dimensions show n below are in:
inches [m ill imet ers]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
Page 8
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
CROSSVOLT™
2
E
CMOS
TM
FACT™
FACT Quiet Series™
®
FAST
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or
In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. D
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