Datasheet FDB060AN08A0, FDP060AN08A0 Datasheet (Fairchild)

FDB060AN08A0 / FDP060AN08A0

N-Channel PowerTrench® MOSFET
75V, 80A, 6.0mΩ

FDB060AN08A0 / FDP060AN08A0

November 2002

Features

•r

•Q

• Low Miller Charge

•Low Q

= 4.8mΩ (Typ .), V

DS(ON)

(tot) = 73nC (Typ.), V

g

Body Diode

RR

= 10V, ID = 80A

GS

= 10V

GS

Applications

• Elec tr on ic Valve Train Sys te m s

• DC-DC converters and Off -line UPS

• Distributed Power Architectures and VRMs

• Primary Switch for 24V and 48V systems

• UIS Capability (Single Pulse and Repetitive Pulse)

Formerly developmental type 82680

DRAIN

(FLANGE)

GATE

TO-220AB

FDP SERIES

MOSFET Maximum Ratings

SOURCE

DRAIN

GATE

SOURCE

TO-263AB

FDB SERIES

TC = 25°C unless otherwise noted

DRAIN

(FLANGE)

D

G

S

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Sou r c e Voltage 75 V
Gate to Source Voltage ±20 V
Drain Curr e nt

I

D

Continuous (T
Continuous (T

< 127oC, VGS = 10V)

C

= 25oC, VGS = 10V, with R

amb

= 43oC/W) 16 A

θJA

80 A

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse Avalanche Energy (Note 1) 350 mJ
Power dissipation 255 W
Derate above 25oC1.7W/
Operating and Storage Temperature -55 to 175

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

Thermal Resistance Junction to Case TO-220,TO-263 0.58
Thermal Resistance Junction to Ambien t TO-220,TO -263 (Note 2) 62
Thermal Resistan ce Junction to Ambient TO-263, 1in2 copper pad ar ea 43

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

o

C/W

o

C/W

o

C/W

FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semiconductor Corporation

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDB060 AN08A0 FDB060AN08A0 TO-263AB 330mm 24mm 800 uni ts
FDP060AN08A0 FDP060AN08A0 TO-220AB Tube N/A 50 unit s

FDB060AN08A0 / FDP060AN08A0

Electrical Characteristics

TC = 25°C unless othe rw ise noted

Symbol Parame ter Test Conditions Min Typ Max Units

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain to Sou r c e Br ea k down Voltag e ID = 250µA, VGS = 0V 75 - - V

V

= 60V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- -250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

ID = 80A, VGS = 10V - 0.0048 0.006
I

= 40A, VGS = 6V - 0.0066 0.010

Drain to S ou r c e On Re si st ance

D

= 80A, VGS = 10V,

I

D

T

= 175oC

J

- 0.010 0.013

Dynamic Characteristics

C
C
C
Q
Q
Q
Q
Q

ISS
OSS
RSS

g(TOT)
g(TH)
gs
gs2
gd

Input Capacitance
Output Capacitance - 800 - pF
Reverse Transfer Capacitance - 230 - pF

V

= 25V, VGS = 0V,

DS

f = 1MHz

Total Gate Charge at 10V VGS = 0V to 10V
Threshold Gate Charge VGS = 0V to 2V - 10 13 nC
Gate to Source Gate Charg e - 2 9 - nC
Gate Charge Threshold to Plateau - 19 - nC

VDD = 40V

= 80A

I

D

I

= 1.0m A

g

- 5150 - pF

73 95 nC

Gate to Drain “Miller” Charge - 16 - nC

µA

Ω

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 19 - ns
Rise Time - 79 - ns
Turn-Off Delay Time - 37 - ns
Fall Time - 38 - ns
Turn-Off Time - - 113 ns

(VGS = 10V)

Drain-Source Diode Characteristics

V

SD

t

rr

Q

RR

Notes:
1: Starting TJ = 25°C, L = 109µH, IAS = 80A.
2: Pulse width = 100s

Source to Drain Diode V oltage
Reverse Recovery Time ISD = 75A, dISD/dt = 100A/µs- -37ns

Reverse Recovered Charge ISD = 75A, dISD/dt = 100A/µs- -38nC

--147ns

VDD = 40V, ID = 80A
VGS = 10V, RGS = 3.9Ω

I

= 80A - - 1.25 V

SD

= 40A - - 1.0 V

I

SD

FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semiconductor Corporation

FDB060AN08A0 / FDP060AN08A0

Typical Characteristics

TC = 25°C unless othe rw ise noted

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

10

150

125

100

75

50

, DRAIN CURRENT (A)

D

I

25

0

150

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

10

CURRENT LIMITED
BY PACKAGE

TC, CASE TEMPERATURE (oC)

Case Temperature

P

DM

NOTES:
DUTY FACTOR: D = t1/t

PEAK TJ = PDM x Z

-1

10

θJC

10

0

x R

t

1

t

2

2

+ T

θJC

C

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

2000

TRANSCONDUCTANCE

1000

MAY LIMIT CURRENT
IN THIS REGION

VGS = 10V

, PEAK CURRENT (A)

DM

I

100

70

-5

10

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:

175 - T

I = I

25

10

C

150

0

1

10

Figure 4. Peak Current Capability

FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semiconductor Corporation

FDB060AN08A0 / FDP060AN08A0

Typical Characteristics

1000

100

OPERATION IN THIS

10

, DRAIN CURRENT (A)

D

I

0.1

AREA MAY BE

LIMITED BY r

1

SINGLE PULSE

TJ = MAX RATED
TC = 25oC

110100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

TC = 25°C unless othe rw ise noted

10µs

100µs

1ms

10ms

DC

Figure 5. Forward Bias Safe Operating Area

175

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

150

125

= 15V

V

DD

500

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

100

10

, AVALANCHE CURRENT (A)

AS

I

1

0.01 0.1 1 10 100

STARTING TJ = 150oC

tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

DSS

STARTING TJ = 25oC

- VDD) +1]

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

175

150

125

VGS = 10V

V

= 7V

GS

VGS = 6V

100

75

, DRAIN CURRENT (A)

50

D

I

25

TJ = 25oC

0

3.5 4.0 4.5 5.0 5.5 6.0
VGS, GATE TO SOURCE VOLTAGE (V)

TJ = 175oC

TJ = -55oC

100

75

, DRAIN CURRENT (A)

50

D

I

25

0

0 0.5 1.0 1.5 2.0

VDS, DRAIN TO SOURCE VOLTAGE (V)

TC = 25oC

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

7.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

7.0

6.5

6.0

5.5

5.0

4.5

DRAIN TO SOURCE ON RESISTANCE(mΩ)

4.0
0 20406080

VGS = 6V

VGS = 10V

ID, DRAIN CURRENT (A)

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = 5V

VGS = 10V, ID = 80A

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semiconductor Corporation

FDB060AN08A0 / FDP060AN08A0

Typical Characteristics

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

TC = 25°C unless othe rw ise noted

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

7000

C

= CGS + C

1000

ISS

C

≅ C

+ C

OSS

DS

GD

C

= C

RSS

GD

GD

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200
T

, JUNCTION TEMPERATURE (oC)

J

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 40V

8

6

4

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

100

0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Sour ce

Voltage

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

75

0 20406080

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 80A
ID = 16A

Figure 14. Gat e Charge Waveforms for Constant

Gate Current

FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semiconductor Corporation

Test Circuits and Waveforms

V

DS

L

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

I

AS

DUT

t

0V

P

I

AS

0.01Ω

0

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Wavef orm s

V

DS

V

DD

V

Q

I

g(REF)

L

V

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

= 2V

Q

gs2

Q

g(TH)

Q

gs

0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

BV

DSS

t

P

t

AV

Q

g(TOT)

DS

gd

V

V

GS

FDB060AN08A0 / FDP060AN08A0

DS

V

DD

V

= 10V

GS

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

t

r

10%

PULSE WIDTH

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semiconductor Corporation

d(OFF)

90%

t

OFF

t

f

90%

10%

50%50%

Thermal Resistance vs. Mounting Pad Area

80

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serve s as the basis for establishing the rating of the part.

P

DM

In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power d issipati on rating s. Precise d etermin ation of P
comple x and infl uenced by many factors :

1. Mou nting pa d area onto which the device is a ttached and
whet her the re is copp er on one s ide or both side s of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orie ntation .

6. For no n steady state applic ations, th e pulse widt h, the
duty cycle and the transi ent thermal response of the part,
the boa rd and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally
positi on ed FR-4 board w ith 1oz c o pp er after 1 00 0 se c onds
of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides
the necessary information for calculation of the steady s tate
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice t hermal model or manu ally utilizing the no rmalized
maximum transient thermal impedance curve.

(oC), and th ermal res istance R

A

TJMTA–()

----------------- ------------=

R

θJA

for the device as a function of the top

θJA

(oC/W)

θJA

(EQ. 1)

DM

is

60

C/W)

o

(

θJA

R

40

20

Figure 21. Thermal Resistance vs Mounting

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

(0.645) (6.45) (64.5)

AREA, TOP COPPER AREA in2 (cm2)

1100.1

Pad Area

FDB060AN08A0 / FDP060AN08A0

Therma l resistances corresp onding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inch es squ are and equ ation 3 is for area in cent imeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

19.84

=

R

R

θJA

θJA

=

26.51

26.51

-------------------------------------+

0.262 Area+()

Area in Inches Squared

128

----------------------------------+

1.69 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semiconductor Corporation

PSPICE Electrical Mod el

.SUBCKT FDP060AN08 A0 2 1 3 ; rev Oct ober 2002
Ca 12 8 2.5e-9
Cb 15 14 2.1e-9
Cin 6 8 4.7e-9

Dbod y 7 5 DbodyM OD
Dbreak 5 11 Db reakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 82.1
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1

ESG

Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgat e 1 9 5.3e-9

GATE

1

LGATE

RLGATE

RGATE

9

EVTEMP

+

20

18
22

Ldrain 2 5 1.0e -9
Lsou rce 3 7 5e-9

RLgate 1 9 53
RLdr ai n 2 5 10

S1A

12

RLsource 3 7 50
Mmed 16 6 8 8 M m edMOD

Mstro 16 6 8 8 MstroMOD

S1B

CA

Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1

Rdrain 50 16 RdrainMOD 9e-4
Rgate 9 20 1.4
RSLC1 5 51 RSL CM OD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3e-3
Rvthres 22 8 RvthresMO D 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BM OD
S2a 6 15 14 13 S2AM OD
S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ ABS(V(5,51)))*(PWR (V (5,51)/(1 e-6*350),5) )}

.MODEL DbodyMOD D (IS=2E-11 N=1.04 RS=1.76e-3 TRS1=2.7e-3 TRS2=1e-6
+ CJO=3.2e-9 M= 5.6e-1 TT=3e-10 XTI=3.9)
.MODEL DbreakMOD D (RS= 3e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.56e-9 IS=1e-30 N=10 M=0.53)

.MODEL MmedMOD NMOS (VTO=3.6 KP=6 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.4)
.MODEL Mstro M OD NMOS (VTO=4.22 K P =220 IS=1e-30 N=10 T OX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=14 RS=0.1)

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

19

6

-

S2A

13

14

8

13

S2B

13

+

+

6

EGS EDS

8

-

-

5

RSLC1

51

+

5

ESLC

51

­50

RDRAIN

16

21

-

8

MSTRO

CIN

15

CB

8

14

+

5
8

-

DBREAK

EBREAK

MWEAK

MMED

RSOURCE

17 18

IT

8

11

+

17
18

-

RBREAK

RVTHRES

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB060AN08A0 / FDP060AN08A0

.MODEL RbreakMOD RES (TC1=9.4e-4 TC2=-9e-7)
.MODEL Rd rai nMOD RES (TC1=2.2e-2 TC2=6e-5)
.MODEL RSLCMOD RES (TC1=2e-3 TC2=1e-5)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1 e-6)
.MODEL RvthresMOD RE S (TC1=-6e-3 T C2=-1.6e-5 )
.MODEL RvtempMOD RES (T C1=-2.4e-3 TC 2=1e-6)

.MODEL S1AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 8 VOFF =-5 )
.MODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 5 VOFF =-8 )
.MODEL S2AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 4 VOFF =-3 .5 )
.MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 3.5 VO FF=- 4)
.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, wri t ten by William J. Hepp and C. Frank
Wheatley.

FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semiconductor Corporation

SABER Electrical Model

rev October 2002
template FDP 060AN08A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2e-11,nl=1.04,rs=1.76e-3,trs1=2.7e-3,trs2=1e-6,cjo=3.2e-9,m=5.6e-1,tt=3e-10,xti=3.9)
dp..model dbreakmod = (rs=3e -1, trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.56e-9,isl=10e-30,nl=10,m=0.53)
m..model mmedmod = (type=_n,vto=3.6,kp=6,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.22,kp=220,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3,kp=0.03,is=1e-30, tox=1,rs=0.1)
sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0.1, von=-8,voff=-5)
sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0.1, von=-5,voff=-8)
sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0.1, von=-4,voff=-3.5)
sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0.1, von=-3.5,voff=-4)
c.ca n12 n8 = 2.5e-9
c.cb n15 n14 = 2.1e-9
c.cin n6 n8 = 4.7e -9

dp.dbody n7 n5 = model=dbodym od
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplca pm od

spe.ebreak n11 n7 n17 n18 = 82.1
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1

GATE

1

LGATE

RLGATE

RGATE

9

EVTEMP
+

20

spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1
l.lgate n1 n9 = 5.3e-9

l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 5e-9

res.rlgate n1 n9 = 53

CA

S1A

12

S1B

res.rldrai n n2 n5 = 10
res.rlsource n3 n7 = 50

m.mmed n16 n6 n8 n8 = m odel=mmedm od, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mwea kmod, l=1u, w=1u

ESG

18
22

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

19

8

6

-

S2A

13

14

8

13

S2B

13

+

+

6

EGS EDS

8

-

-

15

CIN

CB

-

+

-

5

MSTRO

14

5
8

RSLC1

51

ISCL

50
RDRAIN

16

21

8

MMED

8

DBREAK

11

MWEAK

EBREAK

+

RSOURCE

RBREAK

17 18

IT

RVTHRES

17
18

­7

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

RVTEMP
19

VBAT

DRAIN

2

SOURCE

3

FDB060AN08A0 / FDP060AN08A0

res.rbreak n17 n18 = 1, tc1=9.4e- 4, tc 2=-9e-7
res.rdrain n50 n16 = 9e-4, tc1=2 .2e-2,tc2=6e-5
res.rgate n9 n20 = 1.4
res.rslc1 n5 n51 = 1e-6, tc1=2e -3, tc2=1e-5
res.rslc2 n5 n50 = 1e3
res.rsour ce n8 n7 = 3e-3, tc1=1e- 3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-6e- 3, tc 2=-1.6e-5
res.rvtemp n18 n19 = 1, tc1=-2.4e-3,tc2=1e-6
sw_vcsp.s1 a n6 n12 n13 n8 = model= s1amod
sw_vcsp.s1 b n13 n12 n13 n8 = model =s1bmod
sw_vcsp.s2 a n6 n15 n14 n13 = model =s2amod
sw_vcsp.s2 b n13 n15 n14 n13 = model =s2bmod

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/350 ))** 5))
}
}

FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semiconductor Corporation

FDB060AN08A0 / FDP060AN08A0

PSPICE Thermal Model

REV 23 October 2002
FDP060AN08A0T
CTHERM1 TH 6 9.6e-3

CTHERM2 6 5 9. 7e-3
CTHERM3 5 4 9. 8e-3
CTHERM4 4 3 1e-2
CTHERM5 3 2 3e-2
CTHERM6 2 TL 9e-2

RTHERM1 TH 6 3.2e-3
RTHERM2 6 5 8. 1e-3
RTHERM3 5 4 2. 3e-2
RTHERM4 4 3 1. 2e-1
RTHERM5 3 2 1. 5e-1
RTHERM6 2 TL 1.6e-1

SABER Thermal Model

SABER therm al m odel F DP060AN08A0T
template thermal_model th tl
thermal_ c th , tl
{
ctherm.c th erm 1 th 6 =9.6e-3
ctherm.ctherm2 6 5 =9.7e-3
ctherm.ctherm3 5 4 =9.8e-3
ctherm.ctherm4 4 3 =1e-2
ctherm.ctherm5 3 2 =3e-2
ctherm.ctherm6 2 tl =9e-2

rtherm.rtherm1 th 6 =3.2e-3
rtherm.rtherm2 6 5 =8.1e-3
rtherm.rtherm3 5 4 =2.3e-2
rtherm.rtherm4 4 3 =1.2e-1
rtherm.rtherm5 3 2 =1.5e-1
rthe r m.rtherm6 2 tl =1 . 6 e-1
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

RTHERM6

2

CTHERM6

tl

CASE

FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semiconductor Corporation

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Design

Preliminary First Production This datasheet contains prel iminary dat a, and

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Rev. I1