Datasheet FAN3100TSX Specification

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Page 1

FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

FAN3100C / FAN3100T

1 6

IN+

AGND

VDD

IN-

PGND

OUT

VDD

GND

IN+ IN−

OUT

Single 2 A High-Speed, Low-Side Gate Driver

Features

3 A Peak Sink/Source at VDD = 12 V

  4.5 to 18 V Operating Range  2.5 A Sink / 1.8 A Source at V

OUT

= 6 V

 Dual-Logic Inputs Allow Configuration as

Non-Inverting or Inverting w ith Enable Function

 Internal Resistors Turn Driver Off If No Inputs  13 ns Typical Rise Time and 9 ns Typical Fall-Time

w ith 1 nF Load

 Choice of TTL or CMOS Input Thresholds  MillerDrive™ Technology  Typical Propagation D elay Time Under 20 ns w ith

Input Fal ling or Rising

 6-Lead, 2x2 mm MLP or 5-Pin, SOT23 Packages  Rated from –40° C to 125°C Ambient

Applications

Sw itched-Mode Pow er Supplies (SMPS)

  High-Efficiency MOSFET Sw itching  Synchronous Rectifier Circuits  DC-to-DC C onverters  Motor Control

Description

The FAN3100 2 A gate driver is designed to drive an Nchannel enhancement-mode MOSFET in low -side sw itching applications by providing high peak current pulses during the s hort s witching interv als. The dr iv er is available with either TTL (FAN3100T) or CMOS (FAN3100C) input thresholds. Internal circuitry pr ovides an under-v oltage lockout function by holding the output LOW until the supply voltage is within the operating range. The FAN3100 delivers fast MOSFET sw itching performance, w hich helps maximize efficiency in highfrequency power converter designs.

FAN3100 drivers incorporate MillerDrive™ architecture for the final output stage. This bipolar-MOSFET combination prov ides high peak curr ent dur ing the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize sw itching loss, w hile providing rail-to-rail voltage sw ing and reverse current capability.

The FAN3100 also offers dual inputs that can be conf igured to operate in non-inverting or inverting mode and allow implementation of an enable f unc tion. If one or both inputs are left unconnec ted, internal res istor s bias the inputs s uch t hat the output is pulled LOW to hold the power MOSFET off.

The FAN3100 is available in a lead-free finish, 2x2 mm, 6lead, Molded Leadless Package (MLP) for the smallest size with excellent thermal performance; or industrystandard, 5-pin, SOT23.

Functional Pin Configurations

Page 2

FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Figure 1. 6-Lead MLP (Top View)

Figure 2. SOT23-5 (Top View)

1 6

IN+

AGND

VDD

IN−

PGND

OUT

VDD

GND

IN+ IN−

OUT

Figure 3. 6-Lead MLP (Top View)

Figure 4. SOT23-5 (Top View)

Ordering Information

Pa rt Number

Input

Threshold

Package Pa cking Me thod Quantity / Reel

FAN3100CMPX CMOS 6-Lead, 2x2 mm MLP Tape & Reel 3000 FAN3100CSX CMOS 5-Pin, SOT23 Tape & Reel 3000 FAN3100TMPX TTL 6-Lead, 2x2 mm MLP Tape & Reel 3000 FAN3100TSX TTL 5-Pin, SOT23 Tape & Reel 3000

Package Outlines

Thermal Characteristics

6-Lead, 2x2 mm Molded Leadless Package (MLP) 2.7 133 58 2.8 42 °C/W SOT23-5 56 99 157 51 5 °C/W

Notes:

1. Estimates derived from thermal simulation; actual values depend on the application.

2. Theta_JL (Θ (including any thermal pad) that are typically soldered to a PCB.

3. Theta_JT (Θ assuming it is held at a uniform temperature by a top-side heatsink.

4. Theta_JA (Θ airflow. The value given is for natural convection with no heatsink using a 2SP2 board, as specified in J EDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.

5. Ps i_JB ( Ψ and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP-6

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package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOT23-5 package, the board reference is defined as the PCB copper adjacent to pin 2.

6. Ps i_JT (Ψ temperature and the center of the top of the package for the therm al environment defined in Note 4.

): Thermal resistance betw een the semiconductor junction and the bottom surface of all the leads

): Thermal resistance betw een the semiconductor junction and the top surface of the package,

): Thermal resistance betw een junction and ambient, dependent on the PC B design, heat sinking, and

): Thermal characterization parameter providing correlation betw een semiconductor junction temperature

): Thermal characterization parameter providing correlation betw een the semiconductor junction

Package

(1)

(2)

(3)

(4)

(5)

(6)

Units

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Pin Definitions

SOT23

Pin #

MLP

Pin #

1 3 VDD Supply Voltage. Provides power to the IC.

2 AGND Analog ground for input signals (MLP only). Connect to PGND underneath the IC. 2 GND Ground (SOT-23 only). Common ground reference for input and output circuits. 3 1 IN+ Non-Inverting Input. Connect to VDD to enable output. 4 6

5 4 OUT

Pad P1

5 PGND

Name Pin Description

Inverting Input. Connect to AGND or PGND to enable output.

G ate Drive Output: Held LOW unless required inputs are present and V threshold.

Thermal Pad (MLP only). Exposed metal on the bottom of the package, which is electrically connected to pin 5.

Power Ground (MLP only). For output drive circuit; separates sw itching noise from inputs.

is above U VLO

Output Logic

IN+ IN− OUT

(7)

0 0

(7)

0 1 0 1 1 1

Note :

7. Default input signal if no external connection is made.

(7)

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

VDD

OUT

GND

UVLO

DD_OK

IN+

100kΩ

VDD

OUT

PGND

UVLO

DD_OK

IN+

100kΩ

AGND

0.4Ω

Block Diagrams

Figure 5. Simplified Block Diagram (SOT23 Pin-out)

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Figure 6. Simplified Block Diagram (MLP Pin-out)

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Absolute Maximum Ratings

Stres ses ex ceeding the abs olute maximum ratings may damage the devic e. The device may not func tion or be operable above the r ec ommended oper ating conditions and s tr ess ing the parts to thes e levels is not rec ommended. In addition, extended ex pos ure to s tres s es abov e the r ecommended oper ating conditions may aff ec t device reliability. The absolute maximum ratings are stress ratings only.

Symbol

VDD VDD to PGND -0.3 20.0 V

VIN Voltage on IN+ and IN- to GND, AGND, or PGND GND - 0.3 VDD + 0.3 V

Voltage on OUT to GND, AGND, or P GND GND - 0.3 VDD + 0.3 V

OUT

TL Lead Soldering Temperature (10 Seconds) +260 ºC TJ Junction Temperature -55 +150 ºC

Storage Temperature -65 +150 ºC

STG

Parameter Min. Max. Unit

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specif ied to ensure optimal perf ormance to the datasheet specif ications. ON Semiconduct or does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

VDD Supply Voltage Range 4.5 18.0 V

VIN Input Voltage IN+, IN- 0 VDD V

Parameter Min. Max. Unit

TA Operating Ambient Temperature -40 +125 ºC

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Electrical Characteristics

Unless otherw is e noted, VDD = 12 V, TJ = -40°C to +125°C. Currents are defined as positive into the device and negative out of the device.

Symbol Parameter Conditions Min. Typ. Max. Unit

Supply

IDD

Supply Current Inputs/EN Not Connected

FAN3100C FAN3100T 0.50 0.80 mA

(8)

0.20 0.35 mA

VON Turn-On Voltage 3.5 3.9 4.3 V

VDD Operating Range 4.5 18.0 V

Turn-Off Voltage 3.3 3.7 4.1 V

OFF

Inputs (FAN3100T)

IN+, IN- Logic LOW Voltage, Maximum 0.8 V

INL_T

IN+, IN- Logic HIGH Voltage, Minimum 2.0 V

INH_T

Non-inverting Input IN from 0 to VDD -1 175 µA

IN+

Inverting Input IN from 0 to VDD -175 1 µA

IN-

IN+, IN- Logic Hysteresis Voltage 0.2 0.4 0.8 V

HYS

Inputs (FAN3100C)

IN+, IN- Logic LOW Voltage 30 %VDD

INL_C

IN+, IN- Logic HIGH Voltage 70 %VDD

INH_C

IN Current, LOW IN from 0 to VDD -1 175 µA

INL

IN Current, HIGH I N from 0 to VDD -175 1 µA

INH

IN+, IN- Logic Hysteresis Voltage 17 %VDD

HYS_C

Output

OUT Current, Mid-Voltage, Sinking

SINK

OUT Current, Mid-Voltage, Sourcing

SOURCE

OUT Current, Peak, Sinking

PK_SINK

PK_SOURCE

OUT Current, Peak, Sourcing

Output Rise Time

RISE

Output Fall Time

FALL

(10)

(9)

tD1, tD2 Output Prop. Delay, CMOS Inputs tD1, tD2 Output Prop. Delay, TTL Inputs

Output Reverse Current Withstand

RVS

(9)

(10)

0 – 5 VIN; 1 V/ns Slew Rate 9 16 30 ns

(9)

OUT at V C

LOAD

OUT at V

(9)

LOAD

0 – 12 VIN; 1 V/ns Slew Rate 7 15 28 ns

500 mA

/2,

= 0.1 µF, f = 1 kHz

/2,

= 0.1 µF, f = 1 kHz

2.5 A

-1.8 A

= 0.1 µF, f = 1 kHz 3 A

= 0.1 µF, f = 1 kHz -3 A = 1000 pF 13 20 ns = 1000 pF 9 14 ns

Note s:

8. Low er supply current due to inactive TTL circuitry.

9. Not tested in production.

10. See Timing Diagrams of Figure 7 and Figure 8.

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

90%

10%

Output

Input

RISE

FALL

INL

INH

90%

10%

Output

Input

FALL

RISE

INL

INH

Figure 7. Non-Inverting

Figure 8. Inverting

Timing Diagrams

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Figure 9. IDD (Static) vs. Supply Voltage

Figure 10. IDD (Static) vs. Supply Voltage

Figure 11. IDD (No-Load) vs. Frequency

Figure 12. IDD (No-Load) vs. Frequency

Figure 13. IDD (1 nF Load) vs. Frequency

Figure 14. IDD (1 nF Load) vs. Frequency

Typical Perform ance Characteristics

Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Figure 15. IDD (Static) vs. Temperature

Figure 16. IDD (Static) vs. Temperature

Figure 17. Input Thresholds vs. Supply Voltage

Figure 18. Input Thresholds vs. Supply Voltage

Figure 19. Input Thresholds % vs. Supply Volta ge

Typical Perform ance Characteristics

Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Figure 20. CMOS Input Thresholds vs. Temperature

Figure 21. TTL Input Thresholds vs. Temperature

Figure 22. U VLO Thresholds vs. Temperature

Figure 23. UVLO Hysteresis vs. Temperature

Figure 24. Propagation Delay vs. Supply Voltage

Figure 25. Propagation Delay vs. Supply Voltage

Typical Perform ance Characteristics

Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Figure 26. Propagation Delay vs. Supply Voltage

Figure 27. Propagation Delay vs. Supply Voltage

Figure 28. Propagation Delay vs. Temperature

Figure 29. Propagation Delay vs. Temperature

Figure 30. Propagation D elay vs. Temperature

Figure 31. Propagation Delay vs. Temperature

Typical Perform ance Characteristics

Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Figure 32. Fall Time vs. Supply Voltage

Figure 33. R ise Time vs. Supply Voltage

Figure 34. R ise and Fall Time vs. Temperature

Figure 35. Rise / Fall Waveforms with 1 nF Load

Figure 36. Rise / Fall Waveforms with 10 nF Load

Typical Perform ance Characteristics

Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Figure 37. Quas i-Static Source Current with VDD=12 V

Figure 38. Quas i-Static Sink Current with VDD=12 V

Figure 39. Quas i-Static Source Current wi th VDD=8 V

Figure 40. Quas i-Static Sink Current with VDD=8 V

470µF

Al. El

OUT

1µF

ceramic

4.7µF

ceramic

LOAD

0.1µF

OUT

1kHz

Current Probe

LECROY AP

015

Figure 41. Quas i-Static I

/ V

Test Circuit

Typical Perform ance Characteristics

Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.

OUT

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Input stage

OUT

Applications Information

Input Thresholds

The FA N3 100 offers TTL or CMOS input thresholds. In the FAN3100T, the input thresholds meet industry-standard TTL logic thr es holds, independent of the V

voltage, and

there is a hysteresis voltage of approximately 0.4 V. These levels permit the inputs to be driven from a range of input logic s ignal levels f or w hich a voltage over 2 V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and f alling edges w ith a slew rate of 6 V/µs or f as ter, s o the ris e time fr om 0 to

3.3 V s hould be 550 ns or less . With reduced s lew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. In the FAN3100C, the logic input thresholds are dependent on the V edge thres hold is approximately 55% of V falling edge threshold is approximately 38% of V

level and, w ith VDD of 12 V, the logic rising

and the input

. The CMOS input conf iguration of fers a hyster esis voltage of approximately 17% of V

. The CMOS inputs can be used

with relatively slow edges (approaching DC) if good decoupling and bypass techniques are incorporated in the sy stem design to prevent noise f rom violating the input voltage hyster esis w indow . This allow s setting precise timing intervals by fitting an R-C circuit between the contr olling signal and the IN pin of the driver. The slow rising edge at the IN pin of the dr iver introduc es a delay betw een the controlling signal and the OUT pin of the driver.

Static Supply Current

In the IDD (static) typical perf ormance graphs (Figure 9 Figure 10 and Figure 15 - Figure 16), the curve is produced w ith all inputs floating (OUT is LOW) and indicates the lowest static I

current for the tested

conf iguration. For other states, additional current f low s through the 100 kΩ res istors on the inputs and outputs show n in the block diagrams (see Figure 5 - Figure 6). In these cases, the actual static I

current is the value

obtained from the curves plus this additional current.

MillerDrive™ Gate Drive Technology

FAN3100 drivers incorporate the MillerDrive™ architecture show n in Figure 42 for the output s tage, a combination of bipolar and MOS devices capable of providing large currents over a w ide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between 1/3 to 2/3 V or low rail. The pur pose of the MillerDrive™ arc hitectur e is to s peed up sw itc hing by pr oviding the highest c urr ent during the Miller plateau r egion when the gate-dr ain capac itance of the M OSFET is being charged or discharged as part of the turn-on / turn-off process. For applications that have z ero v oltage sw itc hing during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast sw itching even though

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and the MOS devices pull the output to the high

the Miller plateau is not present. This situation often occ urs in sy nc hronous rec tif ier applications bec aus e the body diode is gener ally conduc ting bef ore the MOSFET is sw itched on. The output pin slew rate is determined by V

voltage and

the load on the output. It is not user adjustable, but if a slow er r ise or f all time at the MOSFET gate is needed, a series resistor can be added.

Figure 42. MillerDrive™ Output Architecture

Under-Voltage Lockout

The FAN3100 start-up logic is optimized to drive ground referenced N-channel MOSFETs w ith a under-voltage lockout (UVLO) f unc tion to ensur e that the IC starts up in an orderly fashion. When V

is rising, yet below the

3.9 V operational level, this c irc uit holds the output LOW, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.2 V before the part shuts down. This hys teres is helps prev ent c hatter w hen low V

supply voltages have noise from the power

sw itching. This configuration is not suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver w ould turn the P-channel MOSFET on w ith V

below 3.9 V.

VDD Bypass Capacit or Guidelines

To enable this IC to turn a pow er device on quickly, a local, high-frequency, bypass capacitor C ESR and ESL should be connected betw een the VDD and GND pins w ith minimal trace length. This c apacitor is in addition to bulk electrolytic capacitance of 10µF to 47µF often found on driver and controller bias circuits.

A typical criterion for choosing the value of C keep the ripple voltage on the V

supply ≤5%. Often this

is achieved w ith a value ≥ 20 times the equivalent load

capacitance C

, defined here as Q

EQV

capac itors of 0.1µF to 1 µF or larger are common choices, as are dielectrics, s uch as X5R and X7R, w hich have good temperature char acteristics and high pulse curr ent capability. If cir cuit noise af fects normal operation, the value of C may be inc reas ed to 50-100 times the C be split into tw o capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10 nF, mounted c loses t to the VDD and GND pins to carry the higher-frequency components of the current pulses.

BYP

gate/VDD

, or C

EQV

w ith low

is to

BYP

. Ceramic

BYP

may

BYP

Page 15

FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

PWM

BYP

FAN3100

PWM

BYP

FAN3100

IN+

IN-

OUT

0 0 0 0 1 0 1 0 1 1 1

VDD

GND

IN+

OUT

PWM

FAN3100

VDD

GND

IN-

IN+

OUT

PWM

FAN3100

Layout and Connection Guidelines

The FAN3100 incorporates fast-reacting input circuits, short propagation delays, and pow erful output stages capable of deliver ing c urr ent peaks ov er 2 A to f ac ilitate voltage tr ansition times f r om under 10 ns to over 100 ns.

Figure 44 show s the current path when the gate driv er turns the MOSFET off. Ideally, the driver shunts the current directly to the sour ce of the MOSFET in a small circuit loop. For fast turn-off times, the r esistance and inductance in this path should be mi nimized.

The following layout and connection guidelines are strongly recommended:

 Keep high-current output and pow er ground paths

separate from logic input signals and signal ground paths. This is especially critical when dealing with TTL-level logic thresholds.

 Keep the driver as close to the load as possible to

minimize the length of high-current traces. This reduces the series inductance to improve high-speed sw itching, while reducing the loop area that can radiate EMI to the driver inputs and other surrounding circuitry.

 The FAN3100 is available in two packages w ith

slightly different pinouts, offering similar performance. In the 6-pin MLP package, Pin 2 is internally connected to the input analog ground and should be connected to pow er ground, Pin 5, through a short direct path underneath the IC . In the 5-pin SOT23, the internal analog and power ground connections are made through separate, individual bond wires to Pin 2, which should be used as the common ground point for pow er and control signals.

Figure 44. Current Path for MOSFET Turn-Off

Truth Table of Logic Oper ation

The tr uth table indicat es the oper ational states using the dual-input configuration. In a non-inverting driver configuration, the IN- pin should be a logic LOW signal. If the IN- pin is connected to logic HIGH, a disable function is realized, and the driver output remains LOW regardless of the state of the IN+ pin.

 Many high-speed pow er circuits can be susceptible

to noise injected from their ow n output or other external sources, possibly causing output retriggering. These effects can be especially obvious if the circuit is tested in breadboard or non-optimal circuit layouts w ith long input, enable, or output leads. For best results, make connections to all pins as short and direct as possible.

In the non-inver ting driver configuration in Figure 45, the IN- pin is tied to ground and the input signal (PWM) is applied to IN+ pin. The IN- pin can be c onnec ted to logic HIGH to disable the driver and the output remains LOW, regardless of the state of the IN+ pin.

 The turn-on and turn-off current paths should be

minimized as discussed in the following sections.

Figure 43 show s the pulsed gate drive current path w hen the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, C MOSFET gate and to ground. To reach the high peak currents possible, the resistanc e and inductanc e in the path should be minimized. The localized C contain the high peak current pulses w ithin this driverMOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller.

, and flows through the driver to the

BYP

acts to

BYP

Figure 45. Dual-Input Driver Enabled,

Non-Inverting Configuration

In the inver ting driver application show n in Figure 46, the IN+ pin is tied HIGH. Pulling the IN+ pin to GND f orc es the output LOW, regardless of the state of the IN- pin.

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Figure 43. Current Path for MOSFET Turn-On

Inverting Configuration

Figure 46. Dual-Input Driver Enabled,

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

IN+

IN-

OUT

Turn-on Threshold

IN+

)

IN-

OUT

Turn-on Threshold

GAT E

= QG • VGS • fSW

(2)

DYNAMIC

= I

DYNA MI C

• VDD

(3)

DYNAMIC

= 8 mA • 10 V = 0.080 W

(6)

Operational Wave forms

At power up, the dr iver output remains LOW until the VDD

source voltage, V sw itching frequency, f

, with gate charge, QG, at

, is determined by:

voltage reac hes the turn-on thres hold. The magnitude of the OUT pulses r ises w ith V reached. The non-inverting operation illustrated in Figure 47 s how s that the output remains LOW until the UV LO thres hold is reac hed, then the output is in-phase w ith the input.

until steady -state VDD is

Dynamic Pre-driv e / Shoot-through Current: A pow er loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-dow n resistors , c an be obtained using

(no-Load) vs. Frequency graphs in Typical

the I

Performance Characteristics to determine the current

draw n from VDD under actual operating

DYNAMIC

conditions:

Once the pow er dissipated in the driver is determi ned, the driver junction rise w ith res pect to circ uit board c an be evaluated us ing the f ollow ing thermal equation, ass uming

w as determined for a similar thermal design (heat

sinking and air flow ):

TOTAL

•

+ TB (4)

TJ = P where:

Figure 47. Non-Inverting Start-Up Waveforms

For the inverting configuration of Figure 46, start-up wavef or ms are s hown in Figure 48. With IN+ tied to VDD and the input signal applied to IN–, the OUT pulses are inverted w ith respect to the input. At pow er up, the inverted output remains LOW until the V reaches the turn-on thres hold, then it follow s the input with inverted phase.

voltage

= driver junction temperature

= (psi) thermal characterization parameter

relating temperature rise to total power dissipation

TB = board temperature in location defined in the

Thermal Characteristics table.

In a typic al f orw ard c onv erter application with 48 V input, as show n in Figure 49, the FDS2672 would be a potential MOSFET selection. The typical gate charge w ould be 32 nC with V

= VDD = 10 V. Using a TTL input driver at a

sw itching frequency of 500 kHz, the total power dissipation can be calculated as:

= 32 nC • 10 V • 500 kHz = 0.160 W (5)

GAT E

= 0.24 W (7)

TOTAL

The 5-pin SOT23 has a junction-to-lead thermal characterization parameter

= 51°C/W.

In a sy s tem application, the localized temperature around the devic e is a f unc tion of the layout and c onstr uc tion of

Figure 48. Inverting Start-Up Waveforms

the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from

Thermal Guidelines

Gate drivers us ed to s witch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of pow er. It is important to deter mine the driver power diss ipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits.

The total pow er diss ipation in a gate driv er is the s um of two components; P

= P

TOTAL

Gate Driving Loss: The most s ignificant pow er loss

GAT E

results f rom supplying gate cur rent ( char ge per unit time) to sw itc h the load MOSFET on and off at the

GAT E

+ P

and P

DYNAMIC

sw itching frequency. The power dissipation that

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results f rom driving a MOSFET at a specif ied gate-

DYNAMIC

(1)

exceeding the maximum rating of 150°C; with 80% derating, T

would be limited to 120°C. Rearranging

Equation 4 deter mines the boar d temperatur e required to maintain the junction temperature below 120°C:

= TJ - P

B,MA X

= 120°C – 0.24W • 51°C/W = 108°C (9)

B,MA X

TOTAL

•

(8)

For comparison purpos es , replace t he 5-pin SOT23 used in the previous example w ith the 6-pin MLP package with

= 2.8°C/W. The 6-pin MLP package can operate at a

PCB temperature of 119°C, w hile maintaining the junction temperature below 120°C. This illustrates that the physically smal ler MLP package with thermal pad offers a more c onductiv e path to remove the heat f r om the driver . Consider the tradeof fs betw een r educing overall circ uit size w ith junction temperature reduction for increased reliability.

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

IN+

IN-

OUT

VDD

PGND

FAN3100

PWM

ENABLE

Active LOW

1 2 3

AGND

SEC

PWM

0.1µF

FAN3100

OUT

PWM Control/ Isolation

SEC

ISOLATION

DRV

FAN3100

FAN3100C

OUT

Delay

OUT

Typical Application Diagrams

Figure 49. Forward Converter, Primary-Side G ate D rive (MLP Package Shown)

Figure 50. Driver for Two-Transistor Forward Converter Gate Transformer

Figure 51. Secondary Synchronous Rect ifi er Driver

www.onsemi.com 17

Figure 52. Programmable Delay Using CMOS Input

Page 18

FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Table 1. Related Products

Part

Number

FAN3100C

Type

Single 2 A

Gate

(11)

Drive

(Sink/Src)

+2.5 A / -1.8A CMOS Singl e Channel of Tw o-Input/One-Output SOT23-5, M LP6

Threshold

Input

Logic Package

FAN3100T

FAN3226C Dual 2 A

FAN3226T Dual 2 A

FAN3227C Dual 2 A

FAN3227T Dual 2 A

FAN3228C Dual 2 A

FAN3228T Dual 2 A

Single 2 A

+2.5 A / -1.8A TTL S ingle Channel of Two-Input/One-Output SOT23-5, M LP6

+2.4 A / -

1.6 A

+2.4 A / -

1.6 A

+2.4 A / -

1.6 A

+2.4 A / -

1.6 A

+2.4 A / -

1.6 A

+2.4 A / -

1.6 A

CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8

TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8

CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8

TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8

CMOS Dual Channels of Two-Input/One-Output, Pin Config.1 S OIC8, M L P8

TTL Dual Channels of Two-Input/One-Output, Pin Config.1 S OIC8, M L P8

FAN3229C Dual 2 A

FAN3229T Dual 2 A

FAN3223C Dual 4 A

FAN3223T Dual 4 A

FAN3224C Dual 4 A

FAN3224T Dual 4 A

FAN3225C Dual 4 A

FAN3225T Dual 4 A

+2.4 A / -

1.6 A

+2.4 A / -

1.6 A

+4.3 A / -

2.8 A

+4.3 A / -

2.8 A

+4.3 A / -

2.8 A

+4.3 A / -

2.8 A

+4.3 A / -

2.8 A

+4.3 A / -

2.8 A

CMOS Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP 8

TTL Dual Channels of Two-Input/One-Output, Pin Config.2 S OIC8, M L P8

CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8

TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8

CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8

TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8

CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8

TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8

Note :

11. Typical currents w ith OUT at 6 V and V

= 12 V.

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Page 19

FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Physical Dimensions

TOP VIEW

0.05

2.0

PIN#1 IDENT

SIDE VIEW

RECOMMENDED

LAND PATTERN

BOTTOM VIEW

SEATING PLANE

PIN #1 IDENT

0.65

1.30

1.21

0.52(6X)

0.90

0.42(6X)

0.65

2.25

1.68

(0.40)

(0.70)

NOTES:

A. PACKAGE DOES NOT FULLY CONFORM

O JEDEC MO-229 REGISTRATION

B. D

IMENSIONS ARE IN MILLIMETERS.

C.DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 2009.

D.LAND PATTERN RECOMMENDATION IS

EXIST

ING INDUSTRY LAND PATTERN.

E. DRAWING FILENAME: MKT-MLP06Krev5.

2.00±0.05

1.40±0.05

0.80±0.05

(0.20)4X

0.32±0.05

0.10 C A B

0.05

0.30±0.05

(6X)

(0.60)

0.08

0.10

0.75±0.05

0.025±0.025

0.20±0.05

1.72

0.15

Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms and conditions, specifically the warranty therein, which covers ON Semi conductor products.

Figure 53. 2x2 mm, 6-Lead, Molded Leadless Package (MLP)

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Page 20

FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Physical Dimensions

LAND PATTERN RECOMMENDATION

0.10

0.20

C A B

0.60 REF

0.55

0.35 SEATING PLANE

0.25

GAGE PLANE

8° 0°

NOTES: UNLESS OTHEWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

O-178, ISSUE B, VARIATION AA,

B) AL

L DIMENSIONS ARE IN MILLIMETERS.

1.45 MAX

1.30

0.90

0.15

0.05

1.90

0.95

0.50

0.30

3.00

2.60

1.70

1.50

3.00

2.80

SYMM

0.950.95

2.60

0.70

1.00

SEE DETAIL A

0.22

0.08

C) MA05Brev5

TOP VIEW

(0.30)

Figure 54. 5-Lead SOT-23

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Page 21

FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

PUBLICATION ORDERING INFORMATION

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