Datasheet FAN5071 Datasheet (Fairchild Semiconductor)

www.fairchildsemi.com

FAN5071

High Performance Programmable Synchronous
DC-DC Controller for Multi-Voltage Platforms

Features

• Output programmable in 25mV steps from 1.05V to

1.825V using a dynamically programmable integrated
5-bit DAC

• Controls adjustable linears for Vclock (2.5V),
Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), and
Vadj (1.2V nominal)

• Remote sense

• Programmable Active Droop

™

up to 200mV

• Drives N-Channel MOSFETs

• Overcurrent protection using MOSFET sensing

• Overvoltage protection including startup

• 85% efficiency typical at full load

• Integrated Power Good and Enable/Soft Start functions

• Linears start instantly

• Meets Intel VRM8.5 specifications using minimum
number of external components

• 24 pin SOIC package

Applications

• Power supply for Pentium

• VRM for Pentium III processor

• Programmable multi-output power supply

®

III Platforms

Block Diagram

+3.3V

+1.2V/Adj

+2.5V

9

+

REF

-

10

VCCP

11

+

-

12

OSC

PWRGD,
OCL

REF

PWRGD,
OCL

OCL

-

+

Description

The FAN5071 is a synchronous mode DC-DC controller IC
which provides a highly accurate, programmable set of output
voltages for multi-voltage platforms such as the Intel Pentium III,
and provides a complete solution for all Intel VRM8.5 CPU
applications, and for other high-performance processors. The
FAN5071 features remote voltage sensing, independently
adjustable current limit, and a proprietary wide-range Pro­grammable Active Droop
response and VRM8.5 compliance. The FAN5071 uses a 5-bit
D/A converter to dynamically program the output voltage dur­ing operation from 1.05V to 1.825V in 25mV steps. The
FAN5071 uses a high level of integration to deliver load cur­rents in excess of 28A from a 5V source with minimal exter­nal circuitry. Synchronous-mode operation offers optimum
efficiency over the entire specified output voltage range. An
on-board precision low TC reference achieves 0.8% voltage
regulation without expensive external components. The
FAN5071 includes linear regulator controllers for Vclock
(2.5V),Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V),
and Vadjustable (1.2V nominal) each adjustable with an
external divider. The FAN5071 also offers integrated functions
including open-collector Power Good, Output Enable/Soft

+5V

VCCA

21

-

+

-

+

™

for optimal converter transient

19

R

D

+12V

18

20

24
1

R

VCCP
HIDRV

+5V

S

15

14

3.3/1.5V

Pentium is a registered trademark of Intel Corporation. Programmable Active Droop is a trademark of Fairchild Semiconductor.

13

5-Bit

DAC

87654

VID2

VID0

VID1

V

PWRGD, OCL

VID4

VID3

-

+

1.24V

Reference

-

+

3

GNDA

Digital

Control

16

ENABLE/SS

Powe r

Good

2

23

22

17

LODRV

GNDP

PWRGD

VCC

REV. 1.0.4 1/29/02

2

FAN5071

.

.

Start and current limiting. The linears start instantly, not

Pin Assignments

waiting for softstart. The FAN5071 is available in a 24 pin
SOIC package.

HIDRV

SW

GNDA

VID4
VID3
VID2

VID1

VID0

VADJGATE

VADJFB

VCKGATE

VCKFB

1
2
3
4
5
6
7
8
9
10
11
12

FAN5071

24
23
22
21
20
19
18
17
16
15
14
13

Pin Definitions

Pin Number Pin Name Pin Function Description

1 HIDRV

2SW

3 GNDA

4-8 VID4-0

9 VADJGATE Gate Driver for VADJ Transistor. For Adjustable output.

10 VADJFB Voltage Feedback for VADJ.

11 VCKGATE Gate Driver for VCK Transistor. For 2.5V output.

12 VCKFB

13 VAGPFB Voltage Feedback for VAGP.

14 VAGPGATE Gate Driver for VAGP Transistor. For 3.3/1.5V output.

15 TYPEDET Type Detect. Sets 3.3V or 1.5V for AGP.

16 ENABLE/SS Output Enable. A logic LOW on this pin will disable all outputs. An internal current

17 PWRGD Power Good Flag. An open collector output that will be logic LOW if any output

18 ILIM

19 DROOP Droop Set. Use this pin to set magnitude of active droop.

20 VFB

21 VCCA

22 GNDP

23 LODRV V

24 VCCP

High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The

trace from this pin to the MOSFET gate should be <0.5".

High Side Driver Source and Low Side Driver Drain Switching Node. Together

with DROOP and ILIM pins allows FET sensing for V

current.

CC

Analog Ground. Return path for low power analog circuitry. This pin should be

connected to a low impedance system ground plane to minimize ground loops.

Voltage Identification Code Inputs. These open collector/TTL compatible inputs

will program the output voltage over the ranges specified in Table 1.

Voltage Feedback for VCK.

source allows for open collector control. This pin also doubles as soft start for the
switcher.

voltage is not within ±14% of the nominal output voltage setpoint.

V

Current Feedback. Pin 18 is used in conjunction with pin 2 as the input for the

CC

V

current feedback control loop. Layout of these traces is critical to system

CC

performance. See Application Information for details.

Vcc Voltage Feedback. Pin 20 is used as the input for the V

voltage feedback

CC

control loop. See Application Information for details regarding correct layout.

Analog V

Connect to system 5V supply and decouple with a 0.1µF ceramic

CC

capacitor.

Power Ground. Return pin for high currents flowing in pin 24 (V

Low Side FET Driver. Connect this pin to the gate of an N-channel MOSFET

CC

CCP

).

for synchronous operation. The trace from this pin to the MOSFET gate should be
<0.5".

Power V

For all FET drivers. Connect to system 12V supply through a 33 Ω , and

CC

decouple with a 1µF ceramic capacitor.

VCCP
LODRV
GNDP
VCCA
VFB
DROOP
ILIM
PWRGD
SS/ENABLE
TYPEDET
VAGPGATE
VAGPFB

REV. 1.0.4 1/29/02

PRODUCT SPECIFICATION FAN5071

Absolute Maximum Ratings

Supply Voltage V

Supply Voltage V

to GND 15V

CCP

to GND 13.5V

CCA

Voltage Identification Code Inputs, VID0-VID4 VCCA

All Other Pins 13.5V

Junction Temperature, T

J

150°C

Storage Temperature -65 to 150°C

Lead Soldering Temperature, 10 seconds 300°C

Thermal Resistance Junction-to-case, Θ

Note 1: Component mounted on demo board in free air.

1

JA

75°C/W

Recommended Operating Conditions

Parameter Conditions Min. Typ. Max. Units

Supply Voltage V

CCA

Input Logic HIGH 2.0 V

Input Logic LOW 0.8 V

Ambient Operating Temperature 0 70 °C

Output Driver Supply, V

CCP

4.50 5 5.25 V

10.8 12 13.2 V

Electrical Specifications

(V

= 5V, V

CCA

The • denotes specifications which apply over the full operating temperature range.

Parameter Conditions Min. Typ. Max. Units

V

Regulator

CC

Output Voltage See Table I • 1.05 1.825 V

Output Current 28 A

Initial Voltage Setpoint I

Output Temperature Drift T

Line Regulation V

Internal Droop Impedance

Maximum Programmable Droop • 200 mV

Output Ripple 20MHz BW, I

Total Output Variation, Steady State

Total Output Variation, Transient

Short Circuit Detect Current • 45 50 60 µA

Efficiency I

Output Driver Rise & Fall Time See Figure 3 50 nsec

Output Driver Deadtime See Figure 3 50 nsec

Duty Cycle 0 100 %

5V UVLO • 3.76 4 4.24 V

12V UVLO • 7.65 8.5 9.35 V

Soft Start Current 5 10 17 µA

= 12V, V

CCP

= 1.425V, and T

OUT

3

2

= +25°C using circuits in Figure 1, unless otherwise noted.)

A

= 0.8A, V

LOAD

= 0 to 70°C, V

A

= 4.75V to 5.25V • +10 mV/V

IN

I

= 0.8A to 30A 13.0 14.4 15.8 K Ω

LOAD

1

V

= 1.425V

VID

I

= 0.8A to I

LOAD

= 18A, V

LOAD

= 1.425V 1.453 1.465 1.477 V

VID

= 1.425V • -6 mV

VID

= 28A 20 mVpk

LOAD

3

, V

max

VID

= 1.425V

VID

= 1.425V 83 %

• 1.360 1.490 V

• 1.335 1.515 V

REV. 1.0.4 1/29/02

3

FAN5071

4

≤

≤

≤

≤

Electrical Specifications

(V

CCA

= 5V, V

= 12V, V

CCP

= 1.425V, and T

OUT

(Continued)

= +25°C using circuits in Figure 1, unless otherwise noted.)

A

The • denotes specifications which apply over the full operating temperature range.

Parameter Conditions Min. Typ. Max. Units

Adjustable Linear Regulator

Output Voltage I

Over Current Trip Level 80 %V

2A • 1.188 1.212 1.236 V

LOAD

O

VCLK Linear Regulator

Output Voltage I

Over Current Trip Level 80 %V

2A • 2.375 2.5 2.625 V

LOAD

O

VAGP Linear Regulator

Output Voltage I

Output Voltage I

Over Current Trip Level 80 %V

2A, TYPEDET = 0V • 1.425 1.5 1.575 V

LOAD

2A, TYPEDET = OPEN • 3.135 3.3 3.465 V

LOAD

O

Common Functions

Oscillator Frequency • 255 300 345 kHz

PWRGD Threshold

4

Switcher Logic HIGH [V

Logic LOW [V

+ 85mV]

VID

–155mV]

VID

•

88

•

80

112
120

%

PWRGD Delay Switcher HIGH → LOW 6 µsec

PWRGD Hysteresis Switcher 25 mV

PWRGD Threshold

4

Linear

All Outputs • 80 %V

out

Regulators

Notes:

1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is

measured at the converter’s VFB sense point.

2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than

0.5m Ω trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal
performance.

3. Using the VFB pin for remote sensing of the converter’s output at the load, and the appropriate droop, the converter will be in

compliance with Intel’s VRM 8.5 specification. If Intel specifications on maximum plane resistance from the converter’s output
capacitors to the CPU are met, the specifications at the capacitors will also be met.

4. PWRGD will be high only if BOTH the linears and the switcher conditions are met. PWRGD will be low if EITHER condition is met.

REV. 1.0.4 1/29/02

FAN5071

Table 1. Output Voltage Programming Codes for FAN5071

VID25mV VID3 VID2 VID1 VID0 Nominal V

001001.050V

101001.075V

000111.100V

100111.125V

000101.150V

100101.175V

000011.200V

100011.225V

000001.250V

100001.275V

011111.300V

111111.325V

011101.350V

111101.375V

011011.400V

111011.425V

011001.450V

111001.475V

010111.500V

110111.525V

010101.550V

110101.575V

010011.600V

110011.625V

010001.650V

110001.675V

001111.700V

101111.725V

001101.750V

101101.775V

001011.800V

101011.825V

OUT

5

Note:

1. 0 = processor pin is tied to GND.

1 = processor pin is pulled up to 3.3V.

REV. 1.0.4 1/29/02

PRODUCT SPECIFICATION FAN5071

Typical Operating Characteristics

(V

CCA

= 5V, V

= 12V, and TA = +25°C using circuit in Figure 1, unless otherwise noted.)

CCP

90

85

80

Efficiency (%)

75

70

65

2 4 6 8 10 12 14 16 18 20 22 24 26 28

Vcpu Efficiency vs.Output Current

Output Current (A)

Output Ripple, 1.425 @ 28A

(20mV/div)

CPU

V

1.48

1.46

1.44

1.42

Vout (V)

1.4

1.38

1.36

1.34

0369121518212428

Droop,Circuit of Fig.1

Output Current (A)

Transient Response, 28A to 0.1A

1.515V

(50mV/div)

CPU

V

1.425V

1.335V

(50mV/div)

CPU

V

Time (2µs/division)

Transient Response, 0.1A to 28A

Time (20µs/division)

1.515V

1.425V

1.335V

5V/div 5V/div

Time (20µs/division)

Switching Waveforms, 28A Load

Time (20µs/division)

HIDRV
pin

LODRV
pin

REV. 1.0.4 1/29/02

6

FAN5071

Typical Operating Characteristics (continued)

Output Startup, System Power-up

(1V/div)V

CPU

V

(2V/div)

IM

Time (10ms/division)

Application Circuit

L1

+5V

(Optional)

C

IN

Output Startup from Enable

(1V/div) ENABLE (2V/div)

CPU

V

Time (20ms/div)

VO

VID4
VID3
VID2

VID1

VID0

C

OUT

R8–12

L2

3.3V IN

1.2V†

C2

D1

Q3

C8

Q1

Q2

2.5V†

R7

R6

R5

R2

R3

Q4

C9

C1

1
2

3

4

U1

5

FAN5071

6
7
8
9
10
11

12

24
23

22

21
20
19
18

17
16
15

14

13

TYPEDET

Figure 1. Application Circuit for VRM8.5 Motherboards

(Worst Case Analyzed! See Appendix for Details)

R1

+12V

C5

C3

Q5

C7

C4

3.3/1.5V
(AGP)†

† Adjustable with an external divider.

VCC

ENABLE/SS

R4

PWRGD

C6

7 REV. 1.0.4 1/29/02

FAN5071

Table 3. FAN5071 Application Bill of Materials for Intel VRM8.5 Motherboards

(Components based on Worst Case Analysis—See Appendix for Details)

Reference Manufacturer Part # Quantity Description Requirements/Comments

C1 AVX

TAJB475M010R5

C2, C5 Panasonic

ECU-V1C105ZFX

C3-4,C6 Panasonic

ECU-V1H104ZFX

C7-9 Sanyo

6MV1000FA

C

IN

Rubycon
16ZL1000M

C

OUT

Rubycon

6.3ZL1500M

D1 Motorola

MBRD835L

L1 Any Optional 1.3µH, 10A Inductor DCR ~ 6mΩ

L2 Coiltronics

HC2-1R0

Q1 Fairchild

FDD6690A

Q2 Fairchild

FDD6680A

Q3-5 Fairchild

NDB4032L

R1 Any 1 10Ω

R2-3, R6 Any 3 4.7Ω

R4, R8-12 Any 6 10KΩ

R5 Any 1 27.4KΩ

R7 Any 1 8.66KΩ

U1 Fairchild

FAN5071M

1 4.7µF, 10V Capacitor

2 1µF, 16V Capacitor

3 100nF, 50V Capacitor

3 1000µF, 6.3V

Electrolytic

4 1000µF, 16V

I

RMS

= 2.3A

Electrolytic

8 1500µF, 6.3V

ESR ≤ 23mΩ

Electrolytic

1 8A Schottky Diode

See Note 1.

1 1.0µH, 34A Inductor DCR ~ 1mΩ

2 N-Channel MOSFET R

= 17mΩ @ VGS = 4.5V

DS(ON)

See Note 2.

2 N-Channel MOSFET R

= 13mΩ @ VGS = 4.5V

DS(ON)

See Note 2.

3 N-Channel MOSFET

1 DC/DC Controller

Notes:

1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with
Intel dI/dt requirements. L1 may be omitted if desired.

2. For 30A designs using the TO-220 MOSFETs, heatsinks with thermal resistance Θ
using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections,
refer to Applications Bulletins AB-8 and AB-15.

< 20°C/W should be used. For designs

SA

Test Parameters

t

R

90%

10% 10%

2V

t

DT

2V

Figure 2. Output Drive Timing Diagram

8 REV. 1.0.4 1/29/02

90%

2V

t

F

HIDRV

t

DT

2V

LODRV

PRODUCT SPECIFICATION FAN5071

Application Information

The FAN5071 Controller

The FAN5071 is a programmable synchronous DC-DC con­troller IC. When designed around the appropriate external
components, the FAN5071 can be configured to deliver more
than 28A of output current, as appropriate for Intel’s
VRM8.5, and other processors. The FAN5071 functions as a
fixed frequency PWM step down regulator.

Main Control Loop

Refer to the FAN5071 Block Diagram on page 1. The
FAN5071 implements “summing mode control,” which is
different from both classical voltage-mode and current-mode
control. It provides superior performance to either by allowing
a large converter bandwidth over a wide range of output loads.

The control loop of the regulator contains two main sections:
the analog control block and the digital control block. The
analog section consists of signal conditioning amplifiers
feeding into a comparator which provides the input to the
digital control block. The signal conditioning section accepts
input from the DROOP (current feedback) and VFB (voltage
feedback) pins and sets up two controlling signal paths. The
first, the voltage control path, amplifies the difference
between the VFB signal and the reference voltage from the
DAC and presents the output to one of the summing amplifier
inputs. The second, current control path, takes the difference
between the DROOP and SW pins when the high-side
MOSFET is on, reproducing the voltage across the MOSFET
and thus the input current; it presents the resulting signal to
another input of the summing amplifier. These two signals are
then summed together. This output is then presented to a com­parator looking at the oscillator ramp, which provides the
main PWM control signal to the digital control block.

The digital control block takes the analog comparator input
and the main clock signal from the oscillator to provide the
appropriate pulses to the HIDRV and LODRV output pins.
These two outputs control the external power MOSFETs.

There is an additional comparator in the analog control sec­tion whose function is to set the point at which the FAN5071
current limit comparator disables the output drive signals to
the external power MOSFETs.

High Current Output Drivers

The FAN5071 contains two identical high current output
drivers that utilize high speed bipolar transistors in a push­pull configuration. The drivers’ power and ground are sepa­rated from the chip’s power and ground for switching noise
immunity. The power supply pin, V
external 12V source through a series resistor. The resulting
voltage is sufficient to provide the gate to source drive to the
external MOSFETs required in order to achieve a low
R

.

DS,ON

, is supplied from an

CCP

Internal Voltage Reference

The reference included in the FAN5071 is a precision band­gap voltage reference. Its internal resistors are precisely
trimmed to provide a near zero temperature coefficient (TC).
Based on the reference is the output from an integrated 5-bit
DAC.

In the FAN5071, the DAC monitors the 5 voltage identifica­tion pins, VID0-4, and scales the voltage from 1.050V to

1.825V in 25mV steps according to Table I.

Power Good (PWRGD)

The FAN5071 Power Good function is designed in accor­dance with VRM8.5 and DC-DC converter specifications
and provides a continuous voltage monitor on the VFB pin.
The circuit compares the VFB signal to the VREF voltage
and outputs an active-low interrupt signal to the CPU should
either of two conditions obtain: 1) any of the linear power
supply voltages deviate more than -20% from their nominal
setpoint; 2) The switching power supply output is more than
+14% from (V
120mV). The Power Good flag provides no other control
function to the FAN5071.

+ 80mV), or less than –14% from (V

VID

VID

–

Output Enable/Soft Start (ENABLE/SS)

The FAN5071 will accept an open collector/TTL signal for
controlling the output voltage. The low state disables the out­put voltage. When disabled, the PWRGD output is in the low
state.

Even if an enable is not required in the circuit, this pin
should have attached a capacitor (typically 100nF) to
softstart the switching. A softstart capacitor may be
approximately chosen by the formula:

10µ At•

C

=

---------------------

1.8V

The linear regulators are not softstarted.

Over-Voltage Protection

The FAN5071 continuously monitors the output voltage for
protection against over-voltage conditions. If the voltage at
the VFB pin exceeds approximately 2.5V, an OVP circuit
forces the low-side MOSFET on, over-riding all other
conditions. The OVP circuit remains active, and the low-side
MOSFET remains on, until the VFB voltage drops below
approximately 2.1V. The OVP circuit is functional even
during startup; thus, protection is provided even during
startup with a shorted high-side MOSFET.

Oscillator

The FAN5071 oscillator section uses a fixed frequency of
operation of 300KHz.

REV. 1.0.4 1/29/02 9

FAN5071 PRODUCT SPECIFICATION

Design Considerations and Component
Selection

Additional information on design and component selection
may be found in Fairchild’s Application Note 57.

MOSFET Selection

This application requires N-channel Logic Level Enhance­ment Mode Field Effect Transistors. Desired characteristics
are as follows:

• Low Static Drain-Source On-Resistance, R

DS,ON

< 20mΩ

(lower is better)

• Low gate drive voltage, VGS = 4.5V rated

• Power package with low Thermal Resistance

• Drain-Source voltage rating > 15V.

The on-resistance (R

) is the primary parameter for

DS,ON

MOSFET selection. The on-resistance determines the power
dissipation within the MOSFET and therefore significantly
affects the efficiency of the DC-DC Converter. For details
and a spreadsheet on MOSFET selection, refer to Applica­tions Bulletin AB-8.

Inductor Selection

Choosing the value of the inductor is a trade-off between
allowable ripple voltage and required transient response. The
system designer can choose any value within the allowed
minimum to maximum range in order to either minimize rip­ple or maximize transient performance. The first order equa­tion (close approximation) for minimum inductance is:

(V

– V

)

in

L

=

min

out

f

V

x

ESR

out

x

V

V

in

ripple

Some margin should be maintained away from both L

. Adding margin by increasing L almost always adds

L

max

min

and

expense since all the variables are predetermined by system
performance except for Co, which must be increased to
increase L. Adding margin by decreasing L can be done by
purchasing capacitors with lower ESR. The FAN5071 pro­vides significant cost savings for the newer CPU systems
that typically run at high supply current.

FAN5071 Short Circuit Current Characteristics

The FAN5071 protects against output short circuit on the
core supply by latching off both the high-side and low-side
MOSFETs. The FAN5071 short circuit current characteristic
includes a hysteresis function that prevents the DC-DC con­verter from oscillating in the event of a short circuit. The
short circuit limit is set with the R
formula

R

=

S

with I

≈ 50µA, ISC the desired current limit, and R

Detect

the high-side MOSFET’s on resistance. Remember to make
the RS large enough to include the effects of initial tolerance
and temperature variation on the MOSFET’s R
nately, use of a sense resistor in series with the source of the
MOSFET, as shown in Figure 6, eliminates this source of
inaccuracy in the current limit.

As an example, Figure 3 shows the typical characteristic of
the DC-DC converter circuit with two FDD6690A high-side
MOSFETs (RDS = 17mΩ maximum at 25°C * 1.25 at 75°C
= 21.25mΩ each for a total of 10.6mΩ) and a 6.19KΩ RS.

resistor, as given by the

S

I

*R

SC

DS, on

I

Detect

DS,on

DS,on

. Alter-

where:
Vin = Input Power Supply

= Output Voltage

V

out

f = DC/DC converter switching frequency
ESR = Equivalent series resistance of all output capacitors in

(V)

OUT

V

parallel
V

= Maximum peak to peak output ripple voltage budget.

ripple

The first order equation for maximum allowed inductance is:

(V

– V

) Dm V

in

2C

L

=

max

O

out

2

I

pp

tb

0 10 20 30 40 50

Output Current (A)

Figure 3. FAN5071 Short Circuit Characteristic

where:
Co = The total output capacitance
Ipp = Maximum to minimum load transient current
Vtb = The output voltage tolerance budget allocated to load
transient
Dm = Maximum duty cycle for the DC/DC converter (usu­ally 95%).

The converter exhibits a normal load regulation characteris­tic until the voltage across the MOSFET exceeds the internal
short circuit threshold of 50µA * 6.2KΩ = 310mV, which
occurs at 310mV/10.6mΩ = 29A. [Note that this current
limit level can be as high as 310mV/6.5mΩ = 48A, if the
MOSFET has typical R

rather than maximum, and is at

DS,on

25°C. This is the reason for using the external sense resistor.]
At this point, the internal comparator trips and signals the

10 REV. 1.0.4 1/29/02

PRODUCT SPECIFICATION FAN5071

controller to reduce the converter’s duty cycle to approxi­mately 20%. This causes a drastic reduction in the output
voltage as the load regulation collapses into the short circuit
control mode. With a 4mΩ output short, the voltage is
reduced to 29A * 4mΩ = 116mV. The output voltage does
not return to its nominal value until the output current is
reduced to a value within the safe operating range for the
DC-DC converter.

Schottky Diode Selection

The application circuits of Figure 1 shows a Schottky diode,
D1, which is used as a free-wheeling diode to assure that the
body-diode in Q2 does not conduct when the upper MOS­FET is turning off and the lower MOSFET is turning on. It is
undesirable for this diode to conduct because its high for­ward voltage drop and long reverse recovery time degrades
efficiency, and so the Schottky provides a shunt path for the
current. Since this time duration is very short, the selection
criterion for the diode is that the forward voltage of the
Schottky at the output current should be less than the for­ward voltage of the MOSFET’s body diode.

Output Filter Capacitors

The output bulk capacitors of a converter help determine its
output ripple voltage and its transient response. It has
already been seen in the section on selecting an inductor that
the ESR helps set the minimum inductance, and the capaci­tance value helps set the maximum inductance. For most
converters, however, the number of capacitors required is
determined by the transient response and the output ripple
voltage, and these are determined by the ESR and not the
capacitance value. That is, in order to achieve the necessary
ESR to meet the transient and ripple requirements, the
capacitance value required is already very large.

The most commonly used choice for output bulk capacitors
is aluminum electrolytics, because of their low cost and low
ESR. The only type of aluminum capacitor used should be
those that have an ESR rated at 100kHz. Consult Application
Bulletin AB-14 for detailed information on output capacitor
selection.

The output capacitance should also include a number of
small value ceramic capacitors placed as close as possible to
the processor; 0.1µF and 0.01µF are recommended values.

Input Filter

The DC-DC converter design may include an input inductor
between the system +5V supply and the converter input as
shown in Figure 5. This inductor serves to isolate the +5V
supply from the noise in the switching portion of the DC-DC
converter, and to limit the inrush current into the input capac­itors during power up. A value of 2.5µH is recommended.

deliver current when the high side MOSFET switches on.
Figure 4 shows 3 x 1000µF, but the exact number required
will vary with the speed and type of the processor. Capacitor
ripple current rating is a function of temperature, and so the
manufacturer should be contacted to find out the ripple cur­rent rating at the expected operational temperature. For
details on the design of an input filter, refer to Applications
Bulletin AB-15.

2.5µH

™

Vin

1000µF, 10V
Electrolytic

5V

0.1µF

Figure 4. Input Filter

Programmable Active Droop

The FAN5071 includes Programmable Active Droop™: as
the output current increases, the output voltage drops, and
the amount of this drop is user adjustable. This is done in
order to allow maximum headroom for transient response of
the converter. The current is typically sensed by measuring
the voltage across the R

of the high-side MOSFET

DS,on

during its on time, as shown in Figures 1 and 2.

To program the amount of droop, use the formula

14.4KΩ *I

R

D

where I
R

sense

is the current at which the droop occurs, and

max

is the resistance of the current sensor, either the source

V

max

Droop

*R

*3

sense

resistor or the high-side MOSFET’s on-resistance. For exam­ple, to get 120mV of droop with a maximum output current
of 30A and a 10mΩ sense resistor, use RD = 14.4KΩ * 30A *
10mΩ/(120mV *3) = 12KΩ. The value of the product
Imax*Rsense must be < 600mV for proper functioning of
the droop circuit. If this product is exceeded, a lower resis­tance MOSFET must be used. Further details on use of the
Programmable Active Droop™ may be found in Applications
Bulletin AB-24.

Remote Sense

The FAN5071 offers remote sense of the output voltage to
minimize the output capacitor requirements of the converter.
It is highly recommended that the remote sense pin, Pin 20,
be tied directly to the processor power pins, so that the
effects of power plane impedance are eliminated. Further
details on use of the remote sense feature of the FAN5071
may be found in Applications Bulletin AB-24.

It is necessary to have some low ESR aluminum electrolytic
capacitors at the input to the converter. These capacitors

REV. 1.0.4 1/29/02 11

FAN5071 PRODUCT SPECIFICATION

Adjusting the Linear Regulators’ Output
Voltages

Any or all of the linear regulators’ outputs may be adjusted
high to compensate for voltage drop along traces, as shown
in Figure 5.

VGATE

VOUT

R

VFB

10KΩ

Figure 5. Adjusting the Output Voltage of the

Linear Regulator

The resistor value should be chosen as

V

R2KΩ*

For example, to get the V

=

ADJ

out

V

nom

voltage to be 1.50V instead of

1.20V, use R = 2KΩ * [(1.50/1.20) – 1] = 500Ω.

Using the FAN5071 for Vnorthbridge = 1.8V

Similarly, the FAN5071 can also be used to generate Vnorth­bridge = 1.8V by utilizing the AGP regulator as shown in
Figure 5: tie the TYPEDET pin to ground, and use R = 399Ω.

Coppermine/Tualatin VTT

The adjustable regulator may be used for powering VTT
in systems in which either a Coppermine or a Tualatin
processor may be used, as shown in Figure 6.

VGATE

VTT

100Ω

VFB

487Ω

10KΩ

3.16KΩ

PCB Layout Guidelines

• Placement of the MOSFETs relative to the FAN5071 is
critical. Place the MOSFETs such that the trace length of
the HIDRV and LODRV pins of the FAN5071 to the FET
gates is minimized. A long lead length on these pins will
cause high amounts of ringing due to the inductance of the
trace and the gate capacitance of the FET. This noise
radiates throughout the board, and, because it is switching
at such a high voltage and frequency, it is very difficult to
suppress.

• In general, all of the noisy switching lines should be kept
away from the quiet analog section of the FAN5071. That
is, traces that connect to pins 1, 2, 23, and 24 (HIDRV,
SW, LODRV and V
traces that connect to pins 3, 20 and 21.

• Place the 0.1µF decoupling capacitors as close to the
FAN5071 pins as possible. Extra lead length on these
reduces their ability to suppress noise.

• Each VCC and GND pin should have its own via to the
appropriate plane. This helps provide isolation between
pins.

• Place the MOSFETs, inductor, and Schottky as close
together as possible for the same reasons as in the first
bullet above. Place the input bulk capacitors as close to
the drains of the high side MOSFETs as possible. In
addition, placement of a 0.1µF decoupling cap right on the
drain of each high side MOSFET helps to suppress some
of the high frequency switching noise on the input of the
DC-DC converter.

• Place the output bulk capacitors as close to the CPU as
possible to optimize their ability to supply instantaneous
current to the load in the event of a current transient.
Additional space between the output capacitors and the
CPU will allow the parasitic resistance of the board traces
to degrade the DC-DC converter’s performance under
severe load transient conditions, causing higher voltage
deviation. For more detailed information regarding
capacitor placement, refer to Application Bulletin AB-5.

• A PC Board Layout Checklist is available from Fairchild
Applications. Ask for Application Bulletin AB-11.

Additional Information

For additional information contact your local Fairchild
Semiconductor representative, or visit us at our web site
www.fairchildsemi.com.

) should be kept far away from the

CCP

10KΩ

AF36

Figure 6. Using VADJ to Generate VTT

2N7002

2N7002

12 REV. 1.0.4 1/29/02

PRODUCT SPECIFICATION FAN5071

Appendix

Worst-Case Formulae for the Calculation of
C

, C

in

, R5, R7 and R

out

to Figure 1 only)

The following formulae design the FAN5071 for worst-case
operation, including initial tolerance and temperature depen­dence of all of the IC parameters (initial setpoint, reference
tolerance and tempco, internal droop impedance, current
sensor gain), the initial tolerance and temperature depen­dence of the MOSFET, and the ESR of the capacitors. The
following information must be provided:

VS+, the value of the positive static voltage limit;

|VS-|, the absolute value of the negative static voltage limit;

, the value of the positive transient voltage limit;

V

T+

|V

|, the absolute value of the negative transient voltage

T-

limit;

IO, the maximum output current;

V

, the nominal output voltage;

nom

Vin, the input voltage (typically 5V);

I

, the ripple current rating of the input capacitors, per cap

rms

(2A for the Sanyo parts shown in this data sheet);

RD, the resistance of the current sensor (usually the MOSFET);

, the tolerance of the current sensor (usually about 67%

∆

RD

for MOSFET sensing, including temperature); and

ESR, the ESR of the output capacitors, per cap (44mΩ for
the Sanyo parts shown in this data sheet).

(Circuits similar

offset

Number of capacitors needed for C

X=

VT-+ V

= the greater of:

OUT

ESR * I

O

– .024 * V

S+

nom

or

ESR * I

Y

=

VT+ – V

S+

+

O

14400 * I

18 * R5 * 1.1

* R

O

D

Example: Suppose that the static limits are +89mV/-79mV,
transient limits are ±134mV, current I is 14.2A, and the nom­inal voltage is 2.000V, using MOSFET current sensing. We
have V

14.2, V

= 0.089, |VS-| = 0.079, VT+ = |VT-| = 0.134, IO =

S+

= 2.000, and ∆RD = 1.67. We calculate:

nom

2.000

*14.2

=

C

in

0.089 – .014 * 2.000 – .029

=

R

offset

14.2 * 0.020 * (1 + 0.67)

=

R7

14400 * 14.2 * 0.020 * (1 + 0.67) * 1.1

=

R5

18 * (0.089 + 0.079 – .024 * 2.000)

X==

0.134 + 0.089 – .024 * 2.00

–

5

2

0.29 + 2.000

45 * 10

0.044 * 14.2

2.000

5

-6

2

=

3.47 ⇒ 4 caps

*1000 = 15.8Ω

10.5KΩ

=

3.57

=

3.48KΩ

2

I

rms

V

nom

–

V

in

V

nom

*IO

V

=

C

in

in

=

Y

0.134 – 0.089

0.044 * 14.2

14400 * 14.2 * 0.020

+

18 * 3640 * 1.1

6.14

=

Since Y > X, we choose Y, and round up to find we need 7

R

offset

=

V

S+

– .014 * V

.029 * V

nom

nom

– .029

capacitors for C

* 1KΩ

A detailed explanation of this calculation may be found in

OUT

.

Applications Bulletin AB-24.

IO* RD * (1 + ∆RD)

R7

=

14400 * IO* RD * (1 + ∆RD) *1.1

R5 =

18 * (V

S+

45 * 10

+ V

-6

– .024 * V

S-

nom

)

REV. 1.0.4 1/29/02 13

PRODUCT SPECIFICATION FAN5071

Mechanical Dimensions

24 Lead SOIC

Symbol

A .093 .104 2.35 2.65

A1 .004 .012 0.10 0.30

B .013 0.33

C .009 .013 0.23 0.32
D .599 .614 15.20 15.60

E .290 .299 7.36 7.60

e

H

h

L .016 .050 0.40 1.27

N24 24

α

ccc .004 0.10——

24 13

Inches

Min. Max. Min. Max.

.020 0.51

.050 BSC 1.27 BSC

.394 .419 10.00 10.65

.010 .020 0.25 0.51

0° 8° 0° 8°

Millimeters

Notes

5
2

2

3
6

H

E

Notes:

1.

Dimensioning and tolerancing per ANSI Y14.5M-1982.

2.

"D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).

3.

"L" is the length of terminal for soldering to a substrate.

4.

Terminal numbers are shown for reference only.

5.

"C" dimension does not include solder finish thickness.

6.

Symbol "N" is the maximum number of terminals.

112

D

A

e

B

A1

SEATING
PLANE

– C –

LEAD COPLANARITY

ccc C

h x 45°

C

α

L

REV. 1.0.4 1/29/02 14

FAN5071

Ordering Information

Product Number Description Package

FAN5071M VRM8.5 24 pin SOIC

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

www.fairchildsemi.com

2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

1/29/02 0.0m 005

Stock#DS30005071

 2001 Fairchild Semiconductor Corporation